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1 4 megabit (512k x8) superflash eeprom sst28sf040a / sst28vf040a data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ? 2000 silicon storage technology, inc. the sst logo and superflash are registered trademarks of silicon storage technology, i nc. ssf is a trademark of silicon storage technology, inc. 310-3 6/00 these specifications are subject to change without notice. product description the sst28sf040a/28vf040a are 512k x8 bit cmos sector-erase, byte-program eeproms. the sst28sf040a/28vf040a are manufactured using ssts proprietary, high performance cmos superflash eeprom technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative ap- proaches. the sst28sf040a/28vf040a erase and program with a single power supply. the sst28sf040a/28vf040a conform to jedec standard pinouts for byte wide memories and are compatible with existing industry standard flash eeprom pinouts. featuring high performance programming, the sst28sf040a/28vf040a typically byte-program in 35 s. the sst28sf040a/28vf040a typically sector- erase in 2 ms. both program and erase times can be optimized using interface features such as toggle bit or data# polling to indicate the completion of the write cycle. to protect against an inadvertent write, the sst28sf040a/28vf040a have on chip hardware and software data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, the sst28sf040a/28vf040a are offered with a guaranteed sector endurance of 10 4 cycles. data retention is rated greater than 100 years. the sst28sf040a/28vf040a are best suited for appli- cations that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. for all system applications, the sst28sf040a/28vf040a sig- nificantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or eprom approaches. flash eeprom technology makes possible convenient and economical updating of codes and control programs on- line. the sst28sf040a/28vf040a improve flexibility, while lowering the cost of program and configuration storage application. the functional block diagram shows the functional blocks of the sst28sf040a/28vf040a. figures 1 and 2 show the pin assignments for the 32 pin tsop, 32 pin pdip, and 32 pin plcc packages. pin description and operation modes are described in tables 1 through 4. device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. note, during the software data protection sequence the addresses are latched on the rising edge of oe# or ce#, whichever occurs first. features: ? single voltage read and write operations C 5.0v-only for the sst28sf040a C 2.7-3.6v for the sst28vf040a ? superior reliability C endurance: 100,000 cycles (typical) C greater than 100 years data retention ? memory organization: 512k x8 ? sector-erase capability: 256 bytes per sector ? low power consumption C active current: 15 ma (typical) for 5.0v and 10 ma (typical) for 2.7-3.6v C standby current: 5 a (typical) ? fast sector-erase/byte-program operation C byte-program time: 35 s (typical) C sector-erase time: 2 ms (typical) C complete memory rewrite: 20 sec (typical) ? fast read access time C 5.0v-only operation: 90 and 120 ns C 2.7-3.6v operation: 150 and 200 ns ? latched address and data ? hardware and software data protection C 7-read-cycle-sequence software data protection ? end-of-write detection C toggle bit C data# polling ? ttl i/o compatibility ? jedec standard C flash eeprom pinouts ? packages available C 32-pin pdip C 32-pin plcc C 32-pin tsop (8mm x 14mm and 8mm x 20mm)
2 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet command definitions table 3 contains a command list and a brief summary of the commands. the following is a detailed description of the operations initiated by each command. sector-erase operation the sector-erase operation erases all bytes within a sector and is initiated by a setup command and an execute command. a sector contains 256 bytes. this sector erasability enhances the flexibility and usefulness of the sst28sf040a/28vf040a, since most applica- tions only need to change a small number of bytes or sectors, not the entire chip. the setup command is performed by writing 20h to the device. the execute command is performed by writing d0h to the device. the erase operation begins with the rising edge of the we# or ce#, whichever occurs first and terminates automatically by using an internal timer. the end-of-erase can be determined using either data# polling, toggle bit, or successive reads detection methods. see figure 8 for timing waveforms. the two-step sequence of a setup command followed by an execute command ensures that only memory con- tents within the addressed sector are erased and other sectors are not inadvertently erased. sector-erase flowchart description fast and reliable erasing of the memory contents within a sector is accomplished by following the sector-erase flowchart as shown in figure 17. the entire procedure consists of the execution of two commands. the sector- erase operation will terminate after a maximum of 4 ms. a reset command can be executed to terminate the sector-erase operation; however, if the erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. a sector-erase command can be reissued as many times as necessary to complete the erase operation. the sst28sf040a/28vf040a cannot be overerased. chip-erase operation the chip-erase operation is initiated by a setup command (30h) and an execute command (30h). the chip-erase operation allows the entire array of the sst28sf040a/ 28vf040a to be erased in one operation, as opposed to 2048 sector-erase operations. using the chip-erase operation will minimize the time to rewrite the entire memory array. the chip-erase operation will terminate after a maximum of 20 ms. a reset command can be executed to terminate the erase operation; however, if the chip-erase operation is terminated prior to the 20 ms time-out, the chip may not be completely erased. if an erase error occurs a chip-erase command can be reis- sued as many times as necessary to complete the chip- erase operation. the sst28sf040a/28vf040a cannot be overerased. (see figure 7) byte-program operation the byte-program operation is initiated by writing the setup command (10h). once the program setup is performed, programming is executed by the next we# pulse. see figures 4 and 5 for timing waveforms. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first, and begins the program operation. the program operation is terminated automatically by an internal timer. see figure 15 for the programming flowchart. the two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvert- ently programmed. the byte-program flowchart description programming data into the sst28sf040a/28vf040a is accomplished by following the byte-program flowchart shown in figure 15. the byte-program command sets up the byte for programming. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first and begins the program opera- tion. the end of program can be detected using either the data# polling, toggle bit, or successive reads. reset operation the reset command is provided as a means to safely abort the erase or program command sequences. fol- lowing either setup commands (erase or program) with a write of ffh will safely abort the operation. memory contents will not be altered. after the reset command, the device returns to the read mode. the reset com- mand does not enable software data protection. see figure 6 for timing waveforms.
3 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet read the read operation is initiated by setting ce#, and oe# to logic low and setting we# to logic high (see table 2). see figure 3 for read cycle timing waveform. the read operation from the host retrieves data from the array. the device remains enabled for read until another operation mode is accessed. during initial power-up, the device is in the read mode and is software data protected. the device must be unprotected to execute a write com- mand. the read operation of the sst28sf040a/28vf040a are controlled by oe# and ce# at logic low. when ce # is high, the chip is deselected and only standby power will be consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when ce# or oe# are high. read-id operation the read-id operation is initiated by writing a single command (90h). a read of address 0000h will output the manufacturers code (bfh). a read of address 0001h will output the device code (04h). any other valid com- mand will terminate this operation. data protection in order to protect the integrity of nonvolatile data stor- age, the sst28sf040a/28vf040a provide both hardware and software features to prevent inadvertent writes to the device, for example, during system power- up or power-down. such provisions are described below. hardware data protection the sst28sf040a/28vf040a are designed with hard- ware features to prevent inadvertent writes. this is done in the following ways: 1. write cycle inhibit mode: oe# low, ce#, or we# high will inhibit the write operation. 2. noise/glitch protection: a we# pulse width of less than 5 ns will not initiate a write cycle. 3. v cc power up/down detection: the write operation is inhibited when v cc is less than 2.0v. 4. after power-up the device is in the read mode and the device is in the software data protect state. software data protection (sdp) the sst28sf040a/28vf040a have software methods to further prevent inadvertent writes. in order to perform an erase or program operation, a two-step command sequence consisting of a set-up command followed by an execute command avoids inadvertent erasing and programming of the device. the sst28sf040a/28vf040a will default to software data protection after power up. a sequence of seven consecutive reads at specific addresses will unprotect the device the address sequence is 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 041ah. the address bus is latched on the rising edge of oe# or ce#, which- ever occurs first. a similar seven read sequence of 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 040ah will protect the device. also refer to figures 9 and 10 for the 7 read cycle sequence software data protection. the i/o pins can be in any state (i.e., high, low, or tristate). write operation status detection the sst28sf040a/28vf040a provide three means to detect the completion of a write operation, in order to optimize the system write operation. the end of a write operation (erase or program) can be detected by three means: 1) monitoring the data# polling bit; 2) monitoring the toggle bit; or 3) by two successive reads of the same data. these three detection mechanisms are described below. the actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with the dq used. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the ac- cessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) the sst28sf040a/28vf040a feature data# polling to indicate the write operation status. during a write opera- tion, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on dq 7 . once the write cycle is completed, dq 7 will show true data. the device is then ready for the next operation. see figure 11 for data# polling timing wave- forms. in order for data# polling to function correctly , the byte being polled must be erased prior to programming.
4 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f unctional b lock d iagram of sst28sf040a/28vf040a toggle bit ( dq 6 ) an alternative means for determining the write operation status is by monitoring the toggle bit, dq 6 . during a write operation, consecutive attempts to read data from the device will result in dq 6 toggling between logic 0 (low) and logic 1 (high). when the write cycle is com- pleted, the toggling will stop. the device is then ready for the next operation. see figure 12 for toggle bit timing waveforms. successive reads an alternative means for determining an end of a write operation is by reading the same address for two con- secutive data matches. product identification the product identification mode identifies the device as sst28sf040a/28vf040a and the manufacturer as sst. this mode may be accessed by hardware and software operations. the hardware operation is typically used by an external programmer to identify the correct algorithm for the sst28sf040a/28vf040a. users may wish to use the software operation to identify the device (i.e., using the device code). for details see table 2 for the hardware operation and figure 18 for the software operation. the manufacturer and device codes are the same for both operations. y-decoder i/o buffers and data latches 310 ill b1.0 address buffer & latches x-decoder dq 7 - dq 0 a 18 - a 0 we# oe# ce# 4,194,304 bit eeprom cell array control logic p roduct i dentification t able byte data manufacturers id 0000 h bf h device id 0001 h 04 h
5 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 2: p in a ssignments for 32- pin p lastic dip s and 32-p in plcc s f igure 1: s tandard p in a ssignments for 32- pin tsop 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 a16 a18 v cc we# a17 32-lead plcc top view 32-pin pdip top view 310 ill f02.0 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 a11 a9 a8 a13 a14 a17 we# v cc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 310 ill f01.1 standard pinout top view die up t able 1: p in d escription symbol pin name functions a 18 -a 8 row address inputs to provide memory addresses. row addresses define a sector. a 7 -a 0 column address inputs selects the byte within the sector. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe#, ce # is high. ce# chip enable to activate the device when ce # is low. (1) oe# output enable to gate the data output buffers. we# write enable to control the write operations. (1) vcc power supply to provide 5-volt supply ( 10%) for the sst28sf040a, and 2.7-3.6v supply for the sst28vf040a vss ground note: (1) this pin is internally pull-up with a resistor. 310 pgm t1.2
6 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet t able 2: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in byte-program v il v ih v il d in a in, see table 3 sector-erase v il v ih v il d in a in, see table 3 standby v ih x x high z x write inhibit x v il x high z/ d out x write inhibit x x v ih high z/ d out x software chip-erase v il v ih v il d in see table 3 product identification hardware mode v il v il v ih manufacturer id (bfh) a 18 -a 1 =v il , a 9 =v h , a 0 =v il device id (04h) a 18 -a 1 =v il , a 9 =v h , a 0 =v ih software mode v il v il v ih see table 3 sdp enable & disable v il v il v ih see table 3 mode reset v il v ih v il see table 3 310 pgm t2.2 t able 4: m emory a rray d etail sector select byte select a 18 - a 8 a 7 - a 0 310 pgm t4.0 t able 3: s oftware c ommand s ummary command required setup command cycle execute command cycle sdp (5) summary cycle(s) type (1) addr (2,3) data (4) type (1) addr (2,3) data (4) sector-erase 2 w x 20h w sa d0h n byte-program 2 w x 10h w pa pd n chip-erase 2 w x 30h w x 30h n reset 1 w x ffh y read-id 2 w x 90h r (8) (8) y software data protect 7 r (6) software data unprotect 7 r (7) notes: 1. type definition: w = write, r = read, x= dont care 2. addr (address) definition: sa = sector address = a 18 - a 8 , sector size = 256 bytes; a 7 - a 0 = x for this command. 3. addr (address) definition: pa = program address = a 18 - a 0 . 4. data definition: pd = program data, h = number in hex. 5. sdp = software data protect mode using 7 read cycle sequence. a) y = the operation can be executed with protection enabled b) n = the operation cannot be executed with protection enabled 6. refer to figure 10 for the 7 read cycle sequence for software_data_protect. 7. refer to figure 9 for the 7 read cycle sequence for software_data_unprotect. 8. address 0000h retrieves the manufacturers id of bfh and address 0001h retrieves the device id of 04h. 9. the chip-erase function is not supported on sst28vf040a industrial parts. 310 pgm t3.1
7 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet absolute maximum stress ratings (applied conditions greater than those listed under absolute maximum stress ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias ......................................................................................................... ........ -55c to +125c storage temperature ............................................................................................................ .......... -65c to +150c d. c. voltage on any pin to ground potential ............................................................................. -0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential ......................................................... -1.0v to v cc + 1.0v voltage on a 9 pin to ground potential ................................................................................................ -0.5v to 14.0v package power dissipation capability (ta = 25c) ............................................................................... ............ 1.0w through hole soldering temperature (10 seconds) ................................................................................ ....... 300c surface mount lead soldering temperature (3 seconds) ........................................................................... .... 240c output short circuit current (1) ....................................................................................................................... 100 ma note: (1) outputs shorted for no more than one second. no more than one output shorted at a time. sst28sf040a o perating r ange range ambient temp v cc commercial 0c to +70c 5v10% industrial -40c to +85c 5v10% sst28vf040a o perating r ange range ambient temp v cc commercial 0c to +70c 2.7 to 3.6v industrial -40c to +85c 2.7 to 3.6v ac c onditions of t est input rise/fall time ......... 10 ns output load 1 ttl gate and c l = 100 pf for sst28sf040a c l = 100 pf for sst28vf040a see figures 13 and 14
8 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet t able 5: sst28sf040a dc o perating c haracteristics limits symbol parameter min max units test conditions i cc power supply current ce# = oe# =v il , we# =v ih , all i/os open read 32 ma address input = v il /v ih, at f=1/t rc min. v cc = v cc max program and erase 40 ma ce# =we# =v il , oe# =v ih v cc =v cc max. i sb1 standby v cc current 3 ma ce# =v ih , v cc =v cc max. (ttl input) i sb2 standby v cc current 20 a ce# = v cc -0.3v, (cmos input) v cc =v cc max i li input leakage current 1 a v in = gnd to v cc, v cc = v cc max. i lo output leakage current 10 a v out =gnd to v cc, v cc = v cc max. v il input low voltage 0.8 v v cc = v cc min. v ih input high voltage 2.0 v v cc = v cc max. v ol output low voltage 0.4 v i ol = 2.1 ma, v cc = v cc min. v oh output high voltage 2.4 v i oh = -400 a, v cc = v cc min. v h supervoltage for a 9 11.6 12.4 v ce#=oe#=v il, we#=v ih i h supervoltage current 200 a ce#=oe#=v il, we#=v ih, a 9 = v h max. for a 9 310 pgm t5.3 t able 6: sst28vf040a dc o perating c haracteristics limits symbol parameter min max units test conditions i cc power supply current ce# = oe# =v il , we# =v ih , all i/os open read 10 ma address input = v il /v ih, at f=1/t rc min. v cc = v cc max program and erase 25 ma ce# =we# =v il , oe# =v ih v cc =v cc max. i sb2 standby v cc current 20 a ce# = v cc -0.3v, (cmos input) v cc =v cc max i li input leakage current 1 a v in = gnd to v cc, v cc = v cc max. i lo output leakage current 10 a v out =gnd to v cc, v cc = v cc max. v il input low voltage 0.8 v v cc = v cc min. v ih input high voltage 2.0 v v cc = v cc max. v ol output low voltage 0.4 v i ol = 100 a, v cc = v cc min. v oh output high voltage 2.4 v i oh = -100 a, v cc = v cc min. v h supervoltage for a 9 11.6 12.4 v ce#=oe#=v il, we#=v ih i h supervoltage current 200 a ce#=oe#=v il, we#=v ih, a 9 = v h max. for a 9 310 pgm t6.3
9 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet t able 8: c apacitance (t a = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o (1) i/o pin capacitance v i/o = 0v 12 pf c in (1) input capacitance v in = 0v 6 pf note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this parameter . 310 pgm t8.0 t able 7: r ecommended s ystem p ower - up t imings symbol parameter m inimum units t pu-read (1) power-up to read operation 10 ms t pu-write (1) power-up to write operation 10 ms 310 pgm t7.3 t able 9: r eliability c haracteristics symbol parameter minimum specification units test method n end endurance 10,000 cycles jedec standard a117 t dr (1) data retention 100 years jedec standard a103 v zap_hbm (1) esd susceptibility 1000 volts jedec standard a114 human body model v zap_mm (1) esd susceptibility 200 volts jedec standard a115 machine model i lth (1) latch up 100 + i cc ma jedec standard 78 note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this paramete r. 310 pgm t9.5
10 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet ac characteristics t able 10: sst28sf040a r ead c ycle t iming p arameters ieee industry sst28sf040a-90 sst28sf040a-120 symbol symbol parameter min max min max units tavav t rc read cycle time 90 120 ns tavqv t aa address access time 90 120 ns telqv t ce chip enable access time 90 120 ns tglqv t oe output enable access time 45 50 ns tehqz t clz (1) ce# low to active output 0 0 ns tghqz t olz (1) oe# low to active output 0 0 ns telqx t chz (1) ce# high to high-z output 20 30 ns tglqx t ohz (1) oe# high to high-z output 20 30 ns taxqx t oh (1) output hold from address 0 0 ns change 310 pgm t10.5 310 pgm t12.4 t able 11: sst28vf040a r ead c ycle t iming p arameters ieee industry sst28vf040a-150 sst28vf040a-200 symbol symbol parameter min max min max units tavav t rc read cycle time 150 200 ns tavqv t aa address access time 150 200 ns telqv t ce chip enable access time 150 200 ns tglqv t oe output enable access time 75 100 ns tehqz t clz (1) ce# low to active output 0 0 ns tghqz t olz (1) oe# low to active output 0 0 ns telqx t chz (1) ce# high to high-z output 40 60 ns tglqx t ohz (1) oe# high to high-z output 40 60 ns taxqx t oh (1) output hold from address 0 0 ns change
11 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet t able 12: sst28sf040a e rase /p rogram c ycle t iming p arameters ieee industry symbol symbol parameter min max units tava t bp byte-program cycle time 40 s twlwh t wp write pulse width (we#) 90 ns tavwl t as address setup time 10 ns twlax t ah address hold time 50 ns telwl t cs ce# setup time 0 ns twhex t ch ce# hold time 0 ns tghwl t oes oe# high setup time 10 ns twgl t oeh oe# high hold time 10 ns twleh t cp write pulse width (ce#) 90 ns tdvwh t ds data setup time 50 ns twhdx t dh data hold time 10 ns twhwl2 t se sector-erase cycle time 4 ms t rst (1) reset command recovery time 4 s twhwl3 t sce software chip-erase cycle time 20 ms tehel t cph ce# high pulse width 50 ns twhwl1 t wph we# high pulse width 50 ns t pcp (1) protect ce# or oe# pulse width 50 ns t pch (1) protect ce# or oe# high time 50 ns t pas (1) protect address setup time 40 ns t pah (1) protect address hold time 0 ns note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this paramet er. 310 pgm t13.5
12 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet t able 13: sst28vf040a e rase /p rogram c ycle t iming p arameters ieee industry symbol symbol parameter min max units tava t bp byte-program cycle time 40 s twlwh t wp write pulse width (we#) 100 ns tavwl t as address setup time 10 ns twlax t ah address hold time 100 ns telwl t cs ce# setup time 0 ns twhex t ch ce# hold time 0 ns tghwl t oes oe# high setup time 20 ns twgl t oeh oe# high hold time 20 ns twleh t cp write pulse width (ce#) 100 ns tdvwh t ds data setup time 100 ns twhdx t dh data hold time 20 ns twhwl2 t se sector-erase cycle time 4 ms t rst (1) reset command recovery time 4 s twhwl3 t sce software chip-erase cycle time 20 ms tehel t cph ce# high pulse width 50 ns twhwl1 t wph we# high pulse width 50 ns t pcp (1) protect ce# or oe# pulse width 50 ns t pch (1) protect ce# or oe# high time 50 ns t pas (1) protect address setup time 40 ns t pah (1) protect address hold time 0 ns note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this paramet er. 310 pgm t14.5
13 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 3: r ead c ycle t iming d iagram f igure 4: we# c ontrolled b yte -p rogram t iming d iagram 310 ill f03.2 ce# address a 18-0 oe# we# dq 7-0 t clz t oh data valid data valid t olz t oe t ce t chz t ohz t rc t aa 310 ill f04.1 ce# oe# we# t dh t ds t oes t cs t as t ah t wp t wph t oeh t ch t ds t dh t bp address a 18-0 dq 7-0 byte-program setup command i0h data valid
14 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f igure 5: ce# c ontrolled b yte -p rogram t iming d iagram f igure 6: r eset c ommand t iming d iagram 310 ill f05.1 ce# oe# we# t dh t ds t oes t cph t as t ah t cs t ch t oeh t cp t ds t dh t bp address a 18-0 dq 7-0 byte-program setup command i0h data valid 310 ill f06.0 ce# oe# we# t ds t dh t rst address a 18-0 dq 7-0 ffh
15 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 7: c hip -e rase t iming d iagram f igure 8: s ector -e rase t iming d iagram 310 ill f07.0 ce# oe# we# t dh t ds t dh t sce t ds address a 18-0 dq 7-0 30h setup command execute command 30h 310 ill f08.0 ce# oe# we# t dh t ah t as a in t ds t dh t se t ds address a 18-0 dq 7-0 20h setup command execute command d0h
16 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f igure 10: s oftware d ata p rotect t iming d iagram f igure 9: s oftware d ata u nprotect t iming d iagram 310 ill f10.4 oe# ce# we# address t pa h t pa s t pch t pcp note: a. addresses are latched internally on the rising edge of: 1. oe# if ce# is kept at low all time. 2. ce# if oe# is kept at low all time. 3. the first pin to go high if both are toggled. b. above address values are in hex. c. addresses > a12 are "don't care" 1823 1820 1822 0418 041b 0419 040a 310 ill f09.4 oe# ce# we# address t pa h t pa s t pch t pcp note: a. addresses are latched internally on the rising edge of: 1. oe# if ce# is kept at low all time. 2. ce# if oe# is kept at low all time. 3. the first pin to go high if both are toggled. b. above address values are in hex. c. addresses > a12 are "don't care" 1823 1820 1822 0418 041b 0419 041a
17 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 11: d ata # p olling t iming d iagram f igure 12: t oggle b it t iming d iagram 310 ill f11.0 ce# oe# we# note d# t oe t oeh t ce t oes d# d address a 18-0 dq 7-0 note: this time interval signal can be t se or t bp depending upon the selected operation mode. d 310 ill f12.0 ce# oe# we# note two read cycles with same outputs t oeh t oe t oe t oes t ce t ce address a 18-0 dq 6 note: this time interval signal can be t se or t bp depending upon the selected operation mode.
18 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f igure 13: ac i nput /o utput r eference w aveform f igure 14: a t est l oad e xample 310 ill f13.0 reference points output input v ht v lt v ht v lt v iht v ilt 310 ill f14.1 test load example to tester to dut c l r l low r l high v cc ac test inputs are driven at v iht (2.4 v) for a logic 1 and v ilt (0.4 v) for a logic 0. measurement reference points for inputs and outputs are at v ht (2.0 v) and v lt (0.8 v) input rise and fall times (10% ? 90%) are <10 ns. note: v ht Cv high test v lt Cv low test v iht Cv input high test v ilt Cv input low test
19 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 15: b yte -p rogram f lowchart 310 ill f15.3 ye s no no no last address read end-of-write detection ye s data verifies? ye s programming completed? programming completed next address programming failure load address and data & start programming execute byte- program setup command initialize address start
20 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f igure 16: w rite w ait o ptions 310 ill f16.2 no no read byte ye s ye s does dq 6 match? program/erase completed read same byte program/erase initiated toggle bit wait t bp or t se program/erase completed program/erase initiated internal timer read dq 7 is dq 7 = true data? program/erase completed program/erase initiated data# polling
21 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet f igure 17: s ector -e rase f lowchart 310 ill f17.4 no no no no ye s ye s ye s ye s last sector? verify ff erase completed? last address? device erased execute two step sector-erase command increment byte address next sector address end-of-write detection read ff from selected byte address initialize sector address start sector-erase completed erase error
22 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet f igure 18: s oftware p roduct id f low execute read id command (90h) to enter read-id mode read address 0000h mfg's code = sst (bf) read address 0001h device code = 28sf040 (04) execute reset command (ffh) to exit from read-id mode 310 ill f18.3
23 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet product ordering information device speed suffix1 suffix2 sst28xf040a - xxx - xx - xx package modifier h = 32 leads numeric = die modifier package type p = pdip n = plcc e = tsop (die up) (8mm x 20mm) w = tsop (die up) (8mm x 14mm) u = unencapsulated die operating temperature c = commercial = 0 to 70c i = industrial = -40 to 85c minimum endurance 4 = 10,000 cycles read access speed 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns voltage s = 5v-only v = 2.7-3.6v
24 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet sst28sf040a valid combinations sst28sf040a-90-4c-eh sst28sf040a- 90-4c-nh sst28sf040a- 90-4c-wh sst28sf040a-120-4c-eh sst28sf040a-120-4c-nh sst28sf040a-120-4c-wh sst28sf040a-120-4c-ph sst28sf040a-120-4c-u2 sst28sf040a-120-4i-eh sst28sf040a-120-4i-nh sst28sf040a-120-4i-wh sst28vf040a valid combinations sst28vf040a-150-4c-eh sst28vf040a-150-4c-nh sst28vf040a-150-4c-wh sst28vf040a-200-4c-eh sst28vf040a-200-4c-nh sst28vf040a-200-4c-wh sst28vf040a-200-4c-u2 sst28vf040a-200-4i-eh sst28vf040a-200-4i-nh sst28vf040a-200-4i-wh example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. note: the software chip-erase function is not supported by the industrial part. please contact sst if you require this function for a n industrial temperature part.
25 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet 32-l ead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh 32-l ead p lastic d ual - in -l ine p ackage (pdip) sst p ackage c ode : ph packaging diagrams 32.pdipph-ill.1 pin 1 index c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .170 .200 7? 4 plcs. .600 bsc .100 bsc .120 .150 .016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 0? 15? .600 .625 .530 .550 .030 .040 .013 .021 .490 .530 .075 .095 .015 min. .125 .140 top view side view bottom view 1 232 .026 .032 .400 bsc 32.plcc.nh-ill.1 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. .050 bsc. .050 bsc. .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 optional pin #1 identifier .547 .553 .585 .595 .485 .495 .020 r. max. .106 .112 r. x 30?
26 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet 32-l ead t hin s mall o utline p ackage (tsop) 8 mm x 20 mm sst p ackage c ode : eh 32.tsop-eh-ill.3 note: 1. complies with jedec publication 95 mo-142 bd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 8.10 7.90 .27 .17 1.05 0.95 .50 bsc 0.15 0.05 18.50 18.30 20.20 19.80 0.70 0.50 pin # 1 identifier
27 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data sheet 32-l ead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh 32.tsop-wh-ill.3 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 8.10 7.90 .270 .170 1.05 0.95 .50 bsc 0.15 0.05 12.50 12.30 pin # 1 identifier 14.20 13.80 0.70 0.50
28 ? 2000 silicon storage technology, inc. 310-3 6/00 4 megabit superflash eeprom sst28sf040a / sst28vf040a data sheet silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.ssti.com ? literature faxback 888-221-1178, international 732-544-2873

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