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pt0141(06/03) ver:0 1 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| features ? complete 2.4ghz high performance radio transceiver ? no external trimming is required in production ? bluetooth wireless technology, 2.4 ghz license- free band ? compliant to the bluetooth? specification v1.1 ? bluetooth class 2, 3 level output power ? high receive sensitivity -85 dbm typ. ? communications of up to 10m range in free space ? frequency hopping spread spectrum (fhss) with gaussian frequency shift keying (gfsk) ? transmission scheme tdd ? time division duplex. ? frequency 2402 to 2480 mhz ? channel intervals 1 mhz ? number of channels 79 ch ? symbol rate 1m symbol/s ? compliant to fcc, ce, etsi and other countries' emi standards ? very good data quality--tolerates blocking by other services ? internal 16mhz crystal and clock oscillator ? integrated rf bandpass filter ? spi interface for installing and configuring the module ? low power standby modes to enable very efficient power management ? available for either external antenna or internal patch_antenna ? power supply voltage 2.7 v and 3.3v ? operation temperature: 0 ~ 40c ? small size, lightweight, size 33mm x 20mm x 1.5mm ? available in small quantities application ? laptop and desktop pcs ? computer accessories (compact flash, pcmcia and sd cards) ? cordless game controllers ? printers, fax, webpad ? personal digital assistants (pdas) ? cordless headsets ? digital camera ? usb dongle /rs232 adaptor ? and many other computer peripherals or embedded devices applications, including wireless keyboard, mouse, joystick etc. general descriptions the pt8r2401 is well suited to applications that fall within the 2.4 ghz radio spectrum designated as industrial, scientific and medical (ism). transmission scheme tdd ? time division duplex. spreading type fhss ? frequency hopping spread spectrum. number of channels 79. channel intervals 1 mhz [(f = 2.402 + k) ghz, k = 0,1,2,?78]. hop rate 1.6k hops/second. modulation method gfsk 0.5bt gaussian. support point-to-multipoint functionality. the pt8r2401 control interface consists of a data interface and a control interface for transmitting and receiving data, and a serial interface for programming the internal registers of the pt8r2401. there are two subsections of the interface: rf data and control path register control interface (serial). six signals are used in the rf data and control path (txdata, rxdata, txactive, rxactive, txdata_en, syncdetect). four in the serial register control interface ( tdi, tdo, tms, tck), one system clock (dataclk) and one reset signal (ret). all of the signals are unidirectional. standard pt8r2401 has built-in antenna. option pt8r2401n has no built-in antenna. customer can use external antenna. these modules can be integrated into almost any radio electrical device for wireless data communications, including pdas, mobile phones, laptop computers, and game pad devices.
pt0141(06/03) ver:0 2 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ordering information description device type size order number pt8r2401 have built-in antenna 33x20x1.5 (mm) PT8R2401MD pt8r2401n no built-in antenna 33x20x1.5 (mm) PT8R2401MD block diagram txdata 12 rxdata 11 txactive 9 rxactive 10 txdata_en 13 dataclk 14 tclk 17 tms 20 tdi 19 tdo 18 syncdetect 21 mdsel 40 rf_out 34 rf_i n 37 pa_cnt 39 test_p1 3 test_p2 4 test_p3 5 test_p4 6 test_p5 7 test_p6 30 xtalin 23 xtalout 22 an_vcc 1 an_vcc 2 an_vcc 24 an_vcc 25 dig_vcc 8 rf_vcc 38 rf_vcc 33 vco_vcc 26 vco_vcc 27 vco_vcc 31 vco_vcc 32 io_vcc 15 gnd 41 reset 16 ic1 pt8r1002 c1 15p c2 15p c10 100p r1 10 l2 10n c7 100p c3 47p c5 47p l1 2.7n c6 2.7p c4 47p txdata rxdata txactive rxactive txdata_en tck tms tdi tdo syncdetect r2 100k in 1 3 out 2 fl1 mdr746f reset v2 4 rfc 5 v1 6 rf1 1 gnd 2 rf2 3 sw1 as169-73 rxacti ve txactive vcc2.7 vcc2.7 c9 100p c16 0.1u c11 100p c12 1n c13 1n c14 1n c15 1n vcc3.3 dataclk vcc2.7 vcc2.7 vcc2.7 vcc2.7 vcc2.7 vcc3.3 xtal1 16m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 jp1 header15 gnd txactive rxactive vcc2.7 rxdata txdata dataclk vcc3.3 reset tck tdi tms syncdetect txdata_en c8 100p ant1 c17 0.1u tdo l3 2.2n tp1 tp2
pt0141(06/03) ver:0 3 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| pin information package diagram size 33x20x1.5 (mm) pin descriptions pin pin name type description 1 gnd power gnd 2 vcc2.7 power 2.7v power supply 3 txactive i transmitter enable 4 rxactive i receiver enable 5 rxdata o receive data 6txdata i transmit data 7 txdata_en i timing reference of valid data 8 dataclk o reference data clock 9 vcc3.3 power 3.3v power supply 10 reset i reset 11 tck i a serial register interface clock 12 tdo o phy control register serial data output 13 tdi i phy control register serial data input 14 tms i control signal of phy?s tap controller 15 syncdetect i indication of sync word detection 33 20 2 unit: mm
pt0141(06/03) ver:0 4 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| i/o description rf interface the radio interface establishes the connection of antenna-to-lna in receiving mode and antenna-to-power amplifier in transmitting mode. an antenna filter is located between the antenna and spdt (single pole double throw) switch. the antenna filter blocks unwanted signals in receive mode and suppresses harmonics in the transmit mode. the filter can be either a discrete component or fully integrated in ceramic substrate. the spdt switch isolates the transmit path and the receive path and thus impedance can be matched for entire signal path. a matching circuit is placed between lna_in pin and spdt switch to match the 50 ohm source to the complex input impedance of the lna. another external matching circuit is required at pa_out to transfer maximum power to the antenna. unidirectional interface the interface connections for unidirectional mode are shown as follows: the unidirectional interface can be split into two subsections: rf data and control path, register control interface. in rf interface, ten signals are used in the rf data and con trol path, and four in the register control interface. all of the signals are unidirectional. the unidirectional interface requires that the pt8r2401 control registers interface to the baseband via an ieee 1149.1 jtag interface. the unidirectional interface requires that the baseband portion of the interface is referenced to a baseband generat ed clock. transmit operation in unidirectional interface the primary signal for data transmit is txactive signal. the actual data transmission starts after txdata_en provided by baseband. during transmit mode, dataclk is sent from pt8r2401 to baseband as a timing reference. the baseband circuit transmits data to the pt8r2401 at the falling edge of dataclk, whereas the pt8r2401 latches the data at the rising edge of dataclk. the state of pt8r2401 transits from the idle state when the baseband drives txactive high. txactive enables all the transmit circuitry except for the final output stage. txactive is driven high at a time t tuningtx before the hop frequency synthesizer has settled to allow any frequency offsets caused by the tx circuitry to be eliminated. either when, or just before , the tx circuitry has correctly settled on frequency, the baseband drives txdata_en high, which enables the pa stage, and causes the unidirectional interface to enter the transmit data state . the baseband drives data to the pt8r2401 on the falling edge of dataclk, and the pt8r2401 reads the transmit data on the rising edge. when all the data has been transmitted, the baseband drives txdata_en and txactive low to disable the pa stage and return to the idle state . figure 2. transmit procedure timing diagram in unidirectional interface idle vco tuning tx-ramp-up tx-burst tx-ramp-down idle jtag programming txactive txdata_en txdata rxactive syncdetect rxdata dataclk hop cmd tx data t tuningtx t ramp-up t ramp-down
pt0141(06/03) ver:0 5 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| figure 3. transmit signal timing diagram in unidirectional interface dataclk(13mhz,o) txactive(i) txdata_en(i) txdata(i) rxactive(i) syncdetect(i) rxdata(o) pe sync word te heder+payload pe sync word t ramp-up t ramp-down pe : preamble te : trailer
pt0141(06/03) ver:0 6 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| receive operation in unidirectional interface the primary signal for data reception is rxactive signal. when rxactive goes to high, the rf circuitry starts to operate and send data after fixed time from rxactive. the baseband receives data and searches for the access code. during receive mode, dataclk is sent from pt8r2401 to baseband as a timing reference. the pt8r2401 circuit sends the data to baseband at the rising edge of dataclk, where the baseband latches the data at the falling edge of dataclk. prior to receiving information over air, the baseband transfers control information including the hop frequency over the jtag interfaces, and enters pt8r2401 into search access code state after fixed time to turn on receiver circuitry by driving rxactive high. in the search access code state , the baseband performs all of the tasks required to correlate with the access code from the receive data. when the baseband has correlated the access code, then it drives syncdetect high and makes pt8r2401 enter into receive payload state . during the payload, pt8r2401 eliminates any frequency offset between local and remote bluetooth devices based on its measurement during syncword acquisition. pt8r2401 transmits demodulated data to the baseband at half frequency of dataclk, which can be read by the baseband using appropriate timing recovery algorithm. the unidirectional interface is returns to the idle state with the baseband driving rxactive low after a fixed interval of t rxoff . figure 4. receiver procedure timing-diagram in unidirectional interface figure 5. receiver signal timing diagram in unidirectional interface idle vco tuning search access code rx-burst idle jtag programming txactive txdata_en txdata rxactive syncdetect rxdata dataclk hop cmd valid rx data t tuningrx t accesscode t rxon rx-on t rxoff dataclk(13mhz,o) txactive(i) txdata_en(i) txdata(i) rxactive(i) syncdetect(i) rxdata(o) pe sync word te header+payload t rxon pe : preamble te : trailer t rxoff
pt0141(06/03) ver:0 7 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| power-up sequence the power-up sequence of pt8r2401 is very simple mechanism. after power is applied to the pt8r2401, the activating reset signal into low for t reset is the only required operation. after this procedure, pt8r2401 will come into idle mode for waiting transmit or receive operation indicated by bluetooth baseband. before this normal operation, all spi register value should be initialized even though its value is set by the default value. the initialized value will be provided by pti. after activating reset signal, 13 or 16mhz baseband reference signal, dataclk will be activated until execution of external power down command through spi interface. figure 6. power-up sequence procedure timing-diagram power-off serial programming txactive txdata_en txdata rxactive syncdetect rxdata dataclk hop cmd reset power reset idle vco tuning search access code spi initialization for all registers receiver operation rx-on
pt0141(06/03) ver:0 8 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| power-down sequence the lowest operation power state of pt8r2401 is sleep state , where all clocks including rf and baseband and circuits in the pt8r2401 is placed in their minimum power mode. in this mode, the control register can be accessed through serial interface logic and retain their programmed value. to enter into sleep state , power-down command which sets power-down of clock generator including crystal buffer should be programmed through the serial interface. after power-down command, the dataclk from the pt8r2401 will stop until it comes back to idle state . to escape from sleep state , power-up command which sets power-up of clock generator should be programmed through the serial interface. after power-up command, the dataclk will start again from the pt8r2401 into external baseband. figure 7. power-down sequence procedure timing-diagram idle sleep jtag programming txactive txdata_en txdata rxactive syncdetect rxdata dataclk hop cmd reset power vco tuning transmit operation power down cmd tx-ramp-up idle power up cmd
pt0141(06/03) ver:0 9 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| power control in the pt8r2401, there are five different states with different current consumption; sleep , idle , vco active , tx active , and rx active . upon reset, the pt8r2401 stays in the idle state to wait for the command through serial programming interface from the baseband controller. in the idle state, there is dataclk from the radio to the baseband controller. in the idle mode , all rf circuits are shut down to reduce the static current consumption. only the reference clock oscillator and dataclk pump to the baseband is active. after hop set command through the serial programming, the vco will operate to lock the programmed channel frequency. owing to the signal such as rxactive or txactive, the pt8r2401 will enter into the active state such as tx active state and rx active state . in those state, all rf circuits and gfsk modem will operate and result in the maximum current consumption. in the unidirectional mode, the falling signal of rxactive or txactive will make the pt8r2401 into idle state automatically. in the bidirectional mode, the explicit command to stop receive or transmission through serial programming will make the pt8r2401 into idle state . the pt8r2401 enters into sleep state by power down command through serial programming. sleep state is the least power consumption among other states and all clocks include reference oscillator will stop the operation as well as the power down of all rf circuits. in sleep state , only the serial programming interface logic can operate which uses clock from external device. however, the value of all registers will sustain until the wake up from sleep state . following figure shows the state transition in terms of power control. figure 8. state transition diagram for power control idle state (i idle ) vco active state (i vco ) rx active state (i rx ) sleep state (i sleep ) tx active state (i tx ) hop command transmit command receive command power-down command power-up command rxactive off txactive off
pt0141(06/03) ver:0 10 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| serial programming interface (jtag interface) the serial programming interface is a jtag boundary-scan architecture compliant with ieee 1149.1. interconnection between the serial interface and external baseband consists of four 1-bit digital signals : control data input(tdi), control mode selec t (tms), control clock (tck) and control data output (tdo). you must refer to the full iee std 1149.1-1990 standard test access port and boundary-scan architecture document for a complete, definitive description of the operation of the fundamentals of the jtag interface. pt1002 support tck up to 16mhz. table 1. tap instructions instruction opcode description extest 0x000000 extest initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. extest connects the boundary-scan register between tdi and tdo in the shift_dr state only. when extext is selected, all output signal pin values are driven by values shifted into the boundary-scan register and may change only on the falling-edge of tck in the update_dr state. also, when extest is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of tck in the capture_dr state. values shifted into input latches in the boundary-scan register are never used by the processor?s internal logic. sample / preload 0x000001 sample / preload performs two functions: when the tap controller is in the capture-dr state, the sample instruction occurs on the rising edge of tck and provides a snapshot of the component?s normal operation without interfering with that normal operation. the instruction causes boundary-scan register cells associated with outputs to sample the value being driven by or to the processor. when the tap controller is in the update-dr state, the preload instruction occurs on the falling edge of tck. this instruction causes the transfer of data held in the boundary-scan cells to the slave register cells. typically the slave-latched data is then applied to the system outputs by means of the extest instruction. idcode 0x011111 idcode is used in conjunction with the device identification register. it connects the identification register between tdi and tdo in the shift_dr state. when selected, idcode parallel-loads the hard-wired identification code (32 bits) on tdo into the identification register on the rising edge of tck in the capture_dr state. note: the device identification register is not altered by data being shifted in on tdi. register programming 0x1sssss register programming instruction select the register with address indicator sssss. when the tap controller is in the capture-dr state, the register programming instruction occurs on the rising edge of tck and executes a snapshot of register addressed sssss into serial register. when the tap controller is in the update-dr state, the register programming instruction occurs on the falling edge of tck. this instruction causes the transfer of data held in serial register to register addressed sssss. bypass 0x111111 bypass instruction selects the bypass register between tdi and tdo pins while in shift_dr state, effectively bypassing the processor?s test logic. 0 is captured in the capture_dr state. while this instruction is in effect, all other test data registers have no effect on the operation of the system. test data registers with both test and system functionality perform their system functions when this instruction is selected.
pt0141(06/03) ver:0 11 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| spi register map the values of all registers except read-only are set by default values after rest. the default values can be overrided by accessing each register. typical register values are subject to change and should be obtained from pti. during normal operation, spi access should occur to address the following functions only. z programming pll hop frequency of bt_rf_pll_ctrl0 z setting tx power control value of bt_rf_tx_ctrl in the transmit mode z reading receive signal strength indication of bt_rssi_sta in the receive mode z programming txa or rxa of bt_rf_pll_ctrl1 to indicate transmit or receive mode in bidirectional interface table 2. spi register address map address name attribute description 0x00 bt_soft_reset write reset by serial interface* 0x01 bt_modem_ctrl read/write modem control register 0x02 bt_rf_rx_ctrl read/write rf receiver control register 0x03 bt_rf_tx_ctrl read/write rf transmitter control register 0x04 bt_rf_bb_ctrl0 read/write rf baseband control0 register 0x05 bt_rf_bb_ctrl1 read/write rf baseband control1 register 0x06 bt_rf_pll_ctrl0 read/write rf pll control0 register 0x07 bt_rf_pll_ctrl1 read/write rf pll control1 register 0x08 bt_rf_pll_ctrl2 read/write rf pll control2 register 0x09 bt_rf_pll_ctrl3 read/write rf pll control3 register 0x0a bt_rf_tim_ctrl0 read/write rf timing adjustment configuration0 register 0x0b bt_rf_tim_ctrl1 read/write rf timing adjustment configuration1 register 0x0c bt_rf_tim_ctrl2 read/write rf timing adjustment configuration2 register 0x0d bt_rf_tim_ctrl3 read/write rf timing adjustment configuration3 register 0x0e bt_rf_tim_ctrl4 read/write rf timing adjustment configuration4 register 0x0f bt_rf_tim_ctrl5 read/write rf timing adjustment configuration5 register 0x10 bt_rf_aux_ctrl0 read/write rf auxiliary control0 register 0x11 bt_rf_aux_ctrl1 read/write rf auxiliary control1 register 0x12 bt_rssi_sta read modem rssi register 0x13 bt_rf_sta read rf status register 0x14 bt_dac_test_ctrl read/write dac test register 0x15 bt_pwd_ctrl0 read/write modem power detector register0 0x16 bt_pwd_ctrl1 read/write modem power detector register1 0x17~0x1d - - reserved 0x1e bt_pwdn write power down register 0x1f idcode read idcode * equivalent to hardware reset by asserting reset pin.
pt0141(06/03) ver:0 12 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| * the values in all registers are the recommended initial value to be set by the serial programming interface, since some of them may be different value with the default configuration by hardware after reset. also, these value can be changed in order t o be optimized for special purpose. please contact pti semiconductor to get up-to-date configuration. 0x01 bt_modem_ctrl 1514131211109876543 2 10 cks tepm 0 01011b 0111b 0 1 1 1 00b tepm external power amp drive enable mode 00 : off 01 : on 10/11 : on during txactive is high cks reference clock select flag 0 : 13mhz 1 : 16mhz 0x02 bt_rf_rx_ctl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01b 0 01b 1000b 0b 000000b 0x03 bt_rf_tx_ctl 1514131211109876543210 os tpg tag 1 0 0111b 11111b 001b os output dataclk pad strength 0 : the driving capability of dataclk is low 1 : the driving capability of dataclk is high tpg external power amp gain control 00000b (1ma) ~ 11111b(0ma) with 32ua step tag transmission agc gain control 000b(-3db), 001b(-1.5db), 010b(0db), 011b(1.5db), 100b(3db), 101b(4.5db), 110(6db), 111(7.5db) 0x04 bt_rf_bb_ctrl0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 1 11b 0 0011b 0 0x05 bt_rf_bb_ctrl1 1514131211109876543210 0 1010b 0 111b 011b 0000b 0x06 bt_rf_pll_ctrl0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txa rxa tg ch 0 0 0111111b 0000000b txa internal txactive signal generation in bidirectional interface. writing high for more detail operation, refer to i/o description of transmit operation. this field does not affect in unidirectional interface. rxa internal rxactive signal generation in bidirectional interface. for more detail operation, refer to i/o description of receiver operation. this field does not affect in unidirectional interface. tg[6] internal pre power amp gain control with bias change 1 : gain increase, 0 : gain decrease tg[5:0] internal pre power amp gain control with driving ability 000000b(minimum gain) ~ 111111b(maximum gain) ch frequency channel selection 0000000b : 0 channel(2402mhz), 0000001b : 1 channel(2403mhz), ? 0x07 bt_rf_pll_ctrl1 1514131211109876543210 0 0 00000000 00000 0x08 bt_rf_pll_ctrl2 1514131211109876543210 0 00b 11b 001b 00b 10b 1 010b 0x09 bt_rf_pll_ctrl3 1514131211109876543210 1000000000b 00b 00b 0 0 0x0a bt_rf_tim_ctrl0 1514131211109876543210 tbd tbd tbd tbd
pt0141(06/03) ver:0 13 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 0x0b bt_rf_tim_ctrl1 1514131211109876543210 tbd tbd tbd tbd 0x0c bt_rf_tim_ctrl2 1514131211109876543210 tbd tbd tbd tbd 0x0d bt_rf_tim_ctrl3 1514131211109876543210 tbd tbd tbd tbd 0x0e bt_rf_tim_ctrl4 1514131211109876543210 tbd tbd tbd tbd 0x0f bt_rf_tim_ctrl5 1514131211109876543210 tbd tbd tbd tbd tbd tbd tbd 0x10 bt_rf_aux_ctrl0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 01b 0 1000b 1 1 000000b 0x11 bt_rf_aux_ctrl1 1514131211109876543210 pvn pvl 1 000b 01b 01b 1 0 0 0 0 100b pvn pre power amp output power detection enable 0 : disable 1 : enable pvl pre power amp power detector reference level 000b(-7dbm), 001b(-5dbm), 010b(-3dbm), 011b(-1dbm) 100b(0dbm), 101b(1dbm), 110b(2dbm), 111b(3dbm) 0x12 bt_rssi_sta 1514131211109876543210 pvo rssi_po3 rssi_rf rssi_agc pvo 1 : the current power of pre power amp is more than pvl 0 : the current power of pre power amp is less than pvl rssi_agc agc gain value with 3db step from ?3db(0000b) to 42db(1111b) 0x13 bt_pow_sta 1514131211109876543210 css 0x14 bt_dac_test_ctrl 1514131211109876543210 de daci dacq 0 000000b 000000b 0x15 bt_pwd_ctrl0 1514131211109876543210 pwd_start afs dss 10000010b 1 1 0x16 bt_pwd_ctrl1 1514131211109876543210 pbd pwr_th3 pwr_th2 pwr_th1 0 1010b 0100b 0110b 0x1e bt_ pwdn 1514131211109876543210 pd 0 pd 1 : power down mode enable 0 : power down mode disable 0x1f idcode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 idcode[31:16] 0x0000 1514131211109876543210 idcode[15:0] 0x0001
pt0141(06/03) ver:0 14 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| jtag registers programming timing diagram in unidirectional interface figure 9. serial register write programming timing diagram in jtag figure 10. serial register read programming timing diagram in jtag 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ?. 28 29 30 31 0 a0 a1 a2 a3 a4 tck tms tdi a0 a1 a2 a3 a4 a5 tdo h d0 d1 d2 d3 d4 d5 d6 d7 high-z d8 d9 ?. d14 d15 don?t care q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 ?. q14 q15 update register value of phy 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ?.. 29 30 31 32 0 a0 a1 a2 a3 a4 tck tms tdi a0 a1 a2 a3 a4 a5 tdo h q0 q1 q2 q3 q4 q5 q6 q7 high-z q8 ?.. q14 q15 don?t care ?.. q15 x q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 x update register value of bb
pt0141(06/03) ver:0 15 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| electrical specifications absolute maximum rating parameter symbol test condition min typ max unit storage temperature -40 85 c ambient temperature with power applied -20 65 c supply voltage (no damage) 0.8 3.9 v dc input voltage -0.3 vcc +0.3 v dc voltage applied to outputs in high-z state -0.3 vcc +0.3 v digital inputs vcc ? 0.4v vcc+0. 4v v static discharge voltage (digital) 1 2000 v static discharge voltage (rf) 1 500 v latch-up current -200 200 ma note: rating measured using the human body model (hbm). recommended operating conditions parameter symbol test condition min typ max unit supply voltage vcc2.7 2.7 v vcc3.3 3.3 v temperature 0 40 c humidity 95 % dc/ac specification power consumption parameter symbol test condition min typ max unit radio transmit current dh1 pakaet with prbs9 payload, no hops 60 ma radio receive current dh1 pakaet with prbs9 payload, no hops 60 ma radio transmit peak current dh1 pakaet with prbs9 payload, 1.6k hops 70 ma radio receive peak current dh1 pakaet with prbs9 payload, 1.6k hops 70 ma idle current tx and rx no active 20 ma deep sleep current deep sleep mode 20 ua
pt0141(06/03) ver:0 16 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| common radio specifications parameter symbol test condition min typ max unit operating frequency f = (2.402 + k) ghz, k = 0,1,2, ? 78 2402 2480 mhz channel intervals 1mhz channel number of channels 79 duplexing slot time transmission scheme tdd ? time division duplex 625 us symbol rate 1m symbol /s modulation data polarity ? h ? fc +df ? l ? fc ? df hop rate 1600 hops/s ec antenna interface output impedance 50 ohm radio receiver specifications parameter symbol test condition min typ max unit sensitivity 0.1% ber dh1 pakaet with prbs9 payload,no hops, at 2402,2441,2480 mhz -85 -80 dbm maximum received signal 0.1% ber dh1 pakaet with prbs9 payload,no hops, at 2402,2441,2480 mhz -20 -5.0 dbm self channel selectivity c/i co-channel (1) 9 11 dbc adjacent channel selectivity c/i 1mhz (1) -2.0 0 dbc 2 nd adjacent channel selectivity c/i 2mhz (1) -34 -30 3 rd adjacent channel selectivity c/i 3mhz (1) (2) -43 -40 image rejection c/i (1) (3) -12 -9 maximum level of intermodulation interferes (1) (4) -39 -30 dbm maximum level of gsm signal at 1.8ghz 0.1% ber with wanted input at ? 67dbm, and with the rf filter removed from the circuit, dh1 pakaet with prbs9 payload, 1.6k hops -7.0 dbm maximum level of w-cdma signal at 1.8ghz -9.5 maximum level of w-cdma signal at 2.2ghz -11 dbm
pt0141(06/03) ver:0 17 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| radio transmitter specifications parameter symbol test condition min typ max unit rf transmit power level dh1 pakaet with prbs9 payload,no hops, single slot packets, at 2402,2441,2480 mhz dbm rf power control range dh1 pakaet with prbs9 payload,no hops, single slot packe, at 2441 mhz 16 30 db rf power range control resolution 2.0 20 db bandwidth for modulated carrier dh1 pakaet with prbs9 payload,no hops, single slot packets, at 2402,2480 mhz 900 1000 khz initial carrier freq tolerance dh1 pakaet with prbs9 payload, no hops, single slot packe, at 2441 mhz +/- 25 +/- 75 khz frequency deviation single slot, continue 101010 pattern, 11110000 pattern, at 2441 mhz 90 175 khz zero crossing error single slot, continue 101010 pattern, 11110000 pattern, at 2441 mhz -125 125 ns 2 nd adjacent channel transmit power second channel power ( 2 mhz), dh1 pakaet with prbs9 payload,no hops, single slot packets at 2441 mhz -52 -20 dbm >3 rd adjacent channel transmit power third channel power (>3 mhz), dh1 pakaet with prbs9 payload,no hops, single slot packets, at 2441 mhz -57 -40 dbm non-harmonically related spurious 30 mhz ? 12.75 ghz at 2441 mhz ? 57 dbm 2 nd harmonic spurious at 2441 mhz -26 dbm 3 rd harmonic spurious at 2441 mhz -30 dbm 4 th harmonic spurious at 2441 mhz -37 dbm notes: (1) measured according to the bluetooth specification. (2) up to five spurious responses within bluetooth limits are allowed (3) at carrier ? 3mhz. (4) measured at f1 ? f2 = 5mhz. (5) for 0.1% ber with wanted input at ? 67dbm, and with the rf filter removed from the circuit.
pt0141(06/03) ver:0 18 preliminary data sheet PT8R2401MD 2.4ghz rf module ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| notes pericom pericom pericom pericom technology inc. technology inc. technology inc. technology inc. email: support@pti.com.cn web site: www.pti.com.cn, www.pti-ic.com china : no. 20 building, 3/f, 481 guiping road, shanghai, 200233, china tel: (86)-21-6485 0576 fax: (86)-21-6485 2181 asia pacific : unit 1517, 15/f, chevalier commercial centre, 8 wang hoi rd, kowloon bay, hongkong tel: (852)-2243 3660 fax: (852)- 2243 3667 u.s.a. : 2380 bering drive, san jose, california 95131, usa tel: (1)-408-435 0800 fax: (1)-408-435 1100 pericom technology incorporation reserves the right to make changes to its products or specifications at any time, without noti ce, in order to improve design or performance and to supply the best possible product. pericom technology does not assume any responsibility for use of any ci rcuitry described other than the circuitry embodied in pericom technology product. the company makes no representations that circuitry described herein is f ree from patent infringement or other rights, of pericom technology incorporation.

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