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| pq2fads-vr-um revision 0.0 june 12, 2003 pq2fads-vr user?s manual user?s manual ? motorola, inc., 2003 pq2fads-vr user?s manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pq2fads-vr - revision 0.0 user?s manual motorola important notice to users while every effort has been made to ensure the accuracy of all information in this document, motorola assumes no liability to any party for any loss or damage caused by errors or omissions or by statements of any kind in this document, its updates, supplements, or special editions, whether such errors are omissions or statements resulting from negligence, accident, or any other cause. motorola further assumes no liability arising out of the application or use of any information, product, or system described herein: nor any liability for incidental or consequential damages arising from the use of this document. motorola disclaims all warranties regarding the information contained herein, whether expressed, implied, or statutory, including implied warranties of merchantability or fitness for a particular purpose . motorola makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights, nor do the descriptions contained herein imply the granting or license to make, use or sell equipment constructed in accordance with this description. trademarks this document includes these trademarks: motorola and the motorola logo are registered trademarks of motorola, inc. motorola, inc., is an equal opportunity / affirmative action employer. for an electronic copy of this book, visit motorola?s web site at http://e-www.motorola.com/ ? motorola, inc., 2003; all rights reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents motorola pq2fads-vr user manual i table of contents section 1 general information 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 definitions, acronyms, and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 pq2fads-vr features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 section 2 hardware preparation and installation 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 unpacking instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 hardware preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 setting vddl level range - p26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.2 setting vddl supply voltage level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.3 setting modck(1:3) for plls multiplication factor - sw5 (#6 - #8) . . . . . . . . 8 2.3.4 setting hard - reset configuration source - jp7 . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.5 setting boot source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.6 setting modckh(0:3) - for plls multiplication factors . . . . . . . . . . . . . . . . . 11 2.3.7 setting pci_modck - for pci bus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.8 setting pci_arbiter - for pci mode enabled . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.9 setting pci_dll - for pci mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.10 60x bus parity support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.11 clock-in source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.12 fcc2 ethernet port mode - mii/rmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.13 fcc3 ethernet port mode - mii/rmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.14 usb speed selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.15 usb mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.16 cop/jtag connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.17 power on/off switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 installation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 host controlled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 stand alone operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.3 cop/jtag connector - p16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.4 terminal to pq2fads-vr rs-232 connection . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.5 10/100-base-t ethernet ports connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.6 memory installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents ii pq2fads-vr user manual motorola 2.4.6.1 flash memory simm installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 section 3 operating instructions 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 controls and indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 power-on reset switch - sw1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 abort switch - sw3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 soft reset switch - sw2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.4 hard reset - switches - sw2 & sw3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.5 sw6 - reset configuration switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.6 sw7 - software options switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.7 p26 - vddl voltage level range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.8 jp12 - iddl measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.9 jp6 - thermal sense connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.10 jp11 - iddh measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.11 jp13 - vpp source selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.12 gnd bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.13 power o.k. indicator - ld1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.14 12v indicator - ld2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.15 utopia 16 bit indicator - ld15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.16 utopia multi phy indicator - ld16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.17 5v indicator - ld3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.18 3.3v indicator - ld4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.19 usb power indicator - ld17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.20 -12v indicator - ld5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.21 run indicator - ld6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.22 atm on - ld7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.23 fast ethernet port 2 enabled - ld10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.24 fast ethernet port 1 enabled - ld8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.25 rs232 port 1 on - ld11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.26 fast ethernet port 1 full duplex indicator - ld18 . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.27 rs232 port 2 on - ld12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.28 fast ethernet port 1 100base-tx indicator - ld19 . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.29 ethernet port 1 tx/rx indicator - ld20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.30 general purpose led 2 indicator - ld13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.31 ethernet port 1 link indicator - ld21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.32 fast ethernet port 2 full duplex indicator - ld22 . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.33 general purpose led 1 indicator - ld14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.34 fast ethernet port 2 100base-tx indicator - ld23 . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.35 usb enabled indicator - ld9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.36 ethernet port 2 link indicator - ld24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.37 ethernet port 2 tx/rx indicator - ld25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.38 vddl indication - ld26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents motorola pq2fads-vr user manual iii 3.2.39 parallel port connection - ld27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.40 external debugger connection indicator - ld28 . . . . . . . . . . . . . . . . . . . . . . . . 23 section 4 functional description 4.1 reset & reset - configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 power - on resetpq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1.1 power - on reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.2 hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 4.1.2.1 cop/jtag port hard - reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2.2 manual hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2.3 internal sources hard - reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2.4 hard reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.3 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.3.1 cop/jtag port soft - reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.3.2 manual soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.3.3 internal sources soft - reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.4 pci bus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 local interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.1 abort interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 atm uni interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.3 fast ethernet phy interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.4 pci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.1 pq2 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.2 pci clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 4.4 bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.1 single pq2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.2 60x bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5 buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6 chip - select generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 synchronous dram (60x bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7.1 sdram programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.7.2 sdram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.7.3 l2-cache support influence on sdram design . . . . . . . . . . . . . . . . . . . . . . . 41 4.7.4 sdram error correction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.8 flash memory simm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.8.1 flash programming voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.8.2 flash and l2cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.9 e2prom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 4.10 pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.11 l2-cache support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.11.1 l2 cache configuration & control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.12 communication ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents iv pq2fads-vr user manual motorola 4.12.1 atm port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 4.12.2 100/10 base - t ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.12.2.1 dm9161 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.12.3 rs232 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.12.3.1 rs-232 ports? signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.12.4 usb port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.12.5 pc parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.13 board control & status register - bcsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.13.1 bcsr0 - board control - status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.13.2 bcsr1 - board control - status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.13.3 bcsr2 - board control - status register - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.13.4 bcsr3 - board control - status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.13.5 bcsr4 - board control - status register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.13.6 bcsr5 and bcsr7- board control - status register 3 & 5 . . . . . . . . . . . . . . . 60 4.14 cop/jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 section 5 memory map and initialization 5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 pq2 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2.1 system initializations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.2 memory controller registers programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 section 6 physical properties 6.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1.1 5v rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.2 3.3v rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.3 5v stand by rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.4 vddh rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.5 vddl bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.6 12v rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.7 -12v rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.1 atx power connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.2 fast ethernet port connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.3 atm 155 port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.4 rs232 ports connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.5 cpm expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.6 cop/jtag port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.7 logic analyzer connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2.8 mach?s in system programming (isp) connector . . . . . . . . . . . . . . . . . . . . . . . 78 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents motorola pq2fads-vr user manual v 6.2.9 pci connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2.10 system expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2.11 usb connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2.12 parallel port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 section 7 support information 7.1 interconnect signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1.1 p1 - rs232 ports 1 and 2 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1.2 p3 and p4 - 100/10 - base-t ethernet port connector . . . . . . . . . . . . . . . . . . . . 80 7.1.3 p16 - cop / jtag connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.1.4 p7 - cpm expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.1.5 p9, p10, p11, p15, p17, p18, p19, p24, p28,p29, p30- logic analyzer mictor connectors 88 7.1.6 p10, p8, p9 - pci connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1.7 p5 - atx power supply connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.1.8 p21,p23,p25 - mach/lattice isp connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.1.9 p27 - system expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.1.10 p2 - usb connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2 programmable logic equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.1 u35 - bcsr code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.2 u41 - power switch debounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.3 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents vi pq2fads-vr user manual motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables motorola pq2fads-vr user manual vii list of tables 1-1 pq2fads-vr specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2-1 . modck(1:3) encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4-1 bcsr/flash hard reset configuration word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4-2 e2prom hard reset configuration word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4-3 pci interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4-4 pci interrupt mask register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4-5 pq2fads-vr chip select assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4-6 100 mhz sdram mode register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4-7 l2 cache cfg(0:2) settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4-8 bcsr0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4-9 bcsr1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4-10 bcsr2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4-11 flash presence detect (7:5) encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4-12 flash presence detect (4:1) encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4-13 extooli(0:3) assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4-14 pq2 board version encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-15 pq2 board revision encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-16 external tool revision encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-17 l2 cache size encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-18 bcsr3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4-20 pci board present signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4-19 bcsr4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4-21 bcsr5 to bcsr7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4-22 cop/jtag port signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5-1 pq2fads-vr memory map - flash (or bcsr) as boot device . . . . . . . . . . . . 64 5-2 pq2fads-vr memory map - e2prom as boot device . . . . . . . . . . . . . . . . . . . . 66 5-3 bcsr/flash power on reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-4 e2prom power on reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-5 siu registers? programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5-6 memory controller initializations for 100mhz - flash as boot device . . . . . . . . 71 5-7 memory controller initializations for 100mhz - e2prom as boot device . . . . . . 72 5-8 memory controller initializations for 100mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6-1 expansion connectors maximum current consumption . . . . . . . . . . . . . . . . . . . . . 75 6-2 maximum power consumption per add-in card . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7-1 p1 connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-2 p3,p4 - 100/10 base-t ethernet connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-3 p16 - cop/jtag connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-4 p7 - cpm expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7-5 p12, p13, p14 - pci connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7-6 p5 - atx power supply connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables viii pq2fads-vr user manual motorola 7-7 p25 - lattice isp connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-8 p27 - system expansion connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-9 p2 - usb connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-10 pq2fads-vr bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures ix pq2fads-vr user manual motorola list of figures 1-1pq2fads-vr block diagram 5 ix 2-1pq2fads-vr top side part location diagram 7 ix 2-2vddl range selection - p26 7 ix 2-3vddl trimmer - rp2 8 ix 2-4sw5 description 9 ix 2-5hard reset configuration source selection - jp7 10 ix 2-6sw6 description 11 ix 2-7jp10 - 60x parity support selection 12 ix 2-8clock source selection 12 ix 2-9fcc2 ethernet mode selection 13 ix 2-10fcc3 ethernet mode selection 13 ix 2-11host controlled operation scheme - command converter 14 ix 2-12host controlled operation scheme - parallel port 15 ix 2-13stand alone configuration 15 ix 2-14p16 - cop/jtag port connector 16 ix 2-15p1a/p1b - rs232 serial port connector 16 ix 2-16flash memory simm insertion 17 ix 3-1sw7 - description 19 ix 3-2jp6 - therm connector 20 ix 3-3jp13 - vpp source selection 20 ix 4-1pci host configuration registers 31 ix 4-2pci interrupt routing scheme 33 ix 4-3main clock generator scheme 36 ix 4-4pci clock generator scheme 37 ix 4-560x sdram connection scheme - no l2 cache 40 ix 4-6sdram - 60x bus connection scheme with l2 cache 40 ix 4-760x sdram data parity support 42 ix 4-8flash simm connection scheme 44 ix 4-9e2prom connection scheme 46 ix 4-10pci bus scheme 47 ix 4-11rs232 serial ports connector 51 ix 4-12debug station connection schemes 61 ix 4-13cop/jtag port connector 62 ix 6-1pq2fads-vr power scheme 75 ix 1-1 pq2fads-vr block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2-1 pq2fads-vr top side part location diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-2 vddl range selection - p26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-3 vddl trimmer - rp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-4 sw5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-5 hard reset configuration source selection - jp7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures x pq2fads-vr user manual motorola 2-6 sw6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2-7 jp10 - 60x parity support selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2-8 clock source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2-9 fcc2 ethernet mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2-10 fcc3 ethernet mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2-11 host controlled operation scheme - command converter . . . . . . . . . . . . . . . . . . . 14 2-12 host controlled operation scheme - parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2-13 stand alone configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2-14 p16 - cop/jtag port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-15 p1a/p1b - rs232 serial port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-16 flash memory simm insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3-1 sw7 - description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3-2 jp6 - therm connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3-3 jp13 - vpp source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4-1 pci host configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4-2 pci interrupt routing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4-3 main clock generator scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4-4 pci clock generator scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4-5 60x sdram connection scheme - no l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4-6 sdram - 60x bus connection scheme with l2 cache . . . . . . . . . . . . . . . . . . . . . . 40 4-7 60x sdram data parity support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4-8 flash simm connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4-9 e2prom connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4-10 pci bus scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4-11 rs232 serial ports connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4-12 debug station connection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4-13 cop/jtag port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6-1 pq2fads-vr power scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola pq2fads-vr user?s manual 1 1 general information 1.1 introduction this document is an operation guide for the pq2fads-vr board. it contains operational, functional and general information about the pq2fads-vr. this board is meant to serve as a platform for s/w and h/w development for the power quicc ii family of processors in a tepbga package (516 pins for hip4 and hip7). using its on-board resources and a debugger, a developer is able to download code, run it, set breakpoints, display memory and registers and connect proprietary h/w via the expansion connectors, to be incorporated into a desired system with the power quicc ii processors. this board could also be used as a demonstration tool (i.e., application s/w may be programmed 1 into its flash memory and ran in exhibitions etc.). 1. either on or off-board. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general information 2 pq2fads-vr user?s manual motorola 1.2 definitions, acronyms, and abbreviations 1.3 related documentation mpc8260, mpc8250, mpc8275 - user?s manual. vads users? manual. pmc-sierra 5384 long form data sheet dm9161 (by davicom) data sheet pq2fads-vr powerquicc ii family ads board for tepbga package (516 pins in a plastic package) pq2 powerquicc 2 mpc8250 powerquicc 2 hip4 in tepbga package mpc8275 powerquicc 2 hip7 in tepbga package voyager mpc8260 - powerquicc 2 ppc powerpc pci peripheral components interconnect usb universal serial bus cpm communication processor module sdram synchronous dynamic random access memory vads voyager application development system kbyte 1024 bytes lsb least significant byte lsb least significant bit mbyte 1048576 bytes dimm dual in-line memory module simm single in-line memory module tbd to be defined upm user programmable machine evb evaluation board gpcm general purpose chip-select machine gpl general purpose line bcsr board control and status register flash non volatile reprogrammable memory. zif zero input force bga ball grid array adi application development interface. cop common on-chip processor sar segmentation and reassembly utopia universal test & operations interface for atm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general information motorola pq2fads-vr user?s manual 3 1.4 specifications the pq2fads-vr specifications are given in table 1-1. 1.5 pq2fads-vr features supports mpc8250 (hip4) and mpc8275 (hip7) processors. 64 bit powerquicc ii communication processor, running @ up to 100mhz external bus frequency. 32 mbyte synchronous dram (soldered on-board), residing on 60x bus (pbi mode) with optional parity support, controlled by sdram machine 1. optional address latch - multiplexer is available if l2 cache module is assembled. optional 1/2 mbyte l2-cache on-board using 2 mpc2605 look-aside cache modules. 8 mbyte, 80 pin flash simm, buffered from 60x bus. support for upto 32 mbyte, controlled by gpcm, 5v/12v programmable, with automatic flash simm identification, via bcsr. support for both on and off simm flash reset. table 1-1. pq2fads-vr specifications characteristics specifications power requirements (no other boards attached) +5vdc @ tbd a (typ.), tbd a (max.) +3.3vdc @ tbd a (typ.), tbd a (max.) +12vdc - @tbd a max. -12vdc - @tbd a max. microprocessor mpc8250 running @ 66 mhz bus clock frequency. mpc8275 running @ up to 100 mhz bus clock frequency. addressing total address range on ppc bus: total address range on local bus: flash memory simm (ppc bus) synchronous dynamic ram dimm (ppc bus) synchronous dram on local bus 4 giga bytes (32 address lines) 256 kbytes external (18 address lines) 4 giga bytes internal (32 address lines internal decoding) 8 mbyte, 32 bits wide expandable to 32 mbytes 32 mbyte, 64 bits wide with optional parity. 8 mbytes, 32 bit wide with optional parity. operating temperature 0 o c - 70 o c (room temperature) storage temperature -25 o c to 85 o c relative humidity 5% to 90% (non-condensing) dimensions: length width thickness 12" (305 mm) 9" (229 mm) 0.063" (1.6 mm) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general information 4 pq2fads-vr user?s manual motorola 5v/12v vpp (in-circuit programming voltage) for flash simm - jumper selectable. 8 kbytes e 2 prom, buffered from the 60x bus, controlled by the gpcm. board control & status register - bcsr, controlling boards? operation. on-board cop/jtag connector. on-board logic to support direct connection to standard parallel port (epp/spp modes) in desk top pc for debug purposes using metrowerks codewarrior tools. power-on reset option via jtag. programmable power-on reset and hard-reset configuration via e 2 prom or via flash memory for the pq2 core. pci local bus is pci standard 2.2 compliant. 3 pci slots are available to host up to 3 masters/targets cards @ 3.3v only - arbitration is supported by the on-chip arbiter. pci bus supports 25 - 66 mhz @ 3.3v devices (determined by the user). simple generic interrupt controller to handle the pci interrupts (4 in each pci slot). module enable indications for all on-board modules. high density (mictor) logic analyzer connectors, carrying all 60x, local bus and cpm signals, for fast logic analyzer connection. 155 mbps atm uni on fcc1 with optical i/f, connected to the pq2 via utopia level 2 i/f supporting 8/16 bit in single/multi phy, using the pmc-siera 5384. two 100/10-base-t ports on fcc2 and fcc3 with t.p. i/f, mii/rmii controlled, using davicom dm9161. usb port, usb 1.1 standard compliant, using philips pdiusbp11 usb transceiver. usb port is with shutdown option and speed selectable - bcsr controlled. dual rs232 port residing on scc1 & scc2. module disable (i.e., low-power mode) option for all communication transceivers -bcsr controlled, enabling use of communication ports, off-board via the expansion connectors. dedicated pq2 communication ports expansion connectors for convenient tools? connection, carrying also necessary bus signals, for transceivers? m/p i/f connection. use is done with 2 x 128 pin din 41612 receptacle connectors. external tools? identification & status read capability, via bcsr. separate power-on reset push - button, soft / hard 1 reset push - button and abort push - button. atx power supply. multi-range pq2 internal logic operation voltage - selectable by jumper between three ranges - 1.3v to 1.7v for mpc8275 (hip7), 1.7v to 1.9v for pq2 (hip4) or 2.3v to 2.7v. software option switch provides 8 s/w options via bcsr. 1. hard reset is applied by depressing both soft reset & abort buttons. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general information motorola pq2fads-vr user?s manual 5 figure 1-1. pq2fads-vr block diagram flash simm. 8 - 32mbyte l2-cache 512k data transceivers & address latches r s 2 3 2 p o r t # 2 reset, interrupts control & status register jtag dm9161 1 0 0 / 1 0 - b a s e - t sdram 32 mbytes magnetics d-9 rj45-8 atm-155 optical pm5384 60x bus add. 60x bus 60x bus (buffered) 64 - bit 64 - bit 32 - bit scc2 fcc2 fcc1 cpm cpm din 41612 3.3v 3.3v 3.3v 3.3v 5v 3.3v<->5v 3.3v maxim 60x bus data. pq2 buffered system bus 0 ? res. latch-mux optional optional 60x bus pci slot 33/66mhz 3.3v pci slot 33/66mhz 3.3v pci slot 33/66mhz 3.3v pci bus cpm main clock clkin1 60x bus mictors logic analyzer r s 2 3 2 p o r t # 1 d-9 scc1 mictors logic analyzer 3.3v e 2 prom 8kbyte 8 - bit dm9161 magnetics rj45-8 3.3v fcc3 expansion pdiusbp11 usb port scc4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 pq2fads-vr user?s manual motorola 2 hardware preparation and installation 2.1 introduction this chapter provides unpacking instructions, hardware preparation, and installation instructions for the pq2fads-vr. 2.2 unpacking instructions note: if the shipping carton is damaged upon receipt, request carrier?s agent to be present during unpacking and inspection of equipment. unpack equipment from shipping carton. refer to packing list and verify that all items are present. save packing material for storing and reshipping of equipment. caution avoid touching areas of integrated circuitry; static discharge can damage circuits. 2.3 hardware preparation to select the desired configuration and ensure proper operation of the pq2fads-vr board, changes of the dip-switch settings may be required before installation. the location of the switches, indicators, dip-switches, and connectors is illustrated in figure 2-1. . the board has been factory tested and is shipped with dip-switch settings as described in the following paragraphs. parameters can be changed for the following conditions: pq2?s internal logic supply level range via connector p26. pq2?s internal logic supply level within range (vddl) via potentiometer rp2. pq2?s modck(1:3). determining core?s and cpm?s plls multiplication factor via dip- switches sw5(#6 - #8). pq2?s hard reset configuration word source - bcsr or memory (flash/eeprom) - via f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 7 jumper jp7. pq2?s boot code source - eeprom/flash - via dip-switch sw6(1). pq2?s modckh(0:3) via sw5(1-4). pq2?s pci_modck via sw5(5). pq2?s pci_arbiter via sw6(2). pq2?s pci_dll via sw6(3). pq2?s 60x bus parity support on/off - via jumper jp10. clock-in source - external or on-board clock oscillator - jp9. fcc2 and fcc3 mii/rmii modes - via jumpers jp2 and jp3 respectively. usb speed (12mbits/s or 1.5mbits/s) and mode (host or slave) - software controlled in bcsr. pq2?s cop/jtag connection - cop/jtag connector (p16) or direct connection to pc parallel port (p31) - selected automatically by connecting parallel cable. atx power supply on/off switch - via sw4. figure 2-1. pq2fads-vr top side part location diagram 2.3.1 setting vddl level range - p26 to support all revisions of the pq2, provisions are taken to provide necessary voltage levels on vddl, to match the process by which the pq2 is manufactured. via p26, four voltage level ranges are provided (p26 setting options are shown in figure 2-2. ): 1. when a jumper is placed between positions 1 - 2 of p26, a level range of 2.3v to 2.7v on vddl is selected. this level matches the specification for the mpc8260 (hip3). 2. when a jumper is placed between positions 3 - 4 of p26, a level range of 1.7v to 1.9v on vddl is selected. this level matches the specification for the mpc8250 (hip4). 3. when a jumper is placed between positions 5 - 6 of p26, a level range of 1.3v to 1.7v is selected for vddl. this level matches the specification for the mpc8275 (hip7). 4. when a jumper is misplaced for p26, a level range of 1.8v to 2.0v is selected for vddl. . figure 2-2. vddl range selection - p26 3 p26 2 1 p26 p26 2.3v - 2.7v 1.7v - 1.9v 1.3v - 1.7v 4 6 5 3 2 1 4 6 5 3 2 1 4 6 5 p26 1.8v - 2.0v 3 2 1 4 6 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation 8 pq2fads-vr user?s manual motorola warning p26 is factory set according to the revision of pq2 with which it is assembled. prior to chang- ing a pq2 device, extra care should be taken with p26 setup. if a selected voltage range is above the specification for the newly inserted pq2, permanent damage might be inflicted to the device. p26 selects only a range of voltage levels on vddl. the actual level is selected by rp2. see next paragraph. 2.3.2 setting vddl supply voltage level after vddl?s voltage level range is selected via p26, the actual level of vddl is tuned via rp2. vddl may be measured upon jp12, using a dvm or any other high input impedance voltage measuring device. vddl level is factory set at the mid-range for the appropriate level range, but may be changed via rp2. rotating rp2 ccw will increase vddl voltage up to range-high, while rotating it cw, will decrease vddl down to range-low. ld26 provides visual indication for vddl level, it illuminates brighter with rise of vddl. vddl change vs. rp2?s rotation direction is shown in figure 2-3. : figure 2-3. vddl trimmer - rp2 warning while in higher ranges of vddl and higher rang- es of internal operation frequencies, the pq2 might require some sort of cooling measures to be taken. failure in doing so, might result in permanent damage inflicted to the pq2. 2.3.3 setting modck(1:3) for plls multiplication factor - sw5 (#6 - #8) after (1k cycles) the negation of the power on reset signal, the pq2 samples the 7 modck low high rp2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 9 lines - the lower 3 on modck(1-3) and the upper four - modckh(0:3) field, to establish the multiplication factors of the cpm?s and core?s plls. the levels on modck(1:3) lines are set using sw5 , switches #6 - #8 . when an individual switch is at the off position its associated modck line is pulled- high (?1?), while when at the on position, the associated modck is pulled- down (?0?). sw5 is shown in figure 2-4. , while the various combinations for sw5 (#6 - #8) and their associated modck(1:3) values are shown in table 2-1. . . figure 2-4. sw5 description table 2-1. . modck(1:3) encoding modck(1:3) switch 6 switch 7 switch 8 0on on on 1on on off 2on off on 3on off off 4 off on on 5off on off 6off off on 7 off off off sw5 on 1 2 3 4 modck3 modck2 modck1 modck1 modck2 modck3 5 6 7 8 modckh3 modckh2 modckh1 modckh2 modckh3 pci_modck modckh0 modckh1 modckh0 factory set pci_modck 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation 10 pq2fads-vr user?s manual motorola 2.3.4 setting hard - reset configuration source - jp7 the boot sequence which starts when hreset is asserted, may be from two sources: 1. bcsr (default hard-reset configuration word - cs0 is assumed to be assigned to the flash) 2. memories (flash/eeprom - user controlled hard-reset configuration word) when a jumper is placed between positions 1 - 2 of jp7, the hard reset configuration source is a memory (flash/eeprom) as configured by switch sw6-1. when a jumper is set between positions 2 - 3 of jp7, the hard reset configuration source is the bcsr. see figure 2-5. . figure 2-5. hard reset configuration source selection - jp7 2.3.5 setting boot source the hard - reset configuration word 1 , read by the pq2 while hreset is asserted, may be taken from three sources: 1. flash memory simm 2. eeprom 3. bcsr for additional information as for the contents of the hard-reset configuration word see 4.1.2.4 "hard reset configuration" on page 26. sw6#1 actually assigns cs0 to the flash (default when booting from the bcsr) or to the eeprom. when sw6 #1 is off , the hard reset configuration word is taken from eeprom , 1.in fact 8 hard-reset configuration words are read by a configuration master, however only the first is rel- evant for a single pq2. jp7 jp7 123 123 bcsr is hard reset flash/eeprom is hard reset factory setup configuration source configuration source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 11 when it is on , the hard reset configuration word is taken from the flash simm . see figure 2-6. . figure 2-6. sw6 description 2.3.6 setting modckh(0:3) - for plls multiplication factors since the pci mode in the pq2 (hip4 and hip7) is enabled, the modckh(0:3) lines are taken from sw5(#1 - #4) and the modckh(0:3) bits in the hard reset configuration word are ignored. sw5(#1 - #4) set the upper 4 bits of the modck field during hard reset configuration acquisition. when an individual switch of sw4 #1 - #4 is at the off position, its corresponding modckh line is pulled- high (?1?) during hard reset, while when at the on position, pulled- down (?0?) (see figure 2-4. ). 2.3.7 setting pci_modck - for pci bus clock the settings of this line, determines the frequency of the pci bus (when the pq2 is in pci mode). when pci_modck is set low, the pci bus frequency is set by the modck lines. when set high, the pci bus frequency is half of what is set by the modck lines. when switch sw6 #5 is at the off position, its corresponding pci_modck line is pulled- high (?1? - enabled), while when at the on position, pulled- down (?0 - disabled?) (see figure 2-4. ). 2.3.8 setting pci_arbiter - for pci mode enabled the settings of this line, determines the operation of the pci arbiter (when the pq2 is in pci mode). when pci_arbiter is set low, the pci arbiter in the pq2 is enabled. when set high, the pci arbiter is disabled and an external arbiter can be used. when switch sw6 #2 is at the off position, its corresponding pci_arbiter line is pulled- high (?1? - disabled), while when at the on position, pulled- down (?0? - enabled) (see figure 2-6. ). 2.3.9 setting pci_dll - for pci mode enabled the settings of this line, determines the operation of the dll for pci mode enabled. when pci mode is enabled, the dll must be enabled. when pci_dll is set low, the dll is disabled. when set high, the dll is enabled. when switch sw6 #3 is at the off position, its corresponding pci_dll line is pulled- high (?1? - enabled ), while when at the on position, pulled- down (?0? - disabled ) (see figure 2-6. ). sw6 on 1 2 3 4 pci_dll (on) pci_arbiter (off) eeprom boot flash boot pci_arbiter (on) pci_dll (off) pci config 3 pci config 3 factory set 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation 12 pq2fads-vr user?s manual motorola 2.3.10 60x bus parity support error correction (parity) on the 60x bus transactions is optional by setting jp10. since the 8 data parity pins are muxed with other functions, bus mux is used to connect the data parity pins to the sdram device. when a jumper is placed between positions 1 - 2 of jp10, the 60x parity support is disabled . when a jumper is placed between positions 2 ? 3 of jp10, the 60x parity support is enabled . see figure 2-7. figure 2-7. jp10 - 60x parity support selection 2.3.11 clock-in source selection the main clock source can be selected between an external (off-board) source by connecting to p22 or an on-board clock oscilator. the selection is done by setting jp11. when a jumper is placed between positions 1 - 2 of jp9, the external clock source is enabled . when a jumper is placed between positions 2 ? 3 of jp9, the on-board clock oscilator is enabled . see figure 2-8. . figure 2-8. clock source selection 2.3.12 fcc2 ethernet port mode - mii/rmii the ethernet phy on fcc2 is set by default to 100base-tx full duplex and can be configured to operate in mii or rmii interface. the selection is done by setting jp2. when a jumper is placed between positions 1 - 2 of jp2, the mii interface is enabled . when a jumper is placed between positions 2 ? 3 of jp2, the rmii interface is enabled . see figure 2-9. jp10 jp10 123 123 60x parity disabled 60x parity enabled factory setup jp9 jp9 123 123 external clock on-board clock oscilator factory setup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 13 figure 2-9. fcc2 ethernet mode selection note: for the mode change to take place, the setting of jp2 should be done while the board is powered-off. 2.3.13 fcc3 ethernet port mode - mii/rmii the ethernet phy on fcc3 is set by default to 100base-tx full duplex and can be configured to operate in mii or rmii interface. the selection is done by setting jp3. when a jumper is placed between positions 1 - 2 of jp3, the mii interface is enabled . when a jumper is placed between positions 2 ? 3 of jp3, the rmii interface is enabled . see figure 2-10. figure 2-10. fcc3 ethernet mode selection note: for the mode change to take place, the setting of jp3 should be done while the board is powered-off. 2.3.14 usb speed selection the usb port supports two speeds - 12mbits/s and 1.5mbits/s. the selection is software controlled in the bcsr. at power-up, the default selection is 12mbits/s . 2.3.15 usb mode selection the usb port supports two modes - host and slave. the selection is software controlled in the bcsr. at power-up, the default selection is host . 2.3.16 cop/jtag connection there are two options to connect to the cop port of the pq2 - cop/jtag connector or a parallel port (of a pc). the cop/jtag connector requires a command converter while the second option jp2 jp2 123 123 mii mode rmii mode factory setup jp3 jp3 123 123 mii mode rmii mode factory setup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation 14 pq2fads-vr user?s manual motorola connects directly to the parallel port of a pc and eliminates the need for one. the selection is done automaticaly - if a cable is connected to the parallel port in a pc then this connection has the priority over the cop/jtag connector. 2.3.17 power on/off switch the power-on or off is done by switching sw4. 2.4 installation instructions when the pq2fads-vr has been configured as desired by the user, it can be installed according to the required working environment as follows: host controlled operation stand-alone 2.4.1 host controlled operation in this configuration the pq2fads-vr is controlled by a host computer via the cop port, which is a subset of the jtag port. this configuration allows for extensive debugging using on-host debugger. there are two options to connect to the cop port: 1. the host is connected to the board by a cop controller (command converter) provided by a third party. figure 2-11. host controlled operation scheme - command converter 2. the host is connected to the board directly from the host?s parallel port. atx power supply 16 wire flat cable host computer media2cop media i/f media p16 p5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 15 figure 2-12. host controlled operation scheme - parallel port 2.4.2 stand alone operation in this mode, the board is not controlled by the host via the cop port. it may connect to host via one of its other ports, e.g., rs232 port, fast ethernet port, atm155 port etc. operating in this mode requires an application program to be programmed into the board?s flash memory. figure 2-13. stand alone configuration 2.4.3 cop/jtag connector - p16 the pq2fads-vr cop interface connector, p16, is a 16 pin, male, header connector. the connection between the pq2fads-vr and the cop controller is by a 16 line flat cable, supplied with the cop controller board obtained from a third party developer. figure 2-14. shows the pin configuration of the connector. atx power supply standard parallel cable host computer media i/f media p5 atx power supply host computer rs232 u1 p1a/p1b ethernet atm 155 (optics) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation 16 pq2fads-vr user?s manual motorola . figure 2-14. p16 - cop/jtag port connector 2.4.4 terminal to pq2fads-vr rs-232 connection a serial (rs232) terminal or any other rs232 equipment, may be connected to the rs-232 connectors p1a and p1b. the rs-232 connectors are a 9 pin, female, d-type connectors, arranged in a stacked configuration. p1b connected to scc2 of the pq2 is the lower and p1a, connected to scc1 of the pq2, is the upper in the stack. the connectors are arranged in a manner that allows for 1:1 connection with the serial port of an ibm-at 1 or compatibles, i.e. via a flat cable. the pinout which is identical for both p1a and p1b is shown in figure 2-15. . figure 2-15. p1a/p1b - rs232 serial port connector 2.4.5 10/100-base-t ethernet ports connection the 10/100-base-t port connectors - p3 and p4, are an 8-pin, 90 o , receptacle rj45 connector. the connection between the 10/100-base-t ports to the network is done by a standard cable, having two rj45/8 jacks on its ends. the pinout of p3 and p4 is described in table 7-2. "p3,p4 - 100/10 base-t ethernet connector" on page 80. 1.ibm-at is a trademark of international business machines inc. 1 3 5 7 9 2 4 6 8 10 tdo trst v3.3 tdi hreset tms 11 12 13 14 15 16 gnd ckstp_out tck n.c. gnd sreset gnd n.c. gnd qreq 1 tx 2 rx 3 n.c. 4 cts 5 dsr 6 gnd 7 cd 8 9n.c. dtr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hardware preparation and installation motorola pq2fads-vr user?s manual 17 2.4.6 memory installation the pq2fads-vr is supplied with one type of memory module: flash memory simm. 2.4.6.1 flash memory simm installation to install a memory simm, it should be taken out of its package, put diagonally in its socket - u50 - and then raised to a vertical position until the metal lock clips are locked. see figure 2-16. . caution the memory simms have alignment nibble near their # 1 pin. it is important to align the memory correctly before it is twisted, otherwise damage might be inflicted to both the memory simm and its socket. figure 2-16. flash memory simm insertion (1) (2) simm socket metal lock clip flash simm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions 18 pq2fads-vr user?s manual motorola 3 operating instructions 3.1 introduction this chapter provides necessary information to use the pq2fads-vr in host-controlled and stand-alone configurations. this includes controls and indicators, memory map details, and software initialization of the board. 3.2 controls and indicators the pq2fads-vr has the following switches and indicators. 3.2.1 power-on reset switch - sw1 the power-on reset switch sw1 performs power-on reset to the pq2, as if the power was re- applied to the ads. when the pq2 is reset that way, all configuration and all data residing in volatile memories are lost. after porst signal is negated, the pq2 re-acquires the power-on reset and hard-reset configuration data from the hard-reset configuration source. (flash | eeprom | bcsr). 3.2.2 abort switch - sw3 the abort switch is normally used to abort program execution, this by issuing a level 0 interrupt to the pq2. if the ads is in stand alone mode, it is the responsibility of the user to provide means of handling the interrupt, since there is no resident debugger with the pq2fads- vr. the abort switch signal is debounced, and may be disabled by software. 3.2.3 soft reset switch - sw2 the soft reset switch sw3 performs soft reset to the pq2 internal modules, maintaining pq2?s configuration (clocks & chip-selects) and sdrams? contents. the switch signal is debounced, and it is not possible to disable it by software. 3.2.4 hard reset - switches - sw2 & sw3 when both switches - sw2 and sw3 are depressed simultaneously, hard reset is generated to the pq2. when the pq2 is hard reset, all its configuration is lost 1 , including data stored in the sdrams and the pq2 has to be re-initialized. 1.except for hard-reset configuration word, which is acquired only once, after pon-reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions motorola pq2fads-vr user?s manual 19 3.2.5 sw6 - reset configuration switch sw5 is a 4-switch dip-switch. for its function see section 2.3.5 . 3.2.6 sw7 - software options switch sw7 is a 4-switch dip-switch. this switch is connected over swopt(0:2) lines which are available at bcsr2, s/w options may be manually selected, according to sw7 state. sw7 is factory set to all on. see figure 3-1. figure 3-1. sw7 - description 3.2.7 p26 - vddl voltage level range selection p26 selects between 4 different voltage level ranges available for vddl. for further information over its function see section 2.3.1 . 3.2.8 jp12 - iddl measurement jp12 resides in iddl?s main current flow. to measure iddl, jp12 should be removed using a solder tool and a current meter should be connected instead with wires as short and thick as possible. warning the job of removing jp12 and soldering the cur- rent meter connections instead is very delicate and should be done by a skilled technician. if this process is done by unskilled hands or re- peated more than 3 times, permanent damage may occur to the pq2fads-vr. 3.2.9 jp6 - thermal sense connector there are 2 dedicated pins therm(0:1) which provide a way to take internal temperature measurements of the pq2. these pins should be connected to gnd for normal operation. jp6 is factory set with a jumper on its 2 - 3 positions, so that therm1 is connected to gnd. sw7 on 1 2 3 4 swopt0 driven to ?0? swopt1 driven to ?0? swopt2 driven to ?0? swopt0 pulled to ?1? swopt1 pulled to ?1? swopt2 pulled to ?1? reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions 20 pq2fads-vr user?s manual motorola . figure 3-2. jp6 - therm connector 3.2.10 jp11 - iddh measurement jp11 resides in iddh?s main current flow. to measure iddh, jp11 should be removed using a solder tool, and a current meter should be connected, with as wires as short and thick as possible. warning the job of removing jp11 and soldering current meter connections instead is very delicate and should be done by a skilled technician. if this process is done by unskilled hand or re- peated more than 3 times, permanent damage might be inflicted to the pq2fads-vr. 3.2.11 jp13 - vpp source selector jp13 selects the source for vpp - programming voltage for the flash simm. when a jumper is located between pins 2 - 3 of jp13 , the vpp is connected to the vcc plane of the board, providing 5v vpp . when a jumper is located between positions 1 - 2 of jp13, vpp is drawn from the 12v plane, that provides 12v vpp . jp13 options are shown in figure 3-3. . figure 3-3. jp13 - vpp source selection 3.2.12 gnd bridges there are 7 gnd bridges on the pq2fads-vr. these bridges are meant to assist general measurements and logic-analyzer connection. 3 jp6 2 1 gnd therm1 therm0 1 1 jp13 jp13 5v vpp 12v vpp factory set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions motorola pq2fads-vr user?s manual 21 warning when connecting to a gnd bridge, use only in- sulated gnd clips. otherwise, un-insulated clips may cause short- circuits, touching "hot" points around them. failure in doing so, might result in permanent damage to the pq2fads- vr. 3.2.13 power o.k. indicator - ld1 the green power o.k. led indicator lights if the atxpower supply is generating all the voltages. 3.2.14 12v indicator - ld2 the green 12v led - ld2, indicates the presence of the +12v supply on the board. 3.2.15 utopia 16 bit indicator - ld15 the green utopia16 led - ld15, indicates that the utopia is in 16 bit mode. when off - the utopia is in 8 bit mode. 3.2.16 utopia multi phy indicator - ld16 the green multi phy led - ld16, indicates that the utopia is in multi phy mode. when off - the utopia is in single phy mode. 3.2.17 5v indicator - ld3 the green 5v led - ld3, indicates the presence of the +5v supply on the board. 3.2.18 3.3v indicator - ld4 the green 3.3v led - ld4, indicates the presence of the +3.3v supply on the board. 3.2.19 usb power indicator - ld17 the green usb power led - ld17, indicates the presence of 5v in the usb cable. 3.2.20 -12v indicator - ld5 the green -12v led - ld5, indicates the presence of the -12v supply on the board. 3.2.21 run indicator - ld6 when the green run led - ld6 is lit, it indicates that the pq2 is performing cycles on the ppc bus. when dark, the pq2 is either running internally or stuck. 3.2.22 atm on - ld7 when the yellow atm on led is lit, it indicates that the atm-uni transceiver - the pm5384, is enabled for communication. when it is dark, the atm-uni transceiver is disconnected from the pq2, enabling the use of its associated fcc1 pins off-board via the expansion connectors. atm on led is controlled by bcsr1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions 22 pq2fads-vr user?s manual motorola 3.2.23 fast ethernet port 2 enabled - ld10 when the yellow eth2 on led is lit, it indicates that the fast ethernet port 2 transceiver - the dm9161, is connected to fcc3. when it is dark, it indicates that the dm9161 is in power down mode and disconnected from fcc3, enabling the use of its associated fcc3 pins off-board via the expansion connectors. the state of ld10 is controlled by bcsr1. 3.2.24 fast ethernet port 1 enabled - ld8 when the yellow eth1 on led is lit, it indicates that the fast ethernet port 1 transceiver - the dm9161, is connected to fcc2. when it is dark, it indicates that the dm9161 is in power down mode and disconnected from fcc2, enabling the use of its associated fcc2 pins off-board via the expansion connectors. the state of ld8 is controlled by bcsr1. 3.2.25 rs232 port 1 on - ld11 when the yellow rs232 port 1 on led is lit, it designates, that the rs232 transceiver connected to p1a (upper db9 connector), is active and communication via that medium is allowed. when darkened, it designates that the transceiver is in shutdown mode and its associated scc1 pins may be used off-board via the expansion connectors. 3.2.26 fast ethernet port 1 full duplex indicator - ld18 when the dm9161 on fcc2 is enabled and is in full duplex operation mode, the red led - ld18 lights. 3.2.27 rs232 port 2 on - ld12 when the yellow rs232 port 2 on led is lit, it designates, that the rs232 transceiver connected to p1b (lower db9 connector), is active and communication via that medium is allowed. when darkened, it designates that the transceiver is in shutdown mode and its associated scc2 pins may be used off-board via the expansion connectors. 3.2.28 fast ethernet port 1 100base-tx indicator - ld19 when the dm9161 on fcc2 is enabled and is in 100 mbps operation mode, the green led - ld19 lights. 3.2.29 ethernet port 1 tx/rx indicator - ld20 the green ethernet transmit/receive led indicator blinks whenever the dm9161 on fcc2 is transmitting or receiving data via the 10/100-base-t port. 3.2.30 general purpose led 2 indicator - ld13 this is a general purpose red led which is user controlled by bcsr0. 3.2.31 ethernet port 1 link indicator - ld21 the yellow ethernet twisted pair link integrity led indicator - link, lights to indicate good link integrity on the 10/100-base-t port. ld21 is off when the link integrity fails. 3.2.32 fast ethernet port 2 full duplex indicator - ld22 when the dm9161 on fcc3 is enabled and is in full duplex operation mode, the red led - ld20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating instructions motorola pq2fads-vr user?s manual 23 lights. 3.2.33 general purpose led 1 indicator - ld14 this is a general purpose green led which is user controlled by bcsr0. 3.2.34 fast ethernet port 2 100base-tx indicator - ld23 when the dm9161 on fcc3 is enabled and is in 100 mbps operation mode, the green led - ld22 lights. 3.2.35 usb enabled indicator - ld9 the yellow usb enable led indicates that the usb transceiver is connected to the pq2. 3.2.36 ethernet port 2 link indicator - ld24 the yellow ethernet twisted pair link integrity led indicator - link, lights to indicate good link integrity on the 10/100-base-t port. ld24 is off when the link integrity fails. 3.2.37 ethernet port 2 tx/rx indicator - ld25 the green ethernet transmit/receive led indicator blinks whenever the dm9161 on fcc3 is transmitting or receiving data via the 10/100-base-t port. 3.2.38 vddl indication - ld26 the green vddl indicator led - ld26 is lit to indicate a vddl power activity. since vddl level may vary, ld26?s illumination level also varies accordingly. 3.2.39 parallel port connection - ld27 the green parallel port connection led indicates that the board is connected directly to the pc?s parallel port and the cop/jtag connector (p16) is irrelevant. 3.2.40 external debugger connection indicator - ld28 the green external debugger connection led indicates that a command converter can be connected to the cop/jtag connector (p16). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 24 pq2fads-vr user?s manual motorola 4 functional description in this chapter the various modules combining the pq2fads-vr are described to their design details. 4.1 reset & reset - configuration there are several reset sources on the pq2fads-vr: 1. power on reset 2. manual hard-reset 3. manual soft-reset 4. pci bus reset 5. pq2 internal sources. (see also the pq2 u/m ) 4.1.1 power - on resetpq2 the power on reset to the pq2 initializes the processor state after power up. a dedicated logic, using seiko s-80728an-dr-t1, which is a voltage detector of 2.8v +/- 2.4%, assert s poreset input to the pq2 for a period of ~2.5sec. this time period is long enough to cover also the vddl stabilization, powered by a different voltage regulator. it is assumed that the stabilization time for both linear regulators (see also section 6.1 power supply ) are about the same. power-on-reset may be generated manually as well by an on-board dedicated push-button (sw1). power-on reset can also be generated by the jtag logic, which is integrated with bcsr. 4.1.1.1 power - on reset configuration at the end of power - on reset sequence, modck(1:3) are sampled by the pq2 to configure the various clock modes of the pq2 (core, cpm, bus, pci...). selection between the modck(1:3) combination options is done by means of dip-switches ( section 2.3.3 ) on the mother board while pci_modckh(0:3) are obtained from the relevant dedicated pins (by means of dip-switches - section 2.3.6 ). the configuration master is determined upon the rising edge of porst , according to the state of rstconf ( section 2.3.5 ) signal, driven low on this board, to set the pq2 as a configuration master. after power-on reset negates, the hard-reset sequence starts, during which, many other different options are configured (see section 4.1.2.4 "hard reset configuration" on page 26 ), among these options, are additional clock configuration bits - pci_modckh(0:3) - the most significant bits of the modck field, which determine additional options for the clock generator. although these bits are sampled whenever the hard-reset sequence is entered, they are influential only once f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 25 - after power-on reset . if a hard reset sequence is entered later, modckh(0:3), although sampled, are don?t care. the pci_modck signal, which is sampled concurrently with the pci_modck(0:3) pins, determines the pci bus clock frequency (see section 2.3.7 ). when set high, it divides the pci bus frequency by two. when reset low, the pci bus frequency is as determined by the modck(1:3) and pci_modckh(0:3) signals. 4.1.2 hard reset hard-reset may be generated on the ads by the following sources: 1. cop/jtag port 2. manual hard reset. 3. pq2?s internal sources. hard-reset, when generated, causes the pq2 to reset all its internal hardware except for pll logic, re-acquires the hard-reset configuration from its current source, and jumps to the reset vector in the exception table. since hard-reset resets also the refresh logic for dynamic rams, their content is lost as well. hreset when asserted, is extended internally by the pq2 for additional 512 bus clock cycles at the end of which, the pq2 waits for 16 bus clock cycles and then, re-checks the state of the hreset line. hreset is an open-drain signal and must be driven with an open-drain gate by which ever external source is driving it. otherwise, contention will occur over that line, which might cause permanent damage to either board logic and/or to the pq2 itself. 4.1.2.1 cop/jtag port hard - reset to provide convenient hard-reset capability for a cop/jtag controller, hreset line appears at the cop/jtag port connector. the cop/jtag controller may directly generate hard-reset by asserting (low) this line. 4.1.2.2 manual hard reset to allow run-time hard-reset, when the cop controller is disconnected from the pq2fads-vr and to support resident debuggers, manual hard is facilitated. depressing both soft-reset (sw3) and abort (sw2) buttons assert s the hreset pin of the pq2, generating a hard reset sequence. since the hreset line may be driven internally by the pq2, it must be driven to the pq2 with an open-drain gate. if off-board h/w connected to the pq2fads-vr is to drive hreset line, then it should do so with an open-drain gate, this, to avoid contention over this line. when hard reset is generated, the pq2 is reset in a destructive manner, i.e., the hard reset configuration is re-sampled and all registers (except for the pll?s) are reset, including memory controller registers - reset of which results in a loss of dynamic memory contents. to save on board?s real-estate, this button is not a dedicated one, but is shared with the soft-reset button and the abort button - when both are depressed, hard reset is generated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 26 pq2fads-vr user?s manual motorola 4.1.2.3 internal sources hard - reset the pq2 has internal sources which generate hard reset. among these sources are: 1. loss of lock reset. when one of the plls (core, cpm), is out of lock, hard-reset is gen- erated. 2. check-stop reset. when the core enters a check-stop state from some reason, hard-reset may be generated, depended on csre bit in the rmr. 3. bus monitor reset. when the bus monitor is enabled and a bus cycle is not terminated, hard-reset is generated. 4. s/w watch dog reset. when the s/w watch-dog is enabled, and application s/w fails to perform its reset routine, it will generate hard - reset. 5. cop/jtag reset (internal). hard reset may be forced by driving the hreset line via the external pin?s scan chain. not useful for run time. in general, the pq2 asserts a reset line hard or soft for a period 512 clock cycles after a reset source has been identified. a hard reset sequence is followed by a soft reset sequence. 4.1.2.4 hard reset configuration when hard-reset is applied to the pq2 (externally as well as internally), it samples the hard- reset configuration word. this configuration may be taken from an internal default, in case rstconf is negated during hreset asserted or taken from the flash 1 /e 2 prom/bcsr (ms 8 bits of the data bus) in case rstconf signal is asserted along with hreset . the default configuration word can be taken from the e 2 prom/bcsr in case the flash has been tampered with. the selection between the bcsr, flash and the e 2 prom as the source of the default configuration word is determined by a dedicated dip-switch (see section 2.3.5 ) and a jumper (see section 2.3.4 ). during hard reset sequence, the configuration master 2 reads the flash (or e 2 prom or bcsr) memory at addresses 0, 8, 0x18, 0x20,... a byte each time, to assemble the 32 bit configuration word. a total of 64 bytes of data is read from d(0:7) to acquire 8 full configuration words for system that may have upto 8 pq2 chips. the configuration word for a single 3 pq2 is stored in the flash memory simm, in the e 2 prom or as default in the bcsr, while the other seven words are not initialized, as there are no additional pq2 on the pq2fads-vr. the default configuration word is shown in table 4-1. for the flash and in table 4-2. for the e 2 prom. pci module configuration is 256 bytes long and should start at address 0x100. there are four possible configuration words: pq2fads-vr without l2 cache - flash/bcsr is the boot device. cs0 is assigned to the flash and cs4 is assigned to the e 2 prom. 1. in general, from any device residing on cs0 . 2. in general, the pq2 for which rstconf is asserted along with porst asserted or in particular, the pq2 residing on the pq2fads-vr. 3. although the pq2 as configuration master reads 8 configuration words, only the 1?st configuration word is influential. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 27 pq2fads-vr without l2 cache - e 2 prom is the boot device. cs0 is assigned to the e 2 prom and cs4 is assigned to the flash. pq2fads-vr with l2 cache - flash is the boot device. cs0 is assigned to the flash and cs4 is assigned to the e 2 prom. pq2fads-vr with l2 cache - e 2 prom is the boot device. cs0 is assigned to the e 2 prom and cs4 is assigned to the flash. . table 4-1. bcsr/flash hard reset configuration word field data bus bits prog value [bin] implication offset in flash [hex] value [hex] erb 0 ?0? internal arbitration selected. 0 0c / 1c a exmc 1 ?0? internal memory controller. cs0 active at system boot. cdis 2 ?0? core enabled. ebm 3 ?0? /?1? ?0? - single pq2 mode for boards without l2cache ?1? - 60x bus mode a for boards with l2cache bps 4:5 11 32 bit boot port size cip 6 ?0? sets core initial prefix msr[ip]=1, so that system exception table is placed at address 0xfff00100 regardless of flash memory size isps 7 ?0? 64 bit internal space for external master accesses. in fact don?t care on this board since external master is not supported. l2cpc 8:9 ?10? ci /baddr(29)/irq2 selected as baddr(29) w t /baddr(30)/irq3 selected as baddr(30) l2_hit /irq4 selected as unassigned cpu_bg /baddr(31)/irq5 as baddr(31) 8b2 dppc 10:11 ?11? data parity pin configuration as: dp0 as ext_br2 dp1 as ext_bg2 dp2 as ext_dbg2 dp3 as ext_br3 dp4 as ext_bg3 dp5 as ext_dbg3 dp6 as irq6 dp7 as irq7 reserved 12 ?0? reserved. isb 13:15 ?010? immr initial value 0x0f000000, i.e., the internal space resides initially at this address. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 28 pq2fads-vr user?s manual motorola bms 16 ?0? boot memory (flash) at 0xfe000000. 10 36 / 02 b bbd 17 ?0? abb /irq2 pin is abb dbb /irq3 pin is dbb mmr 18:19 ?11?/?00? ?11? - mask masters requests. boot master is pci when pci is enabled in the flash. ?00? - no masking, local bus sdram mode in the bcsr. lbpc 20:21 ?01?/?00? ?11? - local bus pins function as pci bus (flash). ?00? - local bus pins function as local bus (bcsr). appc 22:23 ?10? modck1/ap(1)/tc(0) functions as bksel0 modck2/ap(2)/tc(1) functions as bksel1 modck3/ap(3)/tc(2) functions as bksel2 irq7~/ape~ functions as irq7~ cs11~/ap(0) functions as cs11~ cs10pc 24:25 ?01? cs10~/bctl1/dbg_dis~ functions as bctl1 18 45 ald_en 26 ?0? pci auto load enable. when high, pci bridge configuration is done automatically from the flash/e 2 prom (cpm is configuration master - ppc core should be disabled) right after the hard configuration word. when low, the ppc core should configure the pci bridge. reserved 27 ?0? reserved. modck_hi c 28:31 ?0101? determines the core?s frequency out of power- up reset. actually, not relevant when the pci is active since the pci_modck(0:3) take presidency. a. for l2 cache boards. b. bcsr is set for no pci configuration c. applies only once after power-up reset. table 4-1. bcsr/flash hard reset configuration word field data bus bits prog value [bin] implication offset in flash [hex] value [hex] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 29 pq2fads-vr user?s manual motorola table 4-2. e 2 prom hard reset configuration word field data bus bits prog value [bin] implication offset in flash [hex] value [hex] erb 0 ?0? internal arbitration selected. 0 04 / 14 a exmc 1 ?0? internal memory controller. cs0 active at system boot. cdis 2 ?0? core enabled. ebm 3 ?0? /?1? ?0? - single pq2 mode for boards without l2cache ?1? - 60x bus mode a for boards with l2cache bps 4:5 ?01? 8 bit boot port size cip 6 ?0? sets core initial prefix msr[ip]=1, so that system exception table is placed at address 0xfff00100 regardless of flash memory size isps 7 ?0? 64 bit internal space for external master accesses. in fact don?t care on this board since external master is not supported. l2cpc 8:9 ?10? ci /baddr(29)/irq2 selected as baddr(29) w t /baddr(30)/irq3 selected as baddr(30) l2_hit /irq4 selected as unassigned cpu_bg /baddr(31)/irq5 as baddr(31) 8b2 dppc 10:11 ?11? data parity pin configuration as: dp0 as ext_br2 dp1 as ext_bg2 dp2 as ext_dbg2 dp3 as ext_br3 dp4 as ext_bg3 dp5 as ext_dbg3 dp6 as irq6 dp7 as irq7 reserved 12 ?0? reserved. isb 13:15 ?010? immr initial value 0x0f000000, i.e., the internal space resides initially at this address. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 30 pq2fads-vr user?s manual motorola bms 16 ?0? boot memory (e 2 prom) at 0xfe000000. 10 36 bbd 17 ?0? abb /irq2 pin is abb dbb /irq3 pin is dbb mmr 18:19 ?11? mask masters requests. boot master is pci. lbpc 20:21 ?01? local bus pins function as pci bus. appc 22:23 ?10? modck1/ap(1)/tc(0) functions as bksel0 modck2/ap(2)/tc(1) functions as bksel1 modck3/ap(3)/tc(2) functions as bksel2 irq7~/ape~ functions as irq7~ cs11~/ap(0) functions as cs11~ cs10pc 24:25 ?01? cs10~/bctl1/dbg_dis~ functions as bctl1 18 45 ald_en 26 ?0? pci auto load enable. when high, pci bridge configuration is done automatically from the flash/e 2 prom (cpm is configuration source - ppc core should be disabled) right after the hard configuration word. when low, the ppc core should configure the pci bridge. reserved 27 ?0? reserved. modck_hi b 28:31 ?0101? determines the core?s frequency out of power- up reset. actually, not relevant when the pci is active since the pci_modck(0:3) take presidency. a. for l2 cache boards. b. applies only once after power-up reset. table 4-2. e 2 prom hard reset configuration word field data bus bits prog value [bin] implication offset in flash [hex] value [hex] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 31 the pci configuration registers which are set at hard-reset sequence are shown in figure 4-1. figure 4-1. pci host configuration registers 4.1.3 soft reset soft - reset may be generated on the board from the below sources: 1. cop/jtag port 2. manual soft reset 3. internal pq2 source. soft-reset, when generated, causes the pq2 to reset its internal logic, while keeping its hard-reset configuration and memory controller setup and then jumping to the reset vector in the exception table. since soft-reset does not reset the refresh logic for dynamic rams, their contents is preserved. sreset when asserted, is extended internally by the pq2 for an additional 512 bus clock cycles at the end of which, the pq2 waits for 16 bus clock cycles and then, re-checks the state of the sreset line. sreset is an open-drain signal and must be driven with an open-drain gate by every external source driving it. otherwise, contention will occur over that line, which might cause permanent damage to either the boards? logic and / or to the pq2 itself. 4.1.3.1 cop/jtag port soft - reset to provide convenient soft-reset capability for a cop/jtag controller, sreset line appears at the cop/jtag port connector - p3. the cop/jtag controller may directly generate soft-reset by asserting (low) this line. 4.1.3.2 manual soft reset to allow run-time soft-reset, when the cop controller is disconnected from the pq2fads-vr and to support resident debuggers, a soft reset push-button is provided. when the soft reset reserved device id (0x18c0) vendor id (0x1057) pci status pci command class code standard programming subclass code revision id bist control latency timer header type cache line size max lat interrupt pin min gnt interrupt line 00 04 08 0c 3c address offset (hex) pimmr base address register 10 14 40 44 / / / / / / / / pci arbiter control 18 capability pointer 34 38 / / / / / / / / pci function 2c subsystem id subsystem vendor id f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 32 pq2fads-vr user?s manual motorola push-button is depressed, the sreset line is asserted to the pq2, generating a soft reset sequence. since the sreset line may be driven internally by the pq2, it must be driven by an open-drain gate, to avoid contention over that line. if off-board h/w connected to the pq2fads-vr is to drive sreset line, then, it should do so with an open-drain gate, this, to avoid contention over this line. 4.1.3.3 internal sources soft - reset the only internal soft-reset source is the cop/jtag soft-reset, which may be generated using public jtag instructions to shift active-value (?0?) to the sreset pin via the boundary scan chain. this is not useful for run time. 4.1.4 pci bus reset the pci module in the pq2 can generate a reset signal dedicated for pci devices which reside on the pci bus. this is a reset to the pci bus which is initiated by the pci bus host - the pq2 on this board. this reset can also be initiated by a soft pci reset by setting a dedicated bit in a pci control register (consult the pq2 user manual for details). 4.2 local interrupter there are external interrupts which are applied to the pq2 via its interrupt controller: 1. abort (nmi) 2. atm uni interrupt 3. fast ethernet phy interrupt 4. pci interrupt 4.2.1 abort interrupt the abort (nmi), is generated by a push-button. when this button is depressed, the irq0 input to the pq2 is asserted. the purpose of this type of interrupt, is to support the use of resident debugger if any is made available to the board. this interrupt is enabled by setting the msr[ee] bit. to support external (off-board) generation of an nmi, the irq0 line, is driven by an open-drain gate. this allows for an external h/w, to also drive this line. if an external h/w indeed does so, it is compulsory that irq0 is driven by an open-drain (or open-collector) gate. 4.2.2 atm uni interrupt to support atm uni (user network i/f) event report by means of interrupt, the interrupt output of the uni (intb) is connected to irq 7 line of the pq2. this irq7 input is shared with the fast ethernet phy interrupt. since intb of the uni is an open-drain output, it is possible to connect additional (on and off-board) interrupt requesters on the same irq 7 , provided that they drive irq 7 with open-drain gate as well. when an interrupt request appears in irq7 , it is necessary to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 33 check the source of the interrupt whether it?s the atm uni or the fast ethernet phy. 4.2.3 fast ethernet phy interrupt to support the two fast ethernet transceivers event reports by means of interrupt, the interrupt outputs of the dm9161 are connected to irq7 line of the pq2. this irq7 input is shared with the atm uni interrupt. 4.2.4 pci interrupt each pci slot can generate up to four interrupts to a total of twelve (3 slot x 4 interupts each). each pci expansion board can generate an interrupt at any given time. since there is only one interrupt input available in the pq2, an interrupt controller is used. the interrupt controller receives all the possible interrupts from the pci slots and generate one interrupt (irq6 ) to the pq2. a simple generic interrupt controller is implemented using a cpld device. the interrupt controller is implemented as an interrupt register and an interrupt mask register. the interrupt controller has its? own dedicated chip-select line (cs8 ). a simple priority scheme is devised to prioritize the interrupts from different slots. the pci irq routing are according to figure 4-2. . figure 4-2. pci interrupt routing scheme an interrupt request in any of the intx lines, will set three interrupt bits in the pci interrupt register (if not masked in the interrupt mask register) since there are three possible interrupt sources for every intx line. it is up to the user to implement a polling process to verify the real interrupt source (by polling the interrupt pending bit in the pci device) and clear the other two. the pci interrupt register can be read at any time and accessed at offset 0x0 from cs8 base address. the description of the pci interrupt register is in table 4-3. . slot 0 slot 1 slot 2 a b c d a b c d a b c d inta intb intc intd pci interrupt controller pq2 irq6 irq data address control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola pq2fads-vr user?s manual 34 also available is an interrupt mask register which provides the user with the option to mask any of the possible pci interrupt sources. it can be read or written at any time and accessed at offset 0x4 from cs8 base address.the description of the pci interrupt mask register is in table 4-4. . table 4-3. pci interrupt register description bit mnemonic function pon def att. 0pci0_inta pci slot 0 inta . pci slot 0 interrupt a: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 1pci0_intb pci slot 0 intb . pci slot 0 interrupt b: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 2pci0_intc pci slot 0 intc . pci slot 0 interrupt c: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 3pci0_intd pci slot 0 intd . pci slot 0 interrupt d: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 4pci1_inta pci slot 1 inta . pci slot 1 interrupt a: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 5pci1_intb pci slot 1 intb . pci slot 1 interrupt b: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 6pci1_intc pci slot 1 intc . pci slot 1 interrupt c: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 7pci1_intd pci slot 1 intd . pci slot 1 interrupt d: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 8pci2_inta pci slot 2 inta . pci slot 2 interrupt a: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 9pci2_intb pci slot 2 intb . pci slot 2 interrupt b: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 10 pci2_intc pci slot 2 intc . pci slot 2 interrupt c: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 11 pci2_intd pci slot 2 intd . pci slot 2 interrupt d: ?0? - no interrupt was requested ?1? - an interrupt was requested and waiting to be handled 0r 12-31 reserved un-implemented r/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 35 table 4-4. pci interrupt mask register description bit mnemonic function pon def att. 0mpci0_inta mask pci slot 0 inta . mask pci slot 0 interrupt a: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 1mpci0_intb mask pci slot 0 intb . mask pci slot 0 interrupt b: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 2mpci0_intc mask pci slot 0 intc . mask pci slot 0 interrupt c: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 3mpci0_intd mask pci slot 0 intd . mask pci slot 0 interrupt d: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 4mpci1_inta mask pci slot 1 inta . mask pci slot 1 interrupt a: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 5mpci1_intb mask pci slot 1 intb . mask pci slot 1 interrupt b: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 6mpci1_intc mask pci slot 1 intc . mask pci slot 1 interrupt c: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 7mpci1_intd mask pci slot 1 intd . mask pci slot 1 interrupt d: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 8mpci2_inta mask pci slot 2 inta . mask pci slot 2 interrupt a: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 9mpci2_intb mask pci slot 2 intb . mask pci slot 2 interrupt b: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 10 mpci2_intc mask pci slot 2 intc . mask pci slot 2 interrupt c: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 11 mpci2_intd mask pci slot 2 intd . mask pci slot 2 interrupt d: ?0? - interrupt is available ?1? - interrupt is masked 0r/w 12-31 reserved un-implemented r/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 36 pq2fads-vr user?s manual motorola 4.3 clock generator there are two main clock circuits on board: 1. pq2 system clock 2. pci clock 4.3.1 pq2 clock the pq2 requires a single clock source as the main clock source. all pq2 60x bus timings are referenced to the main clock input - clkin1. the main clock input is in 1:1 ratio to the bus clock, with internal skew elimination (pll). use is done with 66mhz (hip4 devices) 3.3v clock oscilator (100mhz for hip7 device), which is connected to a low inter-skew buffer (u36)to split the load between all various clock consumers on both boards. special care is taken to isolate and terminate the clock route between the on-board pll and the pq2, this to provide a "clean" clock input for proper operation. the main clock scheme is shown in figure 4-3. figure 4-3. main clock generator scheme 4.3.2 pci clock the pci bus clock is derived internally from the main clock input clkin1. the generated pci clock is output from a pci-dedicated pll (named dll). that clock output is feeding an on-board low-skew and fast clock distributor which distributes the pci clock to all on-board pci devices. one of the outputs is fed back to the pci clock to the pq2 through clkin2 input. this clock input is driven to the dll which synchronizes the dll output clock to the clkin2 input clock and thus, maintains low skew between the dll output and clkin2 input. all pci bus timings are referenced to the clkin2 input clock. special care was taken when the board layout was done to keep all copper traces from the clock distributor outputs at the same lengths, including the output that is fed back to clkin2. this is in compliance with the pci standard to achieve bus 66 mhz clock gen. low skew buffers pq2 60x sdram bcsr l2cache expansion mictor lb sdram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 37 synchronization and low skew. the pci clock scheme is shown in figure 4-4. figure 4-4. pci clock generator scheme 4.4 bus configuration the pq2 may be configured in 2 possible bus modes depending on the presence of l2 cache on board. 1. single pq2 mode 2. 60x bus mode. 4.4.1 single pq2 mode when a l2 cache is not present on the board, the pq2 is configured in single pq2 mode. i.e., assuming only one pq2 on the 60x bus, with no support for external master access. this allows for internal address multiplexing to occur which makes the external address multiplexers redundant and therefore not assembled. this improves sdram performance. 4.4.2 60x bus mode when l2 cache is installed on the pq2fads-vr, the pq2 may no longer operate in single pq2 mode since the address must be seen as is by the cache. that requires the use of the external address multiplexers for the sdram. in this mode, sdram performance is decreased due to added wait-state, caused by the delay associated with the external multiplexers, on the 1?st access in a page,. note in this mode, only devices which are 60x com- patible (or devices which have 64 bit data bus and are buffered from the 60x bus) can operate on the 60x bus. this due to the 60x bus address tenure feature. this means that when the l2 66 mhz clock gen. pq2 clkin1 dllout clkin2 in out1 out2 out3 out4 pci device #1 pci device #2 pci device #3 low skew clock buffer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 38 pq2fads-vr user?s manual motorola cache is used, the flash, eeprom, bcsr and pci interrupt controller are not accesible. for further details, consult the pq2 user manual. 4.5 buffering in order to achieve best performance, it is necessary to reduce the capacitive load over the 60x bus as much as possible. therefore, the slower devices on the bus, i.e., the flash simm, e 2 prom, atm uni m/p interface, pci interrupt controller and the bcsr are buffered, while the sdram and the cache are not buffered from the 60x bus. latches are provided over address and strobe (when necessary) lines while transceivers are provided for data. use is done with 74alvt buffers (by philips) which are 3.3v operated and 5v tolerant 1 and provide bus hold to reduce pull-up/pull-down resistors count (as required by the pq2). this type of buffers reduces noise on board due to reduced transitions? amplitude. to further reduce noise and reflections, serial damping resistors are placed over sdram address and all pq2 strobe lines. the data transceivers are open only if there is an access to a valid 2 buffered board address or during hard - reset configuration 3 . that way data conflicts are avoided in case an unbuffered memory read or off-board memory is read - provided that it is not mapped to an address valid on board. it is the users? responsibility to avoid such errors. 4.6 chip - select generator the memory controller of the pq2 is used as a chip-select generator to access on-board (and off- board) memories, saving boards? area, reducing cost, power consumption and increasing flexibility. to enhance off-board application development, memory modules (including the bcsrx) may be disabled via bcsr 4 in favor of an external memory connected via the expansion connectors. that way, a cs line may be used off-board via the expansion connectors, while its associated local memory is disabled. when a cs region, assigned to a buffered 5 memory, is disabled via bcsr, the local data transceivers are disabled during access to that region, avoiding possible 6 contention over data lines. 1. required for flash, e 2 prom, interrupt controller and bcsr 2. an address which is covered in a chip-select region, that controls a buffered device. 3. to allow a configuration word stored in the flash/e 2 prom memory to become active. 4. after the bcsr is removed from the local memory map, there is no way to access it but to re-apply power to the pq2fads-vr. 5. when an unbuffered cs region is being accessed, buffers do not open anyway. 6. during read cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 39 the pq2 chip-select assignments to the various memories / registers on the pq2fads-vr are shown in table 4-5. 4.7 synchronous dram (60x bus) to enhance performance, especially in higher operation frequencies - 32mbytes of sdram are provided on board. the sdram is unbuffered from the pq2 60x bus. use is done with two mtlc4m32b2 by micron or compatibles, which each is 1m x 32bit x 4banks. the sdram?s timing is controlled by sdram machine #1 associated with 60x bus, via its assigned chip select lines (see table 4-5. ). the sdram machine supports pbi (page bank interleave) which increases the sdram throughput. the sdram connection scheme when no table 4-5. pq2fads-vr chip select assignments chip select: assignment bus timing machine cs0 flash simm / e 2 prom a a. selection is done by a dip-switch. 60x (buffered) gpcm cs1 bcsr 60x (buffered) gpcm cs2 sdram 60x (main) sdram machine 1 cs3 unused, user available - - cs4 e 2 prom / flash simm a 60x (buffered) gpcm cs5 atm uni microprocessor i/f 60x (main) gpcm cs6 communication tool m/p interface cs1 . 60x (buffered) gpcm/upmx cs7 communication tool m/p interface cs2 . 60x (buffered) gpcm/upmx cs 8 pci interrupt controller 60x (buffered) gpcm cs( 9- 11) unused, user available - - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 40 pq2fads-vr user?s manual motorola l2 cache is used is shown in figure 4-5. figure 4-5. 60x sdram connection scheme - no l2 cache the sdram connection scheme when l2 cache is installed is shown in figure 4-6. figure 4-6. sdram - 60x bus connection scheme with l2 cache ras cas we a11 a10 a(8:0) cke clk dqmb(0:7) dq(0:63) sdras sdcas sdwe sda10 sysclk d(0:63) sddqm(0:7) a(20:28) a17 mt48lc4m32b2-6 cs0 cs2 ba(1:0) banksel(1:2) a9 a19 cs0 ras cas we ba(1:0) a10 a(8:0) cke clk dqmb(0:7) dq(0:63) cs2 s dras s dcas s dwe clk d(0:63) s ddqm(0:7) banksel(1:2) mt48lc4m32b2-6 a9 psdamux ale psda10 a11 le sdrma(8:0) sdrma9 sdrma11 a(18..6) a(28..21) latch a(6:28) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 41 4.7.1 sdram programming after power-up, the sdram needs to be initialized by means of programming to establish its mode of operation. the sdram is programmed according to the following procedure: 1. issue precharge-all command 2. issue 8 cbr refresh commands 3. issue mode-set command. an sdram is programmed by issuing a mode register set command. during that command, data is passed to the mode register through the sdrams? address lines. this command is fully supported by the sdarm machine of the pq2. before that can take place, the sdram machine of the pq2 has to be initialized. mode register programming values are shown in table 4-6. : 4.7.2 sdram refresh the sdram is refreshed using its auto-refresh mode. i.e., using sdram machine one?s periodic timer, an auto-refresh command is issued to the sdram every 8.2 sec, so that all 4096 sdram rows are refreshed within specified 34 msec, while leaving an interval of ~30 msec of refresh redundancy within that window, as a safety measure, to cover for possible delays in bus availability for the refresh controller. 4.7.3 l2-cache support influence on sdram design to support an optional l2-cache on the pq2fads-vr, the following measures need to be taken: 1. optional latches - multiplexers are added over selected address lines. see figure 4-6. these latches - multiplexers are normally by-passed by 0 ? resistors that are not assem- table 4-6. 100 mhz sdram mode register programming sdram address line a a. actually sdrams? a0 is connected to pq2s? a28 and so on... sdram mode reg field value meaning: a11 (msb) reserved ?0? a10 reserved ?0? a9 opcode ?0? / ?1? 0 - burst read & burst write (copy-back data cache) 1 - burst read & single write (write-through data cache) a8 reserved ?0? a7 reserved ?0? a6 - a4 cas latency ?011? data valid 3 clocks cycles after cas asserted a3 burst type ?0? sequential burst a2 - a0 burst length ?010? 4 operand burst length f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 42 pq2fads-vr user?s manual motorola bled in l2cache boards. 2. the pq2 supports additional wait-state on sdmux line, so that the row-address may be allowed to propagate via the latch - multiplexers in time for the activate command. 3. to support sdram pbi (page based interleaving), the relative location of the row- address field, is shifted up the address lines, depended on the number of internal banks within an sdram. this since the bank select line(s) are inserted between the column (lsb) and row (msb) address lines. 4. the l2 cache used is the mpc2605. this device can operate at maximum speed of 66mhz. therefore, the use of l2 cache will limit the 60x bus frequency to 66mhz only (compared to 100mhz without l2 cache - for the mpc8280). the performance of the sdram is decreased by the addition of the external multiplexers of the sdrams? address lines. 4.7.4 sdram error correction support the pq2fads-vr has an optional support for parity error correction for sdram accesses. to support that option, the dp(0:7) lines are connected to the sdram dp(0:7) lines. since the pq2 muxes dp(0:7) signals with other signals, bus switch is used to select between dp(0:7) signals and other functions. figure 4-7. 60x sdram data parity support note: when using the data parity option, irq6 and irq7 pins change functionality to data parity pins. therfore, the two interrupt lines are switched to irq2 and irq3 so the user should be aware and switch to work with the relevant irqs. to be able to work with irq2 and irq3, this function must be enabled in siumcr register. pq2 dp0/ext_br2 dp1/ext_bg2 dp2/ext_dbg2 dp3/ext_br3 dp4/ext_bg3 dp5/ext_dbg3 dp6/irq6 dp7/irq7 60x sdram dp(0:7) dp(0:7) ext/irq ext_br2 ext_bg2 ext_dbg2 ext_br3 ext_bg3 ext_dbg3 irq6 irq7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 43 4.8 flash memory simm the pq2fads-vr is provided with 8mbyte of 95 nsec flash memory simm, the sm73228xg1jhbgo by smart modular technology which is composed of four lh28f016sct-l95 chips by sharp, arranged as 2m x 32 in a single bank. support is given also to 16mbytes and 32 mbytes simms. the flash simm resides on an 80 pin simm socket and is buffered from the 60x bus to reduce capacitive load over it. to minimize use of pq2s? chip-select lines, only one chip-select line (cs0 or cs4 if the e 2 prom is using cs0 ) is used to select the flash as a whole, while distributing chip-select lines among the module?s internal banks is done by on-board programmable logic, according to the presence- detect lines of the flash simm inserted to the pq2fads-vr. the access time of the flash memory provided with the pq2fads-vr is 95 nsec, however, devices with different delay are supported as well. by reading the delay section of the flash simm presence-detect lines (see table 4-11. ), the debugger can establish (via register or0 in case cs0 is used or or4 if cs4 is used) the correct number of wait-states needed to access the flash simm (considering 100mhz system clock frequency). the control over the flash is done with the gpcm and a dedicated cs0 (or cs4 ) region which controls the whole bank. during hard - reset initialization 1 , the debugger or any application s/w for that matter, reads the flash presence-detect lines via bcsr and determines how to program registers br0 & or0 (or br4 & or4), within which the size and the delay of the region are determined.the flash module may be disabled / enabled at any time by writing ?1? /?0? 1. i.e., initialization that follow the hard reset sequence at system boot. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 44 pq2fads-vr user?s manual motorola respectively to the flashen bit in bcsr1. the flash connection scheme is shown in figure 4-8. . figure 4-8. flash simm connection scheme as can be seen in figure 4-8. , the flash cs is distributed to four cs signals. the distribution depends on the size of the flash module installed - it is read by the bcsr using the pd(1-7) pins. the hard-reset configuration word stored in the flash differs from the one stored in the e 2 prom in the bps field which is the boot port size - the e 2 prom is 8 bits while the flash is 32 bits. 4.8.1 flash programming voltage support is given to 5v as well as 12v programmable modules. the selection between vpp?s voltage levels is done via a dedicated jumper. to avoid inadvertent programming or erasure of the flash it is recommended to leave the jumper open so that no vpp is applied to the flash simm. 4.8.2 flash and l2cache if the l2 cache is installed, the pq2 needs to be programmed to 60x bus mode. this requires the latches for the buffered address bus to the flash (as well as all other slow static devices) to be data(0:31) address(7:29) d(31:0) a(22:0) pd1 pd2 pd3 pd4 pd1 pd2 pd3 pd4 pd5 pd5 pd6 pd7 pd6 pd7 flash simm bcsr flash cs we0 we1 we2 we3 poe cs1 cs2 cs3 cs4 we0 we1 we2 we3 poe cs1 cs2 cs3 cs4 cs0 cs4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 45 enabled. the 3 lowest order address lines for the flash, are provided by the baddr(27-29) lines of the pq2. however, badrr29 function of the pq2 is multiplexed with ci (cache inhibit) function over the same pin. therefore, prior to enabling the l2cache, any code residing in the flash, should be moved into the powerpc bus sdram 1 , prior to changing baddr29 function to ci via siumcr. 4.9 e 2 prom memory the pq2fads-vr is provided with 8 kbytes of e 2 prom memory in a plcc package. the e 2 prom resides on a socket in case it is desired to replace or re-program a different configuration for the board. the e 2 prom is used only for the purpose of supplying the reset configuration word during power-on reset and for storing the pci configuration data. it is used as a back-up for the flash memory in case the flash is not installed or the data it holds is incorrect. as a back-up, it holds the default hard-reset configuration word and the default pci configuration. the hard-reset configuration word stored in the e 2 prom differs from the one stored in the flash in the bps field which is the boot port size - the e 2 prom is 8 bits while the flash is 32 bits. it uses a single chip-select, cs0 or cs4 , which depends on the chip-select used by the flash. the selection of the chip-select is done by a dip-switch. the e 2 prom connection scheme is shown in figure 4-9. the device used is atmel at28hc64b, a 5v byte alterable e 2 prom, 150ns access time with byte-wide jedec pinout. although the device is placed in a socket, it can be programmed on- board. in order to program the device on-board, it has to be unlocked - it can be locked to prevent unauthorized alterations of its contents. the lock can be done by hardware or software. the hardware lock is done by write inhibit - the pq2 does not assert we during write cycles (set in the brx register). the software lock is achieved by writing a unique sequence to the device. to 1. it is required to do so anyway, since the l2cache must operate within a full 64-bit data bus environment. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 46 pq2fads-vr user?s manual motorola unlock, a different unique sequence has to be written. figure 4-9. e 2 prom connection scheme additional address lines are connected to the socket according to the jedec format as an option to use e 2 prom up to 32 kbyte. to allow proper operation with the l2 cache, the pq2 needs to be set to 60x bus mode in which the address bus for the e 2 prom 1 is latched. 4.10 pci bus the pq2 has a pci module which enables it to act as an host (master) or a target. on this board, the pq2 serves only as a pci host - a bridge between the pci bus and the powerpc core. the pq2 pci bridge is designed to connect the powerpc processor and memory system to the pci system bus, to which i/o components are connected. the pci bridge enables the pq2 to gluelessly bridge pci masters and agents to a powerpc system host. it uses a 32-bit multiplexed, address/data bus that can run from 25mhz up to 66mhz. the interface provides address and data parity with error checking and reporting. it also provides three physical address spaces: 32-bit address memory; 32-bit address i/o; and the pci configuration space. the pq2 also includes an on-chip arbiter which enables arbitration of up to three pci masters. only three pci slots are supported on the pq2fads-vr because of the arbiter capacity. each slot can host either a pci master or pci target. the pq2 as a bridge can support more pci devices but that will require extra slots that can host pci targets only. therefore, to avoid dedicated slots for pci targets, only three slots are implemented. 1. as well as all other slow static devices. data(0:7) address(17:31) bcsr e 2 prom cs i/o(7:0) a(14:0) e 2 prom socket cs0 cs4 oe we ce poe we0 cs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 47 the pci bridge is implemented on the pq2 local bus. due to pci standard restrictions, no other application can reside on the local bus. the pci bus can operate at frequencies of 25mhz up to 66mhz @ 3.3v only. the 3.3v restriction is due to the pq2 which is not 5v compliant. the pci bus layout is shown in figure 4-10. special care was taken when the layout of the pq2fads-vr was done so that the pci standard recommendations are followed strictly. figure 4-10. pci bus scheme the clock source for the pq2 is main clock 66mhz (or 100mhz) clock oscillator. the pci clock is derived internally from the main clock and output at dllout. that clock is then distributed to each pci device on the bus in a way that they are all synchronized (by keeping all clock traces the same length). the pci clock is also fed back to the pq2 for synchronization and skew elimination purposes. an interrupt from any pci slot is handled by a simple generic interrupt controller. each slot can generate up to four interrupts for a total of twelve interrupts that the controller will support. it will be made of two register mapped in a dedicated cs region. one is an interrupt register (see table 4-3. ) and the second is interrupt mask register (see table 4-4. ). a simple priority scheme is devised to allow the controller to support more than one interrupt concurrently. 4.11 l2-cache support to enhance benchmarking, optional support is provided for l2-cache. use is done with two mpc2605 devices, each containing 256kbytes of look-aside 1 cache along with its control, providing a total of 512kbyte l2-cache. jtag pq2 pci slot 33/66mhz@3.3v arbiter pci bus dllout clkin2 clkin1 pci clock distribution pci slot 33/66mhz@3.3v pci slot 33/66mhz@3.3v main clock pci clock pci clock pci clock pci clock pci clock 66mhz interrupt controller pci irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 48 pq2fads-vr user?s manual motorola the cache is connected directly over the 60x bus and is supported gluelessly by the pq2. the presence of the l2-cache, calls for the introduction of latch - multiplexers over sdrams? address lines because the mpc2605 snooping logic needs to monitor the address as is (linear rather than multiplexed) and the bus works by the 60x bus protocol, allowing address pipelining 1 . these latch - multiplexers are soldered in place only in case a cache is installed on-board. otherwise they are omitted and bypassed by 0 ? resistors. see also section 4.7.3 l2-cache support influence on sdram design . 4.11.1 l2 cache configuration & control the cache is configured via 5 configuration lines, cfg(0:4), for the following functions: 1. cache size is set by cfg(0:2). the various settings of these lines per each cache module are encoded in table 4-7. 2. snoop is enabled - cfg3 driven low for both modules. 3. aack assertion enabled - cfg4 driven high for both modules. the caches? hreset lines are connected directly to the sreset line of the pq2 so that whenever soft-reset is asserted to or by the pq2, the cache is reset along with it, loosing all data previously stored in it. the cache has 5 control lines that control its operation and state: pwrdwn - constantly set to high (no power down support on the pq2fads-vr) l2flush - assertion of which 2 flushes out the cache array. this signal is controlled by bcsr0. l2miss_inh - in fact cache-lock. when asserted the cache does not change its contents. controlled by bcsr0. l2tag_clr - clears all tag memory. controlled by bcsr0. l2update_inh - in fact cache freeze (without information loss). controlled by bcsr0. all the above signals are connected directly to both cache modules. 1. i.e., residing on the same bus as the processor. 1. only single level is allowed with the pq2. table 4-7. l2 cache cfg(0:2) settings l2 cache size [byte] cfg(0:2) 256k ?000? (reserved) 512k ?010? -1?st module (a26 == 0) ?011? - 2?nd module (a26 == 1) 2. for minimum 8 bus clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 49 4.12 communication ports the pq2fads-vr has several communication ports, to allow convenient evaluation of the cpm features. obviously, it is not possible to provide all types of communication interfaces supported by the cpm, but it is made convenient to connect any communication interface devices to the pq2 via the cpm expansion connectors, residing on the edge of the board. all cpm pins are visible on mictor connectors. in order to avoid long routes and stubs, bus muxing devices are used to direct the cpm signals to a communication element on-board or to the expansion connector. a signal that is used on-board, will not be visible in the expansion connector and vise-versa. the control is done by enabling/disabling the communication elements on-board. the communication ports? interfaces provided on the pq2fads-vr are listed below: 1. 155 mbps atm uni on fcc1 with optical interface, using the utopia level 2 interface - support for 8 or 16 bit in multi or single phy. 2. two 100/10-base-t ports on fcc2 and fcc3 with t.p. interface, mii or rmii (on hip7 devices only) controlled. 3. dual rs232 ports residing on smc1 & smc2. 4. usb port, 1.1 usb standard compliant, with speed control (12 or 1.5 mbps) and mode control (host or slave). 4.12.1 atm port to support the pq2s? atm controller, a 155.52mbps user network interface (uni) is provided on board, connected to fcc1 of the pq2 via utopia i/f. use is done with pm5384 s/uni-155- ultra by pmc-siera. although these transceivers are capable of supporting 51.84mbps rate, support is given to 155.52mbps only. the phy supports utopia level 2 which means support for 8 or 16 bit utopia bus in single or multi phy mode. the control over the mode of utopia bus connection is done through bcsr3. the control over the transceiver is done using the microprocessor interface of the transceiver, controlled by the pq2 memory controllers? gpcm. since the uni is 5v powered and the pq2 is 3.3v powered (5v intolerant), the uni is buffered (lcx buffers) from the pq2 on both the receive part of utopia interface and the microprocessor control ports. the atm transceiver may be enabled / disabled at any time by writing ?0? /?1? respectively to the at m e n bit in bcsrx. when atmen is negated, (?1?) the microprocessor control port is also detached from the pq2 and its associated fcc may be used off-board via the expansion connectors. the atm transceiver reset input is driven by hreset signal of the pq2, so that the uni is reset whenever a hard-reset sequence occurs. the uni may also be reset by either asserting atm_rst bit in bcsr1 (see table 4-9. ) or by asserting (?1?) the reset bit in the master reset and identify / load meters register via the uni microprocessor interface. the uni transmit and receive clocks are fed with a 19.44 mhz +/- 20 ppm, clock generator, 5 v powered, while the receive and transmit fifos? clocks of the utopia interface are provided by the pq2. the pq2 can provide the same clock for both utopia transmit and receive or separate f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 50 pq2fads-vr user?s manual motorola clocks for each, hard-configured 1 . the atm sar is connected to the physical medium by an optical interface. use is done with hp?s hfbr 5805 optical interface, which operates at 1300 nm with upto 2 km transmission range. the atm phy is connected to irq7 and generates an interrupt when an appropriate event occurs. note: when the 60x data parity option is on, irq7 pin switches functionality to parity and the interrupt output is routed to irq3 . it is the responsibilty of the user to set the appropriate functionality of the irq3 pin (siumcr register). note: when 16 bit utopia bus is used, the extra pins are in conflict with other functions. in that case, the16 bit utopia bus will disable the usb, rs232 port 2 and the fast ethernet mdc functions. note: when multi phy utopia bus is used, the extra pins are in conflict with other functions. in that case, the multi phy utopia bus will disable the two rs232 port functions. 4.12.2 100/10 base - t ports two fast ethernet ports with t.p. (100-base-tx) i/f is provided on the pq2fads-vr. these ports also support 10 mbps ethernet (10-base-t) via the same transceiver - the dm9161 by davicom. the dm9161 are connected to fcc2 and fcc3 of the pq2 via mii or rmii interface, which is used for both - devices? control and data path. the initial configuration of the dm9161 on the pq2fads-vr is set by external resistors - 100base-tx full duplex in mii mode. the selection between mii/rmii for fcc2 and fcc3 is done by jumpers jp2 and jp3 respectively. the dm9161 must be set to mii or rmii while in power-down. the dm9161 reset input is driven by either asserting the feth_rst bit in bcsr1 (see table 4- 9. ) or by asserting a specific bit in an internal register via mii i/f. to allow external use of fcc2 and fcc3, their pins appear at the cpm expansion connectors and the ethernet transceiver may be disabled / enabled at any time via the miis? mdio port. the dm9161 is able to interrupt the pq2 via irq7 line. this line is shared also with the cpm expansion connectors. therefore, any tool that is connected to irq7 , should drive these lines with an open drain buffer. note: when the 60x data parity option is on, irq7 pin switches functionality to parity and the interrupt output is routed to irq3 . it is the responsibilty of the user to set the appropriate functionality of the irq3 pin (siumcr register). 4.12.2.1 dm9161 control the dm9161 is controlled via the mii management 2 port which is a 2 wire interface: a clock 1. using resistors. 2. also known as mii mdio port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 51 (mdc) and a bidirectional data line (mdio). this is in fact a bus, i.e., up to 32 devices may reside over it, while the protocol defines a 5-bit slave address field, which is compared against the slave address set to each device by hardware during device reset, according to the levels on some pins. on the board, the slave address is hard-set to b00000 for fcc2 and b00011 for fcc3. the pq2 interfaces this port using two pi/o pins: pc9 for mdio and pc10 for mdc. there is no special support within the pq2 for the mdio port and the protocol is implemented in s/w. the mdio port may interrupt a host in 2 ways: (a 1 ) driving low the mdio line during idle time or (b) using a dedicated interrupt line mdint . this line is connected to the pq2?s dp7/cse1/ irq7 line, appearing also at the cpm expansion connectors. since irq7 may also be driven by any tool, connected to the expansion connectors, it should be driven with an open drain buffer. irq7 is pulled-up on the board. note: if atm 16 bit utopia bus or usb port are enabled, either one will conflict with the mdc and mdio signals. therfore, the mdc and mdio functionality will switch to pc3 and pc2 respectively. 4.12.3 rs232 ports to assist user?s applications and to provide convenient communication channels with both a terminal and a host computer, two identical rs232 ports are provided on the pq2fads-vr, connected to scc1 and scc2 ports of the pq2. use is done with max3241 transceiver which generates rs232 levels internally using a single 3.3v supply and has a standby mode. when the rs232en1 or rs232en2 bits in bcsr1 are asserted (low), the corresponding transceiver is enabled. when negated, the corresponding transceiver is in standby mode, within which the receiver outputs are tri-stated, enabling the use of the corresponding ports? pins off-board via the expansion connectors. nine pins, female d-type stacked connector is used, configured to be directly (via a flat cable) connected to a standard ibm-pc like rs232 connector. figure 4-11. rs232 serial ports connector 4.12.3.1 rs-232 ports? signal description in the list below, the directions ?i?,?o?, and ?i/o? are relative to the pq2fads-vr board. (i.e.?i? means input to the pq2fads-vr) cd (o) - data carrier detect. this line is always asserted by the pq2fads-vr. tx (o) - transmit data. rx (i) - receive data. 1. not supported on the board. 1 tx 2 tx 3 rts 4 cts 5 dsr 6 gnd 7 dcd 8 9n.c. dtr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 52 pq2fads-vr user?s manual motorola dtr (i) - data terminal ready. this signal is used by the software on the pq2fads-vr to detect if a terminal is connected to the board. dsr (o) - data set ready. this line is always asserted by the pq2fads-vr. rts (i) - request to send. this line is not connected in the pq2fads-vr. cts (o) - clear to send. this line is always asserted by the pq2fads-vr. note: rs232 port 2 (scc2) functionality is in conflict with atm 16 bit utopia bus and multi phy utopia bus. rs232 port 1 is in conflict with multi phy utopia bus. it is up to the user to determine the desired function on the shared pins. 4.12.4 usb port the usb port resides on the pq2fads-vr and is driven by the usb port of the mpc8275 (hip7 only) through scc4. a dedicated usb transceiver - the pdiusbp11 by philips is provided, along with a tri-state buffer, separating this port from the mpc8275?s usb port, this to allow port disable option and off-board use of mpc8275 usb pins. to correctly support the 2 speed modes of the usb, detachable pull-up resistors (3.3v) are provided over d+ and d- lines of the usb, controlled by the usb_spd bit of bcsr4. when usb_spd is in low-speed level (low) d- is pulled-up while d+ remains floating. when usb_spd bit is in high-speed level, d+ is being pulled-up and d- floats. also, 5v power will optionally be provided for the usb connector, controlled by usb_vcc0 in bcsr4. when usb_vcc0 is driven low, a 5v supply will be connected to pin 1 of the usb connectors. note: the usb function is in conflict with atm 16 bit utopia bus and fast ethernet mdc functions. it is up to the user to select the desired function on the shared pins. 4.12.5 pc parallel port a new feature to this board is the direct connection to a pc parallel port for the purpose of debugger connection (codewarrior). an on-board logic is used to interface to the parallel port and translate the signals to cop/jtag format. the parallel port support both epp and spp modes of the parallel port in a pc. the direct connection eliminates the need for an external command converter. when connected to a pc?s parallel port, the parallel port connection has automatic priority over the cop/jtag connector interface. 4.13 board control & status register - bcsr most of the hardware options on the pq2fads-vr are controlled or monitored by the bcsr, which is a 32 bit wide read / write register file. the bcsr is accessed via the pq2s? memory controller (see table 4-5. ) and in fact includes 8 registers: bcsr0 to bcsr7. since the minimum block size for a cs region is 32kbytes and only a(27:29) lines are decoded by the bcsr for f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 53 register selection, bcsr0 - bcsr7 are duplicated inside that region. the following functions are controlled / monitored by the bcsr: 1. pbi 2. l2 cache inhibit 3. l2 cache flush 4. l2 cache lock 5. l2 cache tag clear. 6. atm port control which includes: transceiver enable / disable transceiver reset. utopia 8/16 bit utopia single/multi phy 7. fast ethernet ports control which includes: transceiver initial enable transceiver reset 8. rs232 port 1 enable / disable. 9. rs232 port 2 enable / disable. 10. usb port control which includes: transceiver initial enable usb speed usb power 11. flash size / delay identification. 12. cs0 assignment after hard-reset to flash simm / e 2 prom. 13. external (off-board) tools support which include: tool identification tool revision tool status information 14. s/w option identification. 15. board revision code. 16. power-on reset via jtag (optional). 17. pci cards present detect and card type. 18. local bus mode since part of the pq2fads-vrs? modules are controlled by the bcsr and since they may be disabled in favor of external hardware, the enable signals for these modules are presented at the cpm expansion connectors, so that off- board hardware may be mutually exclusive enabled with on-board modules. 4.13.1 bcsr0 - board control - status register 0 the bcsr0 is a control register on the pq2fads-vr. it is accessed at offset 0 from bcsr base f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 54 pq2fads-vr user?s manual motorola address. it may be read or written at any time 1 . bcsr0 gets its defaults upon power-on reset. bcsr0 fields are described in table 4-8. . 4.13.2 bcsr1 - board control - status register 1 the bcsr1 is a control register on the pq2fads-vr. it is accessed at offset 4 from bcsr base address. it may be read or written at any time 2 . bcsr1 gets its defaults upon power-on reset. the 1. provided that bcsr is not disabled. table 4-8. bcsr0 description bit mnemonic function pon def att. 0pbi page base interleaving . in 60x mode (i.e., with l2-cache), this bit should reflect ( system programmer responsibility ) the state of pbi bit in psdmr. in single pq2 mode (i.e., without l2-cache), this bit has no effect . 0r/w 1 reserved s 0r/w 2 l2c_inh l2 cache inhibit . when this bit is active ( low ), the l2 cache is inhibited and unable to respond to cacheable cycles. however, bus activity is still monitored by the cache so that it may respond immediately after this signal is negated. this signal is connected to the mpc2605?s l2 update inh . this signal has no function in a pq2fads-vr that does not have an l2 cache installed. 0r,w 3 l2c_flush l2 cache flush . when this bit is active ( low ) for min. 8 bus cycles, the mpc2605 initiates a process within which, valid lines are marked invalid, while dirty lines are written back to memory and marked invalid. this signal is connected to the l2 flush signal of the mpc2605. this signal has no function in a pq2fads-vr that does not have an l2 cache installed. 1r,w 4 l2c_lock l2 cache lock . when this bit is active ( low ), the mpc2605 will stop entering new data into the cache, while yet maintaining existing data and responding to cacheable cycles. this signal has no function in a pq2fads-vr that does not have an l2 cache installed. 1r,w 5 l2c_clear l2 cache clear . when this bit is active ( low ) for min. 8 bus clock cycles, the l2 cache invalidates all its entries, without flushing, the same process as with hreset asserted. however, it still monitors the bus, so it can immediately respond when this process ends. this signal is connected to the l2 tag clr of the mpc2605, but has no function when a cache is not installed on the pq2fads-vr. 1r,w 6 - 31 reserved un-implemented 0 r 2. provided that bcsr is not disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 55 fields are described in table 4-9. 4.13.3 bcsr2 - board control - status register - 2 bcsr2 is a status register which is accessed at offset 8 from the bcsr base address. its a read- table 4-9. bcsr1 description bit mnemonic function pon def att. 0conf_word config_source . when asserted ( low ) hard reset configuration word is sourced from the bcsr. when negated, hard reset configuration word is sourced from the flash/eeprom. the assignments selection is done via a dedicated jumper jp7. 0r 1 flash_cs0 flash c s0 . when asserted ( low ) cs0 is assigned to the flash simm and cs4 is assigned to e 2 prom. when negated, cs0 is assigned to the e 2 prom and cs4 is assigned to the flash simm. the assignments selection is done via a dedicated jumper. 0r 2atm_en atm port enable . when asserted ( low ) the atm uni chip (pm5350) connected to fcc1 is enabled for transmission and reception. when negated, the atm transceiver is in standby mode and its associated buffers a are in tri-state mode, freeing all its i/f signals for off-board use via the expansion connectors. a. required for voltage levels adaptation. 1r,w 3atm_rst atm port reset . when asserted ( low ), the atm port transceiver is in reset state. this line is driven also by hreset signal of the pq2. 1r,w 4 fethien1 fast ethernet port 1 initial enable . when asserted ( low ) the dm9161?s mii port, residing on fcc2, is enabled after power-up or after feth_rst is negated. when negated ( high ), the dm9161?s mii port is isolated after power-up or after feth_rst is negated and all i/f signals are tri-stated. after initial value has been set, this signal has no influence over the dm9161 and mii isolation may be controlled via mdio 0.10 bit. 1r,w 5 feth1_rst fast ethernet port 1 reset . when active ( low ) the dm9161 is reset. this line is also driven by hreset signal of the pq2. since mddis pin of the dm9161 is driven low with this application, the negation of this signal causes all the h/w configuration bits to be sampled for initial values and device control is moved to the mdio channel, which is the control path of the mii port. 1r,w 6 rs232en_1 rs232 port 1 enable . when asserted ( low ) the rs232 transceiver for port 1, is enabled. when negated, the rs232 transceiver for port 1, is in standby mode and scc1 pins are available for off-board use via the expansion connectors. 1r,w 7 rs232en_2 rs232 port 2 enable . when asserted ( low ) the rs232 transceiver for port 2, is enabled. when negated, the rs232 transceiver for port 2, is in standby mode and scc2 pins are available for off-board use via the expansion connectors. 1r,w 8 - 31 reserved un-implemented 0 r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 56 pq2fads-vr user?s manual motorola only register which may be read at any time 1 . bcsr2s? various fields are described in table 4-10. table 4-10. bcsr2 description bit mnemonic function pon def att. 0 - 7 tstat(0:7) tool status (0:7) . this field is reserved for external tool status report. the exact meaning of each bit within this field is tool unique and therefore will be documented separately per each tool. these signals are available at the system expansion connector. -r 8 - 11 toolrev(0:3) tool revision (0:3) . this field may contain the revision code of an external tool connected to the pq2. the various combinations of this field will be described per each tool users? manual. these signals are available at the system expansion connector. the revision option for the external tools are shown in table 4-16. r 12 - 15 exttoli(0:3) external tools identification . these lines, which are available at the cpm expansion connectors, are intended to serve as tools? identifier. on-board s/ w may check these lines to detect the presence of various tools (h/w expansions) at the cpm expansion connectors. for the external tools? codes and their associated combinations see table 4-13. -r 16 - 17 swopt(0:1) a a. there is additional bit to this field. see next on the same table. software option (0:1) . this field shows the state of a dedicated dip- switches providing an option to manually change a program flow. 0r 18 - 19 l2csize(0:1) l2 cache size (0:1) . this filed encodes the size of the l2 cache, present on the pq2fads-vr. for the encoding of the various cache sizes see table 4-17. - r 20 - 21 bvern(0:1) board version number (0:1) . this field represents the version code, hard- assigned to the pq2fads-vr. see table 4-14. , for version encoding. 11 r 22 - 23 brevn(0:1) board revision number (0:1) . this field represents the revision code, hard-assigned to the pq2fads-vr. see table 4-15. , for revisions? encoding. - r 24 swopt2 software option 2 . this is the lsb of the field. shows the state of a dedicated dip-switch providing an option to manually change a program flow. 0 r 25 - 27 flash_pd(7:5) flash presence detect(7:5) . these lines are connected to the flash simm presence detect lines, which encode the delay of flash simm mounted on the flash simm socket. for the encoding of flash_pd(7:5) see table 4- 11. -r 28 - 31 flash_pd(4:1) flash presence detect(4:1) . these lines are connected to the flash simm presence detect lines which encode the type of flash simm mounted on the flash simm socket. for the encoding of flash_pd(4:1) see table 4-12. -r 1. provided that bcsr is not disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 57 table 4-11. flash presence detect (7:5) encoding flash_pd(7:5) flash delay [nsec] 000 not supported 001 150 010 100/120 011 80/90 100 70 101 - 111 not supported table 4-12. flash presence detect (4:1) encoding flash_pd(4:1) flash type / size 0000 sm73288xg4jhbg0 - 32 mbyte (4 banks of 4 x 2m x 8) by smart modular te c h n o l o g y. 0001 sm73248xg2jhbg0 - 16 mbyte (2 banks of 4 x 2m x 8) by smart modular te c h n o l o g y. 0010 sm73228xg1jhbg0 - 8 mbyte (1 bank of 4 x 2m x 8) by smart modular te c h n o l o g y. 0011 - 1111 not supported table 4-13. extooli(0:3) assignment exttooli(0:3) external tool 0 t/ecom - pq2 communication tool 1reserved 2 t1 circuit emulation tool 3 - e reserved f tool non existent f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 58 pq2fads-vr user?s manual motorola table 4-14. pq2 board version encoding version number (0:1) [hex] pq2 board version 0pq2fads-zu 1reserved 2pq2fads-vr 3 pq27e ads table 4-15. pq2 board revision encoding revision number (0:1) [hex] pq2 board revision 0 eng (engineering) 1pilot 2a 3reserved table 4-16. external tool revision encoding toolrev(0:3) [hex] external tool revision 0 engineering 1pilot 2a 3 - f reserved table 4-17. l2 cache size encoding l2csize(0:1) l2 cache size ?00? reserved ?01? 512 kbytes ?10? reserved ?11? no l2 cache f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 59 4.13.4 bcsr3 - board control - status register 3 bcsr3 is a control register which is accessed at offset 0xc from the bcsr base address. its a read- write register which may be read or written at any time 1 . bcsr3s? various fields are described in table 4-19. 4.13.5 bcsr4 - board control - status register 4 bcsr4 is a status register which is accessed at offset 0x10 from the bcsr base address. its a 1. provided that bcsr is not disabled. table 4-18. bcsr3 description bit mnemonic function pon def att. 0 usb_en usb port enable . when asserted ( low ) the usb chip connected to scc4 is enabled for transmission and reception. when negated, the usb transceiver is in standby mode and its associated buffers a are in tri-state mode, freeing all its i/f signals for off-board use via the expansion connectors. a. required for voltage levels adaptation. 1r/w 1 usb_hi_speed usb hi speed . when asserted ( low ) the usb chip connected to scc4 is set for hi speed (12 mbps) transmission and reception. when negated, the usb transceiver is set to low speed (1.5 mbps) transmission and reception 0r/w 2 usbvcc0 usb port vcc en . when asserted ( high ), 5v power is applied to the usb bus. when negated, power to the usb port is disconnected. 0r/w 3 fethien2 fast ethernet port 2 initial enable . when asserted ( low ) the dm9161?s mii port, residing on fcc3, is enabled after power-up or after feth_rst is negated. when negated ( high ), the dm9161?s mii port is isolated after power-up or after feth_rst is negated and all i/f signals are tri-stated. after initial value has been set, this signal has no influence over the dm9161 and mii isolation may be controlled via mdio 0.10 bit. 1r/w 4 feth2_rst fast ethernet port 2 reset . when active ( low ) the dm9161 is reset. this line is also driven by hreset signal of the pq2. since mddis pin of the dm9161 is driven low with this application, the negation of this signal causes all the h/w configuration bits to be sampled for initial values and device control is moved to the mdio channel, which is the control path of the mii port. 1r/w 5atm16 atm 16 bit utopia . when asserted ( low ) the utopia is set for 16 bit. when negated ( high ), the utopia is set for 8 bit.. 1r/w 6 atm_single_ph y atm single phy . when asserted ( low ) the utopia is set to multi phy. when negated ( high ), the utopia is set for single phy. 1r/w 7pci_mode pci_mode . when asserted ( low ) the local bus function is set to pci. when negated ( high ), the local bus is set for local bus sdram. r 8-31 reserved un-implemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 60 pq2fads-vr user?s manual motorola read- only register which may be read at any time 1 . bcsr4s? various fields are described in table 4-19. table 4-20. pci board present signal definitions 4.13.6 bcsr5 and bcsr7- board control - status register 3 & 5 bcsr5 to bcsr7 are additional control / status registers which may be accessed as a word at offset 0x14 to 0x1c from bcsr base address. these registers are not implemented. they may be read or written but with no valid data nor any effect on the board. the description of bcsr3 and 1. provided that bcsr is not disabled. table 4-19. bcsr4 description bit mnemonic function pon def att. 0 - 1 pci0_prsnt(0:1) pci slot 0 present (0:1) . this field holds a code that tells whether a pci expansion board is pluged in pci slot 0 and the total power requirements of the board according to the pci spec. the different expansion board types are listed in table 4-20. 11 r 2 - 3 pci1_prsnt(0:1) pci slot 1 present (0:1) . this field holds a code that tells whether a pci expansion board is pluged in pci slot 1 and the total power requirements of the board according to the pci spec. the different expansion board types are listed in table 4-20. 11 r 4 - 5 pci2_prsnt(0:1) pci slot 2 present (0:1) . this field holds a code that tells whether a pci expansion board is pluged in pci slot 2 and the total power requirements of the board according to the pci spec. the different expansion board types are listed in table 4-20. 11 r 6m66en 66mhz enable . this field shows if one of the expansion boards used is not capable of operating in 66mhz mode: ?1? - all expansion boards are 66mhz capable ?0? - one of the expansion boards is not 66mhz capable 1r 7 pci_modck pci_modck. this field shows the pci bus clock settings. - r 8-31 reserved un-implemented pcix_prsnt (0:1) [hex] expansion configuration 0 expansion board present, 7.5w maximum 1 expansion board present, 25w maximum 2 expansion board present, 15w maximum 3 no expansion board present f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 61 bcsr5 is shown in table 4-21. 4.14 cop/jtag port the cop - control observation port, is part of the pq2?s jtag machine, implemented as a set of additional instructions and logic within the jtag permissions. this port may be connected to a dedicated debug station 1 , for extensive system debug. there are several third party debug solutions on the market. these debug-stations may be connected to the host computer via either ethernet, parallel-port, rs232 or any other media. the debug station connection scheme is shown in figure 4-12. . figure 4-12. debug station connection schemes to support debug station connection to the cop/jtag port, a 16 pin generic header connector is provided on the pq2fads-vr, carrying the cop/jtag signals as well as additional signals aiding in system debug. the pinout of this connector, which is a general motorola recommendation for including a cop/jtag port in a design, is shown in figure 4-13. and detailed table 4-21. bcsr5 to bcsr7 description bit mnemonic function pon def att. 0 - 31 reserved un implemented - - 1. not provided with the pq2fads-vr. host ads cop 16 wire flat cable media adaptor media media to cop ethernet/ parallel/ rs232/ usb... f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description 62 pq2fads-vr user?s manual motorola in table 4-22. . figure 4-13. cop/jtag port connector table 4-22. cop/jtag port signals description pin no. signal name attribute description 1 tdo o transmit data out. this the jtag?s serial data output driven by falling edge of tck. 2 n.c. - not connected. 3 tdi i transmit data in. this is the jtag serial data input, sampled by the pq2 on the rising edge of tck. this line is pulled up internally by the pq2. 4trst i test port reset (l). when this signal is active (low), it resets the jtag logic. this line is pull-down on the pq2fads-vr with a 1k ? resistor, to provide constant reset of the jtag logic. 5qreq o quiescent request (l). when asserted (low), this line indicates that the pq2 desires to enter low-power mode. this signal may be required by a debug station. 6 v3.3 o 3.3v power supply bus. 7 tck i test port clock. this clock shifts in / out data to / from the pq2 jtag port. data is driven on the falling edge of tck and is sampled both internally and externally on it?s rising edge. tck is pulled up internally by the pq2. 8 n.c. - not connected. 9 tms i test mode select. this signal qualified with tck in a same manner as tdi, changes the state of the jtag machine. this line is pulled up internally by the pq2. 10 n.c. - not connected. 1 3 5 7 9 2 4 6 8 10 tdo trst v3.3 tdi hreset tms 11 12 13 14 15 16 n.c. ckstp_out tck n.c. n.c. sreset gnd "key" gnd qreq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . functional description motorola pq2fads-vr user?s manual 63 11 sreset i/o, o.d. soft reset (l). this is the pq2?s soft reset which is in fact a non- maskable interrupt, making the powerpc take the reset exception from the reset vector. this line may be driven by the pq2 as well during soft-reset sequence, for 512 system clocks. this line is pulled up on the pq2fads-vr with a 1k ? resistor. when driven externally, it must be driven with an open drain gate. failure in doing so might result in permanent damage to the pq2 and / or to board logic. 12 gnd o digital gnd. main gnd plane. 13 hreset i/o, o.d. pq2?s hard reset (l). when asserted by an external h/w, generates hard-reset sequence for the pq2. during that sequence, asserted by the mpc for 512 system clocks. pulled up on the pq2fads-vr using a 1k ? resistor. when driven by an external tool, must be driven with an open drain gate. failure in doing so might result in permanent damage to the pq2 and / or to board logic. 14 n.c. - not connected. 15 xbr3 (ckstop_out ) i/o normally configured as xbr3 which has no function with this connector. may be configured as ckstop_out - check stop out (l). when asserted (low) indicates that the pq2 core has entered a check-stop state. 16 gnd o digital gnd. main gnd plane. table 4-22. cop/jtag port signals description pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization 64 pq2fads-vr user?s manual motorola 5 memory map and initialization 5.1 memory map all accesses to pq2fads-vr?s memory slaves are controlled by the pq2?s memory controller. therefore, the memory map is reprogrammable to the desire of the user. after hard reset is performed by the debug station, the debugger checks for existence, size, delay and type of the flash memory simm mounted on board and decides on the assignments of cs0 and cs4 (e 2 prom and flash) and programs the memory controller accordingly. the sdram, e 2 prom and the flash memory, respond to all types of memory access i.e., problem / supervisory, program / data and dma. this memory map is a recommended memory map and since it is a "soft" map, devices? address may be moved about the map, to the convenience of any user. there are actually two memory maps which depend on the device assigned to cs0 (regardless of the hard reset configuration word source). the memory address for the device assigned to cs0 is always the same as determined in the hard-reset configuration word. since the flash and e 2 prom require different memory spaces, different memory maps are devised for each case. for details see table 5-1. and table 5-2. table 5-1. pq2fads-vr memory map - flash (or bcsr) as boot device address range memory type device name port size memory size 00000000 - 01ffffff 60x sdram 32mbyte 64mbyte 64 64 mbyte 01000000 - 03ffffff 04000000 - 044fffff empty space optional 4mbyte local bus sdram for legacy support -5 mbyte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization motorola pq2fads-vr user?s manual 65 04500000 - 04507fff bcsr(0:7) a 32 32 kbyte 04500000 - 04507fe3 bcsr0 4 byte 04500004 - 04507fe7 bcsr1 4 byte 04500008 - 04507feb bcsr2 4 byte 0450000c - 04507fef bcsr3 4 byte 04500010 - 04507ff3 bcsr4 4 byte 04500014 - 04507ff7 bcsr5 4 byte 04500018 - 04507ffb bcsr6 4 byte 0450001c - 04507fff bcsr7 4 byte 04508000 - 045fffff empty space -~1 mbyte 04600000 - 04607fff b atm uni proc. control pmc5384 m/p i/f 8 32 kbyte 04608000 - 046fffff empty space -~1 mbyte 04700000 c - 0471ffff pq2 internal map d 32 128 kbyte 04720000 - 0472ffff empty space - 64 kbyte 04730000 - 04737fff pci interrupt controller 32 32 kbyte 04738000 - 047fffff empty space - ~800 kbyte 04800000 - 04ffffff pci memory agents pimmr (via pci direct) ~ 8 mbyte 05000000 - 7fffffff empty space tool board is located at 60000000 and 70000000 ~ 2 gbyte 80000000 - bfffffff pci memory pci agents gpl windows 32 1 gbyte table 5-1. pq2fads-vr memory map - flash (or bcsr) as boot device address range memory type device name port size memory size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization 66 pq2fads-vr user?s manual motorola c0000000 - c1ffffff empty space -32 mbyte c2000000 e - c2007fff e 2 prom atmel at28hc64b 8 32 kbyte c2008000 - cfffffff empty space ~200 mbyte d0000000 - d07fffff empty space 8 mbyte d0800000 - fdffffff empty space ~1 gbyte fe000000 f - feffffff flash simm 32m simm - sm73288 32 32 mbyte ff000000 - ff7fffff 16m simm - sm73248 ff800000 - ffffffff 8m simm - sm73228 a. the device appears repeatedly in multiples of its port-size (in bytes) x depth. e.g., bcsr0 appear at memory locations 4700000, 4700020, 4700040..., while bcsr1 appears at 4700004, 4700024, 4700044... and so on. b. the internal space of the atm uni control port is 256 bytes, however, the minimal block size tha may be controlled by the gpcm is 32 kbytes. c. initially at h0f000000 - h0f00ffff, set by hard reset configuration. d. refer to the pq2 user?s manual for complete description of the internal memory map. e. an 8 kbyte device is used (16 kbyte and 32 kbyte devices can also be used) so it appears repeatedly in 8kbyte multiples starting from c2000000. f. set by hard-reset configuration. table 5-2. pq2fads-vr memory map - e 2 prom as boot device address range memory type device name port size memory size 00000000 - 00ffffff sdram dimm 32 mbyte 64 mbyte 64 64 mbyte 01000000 - 03ffffff 04000000 - 044fffff empty space -5 mbyte table 5-1. pq2fads-vr memory map - flash (or bcsr) as boot device address range memory type device name port size memory size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization motorola pq2fads-vr user?s manual 67 04500000 - 04507fff bcsr(0:7) a 32 32 kbyte 04500000 - 04507fe3 bcsr0 4 byte 04500004 - 04507fe7 bcsr1 4 byte 04500008 - 04507feb bcsr2 4 byte 0450000c - 04507fef bcsr3 4 byte 04500010 - 04507ff3 bcsr4 4 byte 04500014 - 04507ff7 bcsr5 4 byte 04500018 - 04507ffb bcsr6 4 byte 0450001c - 04507fff bcsr7 4 byte 04508000 - 045fffff empty space -~1 mbyte 04600000 - 04607fff b atm uni proc. control pmc5384 m/p i/f 8 32 kbyte 04608000 - 046fffff empty space -~1 mbyte 04700000 c - 0471ffff pq2 internal map d 32 128 kbyte 04720000 - 0472ffff empty space - 64 kbyte 04730000 - 04737fff pci interrupt controller 32 32 kbyte 04738000 - 047fffff empty space - ~800 kbyte 04800000 - 04ffffff pci memory agents pimmr (via pci direct) ~ 8 mbyte 05000000 - 7fffffff empty space tool board is located at 60000000 and 70000000 ~ 2 gbyte 80000000 - bfffffff pci memory pci agents gpl windows 32 1 gbyte table 5-2. pq2fads-vr memory map - e 2 prom as boot device address range memory type device name port size memory size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization 68 pq2fads-vr user?s manual motorola 5.2 pq2 register programming the pq2 provides the following functions on the pq2fads-vr: 1. system functions which include: ppc bus sdram controller local bus host to pci bridge chip select generator 2. communication functions which include: atm sar dual fast ethernet controller uart for terminal or host computer connection usb controller c0000000 - c1ffffff empty space -32 mbyte c2000000 - c2ffffff flash simm 32m simm - sm73288 32 32 mbyte c3000000 - c37fffff 16m simm - sm73248 c3800000 - c3ffffff 8m simm - sm73228 c4000000 - cfffffff empty space ~200 mbyte d0000000 - d07fffff empty space 8 mbyte d0800000 - ffffdfff empty space ~1 gbyte fff00000 e - ffffffff e 2 prom atmel at28hc64b 8 32 kbyte a. the device appears repeatedly in multiples of its port-size (in bytes) x depth. e.g., bcsr0 appears at memory locations 4700000, 4700020, 4700040..., while bcsr1 appears at 4700004, 4700024, 4700044... and so on. b. the internal space of the atm uni control port is 256 bytes, however, the minimal block size that may be controlled by the gpcm is 32 kbytes. c. initially at h0f000000 - h0f00ffff, set by hard reset configuration. d. refer to the pq2 user?s manual for complete description of the pq2?s internal memory map. e. an 8 kbyte device is used (16 kbyte and 32 kbyte devices can also be used) so it appears repeatedly in 8kbyte multiples starting from fff00000. table 5-2. pq2fads-vr memory map - e 2 prom as boot device address range memory type device name port size memory size f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization motorola pq2fads-vr user?s manual 69 the internal registers of the pq2 must be programmed after hard reset as described in the following paragraphs. the addresses and programming values are in hexadecimal base. for more information on the following initializations, see the pq2 user?s manual. 5.2.1 system initializations the power-on reset configuration word is set in the bcsr or flash or in the e 2 prom . there are two configuration words - one for the bcsr and flash (when it is assigned to cs0 ) and the other to the e 2 prom ( when it is assigned to cs0 ) . the two configurations are detailed in table 5- 3. and table 5-4. respectively. table 5-3. bcsr/flash power on reset configuration a a. programmed into the flash (e 2 prom) memory in addresses 0x0, 0x8, 0x10 & 0x18 flash address [hex] init value[hex] description 0 0c / (1c b ) b. with l2 cache internal arbitration, internal memory controller, core enabled, single pq2 (60x bus mode b ), 32 bit boot port size, exceptions vectored to 0xfffxxxxx, internal space 64 bit slave for external master. 8 b2 l2cache signals configured as baddrx lines, dp(1:7) configured as l2 cache i/f and irq(6:7),initial internal space @ 0x0f000000 10 32 c / (36 d ) c. programmed in bcsr - local bus pins function is local bus d. programmed in flash - local bus pins function is pci boot memory space @ 0xfe000000 - 0xffffffff, abb/irq2 pin is abb , dbb/ irq3 pin is dbb , no masking on bus request lines, local bus pins function as (in bcsr) pci (in flash), pci is boot master, ap(1;3) configured as bnksel(0:2), ape configured as irq7 and cs11 as cs11 . 18 45 cs10 configured as bctl1 table 5-4. e 2 prom power on reset configuration a eeprom address [hex] init value[hex] description 0 04 / (14 b ) internal arbitration, internal memory controller, core enabled, single pq2 (60x bus mode b ), 8 bit boot size, exceptions vectored to 0xfffxxxxx, internal space 64 bit slave for external master. 8 b2 l2cache signals configured as baddrx lines, dp(1:7) configured as l2 cache i/f and irq(6:7),initial internal space @ 0x0f000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization 70 pq2fads-vr user?s manual motorola 5.2.2 memory controller registers programming the memory controller on the pq2fads-vr is initialized to 100mhz operation, i.e., registers? programming is based on 100mhz timing calculation (it will also work for slower bus speeds but the timing will have to be optimized). there are two possible initializations for the memory controller: flash simm is assigned to cs0 and e 2 prom is assigned to cs4 . flash simm is assigned to cs4 and e 2 prom is assigned to cs0 . 10 36 boot memory space @ 0xfe000000 - 0xffffffff, abb/irq2 pin is abb , dbb/ irq3 pin is dbb , no masking on bus request lines, local bus pins function as pci, pci is boot master, ap(1;3) configured as bnksel(0:2), ape configured as irq7 and cs11 as cs11 . 18 45 cs10 configured as bctl1 a. programmed into the e 2 prom in addresses 0x0, 0x8, 0x10 & 0x18 b. with l2 cache table 5-5. siu registers? programming register init value[hex] description rmr 0001 check-stop reset enabled. immr 04700000 internal space @ 0x047000000 sypcr ffffffc3 software watchdog timer count - ffff, bus-monitor timing ff, ppc bus-monitor - enabled, local bus-monitor - enabled, s/w watch-dog - disabled, s/w watch-dog (if enabled) causes reset, s/w watch-dog (if enabled) - prescaled. bcr 100c0000 (88444000 a ) single pq2 (60x bus mode a ), 1 wait-states on address tenure, no l2cache (l2cache assumed a ), 1 clock hit delay (when l2cache available), 1-level pipeline depth, extended transfer mode enabled for pcc, extended transfer mode disabled for local buses, odd parity for ppc & local buses, external master delay enabled, internal space responds as 64 bit slave for external master (not relevant for this application). a. with l2 cache table 5-4. e 2 prom power on reset configuration a eeprom address [hex] init value[hex] description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization motorola pq2fads-vr user?s manual 71 both options are shown in table 5-6. and table 5-7. table 5-6. memory controller initializations for 100mhz - flash as boot device reg. device type bus init value [hex] description br0 sm73228xg1jhbg0 by smart modular tech. ppc ff801801 base at ff800000, 32 bit port size, no parity, gpcm sm73248xg2jhbg0 by smart modular tech. ff001801 base at ff000000, 32 bit port size, no parity, gpcm sm73288xg4jhbg0 by smart modular tech. fe001801 base at fe000000, 32 bit port size, no parity, gpcm or0 sm73228xg1jhbg0 by smart modular tech. ff800876 8mbyte block size, cs early negate, 11 w.s., timing relax sm73248xg2jhbg0 by smart modular tech. ff000876 16mbyte block size, cs early negate, 11 w.s., timing relax sm73288xg4jhbg0 by smart modular tech. fe000876 32mbyte block size, cs early negate, 11 w.s., timing relax br1 bcsr ppc 04501801 base at 04500000, 32 bit port size, no parity, gpcm or1 ffff8010 32 kbyte block size, all types access, 1 w.s. br2 sdram mt48lc4m32b2 by micron ppc 00000041 base at 0, 64 bit port size, no parity, sdram machine 1 or2 fe002ec0 32mbyte block size, 4 banks per device, row starts at a7, 12 row lines, internal bank interleaving allowed, normal aack operation br4 e 2 prom ppc c2000801 base at c2000000, 8 bit port size, write protect disabled, no parity, gpcm or4 at28hc64b-70jc by atmel ffff8866 32 kbyte block size, cs output half a clock after address, all types access, 6 w.s., timing relax br5 pm5384 - atm uni ppc 04600801 base at 04600000, 8 bit port size, no parity, gpcm on ppc bus. or5 ffff8e56 32k byte block size, delayed cs assertion, early cs and we negation for write cycle, relaxed timing, 7 w.s. for read, 8 for write, extended hold time after read. br8 pci interrupt controller ppc 04731801 base at 04730000, 32 bit port size, no parity, gpcm on ppc bus. or8 ffff8010 32 kbyte block size, all types access, 1 w.s. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization 72 pq2fads-vr user?s manual motorola table 5-7. memory controller initializations for 100mhz - e 2 prom as boot device reg. device type bus init value [hex] description br0 e 2 prom ppc fff00801 base at ffffe000, 8 bit port size, write protect disabled, no parity, gpcm or0 at28hc64b-70jc by atmel ffff8866 32 kbyte block size, cs output half a clock after address, all types access, 6 w.s., timing relax br1 bcsr ppc 04501801 base at 04500000, 32 bit port size, no parity, gpcm or1 ffff8010 32 kbyte block size, all types access, 1 w.s. br2 sdram mt48lc4m32b2 by micron ppc 00000041 base at 0, 64 bit port size, no parity, sdram machine 1 or2 fe002ec0 32mbyte block size, 4 banks per device, row starts at a7, 12 row lines, internal bank interleaving allowed, normal aack operation br4 sm73228xg1jhbg0 by smart modular tech. ppc c3801801 base at c3800000, 32 bit port size, no parity, gpcm sm73248xg2jhbg0 by smart modular tech. c3001801 base at c3000000, 32 bit port size, no parity, gpcm asm73288xg4jhbg0 by smart modular tech. c2001801 base at c2000000, 32 bit port size, no parity, gpcm or4 sm73228xg1jhbg0 by smart modular tech. ff800876 8mbyte block size, cs early negate, 11 w.s., timing relax sm73248xg2jhbg0 by smart modular tech. ff000876 16mbyte block size, cs early negate, 11 w.s., timing relax sm73288xg4jhbg0 by smart modular tech. fe000876 32mbyte block size, cs early negate, 11 w.s., timing relax br5 pm5384 - atm uni ppc 04600801 base at 04600000, 8 bit port size, no parity, gpcm on ppc bus. or5 ffff8e56 32k byte block size, delayed cs assertion, early cs and we negation for write cycle, relaxed timing, 7 w.s. for read, 8 for write, extended hold time after read. br8 pci interrupt controller ppc 04731801 base at 04730000, 32 bit port size, no parity, gpcm on ppc bus. or8 ffff8010 32 kbyte block size, all types access, 1 w.s. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map and initialization motorola pq2fads-vr user?s manual 73 table 5-8. memory controller initializations for 100mhz reg. device type bus init value [hex] description psdmr mt48lc4m32b2 (32 mbyte) ppc single pq2 bus mode c24b36a3 page based interleaving, refresh enabled, normal operation mode, address muxing mode 2, a14-a16 on bnksel, a8 on psda10, 8 clocks refresh recovery, 3 clocks precharge to activate delay, 3 clocks activate to read/write delay, 4 beat burst length, 2 clock last data out to precharge, 2 clock write recovery time, no extra cycle on address phase, normal timing for control lines, 3 clocks cas latency. psrt ppc bus sdram supported ppc 13 divide mptpr output by 20 (psrt +1) generates refresh every 8.2 sec, while 15.6 sec required. this will work also for 66mhz bus (12.4 sec). mptpr all sdrams on board 2800 divide bus clock by 41 (mptpr+1) (decimal) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . physical properties 74 pq2fads-vr user?s manual motorola 6 physical properties 6.1 power supply the board gets the power from the atx power supply (it seats in an atx chassis). all the power rails on the board are derived from the atx power supply. there are 4 power rails with the pq2: 1. vddh (i/o) 2. vddl (internal logic) 3. vccsyn (cpm pll) 4. vccsyn1 (core pll) and there are 5 power rails on the pq2fads-vr: 1. vcc (5v) rail 2. stand by (5v) rail 3. v3.3 (3.3v) rail 4. vddl (1.7v-2.5v) rail 5. +12v rail f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . physical properties motorola pq2fads-vr user?s manual 75 6. -12v rail figure 6-1. pq2fads-vr power scheme to support off-board application development, the power buses are connected to the expansion connectors so that external logic may be powered directly from the board. the maximum current allowed to be drawn from the board on each bus also depends on the current drawn by the pci bus. the figures are shown in table 6-1. the pci standard specifies that each add-in card should consume maximum 25watt from all power sources combined. the maximum current consumption allowed per power source for a total of 25watt according to the pci standard is shown in table 6-2. table 6-1. expansion connectors maximum current consumption power bus max. current vcc tbd v3.3 tbd table 6-2. maximum power consumption per add-in card power rail add-in card 5v 5a max. (system depended) 3.3v 7.6a max. (system depended) 12v 500ma -12v 100ma 3.3v 1.5-2v pq2 vddl vccsyn pq2fads-vr logic & peripherals vddh expansion con. vddl vccsyn1 vddh pci connectors 5v 3.3v 5v 5v 3.3v 3.3v 12v -12v power supply at x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . physical properties 76 pq2fads-vr user?s manual motorola 6.1.1 5v rail some of the pq2fads-vr peripherals (not including the pci add-in cards which should be 3.3v only on the pci interface but can use 5v for other components on-board) reside on the 5v bus. since the pq2 is not 5v tolerant, buffering is provided between 5v peripherals and the pq2, protecting the pq2 from the higher voltage level. 6.1.2 3.3v rail the pq2, sdram, pci add-in cards, address and data buffers are powered by the 3.3 bus, which is produced from the atx power supply. 6.1.3 5v stand by rail the 5v stand by power rail comes from the atx power supply. its? only use is to power the logic required to support the power button in the front panel on the atx chasis. 6.1.4 vddh rail the pq2?s vddh power bus (3.3v) is produced from the 5v bus using a low-voltage drop linear voltage regulator made by micrel, the mic29501-3.3bu. a production option is made so that the level on this bus may be varied by means of trimming potentiometer - tr2. however this will requires replacing some components. this option allows the vddh to be in the range of 3.0v - 3.6v. 6.1.5 vddl bus the pq2?s internal logic and the pll are powered with a lower-voltage power source, voltage of which may be in 3 ranges of levels: 2.3v - 2.7v 1.7v - 1.9v 1.8v - 2.0v selection between the above range levels is done via a jumper, which selects between different resistor values within the vddl?s variable regulator feedback network, while the fine tuning within a range is done by means of a trimming potentiometer. changing the voltage to the core logic of the pq2, obviously has an influence over the maximal speed of the core. there is the power-speed trade-off, i.e., lower operation speeds may be obtained with lower voltage supply. 6.1.6 12v rail the 12v bus from the atx power supply supports the pci slots and the vpp 12v option from programming the flash. 6.1.7 -12v rail the -12v bus from the atx power supply supports the pci slots. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . physical properties motorola pq2fads-vr user?s manual 77 6.2 connectors the pq2fads-vr has connectors attached, to serve the following functions: 1. atx power supply 2. 100 / 10 - base-t ethernet ports 3. atm 155mbps port 4. rs232 port 1 5. rs232 port 2 6. cpm expansion 7. cop / jtag 8. logic analyzer connectors 9. programmable logic in system programming (isp) 10. pci connectors 11. system expansion 12. usb connector 13. parallel port connector 6.2.1 atx power connector the atx power connector is a 20-lead, standard atx power connector. the female part is soldered to the pcb, while the plug is connected to the power supply. that way fast connection / disconnection of power is facilitated. 6.2.2 fast ethernet port connectors the ethernet connector on the pq2fads-vr is a twisted-pair (100/10-base-t) connector. use is done with 90 0 rj45-8 connector. 6.2.3 atm 155 port connection the atm 155 i/f to the media, is optical rather than electrical. use is done with hp?s hfbr 5805 optical i/f which is placed on the edge of the board for convenient connection. 6.2.4 rs232 ports connector the rs232 port connector is a stacked 9 pin, 90 0 , female d-type connector, which saves on board space (made of two connectors for two ports). 6.2.5 cpm expansion connector the cpm expansion connectors carries all cpm pins, i.e., port a to port d signals. use done with din 41612, 128 pin t.h. pcb connector, residing on the board, allowing convenient vertical connection to off-board tools. power supply pins are also provided through this connector. 6.2.6 cop/jtag port connector the debug port connector is a motorola standard cop/jtag connector for the 60x processors f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . physical properties 78 pq2fads-vr user?s manual motorola family.it is a generic 16 pin (2 x 8), male, smd, 90 o protected header connector. 6.2.7 logic analyzer connectors to support fast connection to hps? 16500 logic analyzers series for debugging purposes, a set of dedicated connectors is provided. use is done with 38 pin, smt, high density, matched impedance mictor connectors made by amp. these connectors carry the unbuffered 60x signals and should be placed as near to the pq2 as possible to provide short pcb routes, yielding better reflections and crosstalk immunity. they do not carry the pci bus signals due to the restrictions enforced by the pci standard. there are also connectors for the cpm signals. 6.2.8 mach?s in system programming (isp) connector this is a 10 pin generic 0.100" pitch header connector, providing in system programming capability for vantis made programmable logic on board. 6.2.9 pci connectors a set of three standard pci 3.3v keyed, 124 pin, 32-bit connectors is provided for connecting up to three pci add-in cards. 6.2.10 system expansion connector the system expansion connector is a 128 pin, din 41612 connector, which provides a minimal system i/ f required to interface to other tool-boards which may use the cpm expansion connector. this connector contains 16 bit (lower ppc bus) address lines, 16 bit (higher ppc bus) data lines plus useful gpcm and upm control lines. 6.2.11 usb connector the usb connector is standard type a usb connector. 6.2.12 parallel port connector the parallel connector is a standard 25 pin d-type male connector. 6.3 pcb layout the pq2fads-vr layout was done in a manner suitable for high-frequency operation and it follows closely the pci standard layout recommendations. following is a list of measures which are taken to meet this design goal: traces are as short as possible. clock signals and sensitive strobe signals are shielded and routed as a chain. multilayer pcb, with ground and supply layers. pci signals lengths and impedance according to pci standard rev. 2.2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 79 7 support information in this chapter all information needed for support, maintenance and connectivity to the pq2-ads- pci is provided. 7.1 interconnect signals the pq2fads-vr interconnects with external devices via the following set of connectors: 1. p1 - rs232 ports 1 and 2 2. p2 - usb connector 3. p3 and p4 - 100 / 10 - base-t ethernet ports 4. p15 - cop / jtag 5. p7 - cpm expansion 6. p11, p12, p13, p14, p16, p17, p18, p23, p28,p29,p30 - logic analyzer mictor connectors 7. p10, p8, p9 - pci slots connectors 8. p27 - atx power supply connector 9. p26,p20 - mach/lattice and altera in system programming (isp) 10. p25 - system expansion 11. p31 - parallel port connector 7.1.1 p1 - rs232 ports 1 and 2 connectors p1 is a dual 9 pin d-type connectors as described in table 7-1. table 7-1. p1 connector pin no. signal name description 1 cd carrier detect output from the pq2fads-vr. 2 tx transmit data output from the pq2fads-vr. 3 rx receive data input to the pq2fads-vr. 4 dtr data terminal ready input to the pq2fads-vr. 5 gnd ground signal of the pq2fads-vr. 6 dsr data set ready output from the pq2fads-vr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 80 pq2fads-vr user?s manual motorola 7.1.2 p3 and p4 - 100/10 - base-t ethernet port connector p3 or p4 is a rj-45 type connector for twisted pair ethernet as described in table 7-2. 7.1.3 p16 - cop / jtag connector p16 is a motorola standard cop / jtag connector for the 60x processors family. it is a 16 pin protected header connector as described in table 7-3. 7 n.c. no connect 8 cts clear to send output from the pq2fads-vr. 9 n.c. no connect table 7-2. p3,p4 - 100/10 base-t ethernet connector pin no. signal name description 1 tptx twisted-pair transmit data positive output from the pq2fads-vr. 2 tptx~ twisted-pair transmit data negative output from the pq2fads-vr. 3 tprx twisted-pair receive data positive input to the pq2fads-vr. 4 n.c. not connected, bob smith terminated on the pq2fads-vr. 5 6 tprx~ twisted-pair receive data negative input to the pq2fads-vr. 7 n.c. not connected, bob smith terminated on the pq2fads-vr. 8 table 7-3. p16 - cop/jtag connector pin no. signal name attribute description 1 tdo o transmit data output. this the pq2?s jtag serial data output driven by falling edge of tck. 2 gnd o digital gnd. main gnd plane. 3 tdi i transmit data in. this is the jtag serial data input of the ads, sampled on the rising edge of tck. 4 trst# i test port reset~ (l). when this signal is active (low), it resets the jtag logic of the pq2. this line is pull-down on the ads with a 1k ? resistor, to provide constant reset of the jtag logic. table 7-1. p1 connector pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 81 7.1.4 p7 - cpm expansion connector p7 is a 128 pin, 90 0 , din 41612 connector, which allows for convenient expansion of the pq2?s serial ports. this connector contains all cpm pins plus power supply pins, to provide for easy tool connection as described in table 7-4. 5 qreq# o quiescent request (l). when asserted (low), this line indicates that the pq2 desires to enter low-power mode. this signal may be required by a debug station. 6 3v3 o 3.3v power supply bus. 7 tck i test port clock. this clock shifts in / out data to / from the jtag logic. data is driven on the falling edge of tck and is sampled both internally and externally on it?s rising edge. tck is pulled up internally by the pq2. 8n.c. - not connected. 9 tms i test mode select. this signal qualified with tck in a same manner as tdi, changes the state of the jtag machine. this line is pulled up internally by the pq2. 10 gnd o digital gnd. main gnd plane. 11 sreset# i/o, o.d. soft reset (l). this is the pq2?s soft reset which is in fact a non- maskable interrupt, making the ppc take the reset exception from the reset vector. this line may be driven by the pq2 as well during soft-reset sequence, for 512 system clocks. this line is pulled up on the ads with a 1k ? resistor. when driven externally, it must be driven with an open drain gate. failure to do so may result in permanent damage to the pq2 and / or to ads logic. 12 gnd o digital gnd. main gnd plane. 13 hreset# i/o, o.d. pq2?s hard reset (l). when asserted by an external h/w, generates hard-reset sequence for the pq2. during that sequence, asserted by the pq2 for 512 system clocks. pulled up on the ads using a 1k ? resistor. when driven by an external tool, must be driven with an open drain gate. failure to do so may result in permanent damage to the pq2 and / or to ads logic. 14 n.c. - not connected. 15 xbr3# (ckstop_out#) i/o normally configured as xbr3# which has no function with this connector. may be configured as ckstp_out# - check stop out (l). when asserted (low) indicates that the pq2 core has entered a check- stop state. 16 gnd o digital gnd. main gnd plane. table 7-3. p16 - cop/jtag connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 82 pq2fads-vr user?s manual motorola table 7-4. p7 - cpm expansion connector pin no. signal name attribute description a1 rs_rxd1 (pd31 a ) i/o, t.s. when rs232 port #1 is enabled, this signal is the receive data line for that port. when this port is disabled, this signal is tristated and may be used to any available alternate function for pd31. a2 rs_txd1 (pd30) i/o, t.s. when rs232 port #1 is enabled, this signal is the transmit data line for that port. when this port is disabled, this signal may be used to any available alternate function for pd30. a3 pd29 i/o, t.s pq2?s port d 29 line. parallel i/o or cpm dedicated line.may be used for any of it?s available functions. a4 rs_rxd2 (pd28) i/o, t.s. when rs232 port #2 is enabled, this signal is the receive data line for that port. when this port is disabled, this signal is tristated and may be used to any available alternate function for pd28. a5 rs_txd2 (pd27) i/o, t.s. when rs232 port #2 is enabled, this signal is the transmit data line for that port. when this port is disabled, this signal may be used to any available alternate function for pd27. a6 pd26 i/o, t.s. pq2?s pd(26:18) port d lines. parallel i/o or cpm dedicated lines. may be used for any of their available functions. a7 pd25 a8 pd24 a9 pd23 a10 pd22 a11 pd21 a12 pd20 a13 pd19 a14 pd18 a15 atmrxpty (pd17) i/o, t.s. atm receive parity line. when the atm port is enabled, this line is connected to the receive parity of the pm5350 atm uni. when this port is disabled, this signal is tristated and may be used for any available function of pd17. a16 atmtxpty (pd16) i/o, t.s. atm transmit parity line. when the atm port is enabled, this line is connected to the transmit parity of the pm5350 atm uni. when this port is disabled, this signal may be used for any available function of pd16. a17 i2csda (pd15) i/o, t.s. this signal is connected to the serial i 2 c data line. this line may be used off-board as an i 2 c data line for external i 2 c device. a18 i2cscl (pd14) i/o, t.s. this signal is connected to the serial i 2 c clock line. this line may be used off-board as an i 2 c clock line for external i 2 c device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 83 a19 pd13 i/o, t.s. pq2?s pd(13:4) port d lines. parallel i/o or cpm dedicated lines. may be used for any of their available functions. a20 pd12 a21 pd11 a22 pd10 a23 pd9 a24 pd8 a25 pd7 a26 pd6 a27 pd5 a28 pd4 a29 atmrclkdis i atm receive clock out disable. when active (h), the atmrclk output, on pin c29 of this connector, is tri-stated. when either not connected or driven low, atmrclk on pin c29, is enabled. this provides compatibility with eng revision of t/ecom communication tools. a30 expvcc o 5v supply. connected to ads?s 5v vcc plane. provided as power supply for external tool. a31 a32 b1 atmtxen# (pa31) i/o, t.s. atm transmit enabled (l). when this signal is asserted (low), while the atm port is enabled and atmtfclk is rising, an octet of data, atmtxd(7:0), is written into the transmit fifo of the pm5350. when the atm port is disabled, this line may be used for any available function of pa31. b2 atmtca (pa30) i/o, t.s. atm transmit cell available (h). when this signal is asserted (high), while the atm port is enabled, it indicates that the transmit fifo of the pm5350 is empty and ready to except a new cell. when negated, it may show either that the transmit fifo is full or close to full, depending on pm5350 internal programming. when the atm port is disabled, this line may be used for any available function of pa30. b3 atmtsoc (pa29) i/o, t.s. atm transmit start of cell (h). when this signal is asserted (high) by the pq2, while the atm port is enabled, it indicates to the pm5350 the start of a new atm cell over atmtxd(7:0), i.e., the 1?st octet is present there. when the atm port is disabled, this line may be used for any available function of pa29. table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 84 pq2fads-vr user?s manual motorola b4 atmrxen# (pa28) i/o, t.s. atm receive enable (l). when this signal is asserted (low), while the atm port is enabled and atmrfclk b goes high, on octet of data is available at the pm5350?s atmrxd(7:0) lines. when negated while atmrfclk goes high data on atmrxd(7:0) is invalid, however driven. when the atm port is disabled, this line may be used for any available function for pa28. b5 atmrsoc (pa27) i/o, t.s. atm receive start of cell (h). when this signal is asserted (high), while the atm port is enabled, it indicates, that the 1?st octet of data for the received cell is available at the pm5350?s atmrxd(7:0) lines. this line is updated over the rising edge of atmrfclk. when the atm port is disabled, this line is tristated and may be used for any available function for pa27. b6 atmrca (pa26) i/o, t.s. atm receive cell available (h). when this signal is asserted (high), while the atm port is enabled and atmrfclk goes high, it indicates that the pm5350?s receive fifo is either full or that there are 4 empty bytes left in it - pm5350 internal programming dependent. when the atm port is disabled, this line is tristated and may be used for any available function of pa26. b7 atmtxd0 (pa25) i/o, t.s. atm transmit data (7 c :0). when the atm port is enabled, this bus carries the atm cell octets, written to the pm5350?s transmit fifo. this bus is considered valid only when atmtxen# is asserted and are sampled on the rising edge of atmtfclk. when the atm port is disabled, these lines may be used for any available respective function. b8 atmtxd1 (pa24) b9 atmtxd2 (pa23) b10 atmtxd3 (pa22) b11 atmtxd4 (pa21) b12 atmtxd5 (pa20) b13 atmtxd6 (pa19) b14 atmtxd7 (pa18) b15 atmrxd7 (pa17) i/o, t.s. atm receive data (7 c :0). when the atm port is enabled, this bus carries the cell octets, read from the pm5350 receive fifo. this lines are updated on the rising edge of atmrfclk b . when the atm port is disabled, these lines are tristated and may be used for any available respective function. b16 atmrxd6 (pa16) b17 atmrxd5 (pa15) b18 atmrxd4 (pa14) b19 atmrxd3 (pa13) b20 atmrxd2 (pa12) b21 atmrxd1 (pa11) b22 atmrxd0 (pa10) table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 85 b23 pa9 i/o, t.s. pq2?s port a (9:0). parallel i/o or dedicated cpm lines. may be used for any of their available functions. b24 pa8 b25 pa7 b26 pa6 b27 pa5 b28 pa4 b29 pa3 b30 pa2 b31 pa1 b32 pa0 c1 fethtxer (pb31) i/o, t.s. fast-ethernet d transmit error (h). when the ethernet port is enabled, this signal will be asserted (high) by the pq2 when an error is discovered in the transmit data stream. when the port is operation at 100 mbps, the lxt970 responds by sending invalid code symbols on the line. when the ethernet port is disabled, this line may be used for any available function of pb31. c2 fethrxdv (pb30) i/o, t.s. fast-ethernet receive data valid (h). when this signal is asserted (high) while the fast ethernet port is enabled and fethrxck goes high, it indicates that data is valid on the mii receive data lines - fethrxd(3:0). when the fast ethernet port is disabled, this line is tristated and may be used for any available function go pb30. c3 fethtxen (pb29) i/o, t.s. fast-ethernet transmit enable (h). the pq2 will assert (high) this line, to indicate data valid on the fethtxd(3:0) lines. when the fast-ethernet port is disabled, this line may be used for any available function of pb29. c4 fethrxer (pb28) i/o, t.s. fast-ethernet receive error (h). when this signal is asserted (high) by the lxt970, while the ethernet port is enabled and fethrxck goes high, it indicates that the port is receiving invalid data symbols from the network. when the ethernet port is disabled, this line is tristated and may be used for any available function of pb28. c5 fethcol (pb27) i/o, t.s. fast-ethernet port collision detected (h). when this signal is asserted (high) by the lxt970, while the ethernet port is enabled, it indicates a collision state over the line. when the lxt970 is in full-duplex mode, this line is inactive. when the ethernet port is disabled, this line is tristated and may be used for any available function of the pb27. table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 86 pq2fads-vr user?s manual motorola c6 fethcrs (pb26) i/o, t.s. fast-ethernet carrier sense (h). when this signal is asserted (high), while the ethernet port is enabled and the lxt970 is in half-duplex mode, it indicates that either the transmit or receive media are non-idle. when the lxt970 is in either full-duplex or repeater operation, it indicates that the receive medium is non-idle. when the ethernet port is disabled, this line may be used for any available function of pb26. c7 fethtxd3 (pb25) i/o, t.s. fast ethernet transmit data (3:0). this is the mii transmit data bus. the pq2 drives these lines according to rising edge of fethtxck. when the ethernet port is disabled, these lines may be used for any available respective function. c8 fethtxd2 (pb24) c9 fethtxd1 (pb23) c10 fethtxd0 (pb22) c11 fethrxd0 (pb21) i/o, t.s. fast ethernet receive data (3:0). this is the mii receive data bus. the lxt970 drives these lines according to rising edge of fethrxck. when the ethernet port is disabled, these lines are tristated and may be used for any available respective parenthesized function. c12 fethrxd1 (pb20) c13 fethrxd2 (pb19) c14 fethrxd3 (pb18) c15 pb17 i/o, t.s. pq2?s port b (17:4) parallel i/o lines. may be used to any of their available functions. c16 pb16 c17 pb15 c18 pb14 c19 pb13 c20 pb12 c21 pb11 c22 pb10 c23 pb9 c24 pb8 c25 pb7 c26 pb6 c27 pb5 c28 pb4 c29 atmrclk o, t.s. atm receive clock. a divide by 8 of the atm line clock recovered by the atm receive logic. provided to assist circuit emulation tool. enabled only when pin a29 of this connector is either not connected or driven low. otherwise, tri-stated. table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 87 c30 gnd o digital ground. connected to main gnd plane of the ads. c31 c32 d1 pc31 i/o, t.s. pq2?s port c (31:22) parallel i/o lines. may be used to any of their available functions. d2 pc30 d3 pc29 d4 pc28 d5 pc27 d6 pc26 d7 pc25 d8 pc24 d9 pc23 d10 pc22 d11 atmtfclk (pc21) i/o, t.s. atm transmit fifo clock. upon the rising edge of this clock (driven by the pq2), while the atm port is enabled, the cell octets are written to the pm5350?s transmit fifo. this clock samples atmtxd(7:0), atmtxpty, atmtxen# and atmtsoc. when the atm port is disabled, this line may be used for any available function of pc21. d12 pc20 i/o, t.s. pq2?s parallel i/o port-c 20. parallel i/o line. may be used for any of its available functions d13 fethrxck (pc19) i/o, t.s. fast-ethernet receive clock. when the ethernet port is enabled, this clock (25 mhz for 100 mbps, 2.5 mhz for 10 mbps) is extracted from the received data and driven to the pq2 to qualify incoming receive data. when the ethernet port is disabled, this line is tristated and may be used for any available function of pc19 d14 fethtxck (pc18) i/o, t.s. fast-ethernet transmit clock. when the ethernet port is enabled, this clock (25 mhz for 100 mbps, 2.5 mhz for 10 mbps) is normally extracted from the received data and driven to the pq2 to qualify out coming transmit data. in slave mode (not used with this application) this clock should be input to the lxt970. when the ethernet port is disabled, this line is tristated and may be used for any available function of pc18 d15 pc17 i/o, t.s. pq2?s port c (17:15) parallel i/o lines. may be used to any of their available functions. d16 pc16 d17 pc15 table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 88 pq2fads-vr user?s manual motorola 7.1.5 p9, p10, p11, p15, p17, p18, p19, p24, p28,p29, p30- logic analyzer mictor connectors these are 38 pin, smt, high density, matched impedance connector made by amp. they contain d18 rs_cd1# (pc14) i/o, t.s. rs232 port 1 carrier detect (l). connected via rs232 transceiver to rs232 dtr1# input, allowing detection of a connected terminal to this port. this line is simply a pi/o input line to the pq2. when rs232 port 1 is disabled, this line is tristated and may be used for any available function of pc14. d19 pc13 i/o, t.s. pq2?s port c 13 parallel i/o line. may be used to any of its available functions. d20 rs_cd2# (pc12) i/o, t.s. rs232 port 2 carrier detect (l). connected via rs232 transceiver to rs232 dtr2# input, allowing detection of a connected terminal to this port. this line is simply a pi/o input line to the pq2. when rs232 port 2 is disabled, this line is tristated and may be used for any available function of pc12. d21 pc11 i/o, t.s. pq2?s port c 11 parallel i/o line. may be used to any of its available functions. d22 fethmdc (pc10) i/o, t.s. fast-ethernet port management data clock. this slow clock (s/w generated) qualifies the management data i/o to read / write the lxt970?s internal registers. when the ethernet port is disabled, this line may be used for any available function of pc10. d23 fethmdio (pc9) i/o, t.s. fast-ethernet port management data i/o. this signal serves as bidirectional serial data line, qualified by fethmdc, to allow read / write the lxt970?s internal registers. when the ethernet port is disabled, this line may be used for any available function of pc9. d24 pc8 i/o, t.s. pq2?s port c (8:0) parallel i/o lines. may be used to any of their available functions. d25 pc7 d26 pc6 d27 pc5 d28 pc4 d29 pc3 d30 pc2 d31 pc1 d32 pc0 a. the functions in parenthesis, are pq2?s parallel i/os. b. normally connected to atmtfclk on the ads. c. ms bit. d. for that matter, both 100-base-t and 10-base-t. table 7-4. p7 - cpm expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 89 the pq2 60x bus, 60x system and memory controller signals, unbuffered. the pinout of these connectors is shown in the schematics. for signal description of these connectors, see the pq2 user?s manual. 7.1.6 p10, p8, p9 - pci connectors these are 2 x 62 , 3.3v keyed, 32 bit pci connectors. the pinout of each connector is available in table 7-5. for signal descriptions for these connectors, see the pci v2.2 standard. table 7-5. p12, p13, p14 - pci connectors pin number side b comments side a comments 1 -12v not connected trst# 2tck +12v 3ground tms 4tdo tdi 5+5v +5v 6+5v inta# 7 intb# not connected intc# not connected 8 intd# not connected +5v 9 prsnt1# connected to gnd reserved not connected 10 reserved not connected +3.3v(i/o) 11 prsnt2# connected to gnd reserved not connected 12 connector key 3.3 volt key connector key 3.3 volt key 13 connector key 3.3 volt key connector key 3.3 volt key 14 reserved not connected 3.3vaux not connected 15 ground rst# 16 clk +3.3v (i/o) 17 ground gnt# 18 req# ground 19 +3.3v (i/o) pme# not connected 20 ad[31] ad[30] 21 ad[29] +3.3v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 90 pq2fads-vr user?s manual motorola 22 ground ad[28] 23 ad[27] ad[26] 24 ad[25] ground 25 +3.3v ad[24] 26 c/be[3]# idsel 27 ad[23] +3.3v 28 ground ad[22] 29 ad[21] ad[20] 30 ad[19] ground 31 +3.3v ad[18] 32 ad[17] ad[16] 33 c/be[2]# +3.3v 34 ground frame# 35 irdy# ground 36 +3.3v trdy# 37 devsel# ground 38 ground stop# 39 lock# not connected +3.3v 40 perr# sdone not connected 41 +3.3v sbo# not connected 42 serr# ground 43 +3.3v par 44 c/be[1]# ad[15] 45 ad[14] +3.3v 46 ground ad[13] 47 ad[12] ad[11] 48 ad[10] ground 49 m66en coupled to gnd, using a 0.01uf capacitor ad[09] 50 ground ground 51 ground ground table 7-5. p12, p13, p14 - pci connectors pin number side b comments side a comments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 91 7.1.7 p5 - atx power supply connector this is a standard atx form factor power connector as described in table 7-6. 7.1.8 p21,p23,p25 - mach/lattice isp connector this is a 10 pin generic 0.100" pitch header connector, providing in system programming (isp) 52 ad[08] c/be[0]# 53 ad[07] +3.3v 54 +3.3v ad[06] 55 ad[05] ad[04] 56 ad[03] ground 57 ground ad[02] 58 ad[01] ad[00] 59 +3.3v (i/o) +3.3v (i/o) 60 ack64# not connected req64# not connected 61 +5v +5v 62 +5v +5v table 7-6. p5 - atx power supply connector pin signal pin signal 1 +3.3vdc 11 +3.3vdc-sense 2 +3.3vdc 12 -12vdc 3 groung 13 groung 4 +5vdc 14 power_on 5 groung 15 groung 6 +5vdc 16 groung 7 groung 17 groung 8 power_ok 18 -5vdc 9 +5vstand_by 19 +5vdc 10 +12vdc 20 +5vdc table 7-5. p12, p13, p14 - pci connectors pin number side b comments side a comments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 92 pq2fads-vr user?s manual motorola capability for latice made programmable logic on board. the pinout of p25 is shown in table 7-7. 7.1.9 p27 - system expansion connector p27 is a 128 pin, 90 0 , din 41612 connector, which provides a minimal system i/f required to interface various types of communication transceivers. this connector contains 16 bit (lower ppc bus) address lines, 16 bit (higher ppc bus) data lines plus useful gpcm and upm control lines. the pinout of p17 is shown in table 7-8. table 7-7. p25 - lattice isp connector pin no. signal name attribute description 1 isptck i isp test port clock. this clock shifts in / out data to / from the programmable logic jtag chain. 2n.c. - not connected. 3 isptms i isp test mode select. this signal qualified with isptck, changes the state of the prog. logic jtag machine. 4 gnd o digital gnd. main gnd plane. 5 isptdi i isp transmit data in. this is the prog. logic?s jtag serial data input, sampled on the rising edge of tck. 6 vcc o 5v power supply bus. 7 isptdo o isp transmit data output. this the prog. logic?s jtag serial data output driven by falling edge of tck. 8 gnd o digital gnd. main gnd plane. 9n.c. - not connected. 10 n.c. - not connected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 93 table 7-8. p27 - system expansion connector pin no. signal name attribute description a1 expa16 o expansion address (16 a :31). this is a latched-buffered version of the pq2?s ppc address lines (16:31), provided for external tool connection. to avoid reflection these lines are series terminated with 43 ? resistors. a2 expa17 a3 expa18 a4 expa19 a5 expa20 a6 expa21 a7 expa22 a8 expa23 a9 expa24 a10 expa25 a11 expa26 a12 expa27 a13 expa28 a14 expa29 a15 expa30 a16 expa31 a17 exp12v o these can be connected to the positive 12v source from the pci edge connector thru j3. this line is fused by a 0.5a ressetable poly-switch. a18 a19 n.c. - not connected. a20 exp3.3v o 3.3v power out. these lines are connected to the main 3.3v plane of the pq2pciai-ads, this, to provide 3.3v power where necessary for external tool connected. a21 a22 a23 a24 a25 n.c. - not connected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 94 pq2fads-vr user?s manual motorola a26 expvcc o 5v supply. connected to ads?s 5v vcc plane. provided as power supply for external tool. a27 a28 a29 a30 a31 a32 b1 gnd o digital ground. connected to main gnd plane of the ads. b2 b3 b4 tstat0 i tool status (0 a :7). these lines may be driven by an external tool to be read via bcsr2 of the ads. these lines are pulled-up on the ads, by 10 k ? resistors. see also table 4-10. "bcsr2 description" on page 56. b5 tstat1 b6 tstat2 b7 tstat3 b8 tstat4 b9 tstat5 b10 tstat6 b11 tstat7 b12 toolrev0 i tool revision (0 a :3). these lines should be driven by an external tool with the tool revision code, to be read via bcsr2 of the ads. these lines are pulled-up on the ads, by 10 k ? resistors. see also table 4-10. "bcsr2 description" on page 56. b13 toolrev1 b14 toolrev2 b15 toolrev3 b16 extoli0 i external tool identification (0 a :3). these lines should be driven by an external tool with the tool identification code, to be read via bcsr2 of the ads. these lines are pulled-up on the ads, by 10 k ? resistors. see also table 4-10. "bcsr2 description" on page 56 b17 extoli1 b18 extoli2 b19 extoli3 b20 n.c. - not connected b21 exp3.3v o 3.3v power out. these lines are connected to the main 3.3v plane of the pq2pciai-ads, this, to provide 3.3v power where necessary for external tool connected. b22 b23 b24 table 7-8. p27 - system expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 95 b25 n.c. - not connected b26 expvcc o 5v supply. connected to ads?s 5v vcc plane. provided as power supply for external tool. b27 b28 b29 b30 b31 b32 c1 gnd o digital ground. connected to main gnd plane of the ads. c2 clk8 o buffered system clock.. c3 gnd o digital ground. connected to main gnd plane of the ads. c4 btoolcs1# o buffered tool chip select 1 (l). this is a buffered pq2?s cs6# line, reserved for an external tool. c5 btoolcs2# o buffered tool chip select 2 (l). this is a buffered pq2?s cs7# line, reserved for an external tool. c6 gnd o digital ground. connected to main gnd plane of the ads. c7 atmen# o atm port enable (l). this line enables the atm port uni?s output lines towards the pq2. an external tool, using the same pins as does the atm port should consult this signal before driving the same lines. failure to do so might result in permanent damage to the pm5350 atm uni. c8 atmrst# o atm port reset (l). this signal resets the atm uni (pm5350). an external tool may use this signal to its benefit. c9 fethrst# o ethernet port reset (l). this signal resets the lxt970 ethernet transceiver. an external tool may use this signal to its benefit. c10 hreset# i/o, o.d. pq2?s hard reset (l). when asserted by an external h/w, generates hard-reset sequence for the pq2. during that sequence, asserted by the pq2 for 512 system clocks. pulled up on the ads using a 1k ? resistor. when driven by an external tool, must be driven with an open drain gate. failure to do so might result in permanent damage to the pq2 and / or to ads logic. c11 irq6# i interrupt request 6 (l). connected to pq2?s dp6/cse0/irq6# signal. pulled up on the ads with a 10 k ? resistor. this line is shared with the atm uni?s interrupt line and therefore, when driven by an external tool, must be driven with an open drain gate. failure to do so may result in permanent damage to the pq2 or to ads logic. table 7-8. p27 - system expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 96 pq2fads-vr user?s manual motorola c12 irq7# i interrupt request 7 (l). connected to pq2?s dp7/cse1/irq7# signal. pulled up on the ads with a 10 k ? resistor. this line is shared with the fast ethernet transceiver?s interrupt line and therefore, when driven by an external tool, must be driven with an open drain gate. failure to do so might result in permanent damage to the pq2 and / or to ads logic. c13 gnd o digital ground. connected to main gnd plane of the ads. c14 expd0 i/o, t.s. expansion data (0 a :15). this is a double buffered version of the ppc bus d(0:15) lines, controlled by on-board logic. these lines will be driven only if btoolcs1# or btoolcs2# are asserted. otherwise they are tristated. the direction of these lines is determined by buffered bctl0, in function of w/r#. c15 expd1 c16 expd2 c17 expd3 c18 expd4 c19 expd5 c20 expd6 c21 expd7 c22 expd8 c23 expd9 c24 expd10 c25 expd11 c26 expd12 c27 expd13 c28 expd14 c29 expd15 c30 n.c. - not connected c31 c32 d1 gnd o digital ground. connected to main gnd plane of the ads. d2 d3 d4 expwe0# o expansion write enable (0:1) (l). these are buffered gpcm write enable lines (0:1). they are meant to qualify writes to gpcm controlled 8/16 data bus width memory devices. this to provide eased access to various communication transceivers. expwe0# controls expd(0:7) while expwe1# controls expd(8:15). these lines may also function as upm controlled byte select lines, which allow control over almost any type of memory device. d5 expwe1# table 7-8. p27 - system expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user?s manual 97 d6 gnd o digital ground. connected to main gnd plane of the ads. d7 expgl0# o expansion general purpose lines (0:5) (l). these are buffered gpl(0:5)# lines which assist upm control over memory device if necessary. these are output only signals and therefore, do not support h/ w controlled upm waits. d8 expgl1# d9 expgl2# d10 expgl3# d11 expgl4# d12 expgl5# d13 gnd o digital ground. connected to main gnd plane of the ads. d14 expale o expansion address latch enable (h). this is the buffered pq2?s ale, provided for expansion board?s use. d15 expctl0 o expansion control line 0. this line is a buffered version of pq2?s bctl0 (bus control line 0) which serves as w/r#, provided for expansion board?s use. d16 gnd o digital ground. connected to main gnd plane of the ads. d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 a.ms bit. table 7-8. p27 - system expansion connector pin no. signal name attribute description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 98 pq2fads-vr user?s manual motorola 7.1.10 p2 - usb connector this is a four pin standard usb connector type-a. the pinout is shown in . table 7-9. p2 - usb connector 7.2 programmable logic equations there are 4 programmable logic devices on board. 1. u35 - bcsr and pci interrupt controller 2. u41 - power switch debounce 7.2.1 u35 - bcsr code ! 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' 7" 8 &" " 739 :/7 $% ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% & ' "( ) "* &"' + #& #"+" ","(/<.-=./ *1 pin no. signal name description 1 5v power power line of the usb cable 2 d- twisted-pair transmit data negative 3 d+ twisted-pair receive data positive 4 gnd ground connection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 99 $%23"! ' " 8 &" " 9; $%2", >"! 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" "#6bc b- d 3 fb--d /b<= ) " ,d -b ) " ,d b-0 ) " ,d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 100 pq2fads-vr user ? s manual motorola 0b<< ) " ,d cb-: ) " ,d =b-c ) " ,d :b:/ ) " ,d <b< ) " ,d b:: ) " ,d fb< ) " ,d -/b &6b-0/ ) " "#75!''" d$' &" 5 "; 8 !&6bc ) " "#75!''" d$:/5! ," 5 " g6b-- ) " "#75!''" d$5! # ," 5 " " 6b- ) " "#75!''" d$ 5! ," 5 " # , /6bcc ) " "#75!''" d$ ! , /' , .+> ! # , -6b0 ) " "#75!''" d$ ! , -' , .+> ! 3 , 6b-0c ) " "#75!''" d$ ,! " 5 " 3 , 6b--c ) " ,d$ ,! 5 " 3 ,-:6b ) " "#75!''" d$3-:5 " 5 " 3 ,6b--: ) " ,d$35 " 5 " 3 , # " 96bc ) " "#75!''" d$3 # " 9" 5 " 3 ,! 96b= ) " ,d$3! 9" 5 " 3 , 6b ) " "#75!''" d$ ,! "" 5 3 , ! 6b<: ) " ,d$ ,! "" >" 5) "# " $ 5) 6 6b= ) " "#75!''" d$" 5 " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 101 6b: ) " ,d$ 5 " 6b : ) " "#75!''" d$ """ " + 6b-00 ) " ,d$ + """ " eb< ) " "#75!''" d$ "e #"" " 8 & -6bf ) " "#75!''" d$' " &" " ;-" 5 " 8 & -6b 0 ) " ,d$' " &" " ;- 5 " 8 & 6bc/ ) " "#75!''" d$' " &" " ; " 5 " 8 & 6b 6b ) " "#75!''" d$' " &" " ; "" 5 8 & ! 6b--/ ) " ,d$' " & "" >" 5) $ "# " 5) 6 8 &" -b-/ ) " ,d$8; &;!- 8 &" b: ) " ,d$8; &;! 0 -6b0 ) " "#75!''" d$ 0 -" 5 " 0 -6b=: ) " ,d$ 0 - 5 " 0 6b0 ) " "#75!''" d$ 0 " 5 " 0 6b ) " ,d$ 0 5 " 6 "6b-fd$ !" " 6!6bf ) " ,d$ !3" " g /b:<d$a / g -b:=d$a - g b:-d$a g 0b=fd$a 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 102 pq2fads-vr user ? s manual motorola 6 6b-// ) " ,75!''" d$ " ! ( ;;* 6b36bf<d$ " ! ' , 6b6b- :d$ " ! ' , 6b6b- =d$ " ! ' , 6b6b- /d$ " ! ' , $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% !"# " & 2" " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6bf ) " ,d c6b- ) " ,d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%8 &.3 " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 86-b=<d 86 b==d 860bc=d 86cbc0d /6b=cd$' &."" ,& 2" " ! c6bfcd$"" ,.' && 2" " ! ,6b-0< ) " ,d$& 2" " 8 &-6b-cc ) " ,d$8 &5 g-& 2" " 8 & 6b-0 ) " ,d$8 &5 g & 2" " 8 &06b-c0 ) " ,d$8 &5 g0& 2" " 8 &c6b-c/ ) " ,d$8 &5 gc& 2" " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 103 $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%=0c3b3 " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3 , 6b--fd 3 , ! 6b: ) " ,d$ ", >" '& ' $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%"" h " ! # ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6bc-d $ '6b ) " ,d "" , " " " ; /b00d$ " " b;; '"" ;; -b0-d$ " " b;; '"" ;; "" 6b- ) " ,d$3 ! & "" ! ! (;;* ' "" 6b-< ) " ,d$3 ! ' "" ! ! (;;* 35 /b0/d$ " " b;; '35 ;; 35 -b fd$ " " b;; '35 ;; b b ) " ,d$" 5 ";;b b6b / ) " ,d$3 ! b (7;;* $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% !''" 5 " "" ' #! ! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 104 pq2fads-vr user ? s manual motorola 36b-/ d$ '" 3g + "#"; !' 6b= ) " ,7 >" d$ 5!''" " 5 " -6b <d$ ,, "-; 6b -d$ ,, " ; !' 6bf- ) " ,7 >" d$ 5!''" " 5 " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% "" ' #! # $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 5 6"> "6b--d$" " .83 65 "> " 5 ' bf0d$" " "" ' #! ! " $ .83 ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3! ) ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%) ", "" ' #! ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "b ) " ,d$ 5! ! ! " 5 " "; "b ) " ,d$ 5! ! ! " 5 " "; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% "# " 5 " " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 105 $%"" h " ! # ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "5-b ) "g"" 7 ,d$ "" !&5! "5 ! " 35 "5-b ) "g"" 7 ,d$5 !&5! "5 ! " "" b ) " ,d$" 5 ";;& "" ' "" b ) " ,d$" 5 ";; ' "" $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% 5!''" " 5 "; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ) "" 6b ) " "#75!''" d$) & i"& "" ) "" 6b ) " "#75!''" d$ !5 ") & i"& "" '' 7 '' -7 '' /b ) " "#75!''" d$ 5!'" & 2 '' ! " ''b ) " ,d$ " , ! ' & ! " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% +" "" $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6 6b ) " "#75!''" d$) " "" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! "# " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 3b ) " "#7 >" d$ / " ! 3 / b ) " "#7 >" d$ / " ! / b ) " "#7 >" d$ / " ! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 106 pq2fads-vr user ? s manual motorola / b ) " "#7 >" d$ / " ! - 3b ) " "#7 >" d$ - " ! 3 - b ) " "#7 >" d$ - " ! - b ) " "#7 >" d$ - " ! - b ) " "#7 >" d$ - " ! 3b ) " "#7 >" d$ " ! 3 b ) " "#7 >" d$ " ! b ) " "#7 >" d$ " ! b ) " "#7 >" d$ " ! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! g"# " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 3gb ) " "#75!''" d$ / " ! 3g / gb ) " "#75!''" d$ / " ! g / gb ) " "#75!''" d$ / " ! g / gb ) " "#75!''" d$ / " ! g - 3gb ) " "#75!''" d$ - " ! 3g - gb ) " "#75!''" d$ - " ! g - gb ) " "#75!''" d$ - " ! g - gb ) " "#75!''" d$ - " ! g 3gb ) " "#75!''" d$ " ! 3g gb ) " "#75!''" d$ " ! g gb ) " "#75!''" d$ " ! g gb ) " "#75!''" d$ " ! g $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! "j!" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 107 6 " ! b ) " ,d$#" " " " ! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " " " !; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% a"" " "b ) " ,d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 777kl-7/7;;7;k;d 77l;;7;;7;;d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3bl-d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% # # ! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3lm3 <;;3 fnd lm/;; 8 !&67 g67 " 67 # , /67 # , -67 3 , 67 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 108 pq2fads-vr user ? s manual motorola 3 , 67 3 ,-:67 3 , # " 967 8 & -67 8 & -67 8 & 67 8 & 67 0 -67 0 67 67 67 end " /lm/7 /7 &67 8 !&67 g67 " 67 # , /67 # , -6nd " -lm5 ' 7 5 6"> "67 3 , 67 3 , 6;'57 8 & -67 8 & -6;'57 0 -67 0 6nd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 109 " 0lm 67 67 e7 8 & 67 8 & 6;'57 3 ,-:67 3 , # " 967 6 "6nd >" "#lm &67 8 !&67 g67 " 67 # , /67 # , -67 3 , 67 3 ,-:67 3 , # " 967 8 & -67 8 & 67 0 -67 0 67 67 67 end g" "#lm &67 8 !&67 g67 " 67 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 110 pq2fads-vr user ? s manual motorola # , /67 # , -67 3 , 67 3 , 67 3 ,-:67 3 , # " 967 8 & -67 8 & 67 8 & -67 8 & 67 0 -67 0 67 67 67 end "#lm / 37 / 7 / 7 / 7 - 37 - 7 - 7 - 7 37 7 7 nd g"#lm / 3g7 / g7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 111 / g7 / g7 - 3g7 - g7 - g7 - g7 3g7 g7 g7 gnd lm -67 6nd 8 &! lm8 &c678 &0678 & 678 &-6nd "" lm "" 67 ' "" 6nd "" lm "" 7 ' "" nd lm3 , ! 678 & ! -678 & ! 6nd lm -7 /nd 35 lm35 -735 /nd "5 ! "lm "5-735 "5-nd ) "" lm) "" 67) "" 6nd !"lm 67 -7 /735 -735 /nd '' lm '' 7 '' -7 '' /nd 86lm86c7860786 786-nd l m/67c67 "#67 673 , 67 -67 6nd !' lm !' 67 !' 6nd '3lm3 <73 nd o ' "' 3 p '#) "/lm/7/7/7/7-7-7/7/nd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 112 pq2fads-vr user ? s manual motorola '#) "-lm-7/7-7-7/7/7-7/nd '#) " lm/7/7/7/7/7-7-7/nd '#) "0lm/7/7/7/7 g /7 g -7 g 7 g 0nd q o '"' 3 p '#) "/lm/7/7/7-7-7-7/7/nd '#) "-lm-7/7-7-7/7/7-7/nd '#) " lm/7/7/7/7/7-7-7/nd '#) "0lm/7/7/7/7 g /7 g -7 g 7 g 0nd q $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% +" "" "' $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% b663el/d b6l(6 6;'5llb663e*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%"# " 3""' $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% /63l/d -63l-d 63l d 063l0d c63lcd e@6466/l(r "#6hre 6h664hr3 <hr3 h r3 f*d e@6466-l(r "#6hre 6h664hr3 <hr3 h3 f* f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 113 d e@6466 l(r "#6hre 6h664hr3 <h3 hr3 f* d e@64660l(r "#6hre 6h664hr3 <h3 h3 f* d e@6466cl(r "#6hre 6h664h3 <hr3 hr3 f* d e@6366/l(r "#6hr664hr3 <hr3 hr3 f*d e@6366-l(r "#6hr664hr3 <hr3 h3 f*d e@6366 l(r "#6hr664hr3 <h3 hr3 f*d e@63660l(r "#6hr664hr3 <h3 h3 f*d e@6366cl(r "#6hr664h3 <hr3 hr3 f*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%/"' ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3 6b l/d 3 68 l/d 3 6al/d 3 63l/d @b3636bl/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% +" "'! 3 # ," %%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3 6b 6b683l 3 6b d 3 68 6b683lr 3 68 d 3 6a6b683lr 3 6ad f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 114 pq2fads-vr user ? s manual motorola 3 636b683lr 3 63d @b363/6b683lr@b3636bd @b363-6b683lr@b3636bd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% 3 # ," %%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3 6b 6336lm nd 3 68 6336lm0nd 3 6a6336lmcnd 3 636336lm=nd @b363/6336lm:nd @b363-6336lm 0 6-6b3l/d 0 6 6b3l/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 115 $%%%%%%% +" "'! 3 # ," %%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 36b36b683lr36b3d 366b683lr3663ed 8 -6b36b683lr8 -6b3d 8 -66b683lr8 -663ed 0 6-6b36b683lr 0 6-6b3d 0 6 6b36b683lr 0 6 6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% 3 # ," %%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% b8646336lm/nd 6e6336lm-nd 36b36336lm nd 366336lm0nd 8 -6b36336lmcnd 8 -66336lm=nd 0 6-6b36336lm:nd 0 6 6b36336lm 663el/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 116 pq2fads-vr user ? s manual motorola 3-:6b3l/d 36b@6 96b3l/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% +" "'! 3 # ," %%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6b36b683lr6b3d 66b683l66 @ d 6e6b683lr6e6bd 8 6b36b683lr8 6b3d 8 66b683lr8 663ed 3-:6b36b683lr3-:6b3d 36b@6 96b36b683l36b@6 96b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% 3 # ," %%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6b36336lm/nd 66336lm-nd 6e6336lm nd 8 6b36336lm0nd 8 66336lmcnd 3-:6b36336lm=nd 36b@6 96b36336lm:nd 366336lm <hr3 hr3 f*d e@646 g"#l(r 6hre 6h664hr3 <hr3 h3 f*d e@636 "#l(r 6hr664hr3 <hr3 hr3 f*d e@636 g"#l(r 6hr664hr3 <hr3 h3 f*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! "j!" "' ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $ j"l( / 3s $ / s $ / s $ / s $ - 3s $ - s $ - s $ - s $ 3s $ s $ s $ *d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! "# " "' ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 363 >"l-d$ / " ! 3" " / 63 >"l-d$ / " ! " " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 118 pq2fads-vr user ? s manual motorola / 63 >"l-d$ / " ! " " / 63 >"l-d$ / " ! " " - 363 >"l-d$ - " ! 3" " - 63 >"l-d$ - " ! " " - 63 >"l-d$ - " ! " " - 63 >"l-d$ - " ! " " 363 >"l-d$ " ! 3" " 63 >"l-d$ " ! " " 63 >"l-d$ " ! " " 63 >"l-d$ " ! " " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% +" "'! 3 # ," %%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 36b683lr / 363 >"d / 6b683lr / 63 >"d / 6b683lr / 63 >"d / 6b683lr / 63 >"d - 36b683lr - 363 >"d - 6b683lr - 63 >"d - 6b683lr - 63 >"d - 6b683lr - 63 >"d 36b683lr 363 >"d 6b683lr 63 >"d 6b683lr 63 >"d 6b683lr 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% 3 # ," %%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 36336lm/nd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 119 / 6336lm-nd / 6336lm nd / 6336lm0nd - 36336lmcnd - 6336lm=nd - 6336lm:nd - 6336lm 6336lmfnd 6336lm-/nd 6336lm--nd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! g"# " "' ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 3g63 >"l-d$ / " ! 3g" / g63 >"l-d$ / " ! g" / g63 >"l-d$ / " ! g" / g63 >"l-d$ / " ! g" - 3g63 >"l-d$ - " ! 3g" - g63 >"l-d$ - " ! g" - g63 >"l-d$ - " ! g" - g63 >"l-d$ - " ! g" 3g63 >"l-d$ " ! 3g" g63 >"l-d$ " ! g" g63 >"l-d$ " ! g" g63 >"l-d$ " ! g" $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 120 pq2fads-vr user ? s manual motorola $%%%%%%% +" "'! 3 # ," %%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 3g6b683l / 3g63 >"d / g6b683l / g63 >"d / g6b683l / g63 >"d / g6b683l / g63 >"d - 3g6b683l - 3g63 >"d - g6b683l - g63 >"d - g6b683l - g63 >"d - g6b683l - g63 >"d 3g6b683l 3g63 >"d g6b683l g63 >"d g6b683l g63 >"d g6b683l g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%% 3 # ," %%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% / 3g6336lm/nd / g6336lm-nd / g6336lm nd / g6336lm0nd - 3g6336lmcnd - g6336lm=nd - g6336lm:nd - g6336lm g6336lmfnd g6336lm-/nd g6336lm--nd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 121 $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%8 &" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 83 6b363el/d $ &" "" "" " " #' &"5" + ' $ "" 5"! "+ & " ; f/ /l(86ll*d$- ) "5 g <0 -l(86ll *d$-) "5 g <0 c l(86ll-*d$ ) "5 g <0 cl(86ll/*d$c) "5 g 83 63ba-l( f/ /s <0 -s (<0 c hr3*s (<0 chr3<hr3**d 83 63ba l((<0 c h3*s (<0 chr3<h3**d 83 63ba0l(3<hr3h<0 c*d 83 63bacl(3<h3h<0 c*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3b" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%"" " ; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 122 pq2fads-vr user ? s manual motorola $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3663el/d 8663el/d 3663l() "" 6;'5ll 3663e*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% 5!''" " 5 "; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 8863l-d 886b3lr8863d 886 688l( '' ;'5rl/*d$ &"" ) "j! "' "+" $ "' "> "("#5 *,) $ " + & &"' &."" , b68683 663lre 6h(r/6src6*hr664h ) "" 6;'5d $" '' &."" , ") "; $ ! #& "" ' # b6866b6b63lre 6hr 6hr664d $" ' " ! " ") "; b686363lre 6hr3 , 6hr664d$" ' ,! ,. .' ") " b686 69l(re 6h/6hc6h3 , 6h 6s re 6hr3 , 6h664s re 6hr -6h664s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 123 re 6hr 6h664s re 6h(r/6src6*h664s re 6hr 6h664*d $ &" " ,! + " -+ " + " $' &."" ,+ " + " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% "" ' #! # $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 68@6b6l(5 ' ll-*d$ '4 66b683 l((5 ' ll/*h(5 6"> "6ll/**d $ '4 " 83 6b683 l((5 ' ll-*h(5 6"> "6ll/**d $ '4 " 83 66b6l((5 ' ll/*h(5 6"> "6ll-**d $ '4 " 6b6l((5 ' ll-*h(5 6"> "6ll-**d $ '4 " 3663bl(( "" 6ll/*h() "" 6;'5ll/*h () "" 6;'5ll-**d /63l(/6ll/*d c63l(c6ll/*d 868@6963l(/63hr) "" 6;'5h( '3 ll/*h 68@6b6hr664*d b68@6963l(/63hr) "" 6;'5h( '3 ll-*h 68@6b6hr664*d 68@6963l(/63hr) "" 6;'5h( '3 ll *h 68@6b6hr664*d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 124 pq2fads-vr user ? s manual motorola 8 68@6963l(/63hr) "" 6;'5h( '3 ll0*h 68@6b6hr664*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%j! 7 " # ,;% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! g" "#; gl9ad g" "#; l/d g" "#; l/d >" "#; "lt&''''d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%/ $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , &6 " 3 6b 1 '(e@6466/h ( 3 6b 6336; llr 3 6b *h (rb6s( 3 6b 6b683rl 3 6b **s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 125 (b6h( 3 6b 6b683llr 3 6b *** &" r 3 6b " " 3 6b d "r 3 6b 1 '(e@6466/h ( 3 6b 6336; ll 3 6b *h (rb6s( 3 6b 6b683rlr 3 6b **s (b6h( 3 6b 6b683ll 3 6b *** &" 3 6b " " r 3 6b d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 8 !&6 " 3 68 1 '(e@6466/h ( 3 68 6336; llr 3 68 *h (rb6s( 3 68 6b683rl 3 68 **s (b6h( 3 68 6b683llr 3 68 *** &" r 3 68 " " 3 68 d "r 3 68 1 '(e@6466/h ( 3 68 6336; ll 3 68 *h (rb6s( 3 68 6b683rlr 3 68 **s (b6h( 3 68 6b683ll 3 68 *** &" 3 68 " " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 126 pq2fads-vr user ? s manual motorola r 3 68 d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , g6 " 3 6a1 '(e@6466/h ( 3 6a6336; llr 3 6a*h (rb6s( 3 6a6b683rl 3 6a**s (b6h( 3 6a6b683llr 3 6a*** &" r 3 6a " " 3 6ad "r 3 6a1 '(e@6466/h ( 3 6a6336; ll 3 6a*h (rb6s( 3 6a6b683rlr 3 6a**s (b6h( 3 6a6b683ll 3 6a*** &" 3 6a " " r 3 6ad $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , " 6 " 3 631 '(e@6466/h ( 3 636336; llr 3 63*h (rb6s( 3 636b683rl 3 63**s (b6h( 3 636b683llr 3 63*** &" r 3 63 " " 3 63d "r 3 631 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 127 '(e@6466/h ( 3 636336; ll 3 63*h (rb6s( 3 636b683rlr 3 63**s (b6h( 3 636b683ll 3 63*** &" 3 63 " " r 3 63d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , # , /6 "@b3636b1 '(e@6466/h (@b363/6336; llr@b3636b*h (rb6s(@b363/6b683rl@b3636b**s (b6h(@b363/6b683llr@b3636b*** &" r@b3636b " " @b3636bd "r@b3636b1 '(e@6466/h (@b363/6336; ll@b3636b*h (rb6s(@b363/6b683rlr@b3636b**s (b6h(@b363/6b683ll@b3636b*** &" @b3636b " " r@b3636bd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , # , -6 "@b3636b1 '(e@6466/h (@b363-6336; llr@b3636b*h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 128 pq2fads-vr user ? s manual motorola (rb6s(@b363-6b683rl@b3636b**s (b6h(@b363-6b683llr@b3636b*** &" r@b3636b " " @b3636bd "r@b3636b1 '(e@6466/h (@b363-6336; ll@b3636b*h (rb6s(@b363-6b683rlr@b3636b**s (b6h(@b363-6b683ll@b3636b*** &" @b3636b " " r@b3636bd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%- "& " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,3 , 6 "36b31 '(e@6466-h (36b36336; llr36b3*h (rb6s(36b36b683rl36b3**s (b6h(36b36b683llr36b3*** &" r36b3 " " 36b3d "r36b31 '(e@6466-h (36b36336; ll36b3*h (rb6s(36b36b683rlr36b3**s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 129 (b6h(36b36b683ll36b3*** &" 36b3 " " r36b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,3 , 6 "3663e1 '(e@6466-h (366336; llr3663e*h (rb6s(366b683rl3663e**s (b6h(366b683llr3663e*** &" r3663e " " 3663ed "r3663e1 '(e@6466-h (366336; ll3663e*h (rb6s(366b683rlr3663e**s (b6h(366b683ll3663e*** &" 3663e " " r3663ed $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,8 & -6 "8 -6b31 '(e@6466-h (8 -6b36336; llr8 -6b3*h (rb6s(8 -6b36b683rl8 -6b3**s (b6h(8 -6b36b683llr8 -6b3*** &" r8 -6b3 " " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 130 pq2fads-vr user ? s manual motorola 8 -6b3d "r8 -6b31 '(e@6466-h (8 -6b36336; ll8 -6b3*h (rb6s(8 -6b36b683rlr8 -6b3**s (b6h(8 -6b36b683ll8 -6b3*** &" 8 -6b3 " " r8 -6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,8 & -6 "8 -663e1 '(e@6466-h (8 -66336; llr8 -663e*h (rb6s(8 -66b683rl8 -663e**s (b6h(8 -66b683llr8 -663e*** &" r8 -663e " " 8 -663ed "r8 -663e1 '(e@6466-h (8 -66336; ll8 -663e*h (rb6s(8 -66b683rlr8 -663e**s (b6h(8 -66b683ll8 -663e*** &" 8 -663e " " r8 -663ed $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 0 -6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 131 " 0 6-6b31 '(e@6466-h ( 0 6-6b36336; llr 0 6-6b3*h (rb6s( 0 6-6b36b683rl 0 6-6b3**s (b6h( 0 6-6b36b683llr 0 6-6b3*** &" r 0 6-6b3 " " 0 6-6b3d "r 0 6-6b31 '(e@6466-h ( 0 6-6b36336; ll 0 6-6b3*h (rb6s( 0 6-6b36b683rlr 0 6-6b3**s (b6h( 0 6-6b36b683ll 0 6-6b3*** &" 0 6-6b3 " " r 0 6-6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 0 6 " 0 6 6b31 '(e@6466-h ( 0 6 6b36336; llr 0 6 6b3*h (rb6s( 0 6 6b36b683rl 0 6 6b3**s (b6h( 0 6 6b36b683llr 0 6 6b3*** &" r 0 6 6b3 " " 0 6 6b3d "r 0 6 6b31 '(e@6466-h(3 ,-:6h3 ,! 96*h ( 0 6 6b36336; ll 0 6 6b3*h (rb6s( 0 6 6b36b683rlr 0 6 6b3**s (b6h( 0 6 6b36b683ll 0 6 6b3*** &" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 132 pq2fads-vr user ? s manual motorola 0 6 6b3 " " r 0 6 6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%0 "& " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 6 "6b31 '(e@64660h (6b36336; llr6b3*h (rb6s(6b36b683rl6b3**s (b6h(6b36b683llr6b3*** &" r6b3 " " 6b3d "r6b31 '(e@64660h3 ,-:6h (6b36336; ll6b3*h (rb6s(6b36b683rlr6b3**s (b6h(6b36b683ll6b3*** &" 6b3 " " r6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 6 "66 @ 1 '(e@64660h (66336; llr66 @ *h (rb6s(66b683rl66 @ **s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 133 (b6h(66b683llr66 @ *** &" r66 @ " " 66 @ d "r66 @ 1 '(e@64660h (66336; ll66 @ *h (rb6s(66b683rlr66 @ **s (b6h(66b683ll66 @ *** &" 66 @ " " r66 @ d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,e "6e6b1 '(e@64660h (6e6336; llr6e6b*h (rb6s(6e6b683rl6e6b**s (b6h(6e6b683llr6e6b*** &" r6e6b " " 6e6bd "r6e6b1 '(e@64660h (6e6336; ll6e6b*h (rb6s(6e6b683rlr6e6b**s (b6h(6e6b683ll6e6b*** &" 6e6b " " r6e6bd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 134 pq2fads-vr user ? s manual motorola "6 # ,8 & 6 "8 6b31 '(e@64660h (8 6b36336; llr8 6b3*h (rb6s(8 6b36b683rl8 6b3**s (b6h(8 6b36b683llr8 6b3*** &" r8 6b3 " " 8 6b3d "r8 6b31 '(e@64660h (8 6b36336; ll8 6b3*h (rb6s(8 6b36b683rlr8 6b3**s (b6h(8 6b36b683ll8 6b3*** &" 8 6b3 " " r8 6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,8 & 6 "8 663e1 '(e@64660h (8 66336; llr8 663e*h (rb6s(8 66b683rl8 663e**s (b6h(8 66b683llr8 663e*** &" r8 663e " " 8 663ed "r8 663e1 '(e@64660h (8 66336; ll8 663e*h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 135 (rb6s(8 66b683rlr8 663e**s (b6h(8 66b683ll8 663e*** &" 8 663e " " r8 663ed $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,3 ,-:6 "3-:6b31 '(e@64660h (3-:6b36336; llr3-:6b3*h (rb6s(3-:6b36b683rl3-:6b3**s (b6h(3-:6b36b683llr3-:6b3*** &" r3-:6b3 " " 3-:6b3d "r3-:6b31 '(e@64660h( 6h 0 6*h (3-:6b36336; ll3-:6b3*h (rb6s(3-:6b36b683rlr3-:6b3**s (b6h(3-:6b36b683ll3-:6b3*** &" 3-:6b3 " " r3-:6b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # ,3 , # " 96 "36b@6 96b31 '(e@64660h 0 6h (36b@6 96b36336; llr36b@6 96b3*h (rb6 s(36b@6 96b36b683rl36b@6 96b3** f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 136 pq2fads-vr user ? s manual motorola s (b6 h(36b@6 96b36b683ll r36b@6 96b3*** &" r36b@6 96b3 " " 36b@6 96b3d "r36b@6 96b31 '(e@64660h (36b@6 96b36336; ll36b@6 96b3*h (rb6 s(36b@6 96b36b683rl r36b@6 96b3**s (b6 h(36b@6 96b36b683ll 36b@6 96b3*** &" 36b@6 96b3 " " r36b@6 96b3d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! 3 , 6lr3 , 6d 3 ,6lr3 ,-:6d 3 ,! 96lr3 , # " 96d 6lr 6d + 6lr 6d 8 & -6lr8 & -6d 8 & 6lr8 & 6d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 137 8 &" -l(r8 & -6sr8 & 6*h(r3 ,-:6sr 6*d 8 &" lr8 & -6sr8 & 6sr3 ,-:6sr 6d 0 -6lr 0 -6d 0 6lr 0 6d 6!6lr6 "6d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! "# " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! "#; gl9ad "#; l/d "#; l/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / 3 " / 363 >"1 '((( "" 6ll/*h( / 36b683llr / 363 >"**s (r( "" 6ll/*h((6b36hr / 3g;'5*s / 3g;'5*** &" r / 363 >" " " / 363 >"d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 138 pq2fads-vr user ? s manual motorola "r / 363 >"1 '((( "" 6ll/*h( / 36b683ll / 363 >"**s (r( "" 6ll/*hr6b36hr / 3g;'5** &" / 363 >" " " r / 363 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / " / 63 >"1 '((( "" 6ll/*h( / 6b683llr / 63 >"**s (r( "" 6ll/*h((6b6hr / g;'5*s / g;'5*** &" r / 63 >" " " / 63 >"d "r / 63 >"1 '((( "" 6ll/*h( / 6b683ll / 63 >"**s (r( "" 6ll/*hr6b6hr / g;'5** &" / 63 >" " " r / 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / " / 63 >"1 '((( "" 6ll/*h( / 6b683llr / 63 >"**s (r( "" 6ll/*h((6b6hr / g;'5*s / g;'5*** &" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 139 r / 63 >" " " / 63 >"d "r / 63 >"1 '((( "" 6ll/*h( / 6b683ll / 63 >"**s (r( "" 6ll/*hr6b6hr / g;'5** &" / 63 >" " " r / 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / " / 63 >"1 '((( "" 6ll/*h( / 6b683llr / 63 >"**s (r( "" 6ll/*h((6b6hr / g;'5*s / g;'5*** &" r / 63 >" " " / 63 >"d "r / 63 >"1 '((( "" 6ll/*h( / 6b683ll / 63 >"**s (r( "" 6ll/*hr6b6hr / g;'5** &" / 63 >" " " r / 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - 3 " - 363 >"1 '((( "" 6ll/*h( - 36b683llr - 363 >"**s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 140 pq2fads-vr user ? s manual motorola (r( "" 6ll/*h((6b6hr - 3g;'5*s - 3g;'5*** &" r - 363 >" " " - 363 >"d "r - 363 >"1 '((( "" 6ll/*h( - 36b683ll - 363 >"**s (r( "" 6ll/*hr6b6hr - 3g;'5** &" - 363 >" " " r - 363 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - " - 63 >"1 '((( "" 6ll/*h( - 6b683llr - 63 >"**s (r( "" 6ll/*h((6b36hr - g;'5*s - g;'5*** &" r - 63 >" " " - 63 >"d "r - 63 >"1 '((( "" 6ll/*h( - 6b683ll - 63 >"**s (r( "" 6ll/*hr6b36hr - g;'5** &" - 63 >" " " r - 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 141 "6 # , - " - 63 >"1 '((( "" 6ll/*h( - 6b683llr - 63 >"**s (r( "" 6ll/*h((6b6hr - g;'5*s - g;'5*** &" r - 63 >" " " - 63 >"d "r - 63 >"1 '((( "" 6ll/*h( - 6b683ll - 63 >"**s (r( "" 6ll/*hr6b6hr - g;'5** &" - 63 >" " " r - 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - " - 63 >"1 '((( "" 6ll/*h( - 6b683llr - 63 >"**s (r( "" 6ll/*h((6b6hr - g;'5*s - g;'5*** &" r - 63 >" " " - 63 >"d "r - 63 >"1 '((( "" 6ll/*h( - 6b683ll - 63 >"**s (r( "" 6ll/*hr6b6hr - g;'5** &" - 63 >" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 142 pq2fads-vr user ? s manual motorola " " r - 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 3 " 363 >"1 '((( "" 6ll/*h( 36b683llr 363 >"**s (r( "" 6ll/*h((6b6hr 3g;'5*s 3g;'5*** &" r 363 >" " " 363 >"d "r 363 >"1 '((( "" 6ll/*h( 36b683ll 363 >"**s (r( "" 6ll/*hr6b6hr 3g;'5** &" 363 >" " " r 363 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , " 63 >"1 '((( "" 6ll/*h( 6b683llr 63 >"**s (r( "" 6ll/*h((6b6hr g;'5*s g;'5*** &" r 63 >" " " 63 >"d "r 63 >"1 '((( "" 6ll/*h( 6b683ll 63 >"**s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 143 (r( "" 6ll/*hr6b6hr g;'5** &" 63 >" " " r 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , " 63 >"1 '((( "" 6ll/*h( 6b683llr 63 >"**s (r( "" 6ll/*h((6b36hr g;'5*s g;'5*** &" r 63 >" " " 63 >"d "r 63 >"1 '((( "" 6ll/*h( 6b683ll 63 >"**s (r( "" 6ll/*hr6b36hr g;'5** &" 63 >" " " r 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , " 63 >"1 '((( "" 6ll/*h( 6b683llr 63 >"**s (r( "" 6ll/*h((6b6hr g;'5*s g;'5*** &" r 63 >" " " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 144 pq2fads-vr user ? s manual motorola 63 >"d "r 63 >"1 '((( "" 6ll/*h( 6b683ll 63 >"**s (r( "" 6ll/*hr6b6hr g;'5** &" 63 >" " " r 63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ! g"# " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! g"#; gl9ad g"#; l/d g"#; l/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / 3g " / 3g63 >"1 '(e@646 g"#h ( / 3g6336; llr / 3g63 >"*h (r( "" 6ll/*s( / 3 g6b683llr / 3g63 >"** s (( "" 6ll/*h( / 3g6b683llr / 3g63 >"*** &" r / 3g63 >" " " / 3g63 >"d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 145 "r / 3g63 >"1 '(e@646 g"#h ( / 3g6336; ll / 3g63 >"*h (r( "" 6ll/*s( / 3g6b683ll / 3g63 >"** s (( "" 6ll/*h( / 3g6b683ll / 3g63 >"*** &" / 3g63 >" " " r / 3g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / g " / g63 >"1 '(e@646 g"#h ( / g6336; llr / g63 >"*h (r( "" 6ll/*s( / g6b683llr / g63 >"** s (( "" 6ll/*h( / g6b683llr / g63 >"*** &" r / g63 >" " " / g63 >"d "r / g63 >"1 '(e@646 g"#h ( / g6336; ll / g63 >"*h (r( "" 6ll/*s( / g6b683ll / g63 >"** s (( "" 6ll/*h( / g6b683ll / g63 >"*** &" / g63 >" " " r / g63 >"d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 146 pq2fads-vr user ? s manual motorola $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / g " / g63 >"1 '(e@646 g"#h ( / g6336; llr / g63 >"*h (r( "" 6ll/*s( / g6b683llr / g63 >"** s (( "" 6ll/*h( / g6b683llr / g63 >"*** &" r / g63 >" " " / g63 >"d "r / g63 >"1 '(e@646 g"#h ( / g6336; ll / g63 >"*h (r( "" 6ll/*s( / g6b683ll / g63 >"** s (( "" 6ll/*h( / g6b683ll / g63 >"*** &" / g63 >" " " r / g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , / g " / g63 >"1 '(e@646 g"#h ( / g6336; llr / g63 >"*h (r( "" 6ll/*s( / g6b683llr / g63 >"** s (( "" 6ll/*h( / g6b683llr / g63 >"*** &" r / g63 >" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 147 " " / g63 >"d "r / g63 >"1 '(e@646 g"#h ( / g6336; ll / g63 >"*h (r( "" 6ll/*s( / g6b683ll / g63 >"** s (( "" 6ll/*h( / g6b683ll / g63 >"*** &" / g63 >" " " r / g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - 3g " - 3g63 >"1 '(e@646 g"#h ( - 3g6336; llr - 3g63 >"*h (r( "" 6ll/*s( - 3 g6b683llr - 3g63 >"** s (( "" 6ll/*h( - 3g6b683llr - 3g63 >"*** &" r - 3g63 >" " " - 3g63 >"d "r - 3g63 >"1 '(e@646 g"#h ( - 3g6336; ll - 3g63 >"*h (r( "" 6ll/*s( - 3g6b683ll - 3g63 >"** s (( "" 6ll/*h( - 3g6b683ll - 3g63 >"*** &" - 3g63 >" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 148 pq2fads-vr user ? s manual motorola " " r - 3g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - g " - g63 >"1 '(e@646 g"#h ( - g6336; llr - g63 >"*h (r( "" 6ll/*s( - g6b683llr - g63 >"** s (( "" 6ll/*h( - g6b683llr - g63 >"*** &" r - g63 >" " " - g63 >"d "r - g63 >"1 '(e@646 g"#h ( - g6336; ll - g63 >"*h (r( "" 6ll/*s( - g6b683ll - g63 >"** s (( "" 6ll/*h( - g6b683ll - g63 >"*** &" - g63 >" " " r - g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - g " - g63 >"1 '(e@646 g"#h ( - g6336; llr - g63 >"*h (r( "" 6ll/*s( - g6b683llr - g63 >"** s (( "" 6ll/*h( - g6b683llr - g63 >"*** f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 149 &" r - g63 >" " " - g63 >"d "r - g63 >"1 '(e@646 g"#h ( - g6336; ll - g63 >"*h (r( "" 6ll/*s( - g6b683ll - g63 >"** s (( "" 6ll/*h( - g6b683ll - g63 >"*** &" - g63 >" " " r - g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , - g " - g63 >"1 '(e@646 g"#h ( - g6336; llr - g63 >"*h (r( "" 6ll/*s( - g6b683llr - g63 >"** s (( "" 6ll/*h( - g6b683llr - g63 >"*** &" r - g63 >" " " - g63 >"d "r - g63 >"1 '(e@646 g"#h ( - g6336; ll - g63 >"*h (r( "" 6ll/*s( - g6b683ll - g63 >"** s (( "" 6ll/*h( - g6b683ll - g63 >"*** f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 150 pq2fads-vr user ? s manual motorola &" - g63 >" " " r - g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , 3g " 3g63 >"1 '(e@646 g"#h ( 3g6336; llr 3g63 >"*h (r( "" 6ll/*s( 3 g6b683llr 3g63 >"** s (( "" 6ll/*h( 3g6b683llr 3g63 >"*** &" r 3g63 >" " " 3g63 >"d "r 3g63 >"1 '(e@646 g"#h ( 3g6336; ll 3g63 >"*h (r( "" 6ll/*s( 3g6b683ll 3g63 >"** s (( "" 6ll/*h( 3g6b683ll 3g63 >"*** &" 3g63 >" " " r 3g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , g " g63 >"1 '(e@646 g"#h ( g6336; llr g63 >"*h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 151 (r( "" 6ll/*s( g6b683llr g63 >"** s (( "" 6ll/*h( g6b683llr g63 >"*** &" r g63 >" " " g63 >"d "r g63 >"1 '(e@646 g"#h ( g6336; ll g63 >"*h (r( "" 6ll/*s( g6b683ll g63 >"** s (( "" 6ll/*h( g6b683ll g63 >"*** &" g63 >" " " r g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , g " g63 >"1 '(e@646 g"#h ( g6336; llr g63 >"*h (r( "" 6ll/*s( g6b683llr g63 >"** s (( "" 6ll/*h( g6b683llr g63 >"*** &" r g63 >" " " g63 >"d "r g63 >"1 '(e@646 g"#h ( g6336; ll g63 >"*h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 152 pq2fads-vr user ? s manual motorola (r( "" 6ll/*s( g6b683ll g63 >"** s (( "" 6ll/*h( g6b683ll g63 >"*** &" g63 >" " " r g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "6 # , g " g63 >"1 '(e@646 g"#h ( g6336; llr g63 >"*h (r( "" 6ll/*s( g6b683llr g63 >"** s (( "" 6ll/*h( g6b683llr g63 >"*** &" r g63 >" " " g63 >"d "r g63 >"1 '(e@646 g"#h ( g6336; ll g63 >"*h (r( "" 6ll/*s( g6b683ll g63 >"** s (( "" 6ll/*h( g6b683ll g63 >"*** &" g63 >" " " r g63 >"d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 153 $ " ""# " & 2" " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! 6; "l d c6; "l d r 6le@6366 d r c6le@6366cd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%""# " ; $%3 "# " &>" " 5 );( c " "" " )* $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! "le@6366/s e@6366-s e@63660s ( 68@6b6h/63hr) "" 6;'5*d ; "l ";'5d +&" (e@6366/* &" l" /d " "+&" (e@6366-* &" l" -d " "+&" (e@63660* &" l" 0d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 154 pq2fads-vr user ? s manual motorola " "+&" (868@6963* &" l'#) "/d " "+&" (b68@6963* &" l'#) "-d " "+&" ( 68@6963* &" l'#) " d " "+&" (8 68@6963* &" l'#) "0d "le@636 "#s e@636 g"#d ; "l ";'5d +&" (e@636 "#* &" l "#;'5d " "+&" (e@636 g"#* &" l g"#;'5d $%%%%%%%%%%%%%%%%%%%%%5 6 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%"" # $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! "" ; "l"" d "" l/d$ " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 155 "5-lr( -h(r( "5-; ,h /***d$"" !&25! "5 ! " 35 "5-lr(35 -h(r(35 "5-; ,h35 /***d$35 !&25! "5 ! " "" l "5-; ,h35 "5-; ,d$5 &5! "" ""d ' "" l "5-; ,hr35 "5-; ,d$ ) "" 5! " "" ; "l<d$ " >" "" 7 +)" 5 "; r3 , ! 6lr3 , 6;'5sr "" 6d r8 & ! -6lr8 & -6;'5sr "" 6d r8 & ! 6lr8 & 6;'5sr "" 6d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% "" ' #! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $"j! $ '6; "l d $ '6ld $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%b#" " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 156 pq2fads-vr user ? s manual motorola b6; "lb d b6l/d$;; b lr "5-; ,h35 "5-; ,d$ )5 5! " "" $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% 5!''" " 5 " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! ) "" 6; gl9ad ) "" 6; l/d ) "" 6; l/d ) "" 6; gl9ad ) "" 6; l/d ) "" 6; l/d ) "" 61l "" 6d ) "" 61l) "" 6;'5d !' 6; "l d r !' 6l(r/6s$ >" & "" ' # rc6s r "#6s r 6s r3 , ! 6s$ > " 2& ' + " r -6s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 157 r 6*h (r886 688*d !' 6; "l d r !' 6l(r -6s r 6*h (r886 688*d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% 5!''" 5 "( " " * $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% "+ &e )#" 7& 2 "" ' "' ,' &."" ,! # $%" " " &"" " "j! >" ") " " $% &") "' + #& "" " "(5 * &"& 2 '' $% ",& ",)5" "' b6 688' 6" "! $%+ & ! + ) #5 ! " 5" +"" ' & 5!''" ; "j! '' ; gl9ad '' ; l/d '' ; l/d ''l( '' ;'5ll0*d +&" ((((b68683 663sb686363* h( '' ;'5ll/**s ( '' ;'5rl/**hr( '' ;'5llc*h) "" 6;'5* &" '' 1l '' ;'5u-d " " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 158 pq2fads-vr user ? s manual motorola '' 1l/d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%8 &.& " " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! 8 &! ; "lt&'d r8 &-6l/63h83 63ba-h 66b683 s /63h83 63ba-h6b683 h ) "" 6;'5s c63h83 63ba-h( 66b6s 6b6*d r8 & 6l/63h83 63ba h 66b683 s /63h83 63ba h6b683 h ) "" 6;'5s c63h83 63ba h( 66b6s 6b6*d r8 &06l/63h83 63ba0h 66b683 s /63h83 63ba0h6b683 h ) "" 6;'5s c63h83 63ba0h( 66b6s 6b6*d r8 &c6l/63h83 63bach 66b683 s /63h83 63bach6b683 h ) "" 6;'5s c63h83 63bach( 66b6s 6b6*d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 159 ,6; "l d r ,6l/63h 66b6s /63h6b6h) "" 6;'5s c63h( 66b683 s6b683 *d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3b& " " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! 3 , ! 6; "l d r3 , ! 6lr3 , 6d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% +" "" $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! 6 6; gl9ad 6 6; l/d 6 6; l/d 6 61l 6d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%@" " # " ! "j!" &" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 160 pq2fads-vr user ? s manual motorola "j! 6 " ! l( / 3s / s / s / s - 3s - s - s - s 3s s s *d 6 6; "l6 " ! d$ " 2 ! ! r6 6l6 " ! d$ " ! "j!" & +' " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3! )'! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! a"" " "l36h-sa"" " "; ,d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 161 7.2.2 u41 - power switch debounce +" 6"5 ! " / +" "5 ! " $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%"> "" ;% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " ;% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%) ", .' $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9ab=d & +" 6b-=d$& +" + & +" 6b-: ) " "#d$ +" ! ) +" 2 $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%& +" + &!''" ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +" 6!''" b ) " "#75!''" d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 162 pq2fads-vr user ? s manual motorola $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% " # " g#" " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% >-b ) " ,7g"" d > b ) " ,7g"" d >0b ) " ,7g"" d >cb ) " ,7g"" d >=b ) " ,7g"" d ! " /7 ! " -7 ! " 7 ! " 07 ! " c7 ! " =7 ! " :7 ! " <7 ! " /7 ! " -7 ! " 7 ! " 07 ! " c7 ! " =7 ! " :7 ! " <7 ! " 5/7 ! " 5-7 ! " 5 7 ! " 507 ! " 5c7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 163 ! " 5=7 ! " 5:7 ! " 5<b ) " "#75!''" d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 777kl-7/7;;7;k;d 77l;;7;;7;;d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3bl-d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $% # # ! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ! " lm ! " <7 ! " :7 ! " =7 ! " c7 ! " 07 ! " 7 ! " -7 ! " /nd ! " lm ! " <7 ! " :7 ! " =7 ! " c7 ! " 07 ! " 7 ! " -7 ! " /nd ! " 5lm ! " 5<7 ! " 5:7 ! " 5=7 ! " 5c7 ! " 507 ! " 5 7 ! " 5-7 ! " 5/nd $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%3 +" " ; $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +" l/d +" ''l-d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%j! 7 " # ,;% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 164 pq2fads-vr user ? s manual motorola $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%@" " # +" # &"3 +" ! ); $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% "j! >-lr >=; ,d$#" " # " g > lr >-; ,d >0lr > ; ,d >clr >0; ,d >=lr >c; ,d ! " ; l/d ! " ; l/d ! " ; glr >=; ,d +&" ( ! " ;'5ll ==* &" ! " 1l/" " ! " 1l ! " u-d ! " ; l/d ! " ; l/d ! " ; gl( ! " ;'5ll/*d +&" ( ! " ;'5ll ==* &" ! " 1l/" " ! " 1l ! " u-d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 165 ! " 5; l/d ! " 5; l/d ! " 5; gl( ! " ;'5ll/*d +&" ( ! " 5;'5ll ==* &" ! " 51l/" " ! " 51l ! " 5u-d +" 6!''" ; l/d +" 6!''" ; l/d +" 6!''" ; gl( ! " 5;'5ll/*d +" 6!''" 1l& +" 6d +" 6; "l d +" 6; l/d +" 6; l/d +" 6; gl( ! " 5;'5ll/*d +" 61lr +" 6!''" ;'5d $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% $%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% o '"'3bp q b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 166 pq2fads-vr user ? s manual motorola 7.3 bill of materials the following is the bill of materials for the pq2fads-vr including the l2cache option. table 7-10. pq2fads-vr bill of materials - ! ! " # f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 167 ! ! ! ! ! ! ! !!! ! !!! ! ! ! ! ! ! !!!! !! ! !!! ! ! ! ! !! ! !!! !!!! ! ! ! ! ! ! ! ! ! $ % # table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 168 pq2fads-vr user ? s manual motorola !!! ! ! ! ! ! " # ! ! ! ! ! !! !! !! $ # " # !" ! & # ! ! " ' & ! ! ! !!! ! $ # # $ & ( # ) & * & * %& +++!++ ),'-./01 + + + ! ++++ + + + + &+ 2 ! & # ),'-./01 + + + ! ! ,) + ) )' ) ! ! ,% + % )' ) , + % )' ) ! , + )' ) table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 169 ', & & & ! ! ' &!) ' &!) & + + ! + ! ! &+ ++ ! & # + #,+341-,3$$156 3- & # ! +!+ 7 7 & + + ++ +++ +! +++!++ & ! &+ +++ +, &+ + +* ) + ) + +++ + & + & + &'6-8.096 !&' * + + 2& & + +' ) +' ) ,1:6-3$ 77 && + && + & - ! 77 && && & - ! ! ! ! ! ! ! ! ! ! ! & table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 170 pq2fads-vr user ? s manual motorola ! ! ! # ! ! ! ! ! # + + + ' - ! ! ! ! ! ! !! ! ! ! ! ! ! - ! ! ! - ! ! ! ! ! ! ! ! ! ! ! - table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 171 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! - - - ! - ! !! ! ! - ! 39; < ! ! ! ! ! ! ! ! # ! ! ! ! - ! table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 172 pq2fads-vr user ? s manual motorola ! - - - ! ! ! ! - - - - ! - ! !< ! - - ! ! ! !! ! 222 - - ! ! ' ! - ! ! ! ! ! - ! + , 7 = table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information motorola pq2fads-vr user ? s manual 173 ! ' 7 = !! 7 = ! &' &' = ,+ !*& ' ! ) % ,+ *& ' ) % ' ! ' ! ) ! !!&+ ! !!&+ & - ! &# &# & ' & ' & + '+ + '+ + + ! ) ) ! # & # & +&! +&! +& & & & ! ' +) ' +) 7 + 7 + ! ! 7#7 7#7 ! &,* & * &+! !! !! &+ & ' & ' & &+ &+ >+ & # & # & &+! &+! & & * ! & * ! ! ! +& +& table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . support information 174 pq2fads-vr user ? s manual motorola # & # & - #> !& #> !& ! ' ! ' & & & & - ,&&! & !#)') & & - - ) # & # 1;.53$ - /"563- ! % > % > ?(-1@@ +'# ' +'# ' +1-.53; # & # & ! ! & ! &' ) & ! &' ) & + + + + # & & & # &! &a &! &a & # & ! &a & ! &a & # &a & &a & # &a & &a & # b b + + table 7-10. pq2fads-vr bill of materials - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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