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?2002 fairchild semiconductor corporation june 2002 ISL9N305ASK8T rev a ISL9N305ASK8T ISL9N305ASK8T n-channel logic level pwm optimized ultrafet ? trench power mosfet general description this device employs a new advanced trench mosfet technology and features low gate charge while maintaining low on-resistance. optimized for switching applications, this device improves the overall efficiency of dc/dc converters and allows operation to higher switching frequencies. applications ? dc/dc converters features fast switching r ds(on) = 0.004 ? (typ), v gs = 10v r ds(on) = 0.0064 ? (typ), v gs = 4.5v q g (typ) = 38nc, v gs = 5v q gd (typ) = 11.5nc c iss (typ) = 4260pf mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v dss drain to source voltage 30 v v gs gate to source voltage 20 v `i d drain current 18 a continuous (t a = 25 o c, v gs = 10v) continuous (t a = 100 o c, v gs = 4.5v) 9 a pulsed figure 4 a p d power dissipation derate above 25 o c 2.5 20 w mw/ o c t j , t stg operating and storage temperature -55 to 150 o c r ja fr-4 board with 0.76 in 2 ( 490 mm 2 ) copper pad at 10 seconds 50 o c/w r ja fr-4 board with 0.054 in 2 ( 34.8 mm 2 ) copper pad at 1000 seconds 152 o c/w r ja fr-4 board with 0.0115 in 2 ( 7.42 mm 2 ) copper pad at 1000 seconds 189 o c/w device marking device reel size tape width quantity ISL9N305ASK8T ISL9N305ASK8T 330mm 12mm 2500units drain (8) source (1) drain (7) drain (6) drain (5) source (3) gate (4) source (2) so-8 branding dash 1 5 2 3 4
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T electrical characteristics t a = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 4.5v) switching characteristics (v gs = 10v) unclamped inductive switching drain-source diode characteristics symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 30 - - v i dss zero gate voltage drain current v ds = 25v - - 1 a v gs = 0v t a = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a1-3v r ds(on) drain to source on resistance i d = 18a, v gs = 10v - 0.004 0.005 ? i d = 9a, v gs = 4.5v - 0.0064 0.008 c iss input capacitance v ds = 15v, v gs = 0v, f = 1mhz -4260- pf c oss output capacitance - 750 - pf c rss reverse transfer capacitance - 340 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 15v i d = 9a i g = 1.0ma 72 108 nc q g(5) total gate charge at 5v v gs = 0v to 5v - 38 57 nc q g(th) threshold gate charge v gs = 0v to 1v - 4.1 6.1 nc q gs gate to source gate charge - 10.4 - nc q gd gate to drain ? miller ? charge - 11.5 - nc t on tu r n - o n t i m e v dd = 15v, i d = 9a v gs = 4.5v, r gs = 3.9 ? - - 158 ns t d(on) turn-on delay time - 24 - ns t r rise time - 81 - ns t d(off) turn-off delay time - 44 - ns t f fall time - 52 - ns t off turn-off time - - 145 ns t on tu r n - o n t i m e v dd = 15v, i d = 9a v gs = 10v, r gs = 3.9 ? - - 100 ns t d(on) turn-on delay time - 12 - ns t r rise time - 55 - ns t d(off) turn-off delay time - 66 - ns t f fall time - 50 - ns t off turn-off time - - 173 ns t av avalanche time i d = 2.2a, l = 3mh 145 - - s v sd source to drain diode voltage i sd = 9a - - 1.25 v i sd = 4a - - 1.0 v t rr reverse recovery time i sd = 9a, di sd /dt = 100a/ s- - 40ns q rr reverse recovered charge i sd = 9a, di sd /dt = 100a/ s- - 38nc
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T typical characteristic figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 5 10 20 25 50 75 100 125 150 i d , drain current (a) t a , case temperature ( o c) v gs = 10v, r ja = 50 o c/w v gs = 4.5v, r ja = 189 o c/w 15 0.01 0.1 1 3 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.001 10 -5 t, rectangular pulse duration (s) z ja , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 r ja = 50 o c/w 10 100 1000 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -5 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region v gs = 4.5v i = i 25 150 - t a for temperatures above 25 o c derate peak current as follows: 125 t a = 25 o c r ja = 50 o c/w 2000
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T figure 5. transfer characteristics figure 6. saturation characteristics figure 7. drain to source on resistance vs gate voltage and drain current figure 8. normalized drain to source on resistance vs junction temperature figure 9. noramlized gate threshold voltage vs junction temperature figure 10. normalized drain to source breakdown voltage vs junction temperature typical characteristic (continued) 0 10 20 30 40 50 1234 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = -55 o c t j = 150 o c t j = 25 o c 0 10 20 30 40 50 0 0.2 0.4 0.6 1.0 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v gs = 3v t a = 25 o c v gs = 10v v gs = 4.5v v gs = 3.5v 0.6 0 5 10 15 20 246810 i d = 1a v gs , gate to source voltage (v) r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max i d = 18a 0.6 1.2 1.5 1.8 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 18a pulse duration = 80 s duty cycle = 0.5% max 0.9 0.4 0.6 0.8 1.0 1.2 1.4 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T figure 11. capacitance vs drain to source voltage figure 12. gate charge waveforms for constant gate currents figure 13. switching time vs gate resistance figure 14. switching time vs gate resistance typical characteristic (continued) 100 1000 0.1 1 10 30 6000 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c gs + c gd c rss = c gd 0 2 4 6 8 10 0255075 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15v i d = 18a i d = 1a waveforms in descending order: 0 100 200 300 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 15v, i d = 9a t d(off) t r t f t d(on) 0 200 400 600 010 304050 20 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 15v, i d = 9a t d(off) t r t d(on) t f test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T figure 17. gate charge test circuit figure 18. gate charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application ? s ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the so8 package, the environment in which it is applied will have a significant influence on the part ? s current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer ? s preliminary application evaluation. figure 21 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja values listed in the electrical specifications table. the points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, p dm . thermal resistances corresponding to other copper areas can be obtained from figure 21 or by calculation using equation 2. r ja is defined as the natural log of the area times a coefficient added to a constant. the area, in square inches is the top copper area including the gate and source pads. the transient thermal impedance (z ja ) is also effected by varied top copper board area. figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. each trace represents a copper pad area in square inches corresponding to the descending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. for pulse widths less than 100ms the transient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and rtherm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. (eq. 1) p dm t jm t a ? () r ja ----------------------------- = (eq. 2) r ja 83.2 23.6 area () ln ? = figure 21. thermal resistance vs mounting pad area 120 160 200 240 0.1 1.0 80 0.01 r ja = 83.2 - 23.6* ln (area) 152 o c/w - 0.054in 2 189 o c/w - 0.0115in 2 r ja ( o c/w) area, top copper area (in 2 ) figure 22. thermal impedance vs mounting pad area 30 60 90 120 1 5 0 0 10 -1 10 0 10 1 10 2 10 3 t, rectangular pulse duration (s) z ja , thermal copper board area - descending order 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.00 in 2 impedance ( o c/w)
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T pspice electrical model .subckt isl9n305ask8 2 1 3 ; rev may 2001 ca 12 8 2e-9 cb 15 14 2.3e-9 cin 6 8 4.1e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 32.8 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1.29e-9 lsource 3 7 1.75e-10 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1e-3 rgate 9 20 2.34 rldrain 2 5 10 rlgate 1 9 12.9 rlsource 3 7 1.75 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 3.3e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*150),5))} .model dbodymod d (is = 2e-11 n = 1.04 rs = 4e-3 trs1 = 1e-3 trs2 = 1e-6 xti=2 cjo = 1.4e-9 tt = 9e-10 m = 0.45 xti=2) .model dbreakmod d (rs = 0.22 trs1 = 8e-4 trs2 = -8.9e-6) .model dplcapmod d (cjo = 1.27e-9 is = 1e-30 n = 10 m = 0.46) .model mmedmod nmos (vto = 1.87 kp = 10 is=1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.34) .model mstromod nmos (vto = 2.25 kp = 140 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.5 kp = 0.1 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 23.4 rs = 0.1) .model rbreakmod res (tc1 = 9.2e-4 tc2 = 0) .model rdrainmod res (tc1 = 1.2e-2 tc2 = 3e-5) .model rslcmod res (tc1 = 1e-3 tc2 = 1e-7) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.6e-3 tc2 = -8e-6) .model rvtempmod res (tc1 = -2.9e-3 tc2 = 1e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -3.0 voff= -2.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.0 voff= -3.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff= 0.2) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.2 voff= -0.5) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T saber electrical model rev may 20001 template isl9n305ask8 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2e-11, nl=1.04, rs = 4e-3, trs1 = 1e-3, trs2 = 1e-6, xti=2, cjo = 1.4e-9, tt = 9e-10, m = 0.45) dp..model dbreakmod = (rs = 0.22, trs1 = 8e-4, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 1.29e-9, isl=10e-30, nl=10, m=0.46) m..model mmedmod = (type=_n, vto = 1.87, kp=10, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.25, kp = 140, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.5, kp = 0.1, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -2.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -3.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5) c.ca n12 n8 = 2e-9 c.cb n15 n14 = 2.3e-9 c.cin n6 n8 = 4.1e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.29e-9 l.lsource n3 n7 = 1.75e-10 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.2e-4, tc2 = 0 res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3e-5 res.rgate n9 n20 = 2.34 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 12.9 res.rlsource n3 n7 = 1.75 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 1e-7 res.rvthres n22 n8 = 1, tc1 = -1.6e-3, tc2 = -8e-6 spe.ebreak n11 n7 n17 n18 = 32.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation ISL9N305ASK8T rev a ISL9N305ASK8T spice thermal model rev 18 may 2001 isl9n305ask8_76t copper area = 0.76 in 2 ctherm1 th 8 2.0e-3 ctherm2 8 7 5.0e-3 ctherm3 7 6 1.0e-2 ctherm4 6 5 4.0e-2 ctherm5 5 4 9.0e-2 ctherm6 4 3 0.2 ctherm7 3 2 1.0 ctherm8 2 tl 3.0 rtherm1 th 8 0.1 rtherm2 8 7 0.5 rtherm3 7 6 1.0 rtherm4 6 5 5.0 rtherm5 5 4 8.0 rtherm6 4 3 13 rtherm7 3 2 19 rtherm8 2 tl 29.7 saber thermal model copper area = 0.76 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 0.2 ctherm.ctherm7 3 2 = 1.0 ctherm.ctherm8 2 tl = 3.0 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 13 rtherm.rtherm7 3 2 = 19 rtherm.rtherm8 2 tl = 29.7 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8 table 1. thermal models componant 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.0 in 2 ctherm6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1 ctherm7 0.5 1.0 1.0 1.0 1.0 ctherm8 1.3 2.8 3.0 3.0 3.0 rtherm62620151312 rtherm73924211918 rtherm8 55 38.7 31.3 29.7 25
rev. h7 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. acex ? bottomless ? coolfet ? crossvolt ? dome ? ecospark ? e 2 cmos ? ensigna ? fact ? fact quiet series ? fast ? fastr ? frfet ? globaloptoisolator ? gto ? hisec ? i 2 c ? isoplanar ? littlefet ? microfet ? micropak ? microwire ? optologic ? optoplanar ? pacman ? pop ? power247 ? powertrench ? qfet ? qs ? qt optoelectronics ? quiet series ? silent switcher ? smart start ? spm ? stealth ? supersot ? -3 supersot ? -6 supersot ? -8 syncfet ? tinylogic ? trutranslation ? uhc ? ultrafet ? vcx ? disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only.

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