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| 1994 data sheet description the m pd78p018fy is a member of the m pd78018fy subseries of 78k/0 series products. the internal mask rom of the m pd78018fy is replaced with one-time prom or eprom. because the m pd78p018fy can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time- to-market of new products. caution the m pd78p018fydw and 78p018fykk-s are not guaranteed to maintain the reliability level required for mass production of the customer's devices. please use only experimentally or for evaluation purposes during trial manufacture. detailed function descriptions are provided in the following user's manuals. be sure to read them before designing. m pd78018f, 78018fy subseries user's manual: u10659e 78k/0 series user's manual C instructions: u12326e features pin compatible with mask rom version (except v pp pin) internal prom: 60 kbytes note 1 m pd78p018fydw, 78p018fykk-s: re-programmable (suited for system evaluation) m pd78p018fycw, 78p018fygc-ab8: programmable only once (suited for small-scale production) internal high-speed ram: 1024 bytes note 1 internal expansion ram: 1024 bytes note 2 internal buffer ram: 32 bytes supports the i 2 c bus interface operable over same supply voltage range as mask rom version: v dd = 1.8 to 5.5 v (except an a/d converter) qtop? microcontroller supported notes 1. the capacities of internal prom and internal high-speed ram can be changed by means of the internal memory size switching register (ims). 2. the capacity of the internal expansion ram can be changed by means of the internal expansion ram size switching register (ixs). remarks 1. qtop microcontroller is a general term for microcontrollers which incorporate one-time prom and are totally supported by nec's programming service (from programming to marking, screening, and verification). 2. for the differences between the prom version and mask rom versions, refer to 1. differences between the m pd78p018fy and mask rom versions . in this document, the term prom is used in parts common to one-time prom versions and eprom versions. mos integrated circuit m pd78p018fy 8-bit single-chip microcontroller the mark shows major revised points. the information in this document is subject to change without notice. document no. u10989ej3v0ds00 (3rd edition) date published december 1998 n cp(k) printed in japan
2 m pd78p018fy ordering information part number package internal rom m pd78p018fycw 64-pin plastic shrink dip (750 mils) one-time prom m pd78p018fydw 64-pin ceramic shrink dip (with window) (750 mils) eprom m pd78p018fygc-ab8 64-pin plastic qfp (14 14 mm) one-time prom m pd78p018fykk-s 64-pin ceramic wqfn (14 14 mm) eprom quality grade part number package quality grades m pd78p018fycw 64-pin plastic shrink dip (750 mils) standard m pd78p018fydw 64-pin ceramic shrink dip (with window) (750 mils) not applicable (for function evaluation) m pd78p018fygc-ab8 64-pin plastic qfp (14 14 mm) standard m pd78p018fykk-s 64-pin ceramic wqfn (14 14 mm) not applicable (for function evaluation) please refer to "quality grade on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. 3 m pd78p018fy 78k/0 series product lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. note under planning 80-pin 80-pin basic subseries for driving fip, display output total: 34 pd78044h m pd78044f m n-ch open drain was added to the pd78044f, display output total: 34 m pd78083 m pd780024y m pd780024 m pd780034y m pd780034 m pd78014h m pd78018f m pd78018fy m control fip tm drive 100-pin lcd drive bus interface supported 42/44-pin 80-pin 100-pin 100-pin 100-pin 78k/0 series basic subseries for driving lcds, on-chip uart y subseries products are compatible with i 2 c bus. products under development products in mass production 80-pin 100-pin pd78054 m pd78054y m pd78064b m pd78064 m pd78064y m emi-noise reduced version of the pd78078 m i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m emi-noise reduced version of the pd78064 m pd78058f m pd78058fy m pd780058y note m pd780058 m pd78070a m pd78070ay m pd78078 m pd78078y m 80-pin pd780308 m meter control pd780955 m pd780958 m pd780973 m pd780308y m sio of the pd78064 was enhanced and rom, ram capacity expanded m 100-pin 80-pin 100-pin 80-pin on-chip j1850 (class2) controller pd78075b m 100-pin pd780018ay m 100-pin 64-pin 64-pin 64-pin 64-pin timer was added to the pd78054 and external interface was enhanced m rom-less version of the pd78078 m emi-noise reduced version of the pd78054 m uart and d/a converter were added to the pd78018f and i/o was enhanced m a/d converter of the pd780024 was enhanced m pd780065 m 80-pin ram capacity of pd780024 was expanded serial i/o of the pd78018f was enhanced m serial i/o of the pd78054 was enhanced and emi-noise was reduced m m emi-noise reduced version of the pd78018f m serial i/o of the pd78078y was enhanced and the function is limited m basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) pd780988 m inverter control 100-pin on-chip inverter control circuit and uart. emi-noise was reduced i/o and fip c/d of the pd78044h were enhanced, display output total: 48 pd780232 m 80-pin for panel control. on-chip fip c/d. display output total: 53 m 64-pin on-chip dcan controller on-chip dcan/iebus controller iebus tm controller is added to pd78054. emi-noise was reduced. ultra-low power consumption and on-chip uart for industrial meter control on-chip controller/driver for automotive meter drive m pd780208 m pd780228 m 80-pin 80-pin 80-pin 80-pin pd78098b m pd780948 m pd780701y m pd780833y m 4 m pd78p018fy the major functional differences among the y subseries are shown below. function rom capacity configuration of serial interface i/o v dd min. subseries name value control m pd78078y 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 88 1.8 v 3-wire with automatic transmit/receive function: 1 ch m pd78070ay C 3-wire/uart: 1 ch 61 2.7 v m pd780018ay 48 k to 60 k 3-wire with automatic transmit/receive function: 1 ch 88 time-division 3-wire: 1 ch i 2 c bus (multimaster supported): 1 ch m pd780058y 24 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 68 1.8 v 3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division uart: 1 ch m pd78058fy 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 69 2.7 v 3-wire with automatic transmit/receive function: 1 ch m pd78054y 16 k to 60 k 3-wire/uart: 1 ch 2.0 v m pd780034y 8 k to 32 k uart: 1 ch 51 1.8 v 3-wire: 1 ch m pd780024y i 2 c bus (multimaster supported): 1 ch m pd78018fy 8 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 53 3-wire with automatic transmit/receive function: 1 ch lcd m pd780308y 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 57 2.0 v drive 3-wire/time-division uart: 1 ch 3-wire: 1 ch m pd78064y 16 k to 32 k 3-wire/2-wire/i 2 c: 1 ch 3-wire/uart: 1 ch remark the functions other than the serial interface are common to the subseries without y. 5 m pd78p018fy 60 kbytes note 1 1024 bytes note 1 1024 bytes note 2 32 bytes 64 kbytes 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time cycle modification function provided. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (@ 10.0-mhz operation) 122 m s (@ 32.768-khz operation) ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. total: 53 ? cmos input: 0 2 ? cmos i/o: 47 ? n-channel open-drain i/o (15-v withstand voltage): 4 ? 8-bit resolution 8 channels ? operable over a wide power supply voltage range: v dd = 2.2 to 5.5 v ? 3-wire serial i/o mode/2-wire serial i/o mode/i 2 c bus mode selectable: 1 channel ? 3-wire serial i/o mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel 3 (14-bit pwm output 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (@ 10.0-mhz operation with main system clock), 32.768 khz (@ 32.768-khz operation with subsystem clock) 2.4 khz, 4.9 khz, 9.8 khz (@ 10.0-mhz operation with main system clock) internal: 8 external: 4 internal: 1 1 function overview (1/2) prom high-speed ram expansion ram buffer ram when main system clock selected when subsystem clock selected maskable non-maskable software function item minimum instruction execution time instruction set i/o ports a/d converter serial interface timer timer output clock output buzzer output vectored interrupt sources internal memory memory space general-purpose registers notes 1. the internal prom and internal high-speed ram capacities can be changed with the internal memory size switching register (ims). 2. the internal expansion ram capacity can be changed with the internal expansion ram size switching register (ixs). 6 m pd78p018fy function overview (2/2) test input supply voltage operating ambient temperature package t a = C40 to +85 c function item internal: 1 external: 1 v dd = 1.8 to 5.5 v ? 64-pin plastic shrink dip (750 mils) ? 64-pin ceramic shrink dip (with window) (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin ceramic wqfn (750 mils) 7 m pd78p018fy pin configuration (top view) (1) normal operating mode 64-pin plastic shrink dip (750 mils) m pd78p018fycw 64-pin ceramic shrink dip (with window) (750 mils) m pd78p018fydw cautions 1. connect the v pp pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 1 p20/si1 2 p21/so1 3 p22/sck1 4 p23/stb 5 p24/busy 6 p25/si0/sb0/sda0 7 p26/so0/sb1/sda1 8 p27/sck0/scl 9 p30/to0 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40/ad0 19 p41/ad1 20 p42/ad2 21 p43/ad3 22 p44/ad4 23 p45/ad5 24 p46/ad6 25 p47/ad7 26 p50/a8 27 p51/a9 28 p52/a10 29 p53/a11 30 p54/a12 31 p55/a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14 8 m pd78p018fy 64-pin plastic qfp (14 14 mm) m pd78p018fygc-ab8 64-pin ceramic wqfn (14 14 mm) m pd78p018fykk-s cautions 1. connect the v pp pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p11/ani1 p10/ani0 av ss p04/xt1 xt2 v pp x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p37 v ss p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/sck0/scl p26/so0/sb1/sda1 p25/si0/sb0/sda0 p24/busy p23/stb p22/sck1 p21/so1 p20/si1 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p65/wr 9 m pd78p018fy reset: reset rd: read strobe sb0, sb1: serial bus sck0, sck1: serial clock scl: serial clock sda0, sda1: serial data si0, si1: serial input so0, so1: serial output stb: strobe ti0 to ti2: timer input to0 to to2: timer output v dd : power supply v pp : programming power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground busy: busy buz: buzzer clock intp0 to intp3: interrupt from peripherals p00 to p04: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 pcl: programmable clock 10 m pd78p018fy cautions 1. (l): independently connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. (2) prom programming mode 64-pin plastic shrink dip (750 mils) m pd78p018fycw 64-pin ceramic shrink dip (with window) (750 mils) m pd78p018fydw 1 2 3 4 5 6 7 8 9 d0 10 d1 11 d2 12 d3 13 d4 14 d5 15 d6 16 d7 17 v ss 18 a0 19 a1 20 a2 21 a3 22 a4 23 a5 24 a6 25 a7 26 a8 27 a16 28 a10 29 a11 30 a12 31 a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd v ss (l) open v pp (l) open v dd a9 reset ce oe a14 (l) (l) (l) (l) a15 (l) pgm (l) 11 m pd78p018fy 64-pin plastic qfp (14 14 mm) m pd78p018fygc-ab8 64-pin ceramic wqfn (14 14 mm) m pd78p018fykk-s reset: reset v dd : power supply v pp : programming power supply v ss : ground a0 to a16: address ce: chip enable d0 to d7: data bus oe: output enable pgm: program cautions 1. (l): independently connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss (l) open v pp (l) open v dd a9 reset d7 v ss d0 d1 d2 d3 d4 d5 d6 a0 a1 a2 a3 a4 a5 a6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss v dd a7 a8 a16 a10 a11 a12 a13 v ss a14 oe ce (l) (l) (l) (l) (l) (l) pgm (l) a15 12 m pd78p018fy block diagram 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer serial interface 0 serial interface 1 a/d converter interrupt control watch timer buzzer output clock output control to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/p00- intp3/p03 buz/p36 pcl/p35 78k/0 cpu core prom (60 kbytes) ram (2048 bytes) v dd v ss v pp port0 port1 port2 port3 port4 port5 port6 external access system control p00 p01 to p03 p04 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p04 xt2 13 m pd78p018fy contents 1. differences between m pd78p018fy and mask rom versions .................................. 14 2. pin functions ................................................................................................................ ............... 15 2.1 pins during normal operating mode .............................................................................................................. 15 2.2 pins during prom programming mode ......................................................................................................... 18 2.3 pin i/o circuits and recommended connection of unused pins ............................................................... 19 3. internal memory size switching register (ims) .......................................................... 21 4. internal expansion ram size switching register (ixs) ............................................ 22 5. prom programming ................................................................................................................... 23 5.1 operating modes ............................................................................................................................... ................. 23 5.2 prom write procedure ............................................................................................................................... ...... 25 5.3 prom read procedure ............................................................................................................................... ....... 29 6. program erasure (for m pd78p018fydw, 78p018fykk-s) .............................................. 30 7. opaque film on erasure window (for m pd78p018fydw, 78p018fykk-s) ................ 30 8. one-time prom version screening ..................................................................................... 30 9. electrical specifications ..................................................................................................... 31 10. characteristic curve (reference value) ..................................................................... 59 11. package drawings .................................................................................................................... 60 12. recommended soldering conditions ............................................................................... 64 appendix a. development tools ............................................................................................... 65 appendix b. related documents ............................................................................................... 70 14 m pd78p018fy m pd78p018fy mask rom m pd78011fy: 8 kbytes m pd78012fy: 16 kbytes m pd78013fy: 24 kbytes m pd78014fy: 32 kbytes m pd78015fy: 40 kbytes m pd78016fy: 48 kbytes m pd78018fy: 60 kbytes m pd78011fy: 512 bytes m pd78012fy: 512 bytes m pd78013fy: 1024 bytes m pd78014fy: 1024 bytes m pd78015fy: 1024 bytes m pd78016fy: 1024 bytes m pd78018fy: 1024 bytes m pd78011fy: no m pd78012fy: no m pd78013fy: no m pd78014fy: no m pd78015fy: 512 bytes m pd78016fy: 512 bytes m pd78018fy: 1024 bytes no no yes no yes item mask rom versions 1. differences between the m pd78p018fy and mask rom versions the m pd78p018fy is a single-chip microcontroller with an on-chip one-time prom or eprom that has program write, erase, and rewrite capability. it is possible to make all the functions except for prom specification and mask option of p60 to p63 pins, the same as those of mask rom versions ( m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, and 78018fy) by setting the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). differences between the m pd78p018fy and mask rom versions are shown in table 1-1. table 1-1. differences between m pd78p018fy and mask rom version internal rom type internal rom capacity internal high-speed ram capacity internal expansion ram capacity internal rom, internal high-speed ram capacity changeable with internal memory size switching register (ims) internal expansion ram capacity changeable with internal expansion ram size switching register (ixs) ic pin v pp pin on-chip pull-up resistor mask option of p60 to p63 pins electrical specifications recommended soldering conditions one-time prom or eprom 60 kbytes 1024 bytes 1024 byte yes note 1 yes note 2 no yes no see respective data sheet of individual products. notes 1. the internal prom capacity becomes 60 kbytes and the internal high-speed ram capacity becomes 1024 bytes by the reset input. 2. the internal expansion ram capacity becomes 1024 bytes by the reset input. caution there are differences in noise immunity and noise radiation between the prom and mask rom versions. when pre-producing an application set with the prom version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. 15 m pd78p018fy 2. pin functions 2.1 pins during normal operating mode (1) port pins (1/2) input input/ output input/ output input/ output input p00 p01 p02 p03 p04 note1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input/output can be specified in 1-bit units. when used as an input port, an on-chip pull- up resistor can be specified by means of software. input input intp0/ti0 intp1 intp2 intp3 xt1 ani0 to ani7 si1 so1 sck1 stb busy si0/sb0/sda0 so0/sb1/sda1 sck0/scl to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 input input input/ output input/ output input input input input only input only port 2 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 1 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. note 2 port 0 5-bit input/ output port port 3 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 4 8-bit input/output port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. test input flag (krif) is set to 1 by falling edge detection. notes 1. when using the p04/xt1 pin as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1 (do not use the on-chip feedback resistor of the subsystem clock oscillator). 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, set port 1 to the input mode. at this time, on-chip pull-up resistors are automatically disconnected. pin name i/o function after reset alternate function 16 m pd78p018fy p00/ti0 p01 p02 p03 p25/sb0/sda0 p20 p26/sb1/sda1 p21 p25/si0/sda0 p26/so0/sda1 p25/si0/sb0 p26/so0/sb1 p27/scl p22 p27/sck0 p23 p24 (1) port pins (2/2) input/ output p50 to p57 input/ output p60 p61 p62 p63 p64 p65 p66 p67 input input a8 to a15 port 5 8-bit input/output port. leds can be driven directly. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 6 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. n-ch open-drain input/ output port. leds can be driven directly. rd wr wait astb pin name i/o function after reset alternate function (2) non-port pins (1/2) intp0 intp1 intp2 intp3 si0 si1 so0 so1 sb0 sb1 sda0 sda1 sck0 sck1 scl stb busy input input output input/ output external interrupt request input for which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. input falling edge detection external interrupt request input. serial interface serial data input. serial interface serial data output. serial interface serial data input/output. input input input pin name i/o function after reset alternate function input/ output input serial interface serial clock input/output. output input input input serial interface automatic transmit/receive strobe output. serial interface automatic transmit/receive busy input. 17 m pd78p018fy ti0 ti1 ti2 to0 to1 to2 pcl buz ad0 to ad7 a8 to a15 rd wr wait astb input output external count clock input to 16-bit timer (tm0). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer (tm0) output (shared as 14-bit pwm output). output input/ output clock output (for main system clock, subsystem clock trimming). buzzer output. lower address/data bus for expanding memory externally. higher address bus for expanding memory externally. strobe signal output for read from external memory. strobe signal output for writing to external memory. wait insertion at external memory access. output strobe output that externally latches address information output to port 4 and port 5 to access external memory. output output input output (2) non-port pins (2/2) a/d converter analog input. a/d converter reference voltage input. a/d converter analog power supply. connect to v dd . a/d converter ground potential. connect to v ss . system reset input. connecting crystal resonator for main system clock oscillation. connecting crystal resonator for subsystem clock oscillation. positive power supply. high voltage applied during program write/verify. in normal operating mode, connect to v ss directly. ground potential. ani0 to ani7 av ref av dd av ss reset x1 x2 xt1 xt2 v dd v pp v ss input input input input input 8-bit timer (tm1) output. p00/intp0 p33 p34 p30 p31 p32 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p10 to p17 p04 pin name i/o function after reset alternate function input input input input input input input input input input 8-bit timer (tm2) output. 18 m pd78p018fy sets prom programming mode. when +5 v or +12.5 v is applied to the v pp and low level is applied to reset pin, microcontroller is shifted to prom programming mode. applies high voltage during prom programming mode setting and program write/verify. address bus data bus prom enable input/program pulse input. read strobe input to prom. program/program inhibit input in prom programming mode. positive power supply ground potential 2.2 pins during prom programming mode function pin i/o reset v pp a0 to a16 d0 to d7 ce oe pgm v dd v ss input input input input/ output input input input 19 m pd78p018fy 2.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the input/output circuit configuration of each type, see figure 2-1. table 2-1. types of pin i/o circuits 2 8-a 16 11 8-a 5-a 8-a 5-a 8-a 10-a 5-a 8-a 5-a 5-e 5-a 13-d 5-a 2 16 pin name i/o recommended connection when not used input/output circuit type p00/intp0/ti0 p01/intp1 p02/intp2 p03/intp3 p04/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb reset xt2 av ref av dd av ss v pp input input/output input input/output input connect to v ss . independently connect to v ss via a resistor. connect to v dd . independently connect to v dd or v ss via a resistor. independently connect to v dd via a resistor. independently connect to v dd or v ss via a resistor. independently connect to v dd via a resistor. independently connect to v dd or v ss via a resistor. leave open. connect to v ss . connect to v dd . connect to v ss . connect directly to v ss . 20 m pd78p018fy figure 2-1. pin input/output circuits pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd input enable pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd in schmitt-triggered input with hysteresis characteristic pullup enable data output disable in / out n-ch v ref input enable pullup enable data output disable v p-ch n-ch p-ch in / out dd v dd open drain xt1 (threshold voltage) v p-ch n-ch p-ch dd v p-ch + comparator dd data output disable n-ch in / out v dd rd middle-voltage input buffer feedback cut-off xt2 p-ch p-ch type 2 type 5-a type 5-e type 8-a type 16 type 13-d type 11 type 10-a 21 m pd78p018fy 3. internal memory size switching register (ims) this register is used to disable the use of part of the internal memory by software. by setting this register (ims), it is possible to get the same memory map as that of the mask rom versions with a different internal memory (rom, ram). ims is set with an 8-bit memory manipulate instruction. reset input sets ims to cfh. figure 3-1. internal memory size switching register format symbol 7 6 5 4 3 2 1 0 address after reset r/w fff0h cfh w i ms ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 rom3 rom2 rom1 rom0 selection of internal rom capacity 0 0 1 0 8 kbytes 0 1 0 0 16 kbytes 0 1 1 0 24 kbytes 1 0 0 0 32 kbytes 1 0 1 0 40 kbytes 1 1 0 0 48 kbytes 1 1 1 0 56 kbytes note 1 1 1 1 60 kbytes setting prohibited selection of internal high-speed ram capacity 0 1 0 512 bytes 1 1 0 1024 bytes setting prohibited ram2 ram1 ram0 other than above other than above note if external device expansion functions are to be employed for the m pd78p018fy, set the size of the internal rom to 56 kbytes or below using the internal memory size switching register (ims). 42h 44h c6h c8h cah cch cfh table 3-1 shows the setting values of ims which make the memory map the same as that of the mask rom versions. table 3-1. internal memory size switching register setting values ims setting value target mask rom versions m pd78011fy m pd78012fy m pd78013fy m pd78014fy m pd78015fy m pd78016fy m pd78018fy 22 m pd78p018fy 1 0 1 0 1024 bytes (f400h to f7ffh) 1 0 1 1 512 bytes (f600h to f7ffh) 1 1 0 0 0 bytes setting prohibited 4. internal expansion ram size switching register (ixs) this register is used to disable the use of part of the internal expansion ram capacity by software. by setting this register (ixs), it is possible to get the same memory map as that of the mask rom versions with a different internal expansion ram. ixs is set with an 8-bit memory manipulate instruction. reset input sets ixs to 0ah. figure 4-1. internal expansion ram size switching register format 7 6 5 4 3 2 1 0 address after reset r/w fff4h 0ah w ixs 0 0 0 0 ix ix ix ix ram3 ram2 ram1 ram0 ix ix ix ix ram3 ram2 ram1 ram0 other than above selection of internal expansion ram capacity 0ch note 0bh 0ah table 4-1 shows the setting values of ixs which make the memory map the same as that of the mask rom versions. table 4-1. internal expansion ram size switching register setting values ixs setting value target mask rom versions m pd78011fy m pd78012fy m pd78013fy m pd78014fy m pd78015fy m pd78016fy m pd78018fy note even if a program for the m pd78p018fy in which "mov ixs, #0ch" is written is executed in the m pd78011fy, 78012fy, 78013fy, and 78014fy, the operations are not affected. 23 m pd78p018fy 5. prom programming the m pd78p018fy has an internal 60-kbyte prom as a program memory. for programming, set the prom programming mode by setting the v pp and reset pins. for unused pin connection, refer to pin configuration (top view) (2) prom programming mode . caution when writing in a program, use locations 0000h-efffh (specify the last address as efffh). you cannot write in using a prom programmer that cannot specify the addresses to write. 5.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and the low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 5-1 when the ce, oe, and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 5-1. operating modes of prom programming pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance : l or h 24 m pd78p018fy (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p018fys are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly, after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0 to d7 pins of multiple m pd78p018fys are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high. 25 m pd78p018fy 5.2 prom write procedure figure 5-1. page program mode flow chart g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes write end defective product 26 m pd78p018fy figure 5-2. page program mode timing a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input hi-z 27 m pd78p018fy figure 5-3. byte program mode flow chart g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1-ms program pulse verify verify all bytes write end defective product 28 m pd78p018fy figure 5-4. byte program mode timing cautions 1. v dd should be applied before v pp and cut after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. removing and reinserting while +12.5 v is applied to v pp may adversely affect reliability. a0 to a16 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il data output data input hi-z program program verify 29 m pd78p018fy 5.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configuration (top view) (2) prom programming mode. (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 5-5. figure 5-5. prom read timings a0 to a16 d0 to d7 ce (input) oe (input) hi-z hi-z data output address input 30 m pd78p018fy 6. program erasure (for m pd78p018fydw, 78p018fykk-s) the m pd78p018fydw, 78p018fykk-s are capable of erasing (ffh) the contents of data written in a program memory and rewriting. when erasing the contents of data, irradiate light having a wavelength of less than about 400 nm to the erasure window. normally, irradiate ultraviolet rays of 254 nm wavelength. volume of irradiation required to completely erase the contents of data is as follows: ? uv intensity erasing time: 30 w ? s/cm 2 or more ? erasing time: 40 min. or longer (when a uv lamp of 12 mw/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, contamination of the erasure window, etc.) when erasing the contents of data, set up the uv lamp within 2.5 cm from the erasing window. further, if a filter is provided for a uv lamp, irradiate the ultraviolet rays after removing the filter. 7. opaque film on erasure window (for m pd78p018fydw, 78p018fykk-s) to protect from unintentional erasure by rays other than that of the lamp for erasing eprom contents, or to protect internal circuit other than eprom from misoperating by rays, cover the erasure window with an opaque film when eprom contents erasure is not performed. 8. one-time prom version screening the one-time prom versions ( m pd78p018fycw, 78p018fygc-ab8) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. storage temperature storage time 125 c 24 hours nec provides for a fee one-time prom writing, marking, screening, and verify service for products designated as qtop microcontrollers. for details, contact an nec sales representative. 31 m pd78p018fy parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v av dd C0.3 to v dd + 0.3 v av ref C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage p00 to p04, p10 to p17, p20 to p27, p30 to p37, v i1 p40 to p47, p50 to p57, p64 to p67, x1, x2, C0.3 to v dd + 0.3 v xt2, reset v i2 p60 to p63 open-drain C0.3 to +16 v a9 prom C0.3 to +13.5 v programming mode output voltage v o C0.3 to v dd + 0.3 v analog input p10 to p17 analog input pin v voltage output 1 pin C10 ma current, high i oh total for p10 to p17, p20 to p27, p30 to p37 C15 ma total for p01 to p03, p40 to p47, p50 to p57, p60 to p67 C15 ma output 1 pin peak value 30 ma current, low rms value 15 ma total for p40 to p47, p50 to p55 peak value 100 ma rms value 70 ma total for p01 to p03, p56, p57, peak value 100 ma p60 to p67 rms value 70 ma total for p01 to p03, peak value 50 ma p64 to p67 rms value 20 ma total for p10 to p17, p20 to p27, peak value 50 ma p30 to p37 rms value 20 ma operating ambient C40 to +85 c temperature storage C65 to +150 c temperature 9. electrical specifications absolute maximum ratings (t a = 25 c) v i3 v an i ol note t a t stg av ss C 0.3 to av ref + 0.3 note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceed even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 32 m pd78p018fy parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v. 15 pf i/o capacitance p01 to p03, p10 to p17, f = 1 mhz p20 to p27, p30 to p37, 15 pf c io unmeasured pins p40 to p47, p50 to p57, returned to 0 v. p64 to p67 p60 to p63 20 pf unit mhz ms mhz ms mhz ns 2.7 v v dd 5.5 v 1 10 1.8 v v dd < 2.7 v 1 5 v dd = 4.5 to 5.5 v 10 30 capacitance ( t a = 25 c, v dd = v ss = 0 v ) main system clock oscillator characteristics ( t a = e40 to +85 c, v dd = 1.8 to 5.5 v) resonator ceramic resonator crystal resonator external clock recommended circuit parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) typ. max. test conditions after v dd reaches oscil- lator voltage range min. notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire the area enclosed by the broken line in the above figures as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always keep the ground point of the oscillator capacitor to the same potential as v ss . ? do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. min. 2.7 v v dd 5.5 v 1 10 1.8 v v dd < 2.7 v 1 5 4 1.0 10.0 45 500 remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port functions. x2 x1 c1 c2 v pp x2 x1 c1 c2 v pp x2 x1 m pd74hcu04 33 m pd78p018fy subsystem clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillator voltage min. min. 32 32 5 typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s resonator crystal resonator external clock test conditions v dd = 4.5 to 5.5 v parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) cautions 1. when using the subsystem clock oscillator, wire the area enclosed by the broken line in the above figures as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always keep the ground point of the oscillator capacitor to the same potential as v ss . ? do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consump- tion current, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit xt1 xt2 c4 c3 r1 v pp xt2 xt1 m pd74hcu04 34 m pd78p018fy main system clock: ceramic resonator (t a = C40 to +85 c) recommended oscillator constants ccr4.0mc3 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr4.0mc5 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr4.19mc3 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr4.19mc5 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr5.00mc3 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type fcr5.00mc5 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type ccr8.00mc 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr8.00mc5 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type ccr8.38mc 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr8.38mc5 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type ccr10.00mc 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, surface mounting type fcr10.00mc5 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type csa4.00mg 4.00 30 30 1.8 5.5 insertion type cst4.00mgw 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa4.19mg 4.19 30 30 1.8 5.5 insertion type cst4.19mgw 4.19 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa5.00mg 5.00 30 30 1.8 5.5 insertion type cst5.00mgw 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type csa8.00mtz 8.00 30 30 2.7 5.5 insertion type cst8.00mtw 8.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type csa8.38mtz 8.38 30 30 2.7 5.5 insertion type cst8.38mtw 8.38 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type csa10.00mtz 10.00 30 30 2.7 5.5 insertion type cst10.00mtw 10.00 on-chip on-chip 2.7 5.5 on-chip capacitor, insertion type name manufacturer remarks frequency (mh z ) oscillation voltage range recommended oscillator constants c1 (pf) c2 (pf) min. (v ) max. (v) tdk murata mfg. co., ltd. caution the oscillator constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. if oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit. please contact directly the manufacturer of the resonator to be used. 35 m pd78p018fy main system clock: ceramic resonator (t a = e20 to +80 c) pbrc4.00a 4.00 33 33 1.8 5.5 surface mounting type pbrc4.00b 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type kbr-4.00msa 4.00 33 33 1.8 5.5 insertion type kbr-4.00mks 4.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type pbrc5.00a 5.00 33 33 1.8 5.5 surface mounting type pbrc5.00b 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, surface mounting type kbr-5.00msa 5.00 33 33 1.8 5.5 insertion type kbr-5.00mks 5.00 on-chip on-chip 1.8 5.5 on-chip capacitor, insertion type kbr-8m 8.00 33 33 2.7 5.5 insertion type kbr-10m 10.00 33 33 2.7 5.5 insertion type name manufacturer remarks frequency (mh z ) oscillation voltage range recommended oscillator constants c1 (pf) c2 (pf) min. (v) max. (v) kyocera corporation caution the oscillator constants and oscillation voltage range indicate conditions for stable oscillation. the oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. 36 m pd78p018fy parameter symbol test conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67 v ih2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8v dd v dd v p33, p34, reset 0.85v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7v dd 15 v (n-ch open-drain) 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p04, xt2 4.5 v v dd 5.5 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v 1.8 v v dd < 2.7 v note 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67 v il2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, reset 0 0.15v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p04, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v 1.8 v v dd < 2.7 v note 0 0.1v dd v output v oh1 v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v voltage, high i oh = C100 m av dd C 0.5 v output v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v voltage, low i ol = 15 ma p01 to p03, p10 to p17, p20 to p27, v dd = 4.5 to 5.5 v, 0.4 v p30 to p37, p40 to p47, p64 to p67 i ol = 1.6 ma v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, open- 0.2v dd v drain pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) 0.8v dd v dd v note when using xt1/p04 as p04, input the inverse phase of p04 should be input to xt2 using an inverter. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 0 0.2v dd v 37 m pd78p018fy parameter symbol test conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 m a current, high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, reset i lih2 x1, x2, xt1/p04, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, C3 m a current, low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, reset i lil2 x1, x2, xt1/p04, xt2 C20 m a i lil3 p60 to p63 C3 note m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low software r v in = 0 v, p01 to p03, p10 to p17, p20 to p27, p30 to p37, 15 40 90 k w pull-up resistor p40 to p47, p50 to p57, p64 to p67 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) note for pins p60 to p63, a low-level input leak current of C200 m a (max.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (p6) or port mode register 6 (pm6). outside the period of 3 clocks following execution a read-out instruction, the current is C3 m a (max.). remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 38 m pd78p018fy parameter symbol test conditions min. typ. max. unit supply i dd1 10.00-mhz crystal v dd = 5.0 v 10 % note 2 12.0 24.0 ma current note 1 oscillation operation mode v dd = 3.0 v 10 % note 3 1.4 2.8 ma i dd2 10.00-mhz crystal v dd = 5.0 v 10 % note 2 4.0 8.0 ma oscillation halt mode v dd = 3.0 v 10 % note 3 1.4 2.8 ma i dd3 32.768-khz crystal v dd = 5.0 v 10 % 150 300 m a oscillation operation mode note 4 v dd = 3.0 v 10 % 100 200 m a v dd = 2.0 v 10 % 60 120 m a i dd4 32.768-khz crystal v dd = 5.0 v 10 % 25 50 m a oscillation halt mode note 4 v dd = 3.0 v 10 % 5 15 m a v dd = 2.0 v 10 % 2.5 10 m a i dd5 xt1 = v dd v dd = 5.0 v 10 % 2.0 30 m a stop mode when using feedback v dd = 3.0 v 10 % 1.0 10 m a resistor v dd = 2.0 v 10 % 0.5 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10 % 0.1 30 m a stop mode when not using v dd = 3.0 v 10 % 0.05 10 m a feedback resistor v dd = 2.0 v 10 % 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. refers to the current flowing to the v dd pin. the current flowing to the on-chip pull-up resistors, ports, and a/d converter is not included. 2. when operating at high-speed mode (when the processor clock control register (pcc) is set to 00h) 3. when operating at low-speed mode (when pcc is set to 04h) 4. when main system clock operation stopped. 39 m pd78p018fy parameter symbol test conditions min. typ. max. unit cycle time t cy operating with main system 3.5 v v dd 5.5 v 0.4 64 m s (min. instruction clock 2.7 v v dd < 3.5 v 0.8 64 m s execution time) 1.8 v v dd < 2.7 v 2.0 64 m s operating with subsystem clock 40 note 1 122 125 m s ti0 input t tih0 , 3.5 v v dd 5.5 v 2/f sam +0.1 note 2 m s high- /low-level t til0 2.7 v v dd < 3.5 v 2/f sam +0.2 note 2 m s width 1.8 v v dd < 2.7 v 2/f sam +0.5 note 2 m s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 , high-/low-level t til1 width interrupt t inth , intp0 3.5 v v dd 5.5 v 2/f sam +0.1 note 2 m s request input t intl 2.7 v v dd < 3.5 v 2/f sam +0.2 note 2 m s high-/low-level 1.8 v v dd < 2.7 v 2/f sam +0.5 note 2 m s width intp1 to intp3, kr0 to kr7 v dd = 2.7 to 5.5 v 10 m s 20 m s reset low- t rsl v dd = 2.7 to 5.5 v 10 m s level width 20 m s ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) v dd = 4.5 to 5.5 v 100 ns 1.8 m s notes 1. value when an external clock is used. this value is 114 m s (min.) when a crystal resonator is used. 2. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f x /2 n+1 , f x /64, and f x /128 (when n= 0 to 4). t cy vs. v dd (at main system clock operation) 60.0 5.0 1.0 0.5 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 3.5 5.5 2.7 operation guaranteed range m 40 m pd78p018fy parameter symbol test conditions min. max. unit astb high-level width t asth 0.5t cy ns address setup time t ads 0.5t cy C30 ns address hold time t adh 50 ns data input time from address t add1 (2.5+2n)t cy C50 ns t add2 (3+2n)t cy C100 ns data input time from rd t rdd1 (1+2n)t cy C25 ns t rdd2 (2.5+2n)t cy C100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5+2n)t cy C20 ns t rdl2 (2.5+2n)t cy C20 ns wait input time from rd t rdwt1 0.5t cy ns t rdwt2 1.5t cy ns wait input time from wr t wrwt 0.5t cy ns wait low-level width t wtl (0.5+2n)t cy +10 (2+2n)t cy ns write data setup time t wds 100 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.5+2n)t cy C20 ns rd delay time from astb t astrd 0.5t cy C30 ns wr delay time from astb t astwr 1.5t cy C30 ns astb - delay time from t rdast t cy C10 t cy +40 ns rd - in external fetch address hold time from t rdadh t cy t cy +50 ns rd - in external fetch write data output time from rd - t rdwd v dd = 4.5 to 5.5 v 0.5t cy +5 0.5t cy +30 ns 0.5t cy +15 0.5t cy +90 ns write data output time from wr t wrwd v dd = 4.5 to 5.5 v 5 30 ns 15 90 ns address hold time from wr - t wradh v dd = 4.5 to 5.5 v t cy t cy +60 ns t cy t cy +100 ns rd - delay time from wait - t wtrd 0.5t cy 2.5t cy +80 ns wr - delay time from wait - t wtwr 0.5t cy 2.5t cy +80 ns (2) read/write operation (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) remarks 1. t cy = t cy /4 2. n indicates the number of waits. 41 m pd78p018fy (ii) 3-wire serial i/o mode (sck0... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-/low-level t kh2 , 4.5 v v dd 5.5 v 400 ns width t kl2 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si0 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time t ksi2 400 ns (from sck0 - ) so0 output delay time t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck0 500 ns sck0 rise/fall time t r2 , when external device 160 ns t f2 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (3) serial interface (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-/low-level t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2C50 ns width t kl1 t kcy1 /2C100 ns si0 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si0 hold time t ksi1 400 ns (from sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0 note c is the load capacitance of sck0 and so0 output lines. note c is the load capacitance of so0 output line. 42 m pd78p018fy parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 2.7 v v dd 5.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh4 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1300 ns 2100 ns sck0 low-level width t kl4 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns sb0, sb1 setup time t sik4 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sb0, sb1 output delay t kso4 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns time from sck0 c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 0 800 ns sck0 rise/fall time t r4 , when external device 160 ns t f4 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (iii) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k w , 2.7 v v dd 5.5 v 1600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh3 v dd = 2.7 to 5.5 v t kcy3 /2C160 ns t kcy3 /2C190 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2C50 ns t kcy3 /2C100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 - ) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi3 600 ns (from sck0 - ) sb0, sb1 output delay t kso3 0 300 ns time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (iv) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 43 m pd78p018fy parameter symbol test conditions min. typ. max. unit scl cycle time t kcy5 r = 1 k w , 2.7 v v dd 5.5 v 10 m s c = 100 pf note 2.0 v v dd < 2.7 v 20 m s 30 m s scl high-level width t kh5 v dd = 2.7 to 5.5 v t kcy5 C160 ns t kcy5 C190 ns scl low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 C50 ns t kcy5 C100 ns sda0, sda1 setup time t sik5 2.7 v v dd 5.5 v 200 ns (to scl - ) 2.0 v v dd < 2.7 v 300 ns 400 ns sda0, sda1 hold time t ksi5 0ns (from scl ) sda0, sda1 output t kso5 4.5 v v dd 5.5 v 0 300 ns delay time from scl 2.0 v v dd < 4.5 v 0 500 ns 0 600 ns sda0, sda1 from scl - t ksb 200 ns or sda0, sda1 - from scl - scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns 500 ns sda0, sda1 high-level t sbh 500 ns width (v) i 2 c bus mode (scl... internal clock output) note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. parameter symbol test conditions min. typ. max. unit scl cycle time t kcy6 1000 ns scl high-/low-level t kh6 ,v dd = 2.0 to 5.5 v 400 ns width t kl6 600 ns sda0, sda1 setup time t sik6 v dd = 2.0 to 5.5 v 200 ns (to scl - ) 300 ns sda0, sda1 hold time t ksi6 0ns (from scl ) sda0, sda1 output t kso6 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns delay time from scl c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 0 600 ns sda0, sda1 from scl - t ksb 200 ns or sda0, sda1 - from scl - scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns 500 ns sda0, sda1 high-level t sbh v dd = 2.0 to 5.5 v 500 ns width 800 ns scl rise/fall time t r6 , when external device 160 ns t f6 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (vi) i 2 c bus mode (scl... external clock input) note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. 44 m pd78p018fy (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh8 , 4.5 v v dd 5.5 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik8 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi8 400 ns (from sck1 - ) so1 output delay time t kso8 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise/fall time t r8 , when external device 160 ns t f8 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (ii) 3-wire serial i/o mode (sck1... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2C50 ns width t kl7 t kcy7 /2C100 ns si1 setup time t sik7 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 note c is the load capacitance of sck1 and so1 output lines. note c is the load capacitance of the so1 output line. 45 m pd78p018fy (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh9 ,v dd = 4.5 to 5.5 v t kcy9 /2C50 ns width t kl9 t kcy9 /2C100 ns si1 setup time t sik9 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi9 400 ns (from sck1 - ) so1 output delay time t kso9 c = 100 pf note 300 ns from sck1 stb - from sck1 - t sbd t kcy9 /2C100 t kcy9 /2+100 ns strobe signal t sbw 2.7 v v dd 5.5 v t kcy9 C30 t kcy9 +30 ns high-level width 2.0 v v dd < 2.7 v t kcy9 C60 t kcy9 +60 ns t kcy9 C90 t kcy9 +90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal 2.7 v v dd < 4.5 v 150 ns detection timing) 2.0 v v dd < 2.7 v 200 ns 300 ns sck1 from busy t sps 2t kcy9 ns inactive note c is the load capacitance of the sck1 and so1 output lines. 46 m pd78p018fy (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high-/low-level t kh10 , 4.5 v v dd 5.5 v 400 ns width t kl10 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik10 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi10 400 ns (from sck1 - ) so1 output delay time t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise/fall time t r10 , t f10 when external device expansion 160 ns function is used when external device expansion 1000 ns function is not used note c is the load capacitance of the so1 output line. 47 m pd78p018fy ac timing test point (excluding x1, xt1 input) ti timing clock timing 0.8 v dd 0.2 v dd test points 0.8 v dd 0.2 v dd x1 input v ih4 ( min. ) v il4 ( max. ) 1/f x t xl t xh xt1 input v ih5 ( min. ) v il5 ( max. ) 1/f xt t xtl t xth ti0 t til0 t tih0 ti1,ti2 1/f ti1 t til1 t tih1 48 m pd78p018fy read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add1 hi-z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd lower 8-bit address 49 m pd78p018fy external data access (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 hi-z t ads t asth t adh t rdd2 read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl t rdh t rdl2 hi-z lower 8-bit address a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 t ads t asth t adh t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z hi-z lower 8-bit address external data access (wait insertion): 50 m pd78p018fy serial transfer timing 3-wire serial i/o mode: i 2 c bus mode: 2-wire serial i/o mode: si0,si1 so0,so1 m = 1, 2, 7, 8 n = 2, 8 t kcym t klm t khm t sikm t ksim input data t ksom output data t fn t rn sck0,sck1 sck0 sb0, sb1 t kcy3,4 t kl3,4 t kh3,4 t r4 t f4 t kso3,4 t sik3,4 t ksi3,4 scl t sbh t sbk sda0, sda1 t kl5, 6 t kh5, 6 t ksi5, 6 t sik5, 6 t kso5, 6 t ksb t sbk t ksb t kcy5, 6 t f6 t r6 51 m pd78p018fy note the signal is not actually driven low here; it is shown as such to indicate the timing. 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): so1 sck1 si1 stb d2 d1 d0 d2 d1 d0 t sik9,10 t ksi9,10 t kso9,10 t kh9,10 t f10 t r10 t kl9,10 t kcy9,10 t sbw t sbd d7 d7 sck1 busy 7 8 910 10 + n t bys t byh t sps 1 (active high) note note note 52 m pd78p018fy parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error note 2.7 v av ref av dd 0.6 % 2.2 v av ref < 2.7 v 1.4 % conversion time t conv 2.7 v av ref av dd 19.1 200 m s 2.2 v av ref < 2.7 v 38.2 200 m s sampling time t samp 24/f x m s analog input voltage v ian av ss av ref v reference voltage av ref 2.2 av dd v av ref resistance r airef 414 k w a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 2.2 to 5.5 v, av ss = v ss = 0 v) data retention timing (stop mode release by reset) note overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply v dddr 1.8 5.5 v voltage data retention supply i dddr v dddr = 1.8 v 0.1 10 m a current subsystem clock stops and feed- back resistor disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 18 /f x ms wait time release by interrupt request note ms note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 13 /f x and 2 15 /f x to 2 18 /f x is possible. v dd stop instruction execution reset v dddr internal reset operation halt mode operating mode t wait t srel data retention mode stop mode 53 m pd78p018fy data retention timing (standby release signal: stop mode release by interrupt request signal) reset input timing interrupt input request timing v dd stop instruction execution standby release signal (interrupt request) v dddr halt mode operating mode t srel t wait data retention mode stop mode t intl t inth t intl intp0 to intp2 intp3 t rsl reset 54 m pd78p018fy parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma prom programming characteristics dc characteristics (1) prom write mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma note corresponding m pd27c1001a symbol (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) note corresponding m pd27c1001a symbol 55 m pd78p018fy parameter symbol symbol note test conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time (from pgm - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe hold time t oeh 2 m s parameter symbol symbol note test conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe pulse width during data latching t lw t lw 1 m s pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol 56 m pd78p018fy (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbol note test conditions min. typ. max. unit data output time from address t acc t acc ce = oe = v il 800 ns data output delay time from ce t ce t ce oe = v il 800 ns data output delay time from oe t oe t oe ce = v il 200 ns data output float delay time from oe - t df t df ce = v il 060ns data hold time from address t oh t oh ce = oe = v il 0ns note corresponding m pd27c1001a symbol (3) prom programming mode setting (t a = 25 c, v ss = 0 v) parameter symbol test conditions min. typ. max. unit prom programming mode setup time prom write mode timing (page program mode) t sma 10 m s t oe a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input hi? hi? hi? t ah t oeh t oes t ceh t pw t ahv t df t ces t ahl t as t dh t lw t vds t vps t ds t pgms 57 m pd78p018fy notes 1. when reading within the t acc range, the oe input delay time from the ce fall time must be maximum of t acc C t oe . 2. t df is the time from the point at which either oe or ce (whichever is first) reaches v ih . prom write mode timing (byte program mode) cautions 1. v dd must be applied before v pp and cut off after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. removing and reinserting while +12.5 v is applied to v pp may adversely affect reliability. prom read mode timing pgm program program verify t as t ds t vps t vds t oeh t ces t pw t dh hi-z hi-z hi-z t df t ah t oes t oe oe ce v dd v pp d0 to d7 v pp v dd v dd + 1.5 v dd v ih v il v ih v il v ih v il a0 to a16 data input data output oe ce d0 to d7 a0 to a16 t ce t acc t oe hi-z hi-z t oh t df effective address data output note 1 v ih v il v ih v il note 1 note 2 58 m pd78p018fy prom programming mode setting timing a0 to a16 effective address t sma reset v dd v pp v dd 0 v dd 0 59 m pd78p018fy 8. characteristic curve (reference value) i dd vs. v dd (main system clock: 10.0 mhz) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd [v] supply current i dd [ma] 5678 t a = 25 c pcc = 00h pcc = 01h pcc = b0h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 halt) halt (x1 halt, xt1 oscillation) f x = 10.0 mhz f xt = 32.768 khz 60 m pd78p018fy 11. package drawings remark the dimensions and materials of es (engineering sample) versions are the same as those of mass-produced versions. a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2 0.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50 0.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126 0.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mils) 61 m pd78p018fy 64 pin ceramic shrink dip (750 mils) notes 1) each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maximum material condition. item millimeters inches b c a l 18.8 0.740 2) item "k" to center of leads when formed parallel. 58.68 max. 2.310 max. 1.78 max. 0.070 max. 1.778 (t.p.) 0.070 (t.p.) h 1.0 min. 0.039 min. d 0.46 0.05 0.018 0.002 f 0.8 min. 0.031 min. g 3.5 0.3 0.138 0.012 k i 3.0 0.118 j 5.08 max. 0.200 max. 19.05 (t.p.) 0.750 (t.p.) p64dw-70-750a-1 n 0.25 0.010 s 0~15 0~15 m 0.25 0.05 0.010 +0.002 ?.003 r 0.350 f 8.89 f j i h g m r c b f d s m n 64 33 132 a k l 62 m pd78p018fy remark the dimensions and materials of es (engineering sample) versions are the same as those of mass-produced versions. 64 pin plastic qfp (14x14) item millimeters inches i j 0.8 (t.p.) 0.15 0.006 0.031 (t.p.) a 17.6 0.4 0.693 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f g 1.0 1.0 0.039 0.039 h 0.37 0.015 p64gc-80-ab8-4 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 n 0.10 0.004 +0.08 ?.07 +0.08 ?.07 q 0.1 0.1 0.004 0.004 r s 2.85 max. 5 5 5 5 0.113 max. +0.003 ?.004 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. m q r k m l p g f hi s detail of lead end k 1.8 0.2 0.071 0.008 p 2.55 0.1 0.100 0.004 +0.003 ?.004 48 49 32 64 1 17 16 33 s a b cd j ns 63 m pd78p018fy 64 pin ceramic wqfn b z a u c d u1 f g t m j hi r 1 64 s q w k x64kw-80a1 item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 14.0 0.18 13.4 13.4 14.0 0.18 1.84 3.56 max. 0.51 0.1 0.08 0.8 (t.p.) 1.0 0.15 c 0.3 1.0 1.0 r 3.0 10.8 1.4 0.75 0.15 0.10 0.551 0.007 0.528 0.528 0.551 0.007 0.072 0.141 max. 0.02 0.004 0.003 0.031 (t.p.) 0.039 c 0.012 0.039 0.039 r 0.118 0.425 0.055 0.03 0.004 a b c d f g h i j k q r s t u u1 w z +0.007 ?.006 +0.006 ?.007 64 m pd78p018fy 12. recommended soldering conditions the m pd78p018fy should be soldered and mounted under the following recommended conditions. for the recommended soldering conditions, refer to the document "semiconductor device mounting technol- ogy manual" (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 12-1. surface mounting type soldering conditions m pd78p018fygc-ab8: 64-pin plastic qfp (14 14 mm) soldering method soldering conditions infrared reflow vps wave soldering partial heating package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less solder bath temperature: 260 c, time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c max., time: 3 seconds max. (per pin row) ir35-00-3 vp15-00-3 ws60-00-1 symbol caution do not use different soldering methods together (except for partial heating). solder temperature: 260 c max., time: 10 seconds max. pin temperature: 300 c max., time: 3 seconds max. (per pin) table 12-2. insertion type soldering conditions m pd78p018fycw: 64-pin plastic shrink dip (750 mils) m pd78p018fydw: 64-pin ceramic shrink dip (with window) (750 mils) soldering method soldering conditions wave soldering (pin only) partial heating caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. 65 m pd78p018fy appendix a. development tools the following development tools are available for system development using the m pd78p018fy. read (5) cautions on using developing tools for reference. (1) language processing software ra78k/0 assembler package common to 78k/0 series cc78k/0 c compiler package common to 78k/0 series df78014 device file common to m pd78018f subseries cc78k/0-l c compiler library source file common to 78k/0 series (2) prom writing tools pg-1500 prom programmer pa-78p018cw programmer adapter connected to pg-1500 pa-78p018gc pa-78p018kk-s pg-1500 controller pg-1500 control program (3) debugging tool ? when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-70000-98-if-c interface adapter required when using pc-9800 series as host machine (excluding notebook pcs, c bus supported) ie-70000-cd-if-a pc card and interface cable required when using notebook pc of pc-9800 series as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm compatible as host machine (isa bus supported) ie-70000-pci-if adapter when using pc that incorporates pci bus as host machine ie-78018-ns-em1 emulation board common to m pd78018f subseries np-64cw emulation probe for 64-pin plastic shrink dip (cw type) np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) ev-9200gc-64 socket to be mounted on a target system board made for 64-pin plastic qfp (gc-ab8 type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df78014 device file common to m pd78018f subseries 66 m pd78p018fy when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter required when using pc-9800 series as host machine (excluding notebook pcs, c bus supported) ie-70000-pc-if-c interface adapter required when using ibm pc/at compatible as host machine (isa bus supported) ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-70000-pci-if adapter when using pc that incorporates pci bus as host machine ie-78018-ns-em1 emulation board common to m pd78018f subseries ie-78k0-r-ex1 emulation probe conversion board necessary to use ie-78018-ns-em1 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic shrink dip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ev-9200gc-64 socket to be mounted on a target system board made for 64-pin plastic qfp (gc-ab8 type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df78014 device file common to m pd78018f subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series 67 m pd78p018fy (5) cautions on using development tools ? the id-78k0-ns, id78k0, and sm78k0 are used in combination with the df78014. ? the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 and the df78014. ? np-64cw and np-64gc are products made by naitou densei machidaseisakusho (tel: +81-44-822- 3813). contact an nec distributor regarding the purchase of these products. ? for third party development tools, see the 78k/0 series selection guide (u11126e) . ? the host machine and os suitable for each software are as follows: host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k/0 ? note ? cc78k/0 ? note ? pg-1500 controller ? note id78k0-ns ? id78k0 ?? sm78k0 ? rx78k/0 ? note ? mx78k0 ? note ? note dos-based software 68 m pd78p018fy drawing of conversion socket (ev-9200gc-64) and recommended footprint figure a-1. drawing of ev-9200gc-64 (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 f f f f 69 m pd78p018fy figure a-2. recommended footprint of ev-9200gc-64 (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 f f f +0.002 ?.001 +0.003 ?.002 +0.002 ?.001 +0.003 ?.002 +0.004 ?.003 +0.004 ?.003 +0.001 ?.002 f f f +0.001 ?.002 +0.004 ?.005 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution 70 m pd78p018fy appendix b. related documents device related documents document name document no. japanese english m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78018fy data sheet u10281j u10281e m pd78p018fy data sheet u10989j this document m pd78018f, 78018fy subseries user's manual u10659j u10659e 78k/0 series user's manual - instructions u12326j u12326e 78k/0 series instruction list u10903j 78k/0 series instruction set u10904j m pd78018fy subseries special function register list u10287j 78k/0 series application note basics (i) u12704j u12704e floating-point arithmetic programs u13482j iea-1289 development tool documents (user's manual) (1/2) document name document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e ra78k series structured assembler preprocessor u12323j eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how u13034j u13034e pg-1500 prom programmer u11940j u11940e pg-1500 controller pc-9800 series (ms-dos tm ) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos tm ) based eeu-5008 u10540e ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-78018-ns-em1 u13289j to be prepared ep-78240 eeu-986 u10332e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 71 m pd78p018fy development tool documents (user's manual) (2/2) document name document no. japanese english sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external part user open u10092j u10092e interface specification id78k0-ns integrated debugger windows based reference u12900j u12900e id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e embedded software documents (user's manual) document name document no. japanese english 78k/0 series real-time os basic u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 basic u12257j u12257e other documents document name document no. japanese english nec ic package manual (cd-rom) c13388e semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damages for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to quality assurance for semiconductor devices mei-1202 microcomputer C related product guide C third parties u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 72 m pd78p018fy [memo] 73 m pd78p018fy notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. 74 m pd78p018fy fip, iebus, and qtop are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. 75 m pd78p018fy nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 11 m pd78p018fy the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. license not needed: m pd78p018fydw, 78p018fykk-s the customer must judge the need for license: m pd78p018fycw, 78p018fygc-ab8 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 |
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