? semiconductor components industries, llc, 2001 may, 2001 rev. 7 1 publication order number: mc14046b/d mc14046b phase locked loop the mc14046b phase locked loop contains two phase comparators, a voltagecontrolled oscillator (vco), source follower, and zener diode. the comparators have two common signal inputs, pca in and pcb in . input pca in can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. the selfbias circuit adjusts small voltage signals in the linear region of the amplifier. phase comparator 1 (an exclusive or gate) provides a digital error signal pc1 out , and maintains 90 phase shift at the center frequency between pca in and pcb in signals (both at 50% duty cycle). phase comparator 2 (with leading edge sensing logic) provides digital error signals, pc2 out and ld, and maintains a 0 phase shift between pca in and pcb in signals (duty cycle is immaterial). the linear vco produces an output signal vco out whose frequency is determined by the voltage of input vco in and the capacitor and resistors connected to pins c1 a , c1 b , r1, and r2. the sourcefollower output sf out with an external resistor is used where the vco in signal is needed but no loading can be tolerated. the inhibit input inh, when high, disables the vco and source follower to minimize standby power consumption. the zener diode can be used to assist in power supply regulation. applications include fm and fsk modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltagetofrequency conversion and motor speed control. ? buffered outputs compatible with mhtl and lowpower ttl ? diode protection on all inputs ? supply voltage range = 3.0 to 18 v ? pinforpin replacement for cd4046b ? phase comparator 1 is an exclusive or gate and is duty cycle limited ? phase comparator 2 switches on rising edges and is not duty cycle limited maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in input voltage range (all inputs) 0.5 to v dd + 0.5 v i in dc input current, per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14046bcp pdip16 2000/box mc14046bdw so16 2350/box mc14046bdwr2 so16 1000/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14046bcp awlyyww so16 dw suffix case 751g 1 16 14046b awlyyww eiaj so16 f suffix case 966 1 16 mc14046b alyw mc14046bf eiaj so16 refer to note 1. mc14046bfel eiaj so16 refer to note 1. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid ap- plications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused out- puts must be left open.
mc14046b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 r2 pc2 out pca in zener v dd vco in sf out r1 vco out pcb in pc1 out ld v ss c1 b c1 a inh block diagram pca in pcb in vco in inh 14 3 9 5 v dd = pin 16 v ss = pin 8 2pc1 out 13pc2 out 1ld 4vco out 11r1 12r2 6c1 a 7c1 b 10sf out 15zener v ss self bias circuit phase comparator 1 phase comparator 2 voltage controlled oscillator (vco) source follower ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) ??????????? ??????????? ??? ??? ??? ??? v dd ?????? ?????? 55 c ???????? ???????? 25 c ????? ????? 125 c ??? ??? ??????????? ??????????? characteristic ??? ??? symbol ??? ??? v dd vdc ??? ??? min ???? ???? max ??? ??? min ???? ???? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? unit ??????????? ? ????????? ? ??????????? output voltage a0o level v in = v dd or 0 ??? ? ? ? ??? v ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ???? ? ?? ? ???? 0.05 0.05 0.05 ??? ? ? ? ??? e e e ???? ? ?? ? ???? 0 0 0 ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? vdc ??????????? ? ????????? ? ??????????? a1o level v in = 0 or v dd ??? ? ? ? ??? v oh ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 4.95 9.95 14.95 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 4.95 9.95 14.95 ???? ? ?? ? ???? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? e e e ??? ? ? ? ??? vdc ??????????? ? ????????? ? ? ????????? ? ??????????? input voltage (4.) a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ??? ? ? ? ? ? ? ??? v il ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 2.25 4.50 6.75 ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? vdc ??????????? ? ????????? ? ??????????? (v o = 0.5 or 4.5 vdc) a1o level (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) ??? ? ? ? ??? v ih ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 3.5 7.0 11 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 3.5 7.0 11 ???? ? ?? ? ???? 2.75 5.50 8.25 ??? ? ? ? ??? e e e ??? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ??? e e e ??? ? ? ? ??? vdc ??????????? ? ????????? ? ? ????????? ? ? ????????? ? ??????????? output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) ??? ? ? ? ? ? ? ? ? ? ??? i oh ??? ? ? ? ? ? ? ? ? ? ??? 5.0 5.0 10 15 ??? ? ? ? ? ? ? ? ? ? ??? 1.2 0.25 0.62 1.8 ???? ? ?? ? ? ?? ? ? ?? ? ???? e e e e ??? ? ? ? ? ? ? ? ? ? ??? 1.0 0.2 0.5 1.5 ???? ? ?? ? ? ?? ? ? ?? ? ???? 1.7 0.36 0.9 3.5 ??? ? ? ? ? ? ? ? ? ? ??? e e e e ??? ? ? ? ? ? ? ? ? ? ??? 0.7 0.14 0.35 1.1 ??? ? ? ? ? ? ? ? ? ? ??? e e e e ??? ? ? ? ? ? ? ? ? ? ??? madc ??????????? ? ????????? ? ??????????? (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) ??? ? ? ? ??? i ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 0.64 1.6 4.2 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0.51 1.3 3.4 ???? ? ?? ? ???? 0.88 2.25 8.8 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.36 0.9 2.4 ??? ? ? ? ??? e e e ??? ? ? ? ??? madc ??????????? ??????????? input current ??? ??? i in ??? ??? 15 ??? ??? e ???? ???? 0.1 ??? ??? e ???? ???? 0.00001 ??? ??? 0.1 ??? ??? e ??? ??? 1.0 ??? ??? m adc ??????????? ??????????? input capacitance ??? ??? c in ??? ??? e ??? ??? e ???? ???? e ??? ??? e ???? ???? 5.0 ??? ??? 7.5 ??? ??? e ??? ??? e ??? ??? pf ??????????? ? ????????? ? ? ????????? ? ??????????? quiescent current (per package) inh = pca in = v dd , zener = vco in = 0 v, pcb in = v dd or 0 v, i out = 0 m a ??? ? ? ? ? ? ? ??? i dd ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 5.0 10 20 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 0.005 0.010 0.015 ??? ? ? ? ? ? ? ??? 5.0 10 20 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 150 300 600 ??? ? ? ? ? ? ? ??? m adc ??????????? ? ????????? ? ? ????????? ? ??????????? total supply current (5.) (inh = a0o, f o = 10 khz, c l = 50 pf, r1 = 1.0 m w , r2 = r sf = , and 50% duty cycle) ??? ? ? ? ? ? ? ??? i t ??? ? ? ? ? ? ? ??? 5.0 10 15 ????????????????? ? ??????????????? ? ? ??????????????? ? ????????????????? i t = (1.46 m a/khz) f + i dd i t = (2.91 m a/khz) f + i dd i t = (4.37 m a/khz) f + i dd ??? ? ? ? ? ? ? ??? madc 4. noise immunity specified for worstcase input combination. noise margin for both a1o and a0o level = 1.0 vdc min @ v dd = 5.0 vdc 2.0 vdc min @ v dd = 10 vdc 2.5 vdc min @ v dd = 15 vdc 5. to calculate total current in general: i t 2.2 x v dd + 1 x 10 3 (c l + 9) v dd f + vco in 1.65 + v dd 1.35 3/4 r1 r2 vco in 1.65 3/4 + 1.6 x where: i t in m a, c l in pf, vco in , v dd in vdc, f in khz, and r1, r2, r sf in m w , c l on vco out . r sf 1 x 10 1 v dd 2 100% duty cycle of pca in 100 + i q
mc14046b http://onsemi.com 3 electrical characteristics (6.) (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? ???? ???? ????? ????? v dd ???? ???? minimum ???? ???? ???? ???? maximum ??? ??? ??????????????? ??????????????? characteristic ???? ???? symbol ????? ????? v dd vdc ???? ???? device ???? ???? typical ???? ???? device ??? ??? units ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns ???? ? ?? ? ? ?? ? ???? t tlh ????? ? ??? ? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 180 90 65 ???? ? ?? ? ? ?? ? ???? 350 150 110 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? output fall time t thl = (1.5 ns/pf) c l + 25 ns t thl = (0.75 ns/pf) c l + 12.5 ns t thl = (0.55 ns/pf) c l + 9.5 ns ???? ? ?? ? ? ?? ? ???? t thl ????? ? ??? ? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 100 50 37 ???? ? ?? ? ? ?? ? ???? 175 75 55 ??? ? ? ? ? ? ? ??? ns ????????????????????????????????? ????????????????????????????????? phase comparators 1 and 2 ??????????????? ? ????????????? ? ??????????????? input resistance e pca in ???? ? ?? ? ???? r in ????? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ???? 1.0 0.2 0.1 ???? ? ?? ? ???? 2.0 0.4 0.2 ???? ? ?? ? ???? e e e ??? ? ? ? ??? m w ??????????????? ??????????????? e pcb in ???? ???? r in ????? ????? 15 ???? ???? 150 ???? ???? 1500 ???? ???? e ??? ??? m w ??????????????? ? ????????????? ? ??????????????? minimum input sensitivity ac coupled e pca in c series = 1000 pf, f = 50 khz ???? ? ?? ? ???? v in ????? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ???? e e e ???? ? ?? ? ???? 200 400 700 ???? ? ?? ? ???? 300 600 1050 ??? ? ? ? ??? mv pp ??????????????? ??????????????? dc coupled e pca in , pcb in ???? ???? e ????? ????? 5 to 15 ?????????? ?????????? see noise immunity ??? ??? ????????????????????????????????? ????????????????????????????????? voltage controlled oscillator (vco) ??????????????? ? ????????????? ? ??????????????? maximum frequency (vco in = v dd , c1 = 50 pf r1 = 5.0 k w , and r2 = ) ???? ? ?? ? ???? f max ????? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ???? 0.5 1.0 1.4 ???? ? ?? ? ???? 0.7 1.4 1.9 ???? ? ?? ? ???? e e e ??? ? ? ? ??? mhz ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? temperature e frequency stability (r2 = ) ???? ? ?? ? ? ?? ? ???? e ????? ? ??? ? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 0.12 0.04 0.015 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? %/ c ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? linearity (r2 = ) (vco in = 2.5 v 0.3 v, r1 > 10 k w ) (vco in = 5.0 v 2.5 v, r1 > 400 k w ) (vco in = 7.5 v 5.0 v, r1 1000 k w ) ???? ? ?? ? ? ?? ? ???? e ????? ? ??? ? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 1.0 1.0 1.0 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? % ??????????????? ??????????????? output duty cycle ???? ???? e ????? ????? 5 to 15 ???? ???? e ???? ???? 50 ???? ???? e ??? ??? % ??????????????? ??????????????? input resistance e vco in ???? ???? r in ????? ????? 15 ???? ???? 150 ???? ???? 1500 ???? ???? e ??? ??? m w ????????????????????????????????? ????????????????????????????????? sourcefollower ??????????????? ? ????????????? ? ??????????????? offset voltage (vco in minus sf out , rsf > 500 k w ) ???? ? ?? ? ???? e ????? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ???? e e e ???? ? ?? ? ???? 1.65 1.65 1.65 ???? ? ?? ? ???? 2.2 2.2 2.2 ??? ? ? ? ??? v ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? linearity (vco in = 2.5 v 0.3 v, r sf > 50 k w ) (vco in = 5.0 v 2.5 v, r sf > 50 k w ) (vco in = 7.5 v 5.0 v, r sf > 50 k w ) ???? ? ?? ? ? ?? ? ???? e ????? ? ??? ? ? ??? ? ????? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 0.1 0.6 0.8 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? % ????????????????????????????????? ????????????????????????????????? zener diode ??????????????? ??????????????? zener voltage (i z = 50 m a) ???? ???? v z ????? ????? e ???? ???? 6.7 ???? ???? 7.0 ???? ???? 7.3 ??? ??? v ??????????????? ??????????????? dynamic resistance (i z = 1.0 ma) ???? ???? r z ????? ????? e ???? ???? e ???? ???? 100 ???? ???? e ??? ??? w 6. the formula given is for the typical characteristics only.
mc14046b http://onsemi.com 4 figure 1. phase comparators state diagrams phase comparator 1 input stage pca in xx pcb in 00 01 11 10 pc1 out 01 phase comparator 2 input stage pca in xx pcb in pc2 out 01 3state output disconnected ld (lock detect) 0 0 1 refer to waveforms in figure 3. 00 01 10 11 00 10 01 11 00 01 10 11 ???????????? ???????????? characteristic ???????????? ???????????? using phase comparator 1 ??????????? ??????????? using phase comparator 2 ???????????? ? ?????????? ? ???????????? no signal on input pca in . ???????????? ? ?????????? ? ???????????? vco in pll system adjusts to center frequency (f 0 ). ??????????? ? ????????? ? ??????????? vco in pll system adjusts to minimum frequency (f min ). ???????????? ? ?????????? ? ???????????? phase angle between pca in and pcb in . ???????????? ? ?????????? ? ???????????? 90 at center frequency (f 0 ), approaching 0 and 180 at ends of lock range (2f l ) ??????????? ? ????????? ? ??????????? always 0 in lock (positive rising edges). ???????????? ???????????? locks on harmonics of center frequency. ???????????? ???????????? yes ??????????? ??????????? no ???????????? ???????????? signal input noise rejection. ???????????? ???????????? high ??????????? ??????????? low ???????????? ? ?????????? ? ???????????? lock frequency range (2f l ). ?????????????????????? ? ???????????????????? ? ?????????????????????? the frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2f l = full vco frequency range = f max f min . ???????????? ? ?????????? ? ???????????? capture frequency range (2f c ). ?????????????????????? ? ???????????????????? ? ?????????????????????? the frequency range of the input signal on which the loop will lock if it was initially out of lock. ???????????? ? ?????????? ? ???????????? ? ?????????? ? depends on lowpass filter characteristics (see figure 3). f c f l ??????????? ? ????????? ? f c = f l ???????????? ? ?????????? ? ???????????? center frequency (f 0 ). ?????????????????????? ? ???????????????????? ? ?????????????????????? the frequency of vco out , when vco in = 1/2 v dd ???????????? ? ?????????? ? ? ?????????? ? ? ?????????? ? ? ?????????? ? ? ?????????? ? ? ?????????? ? ???????????? vco output frequency (f). note: these equations are intended to be a design guide. since calculated component values may be in error by as much as a factor of 4, laboratory experimentation may be required for fixed designs. part to part frequency variation with identical passive components is typically less than 20%. ?????????????????????? ? ???????????????????? ? ? ???????????????????? ? ? ???????????????????? ? ? ???????????????????? ? ? ???????????????????? ? ? ???????????????????? ? ?????????????????????? where: 10k r 1 1 m 10k r 2 1 m 100pf c 1 .01 m f figure 2. design information + f min f min =(v co input = v ss ) r 2 (c 1 + 32 pf) 1 f max = r 1 (c 1 + 32 pf) 1 (v co input = v dd )
mc14046b http://onsemi.com 5 typical lowpass filters note: sometimes r3 is split into two series resistors each r3 2. a capacitor c c is then placed from the midpoint to ground. the value for c c should be such that the corner frequency of this network does not significantly affect w n . in figure b, the ratio of r3 to r4 sets the damping, r4 (0.1)(r3) for optimum results. figure 3. general phaselocked loop connections and waveforms waveforms note: for further information, see: (1) f. gardner, aphaselock techniqueso, john wiley and son, new york, 1966. (2) g. s. moschytz, aminiature rc filters using phaselocked loopo, bstj, may, 1965. (3) garth nash, aphaselock loop design fundamentalso, an535, motorola inc. (4) a. b. przedpelski, aphaselocked loop design articleso, ar254, reprinted by motorola inc. pca in @ frequency f pcb in 14 3 phase comparator external low-pass filter vco 2 or 13 pc1 out or pc2 out vco in 9 9 10 4 external n counter r1 r2 11 12 6 7 ci a ci b ci sf out r sf vco out @ frequency nf = f (a) input r3 output c2 2f c 1 2 f l r3 c2 (a) input r3 output r4 c2 typically: r 4 c 2 6n f max n 2 f (r 3 3, 000 )c 2 100n f f max 2 r 4 c 2 d f = f max f min definitions: n = total division ratio in feedback loop k f = v dd / p for phase comparator 1 k f = v dd /4 p for phase comparator 2 k vco 2 f vco v dd 2v 2 f r 10 for a typical design w n (at phase detector input) z 0.707 lowpass filter filter a filter b n k k vco nr 3 c 2 n n 2k k vco f(s) 1 r 3 c 2 s 1 n k k vco nc 2 (r 3 r 4 ) 0.5 n (r 3 c 2 n k k vco ) f(s) r 3 c 2 s 1 s(r 3 c 2 r 4 c 2 ) 1 pca in pcb in pc1 out vco in v dd v ss v oh v ol v oh v ol v oh v ol pca in pcb in pc2 out vco in ld v dd v ss v oh v ol v oh v ol v oh v ol v ol v oh phase comparator 1 phase comparator 2 source follower
mc14046b http://onsemi.com 6 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14046b http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14046b http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14046b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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