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1 features ? 64-megabit (4m x 16) flash memory 2.7v - 3.6v read/write high performance ? asynchronous access time ? 70 ns ? page mode read time ? 20 ns ? synchronous burst frequency ? 66 mhz ? configurable burst operation sector erase architecture ? eight 4k word sectors with individual write lockout ? 32k word main sectors with individual write lockout typical sector erase time: 32k word sectors ? 500 ms; 4k word sectors ? 100 ms 64m, four plane organization, permitting concurrent read in any of three planes not being programmed/erased ? memory plane a: 16m of memory including eight 4k word sectors ? memory plane b: 16m of memory consisting of 32k word sectors ? memory plane c: 16m of memory consisting of 32k word sectors ? memory plane d: 16m of memory consisting of 32k word sectors suspend/resume feature for erase and program ? supports reading and programming data from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?30 ma active ? 10 a standby 1.8v i/o option reduces overall system power data polling and toggle bit for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization tsop or cbga package top or bottom boot block configuration available 128-bit protection register common flash interface (cfi) description the at49bn/bv6416(t) is a 2.7-volt 64-megabit flash memory. the memory is divided into multiple sectors and planes for erase operations. the devices can be read or reprogrammed off a single 2.7v power supply, making them ideally suited for in-sys- tem programming. the output voltage can be separately controlled down to 1.65v through the vccq supply pin. the devices can be configured to operate in the asyn- chronous/page read (default mode) or burst read mode (not available for the at49bv6416(t)). the burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. if the avd and the clk signals are both tied to gnd, the device will behave like a standard asynchronous flash memory. in the page mode, the avd signal can be tied to gnd or can be pulsed low to latch the page address. in both cases the clk can be tied to gnd. 64-megabit (4m x 16) burst/page mode 2.7-volt flash memory at49bv6416 at49bv6416t at49bn6416 AT49BN6416T advance information rev. 2481c?flash?5/03
2 at49bn/bv6416(t) 2481c?flash?5/03 pin configurations 1. these signals are not available for use with the at49bv6416(t). the at49bv6416(t) can only be used in the asynchronous/four word page mode. at49bn6416(t) cbga top view at49bv6416(t) tsop top view type 1 pin name pin function i/o0 - i/o15 data inputs/outputs a0 - a21 addresses (1) ce chip enable oe output enable we write enable avd address latch enable clk clock reset reset wp write protect vpp write protection and power supply for accelerated program/erase operations rdy ready vccq output power supply a b c d e f g 1 2345678 a11 a12 a13 a15 vccq vss i/o7 a8 a9 a10 a14 i/o15 i/o14 vss vss a20 a21 rdy i/o6 i/013 i/o5 vcc clk avd a16 i/o4 i/o11 vcc vpp reset we i/o12 i/o2 i/o10 i/o3 a18 a17 a19 wp i/o1 i/o9 vccq a6 a5 a7 ce i/o0 i/o8 a4 a3 a2 a1 a0 oe vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a21 a20 we reset vpp wp a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 vccq gnd i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0
3 at49bn/bv6416(t) 2481c?flash?5/03 the at49bn/bv6416(t) is divided into four memory planes. a read operation can occur in any of the three planes which is not being programmed or erased. this concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. there is no reason to suspend the erase or program operation if the data to be read is in the other memory plane. the end of program or erase is detected by data polling or toggle bit. the vpp pin provides data pr otection and faster programming and erase times. when the v pp input is below 0.8v, the program and erase functions are inhibited. when v pp is at 1.65v or above, normal program and erase operations can be performed. with v pp at 12.0v, the program and erase operations are accelerated. with v pp at 12v, a six-byte command (enter single pulse program mode) to remove the requirement of entering the three-byte progr am sequence is offered to further improve programming time. after entering the six-byte code, only single pulses on the write con- trol lines are required for writing into the device. this mode (single pulse word program) is exited by powering down the device, by taking the reset pin to gnd or by a high-to-low transition on the v pp input. erase, erase suspend/resume, program sus- pend/resume and read reset commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external pro- gramming code. device operation command sequences: the device powers on in the read mode. command sequences are used to place the device in other operating modes such as program and erase. after the completion of a program or an erase cycle, the device enters the read mode. the command sequences are written by applying a low pulse on the we input with ce low and oe high or by applying a low-going pulse on the ce input with we low and oe high. prior to the low-going pulse on the ce or we signal, the address input may be latched by a low-to-high transition on the avd signal or the rising edge of the first clock pulse when avd is low, whichever occurs first. if the avd is not pulsed low, the address will be latched on the falling edge of the we or ce pulse whichever occurs first. valid data is latched on the rising edge of the we or the ce pulse, whichever occurs first. the addresses used in the command sequences are not affected by enter- ing the command sequences. burst configuration command: the program burst configuration register command is used to program the burst configuration register. the burst configuration register determines several parameters that control the read operation of the device. bit b15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. since the page read operation is an asynchronous operation, bit b15 must be set for asynchronous reads to enable the page read feature. bit b14 determines whether a four word page or an eight word page will be used. the rest of the bits in the burst configuration register are used only for the burst read mode. bits b13 - b11 of the burst configuration register determine the clock latency for the burst mode. the latency can be set to two, three, four, five or six cycles. the clock latency versus input clock fre- quency table is shown on page 16. the ?burst read waveform? as shown on page 27 illustrates a clock latency of four; the data is output from the device four clock cycles after the first low-to-high clock edge following the high-to-low avd edge. the b10 bit of the configuration register determines the polarity of the rdy signal. the b9 bit of the
4 at49bn/bv6416(t) 2481c?flash?5/03 burst configuration register determines the number of clocks that data will be held valid (see figure 1). the b8 bit of the burst configuration register determines when the rdy signal will be asserted. when synchronous burst reads are enabled, an interleaved or linear burst sequence can be selected by setting bit b7. table 4 shows the difference between the interleaved and burst sequence. bit b6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. bits b2 - b0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four- or eight-word length will be used in the fixed-length mode. when a four or eight word burst length is selected, bit b3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses. please see table 4. all other bits in the burst configuration register should be programmed as shown on page 16. the default state (after power-up or reset) of the burst configuration register is also shown on page 16. to read the burst configuration register, the product id entry command is given, followed by a normal read operation from address location 00005h. after reading the burst configuration register, the product id exit command must be given prior to performing any other operation. asynchronous read: there are two types of asynchronous reads ? avd pulsed and standard asynchronous reads. the avd pulsed read operation of the device is con- trolled by ce , oe , and avd inputs. the outputs are put in the high-impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in prevent- ing bus contention. the data at the address location defined by a0 - a21 and captured by the avd signal will be read when ce and oe are low. the address location passes into the device when ce and avd are low; the address is latched on the low-to-high transition of avd . low input levels on the oe and ce pins allow the data to be driven out of the device. the access time is measured from stable address, falling edge of avd or falling edge of ce , whichever occurs last. during the avd pulsed read, the clk sig- nal may be static high or static low. for standard asynchronous reads, the avd and clk signal should be tied to gnd. the asynchronous read diagrams are shown on page 24. page read: the page read operation of the device is controlled by ce , oe , and avd inputs. the clk input is ignored during a page read operation and should be tied to gnd. the page size can be four words (default value) or eight words depending on what value bit b14 of the burst configuration register is programmed to. during a page read, the avd signal can transition low and then transition high, transition low and remain low, or can be tied to gnd. if a high to low transition on the avd signal occurs, as shown in page read cycle waveform 1, the page address is latched by the low-to- high transition of the avd signal. however, if the avd signal remains low after the high- to-low transition or if the avd signal is tied to gnd, as shown in page read cycle waveform 2, then the page address (determined by a21 - a3 for an eight word page and a21 - a2 for a four word page) cannot change during a page read operation. the first word access of the page read is the same as the asynchronous read. the first word is read at an asynchronous speed of 80 ns. once the first word is read, toggling a0 and a1 (four word page mode) or toggling a0, a1, and a2 (eight word page mode) will result in subsequent reads within the page being output at a speed of 20 ns. if the avd and the clk pins are both tied to gnd, the device will behave like a standard asynchronous flash memory. the page read diagrams are shown on page 25. synchronous reads: synchronous reads (not available on the at49bv6416(t)) are used to achieve a faster data rate that is possible in the asynchronous/page read mode. the device can be configured for continuous or fixed-length burst access. the burst read operation of the device is controlled by ce , oe , clk and avd inputs. the ini- tial read location is determined as for the avd pulsed asynchronous read operation; it can be any memory location in the device. in the burst access, the address is latched on
5 at49bn/bv6416(t) 2481c?flash?5/03 the rising edge of the first clock pulse when avd is low or the rising edge of the avd sig- nal, whichever occurs first. the clk input signal controls the flow of data from the device for a burst operation. after the clock latency cycles, the data at the next burst address location is read for each following clock cycle. continuous burst read: during a continuous burst read, any number of addresses can be read from the memory. when a page boundary in the memory is transitioned, additional time may be required for the device to continue the burst read. to indicate that it is not ready to continue the burst, the device will drive the rdy pin low (b10 = 0) during the clock cycles in which new data is not being presented. once the rdy pin is driven high (b10 = 0), the next data will be valid. starting with address zero, page boundaries occur every 128 words in the memory. during a continuous burst read, the first page boundary transition may occur before 128 words are read, depending on the initial burst address. the rdy signal will be tri-stated when the ce or oe signal is high. in the ?burst read waveform? as shown on page 27, data d0 is valid asynchronously from point a, the time when the addresses are latched. d0 is valid within 13.0 ns of the clock edge for the specified clock latency (the waveforms show a clock latency of four). the low-to-high transition of the clock at point c results in d1 being read. the transition of the clock at point d results in a burst read of the last word of the page, d127. the clock transition at point e does not cause new data to appear on the output lines because the rdy signal goes low (b10 and b8 = 0) after the clock transition, which sig- nifies that a page boundary in the memory has been crossed and that new data is not available. the clock transition at point f does cause a burst read of data d128 because the rdy signal goes high (b10 and b8 = 0) after the clock transition indicating that new data is available. additional clock transitions, like at point g, will continue to result in burst reads until the next page boundary is crossed between words d255 and d256. fixed-length burst reads: during a fixed-length burst mode read, four or eight words of data may be burst from the device, depending upon the configuration. the device supports a linear or interleaved burst mode. the burst sequence is shown on page 17. the rdy output remains high (b10 = 0) during fixed-length bursts. the ?four- word burst read waveform? on page 27 illustrates a fixed-length burst cycle. as in the continuous burst read, the data d0 is valid asynchronously from point a, the time when the addresses are latched. d0 is valid within 13.0 ns of the clock edge for the specified clock latency (shown for the case of a latency of four). the low-to-high transition of the clock at point c results in d1 being read. similarly, d2 and d3 are output following the next two clock cycles. returning ce high ends the read cycle. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to read or standby mode, depending upon the state of the control pins. erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical ?1?. the entire memory can be erased by using the chip erase command or individual planes or sectors can be erased by using the plane erase or sector erase commands. chip erase: chip erase is a six-bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. after the full chip erase the device will return back to the read mode. the hard- ware reset during chip erase will stop the erase but the data will be of unknown state. any command during chip erase except erase suspend will be ignored.
6 at49bn/bv6416(t) 2481c?flash?5/03 plane erase : as a alternative to a full chip er ase, the device is organized into four planes that can be individually erased. the plane erase command is a six-bus cycle operation. the plane whose address is valid at the sixth falling edge of we will be erased provided none of the sectors within the plane are protected. sector erase: as an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. the sector erase com- mand is a six-bus cycle operation. the sector whose address is valid at the sixth falling edge of we will be erased provided the given sector has not been protected. word programming: the device is programmed on a word-by-word basis. pro- gramming is accomplished via the internal device command register and is a four-bus cycle operation. the programming address and data are latched in the fourth cycle. the device will automatically generate the requ ired internal progr amming pulses. please note that a ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. flexible sector protection: the at49bn/bv6416(t) offers two sector protec- tion modes, the softlock and the hardlock. the softlock mode is optimized as sector protection for sectors whose content changes frequently. the hardlock protection mode is recommended for sectors whose content changes infrequently. once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. each sector can be independently programmed for either the softlock or hardlock sector protection mode. at power-up and reset, all sectors have their softlock protection mode enabled. softlock and unlock: the softlock protection mode can be disabled by issuing a two-bus cycle unlock command to the selected sector. once a sector is unlocked, its contents can be erased or programmed. to enable the softlock protection mode, a six- bus cycle softlock command must be issued to the selected sector. hardlock and write protect (wp ): the hardlock sector protection mode oper- ates in conjunction with the write protection (wp ) pin. the hardlock sector protection mode can be enabled by issuing a six-bus cycle hardlock software command to the selected sector. the state of the write protect pin affects whether the hardlock protec- tion mode can be overridden. when the wp pin is low and the hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. when the wp pin is high, the hardlock protection mode is overridden and the sector can be unlocked via the unlock command. to disable the hardlock sector protection mode, the chip must be either reset or power cycled.
7 at49bn/bv6416(t) 2481c?flash?5/03 sector protection detection: a software method is available to determine if the sector protection softlock or hardlock features are enabled. when the device is in the software product identification mode (see software product identification entry and exit sections) a read from the i/o0 and i/o1 at address location 00002h within a sector will show if the sector is unlocked, softlocked, or hardlocked. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6, and i/o7. all other status bits are don?t care. the table 3 on page 13 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the at49bn/bv6416(t) contains a programmable configuration register. the configuration register allows the user to specify the status bit operation. th e configuration register can be set to one of two different values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is important to note that whether the configuration register is set to a ?00? or to a ?01?, table 1. hardlock and softlock protection configurations in conjunction with wp v pp wp hard lock soft lock erase/ prog allowed? comments v cc /5v 0 0 0 yes no sector is locked v cc /5v 0 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 0 1 1 no hardlock protection mode is enabled. the sector cannot be unlocked. v cc /5v 1 0 0 yes no sector is locked. v cc /5v 1 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 1 1 0 yes hardlock protection mode is overridden and the sector is not locked. v cc /5v 1 1 1 no hardlock protection mode is overridden and the sector can be unlocked via the unlock command. v il x x x no erase and program operations cannot be performed. table 2. sector protection status i/o1 i/o0 sector protection status 0 0 sector not locked 0 1 softlock enabled 1 0 hardlock enabled 1 1 both hardlock and softlock enabled
8 at49bn/bv6416(t) 2481c?flash?5/03 any unsuccessful program or erase operati on requires using the product id exit com- mand to return the device to read mode. the default value (after power-up) for the configuration register is ?00?. using the four-bus cycle set configuration register com- mand as shown in the command definiti on table on page 14, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration register. the value of the configuration register will affect the operation of the i/o7 status bit as described below. data polling: the at49bn/bv6416(t) features data polling to indicate the end of a program cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see table 3 on page 13 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing data. i/o7 will go high when the device has completed a program or erase operation. once i/o7 has gone high, status informa- tion on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 2 and 3. toggle bit: in addition to data polling, the at49bn/bv6416(t) provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a pro- gram cycle. please see table 3 on page 13 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 4 and 5 on page 12. erase/program status bit: the device offers a status bit on i/o5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a byte/word program operation has been successfully performed. the device may also output a ?1? on i/o5 if the system tries to program a ?1? to a location that was previously pro- grammed to a ?0?. only an erase operation can change a ?0? back to a ?1?. if a program (sector erase) command is issued to a protected sector, the protected sector will not be programmed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) operation did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see table 3 on page 13 for more details. v pp status bit: the at49bn/bv6416(t) provides a status bit on i/o3 that provides information regarding the voltage level of the vpp pin. during a program or erase oper- ation, if the voltage on the vpp pin is not high enough to perform the desired operation successfully, the i/o3 status bit will be a ?1?. once the v pp status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. on the other hand, if the voltage level is high enough to perform a program or erase opera- tion successfully, the v pp status bit will output a ?0?. please see table 3 on page 13 for more details.
9 at49bn/bv6416(t) 2481c?flash?5/03 erase suspend/erase resume: the erase suspend command allows the sys- tem to interrupt a sector erase operation and then program or read data from a different sector within the same plane. since this device has a dual plane architecture, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in the other plane. after the erase suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase sus- pend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command, which does require the plane address. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is protected. the command sequence for a chip erase suspend and a sec- tor erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming oper ation and then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. after the program- ming operation has been suspended, the system can then read from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume com- mand. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. 128-bit protection register: the at49bn/bv6416(t) contains a 128-bit regis- ter that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two bloc ks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. to program block b in the protection regis- ter, the four-bus cycle program protection register command must be used as shown in the command definition in hex table on page 14. to lock out block b, the four-bus cycle lock protection register command must be used as shown in the command definition in hex table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be repro- grammed. please see the protection register addressing table on page 15 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not or reading the protection register, the product id exit command must be given prior to performing any other operation. cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to inter- face to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to address 55h. the
10 at49bn/bv6416(t) 2481c?flash?5/03 cfi query command can be written when the device is ready to read data or can also be written when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table 5 on page 33. to exit the cfi query mode, the product id exit command must be given. if the cfi query command is given while the part is in the product id mode, then the product id exit command must first be given to return the part to the product id mode. once in the product id mode, it will be necessary to give another product id exit command to return the part to the read mode. hardware data protection: hardware features protect against inadvertent pro- grams to the at49bn/bv6416(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time-out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) v pp is less than v ilpp . input levels: while operating with a 2.7v to 3.1v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can be driven from 0 to v ccq + 0.6v. output levels: for the at49bn/bv6416(t), output high levels are equal to v ccq - 0.1v (not v cc ). for 2.7v to 3.1v output levels, v ccq must be tied to v cc . figure 1. output configuration valid output valid output valid output valid output valid output clk i/00 - i/015 i/00 - i/015 1 clk data hold (b9 = 0) 2 clk data hold (b9 = 1)
11 at49bn/bv6416(t) 2481c?flash?5/03 figure 2. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 3. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 addr = va i/o7 = 1? i/o3, i/o5 = 1? program/erase operation not successful, write product id exit command no no yes yes program/erase operation successful, write product id exit command
12 at49bn/bv6416(t) 2481c?flash?5/03 figure 4. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes figure 5. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
13 at49bn/bv6416(t) 2481c?flash?5/03 table 3. status bit table i/o7 i/o6 i/o2 configuration register: 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 read address in plane a plane b plane c plane d plane a plane b plane c plane d plane a plane b plane c plane d while programming in plane a i/o7 / 0 data data data to g g l e data data data 1 data data data programming in plane b data i/o7 / 0 data data data to g g l e data data data 1 data data programming in plane c data data i/o7 / 0 data data data to g g l e data data data 1 data programming in plane d data data data i/o7 /0 data data data toggle data data data 1 erasing in plane a 0 / 0 data data data to g g l e data data data to g g l e data data data erasing in plane b data 0 / 0 data data data to g g l e data data data to g g l e data data erasing in plane c data data 0 / 0 data data data to g g l e data data data to g g l e data erasing in plane d data data data 0 / 0 data data data to g g l e data data data to g g l e erase suspended & read erasing sector 1111 1 1 1 1toggletoggletoggletoggle erase suspended & read non- erasing sector data data data data data data data data data data data data erase suspended & program non- erasing sector in plane a i/o7 / 0 data data data to g g l e data data data to g g l e data data data erase suspended & program non- erasing sector in plane b data i/o7 / 0 data data data to g g l e data data data to g g l e data data erase suspended & program non- erasing sector in plane c data data i/o7 / 0 data data data to g g l e data data data to g g l e data erase suspended & program non- erasing sector in plane d data data data i/o7 /0 data data data toggle data data data toggle
14 at49bn/bv6416(t) 2481c?flash?5/03 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex). the address format in ea ch bus cycle is as follows: a11 - a0 (hex), a11 - a21 (don?t care). 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. either one of the product id exit commands can be used. 4. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 18 - 19 for deta ils). 5. once a sector is in the hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled. 6. pa is the plane address (a21 - a20). 7. for the at49bn6416/bv6416: for the AT49BN6416T/bv6416t: xxx = 0xx555 status read from plane a xxx = 3xx555 status read from plane a xxx = 1xx555 status read from plane b xxx = 2xx555 status read from plane b xxx = 2xx555 status read from plane c xxx = 1xx555 status read from plane c xxx = 3xx555 status read from plane d xxx = 0xx555 status read from plane d 8. see ?burst configuration register? on page 16. 9. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 10. the default state (after power-up) of the configuration register is ?00?. command definition in (hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 plane erase 6 555 aa aaa 55 555 80 555 aa aaa 55 pa (6) 20 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 30 word program 4 555 aa aaa 55 555 a0 addr d in enter single-pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single-pulse word program mode 1addrd in sector softlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 40 sector unlock 2 555 aa sa (4) 70 sector hardlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4)(5) 60 erase/program suspend 1 xxx b0 erase/program resume 1 pa (6) 30 product id entry 3 555 aa aaa 55 xxx (7) 90 product id exit (3) 3 555 aa aaa 55 555 f0 product id exit (3) 1 xxx fx program burst configuration register 4 555 aa aaa 55 555 d0 xxx (8) read burst configuration register 4 555 aa aaa 55 xxx (7) 90 005 d out program protection register ? block b 4 555 aa aaa 55 555 c0 addr d in lock protection register ? block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (9) set configuration register 4 555 aa aaa 55 555 e0 xxx 00/01 (10) cfi query 1 x55 98
15 at49bn/bv6416(t) 2481c?flash?5/03 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a21 - a8 = 0. absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages except v pp (including nc pins) with respect to ground ...................................-0.6v to +6.25v v pp input voltage with respect to ground ......................................... 0v to 13.0v all output voltages with respect to ground ...........................-0.6v to v ccq + 0.6v protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0factorya10000001 1factorya10000010 2factorya10000011 3factorya10000100 4userb10000101 5userb10000110 6userb10000111 7userb10001000
16 at49bn/bv6416(t) 2481c?flash?5/03 note: 1. default state 2. this feature is not available on the at49bv6416(t). burst configuration register b15 0 1 (1) synchronous burst reads enabled asynchronous/page reads enabled b14 0 (1) 1 (2) four word page eight word page b13 - b11: 010 011 100 101 110 (1) clock latency of two clock latency of three clock latency of four clock latency of five clock latency of six b10 0 1 (1) rdy signal is active low rdy signal is active high b9 0 1 (1) hold data for one clock hold data for two clocks b8 0 1 (1) rdy asserted during clock cycle in which data is valid rdy asserted one clock cycle before data is valid b7 0 1 (1) interleaved burst sequence linear burst sequence b6 0 1 (1) burst starts and data output on falling clock edge burst starts and data output on rising clock edge b5 - b4 00 (1) reserved for future use b3 0 1 (1) wrap burst within burst length set by b2 - b0 don?t wrap accesses within burst length set by b2 - b0 b2 - b0 001 010 111 (1) four-word burst eight-word burst continuous burst clock latency versus input clock frequency minimum clock latency (minimum number of clocks following address latch) input clock frequency 6 54 mhz 4 40 mhz 2 20 mhz
17 at49bn/bv6416(t) 2481c?flash?5/03 table 4. sequence and burst length start addr. (decimal) wrap b3 = 0 wrap b3 = 1 burst addressing sequence (decimal) 4-word burst length b2 ? b0 = 001 8-word burst length b2 ? b0 = 010 continuous burst b2 ? b0 = 111 linear interleaved linear interleaved linear 0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0 -1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1 -0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2 -3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3 -2-1-0-7-6-5-4 3-4-5-6-7-8-9... 4 0 4-5-6-7-0-1-2-3 4-5-6-7 -0-1-2-3 4-5-6-7-8-9-10... 5 0 5-6-7-0-1-2-3-4 5-4-7-6 -1-0-3-2 5-6-7-8-9-10-11... 6 0 6-7-0-1-2-3-4-5 6-7-4-5 -2-3-0-1 6-7-8-9-10-11-12... 7 0 7-0-1-2-3-4-5-6 7-6-5-4-3 -2-1-0 7-8-9-10-11-12-13... ... ... ... ... ... ... ... ... 14 0 14-15-16-17-18-19-20 15 0 15-16-17-18-19-20-21 ... ... ... ... ... ... ... ... 0 1 0-1-2-3 n/a 0-1-2-3-4-5- 6-7 n/a 0-1-2-3-4-5-6... 1 1 1-2-3-4 n/a 1-2-3-4-5-6- 7-8 n/a 1-2-3-4-5-6-7... 2 1 2-3-4-5 n/a 2-3-4-5-6-7- 8-9 n/a 2-3-4-5-6-7-8... 3 1 3-4-5-6 n/a 3-4-5-6-7-8- 9-10 n/a 3-4-5-6-7-8-9... 4 1 4-5-6-7-8-9-10-11 n /a 4-5-6-7-8-9-10... 5 1 5-6-7-8-9-10-11-12 n/ a 5-6-7-8-9-10-11... 61 6-7-8-9-10-11-12- 13 n/a 6-7-8-9-10-11-12... 71 7-8-9-10-11-12-13- 14 n/a 7-8-9-10-11-12-13... ... ... ... ... ... ... ... ... 14 1 14-15-16-17-18-19-20 15 1 15-16-17-18-19-20-21
18 at49bn/bv6416(t) 2481c?flash?5/03 memory organization ? at49bn/bv6416 6416 plane sector size (words) x16 address range (a21 - a0) a sa0 4k 00000 - 00fff a sa1 4k 01000 - 01fff a sa2 4k 02000 - 02fff a sa3 4k 03000 - 03fff a sa4 4k 04000 - 04fff a sa5 4k 05000 - 05fff a sa6 4k 06000 - 06fff a sa7 4k 07000 - 07fff a sa8 32k 08000 - 0ffff a sa9 32k 10000 - 17fff a sa10 32k 18000 - 1ffff a sa11 32k 20000 - 27fff a sa12 32k 28000 - 2ffff a sa13 32k 30000 - 37fff a sa14 32k 38000 - 3ffff a sa15 32k 40000 - 47fff a sa16 32k 48000 - 4ffff a sa17 32k 50000 - 57fff a sa18 32k 58000 - 5ffff a sa19 32k 60000 - 67fff a sa20 32k 68000 - 6ffff a sa21 32k 70000 - 77fff a sa22 32k 78000 - 7ffff a sa23 32k 80000 - 87fff a sa24 32k 88000 - 8ffff a sa25 32k 90000 - 97fff a sa26 32k 98000 - 9ffff a sa27 32k a0000 - a7fff a sa28 32k a8000 - affff a sa29 32k b0000 - b7fff a sa30 32k b8000 - bffff a sa31 32k c0000 - c7fff a sa32 32k c8000 - cffff a sa33 32k d0000 - d7fff a sa34 32k d8000 - dffff a sa35 32k e0000 - e7fff a sa36 32k e8000 - effff a sa37 32k f0000 - f7fff a sa38 32k f8000 - fffff b sa39 32k 100000 - 107fff b sa40 32k 108000 - 10ffff b sa41 32k 110000 - 117fff b sa42 32k 118000 - 11ffff b sa43 32k 120000 - 127fff b sa44 32k 128000 - 12ffff b sa45 32k 130000 - 137fff b sa46 32k 138000 - 13ffff b sa47 32k 140000 - 147fff b sa48 32k 148000 - 14ffff b sa49 32k 150000 - 157fff b sa50 32k 158000 - 15ffff b sa51 32k 160000 - 167fff b sa52 32k 168000 - 16ffff b sa53 32k 170000 - 177fff b sa54 32k 178000 - 17ffff b sa55 32k 180000 - 187fff b sa56 32k 188000 - 18ffff b sa57 32k 190000 - 197fff b sa58 32k 198000 - 19ffff b sa59 32k 1a0000 - 1a7fff b sa60 32k 1a8000 - 1affff b sa61 32k 1b0000 - 1b7fff b sa62 32k 1b8000 - 1bffff b sa63 32k 1c0000 - 1c7fff b sa64 32k 1c8000 - 1cffff b sa65 32k 1d0000 - 1d7fff b sa66 32k 1d8000 - 1dffff b sa67 32k 1e0000 - 1e7fff b sa68 32k 1e8000 - 1effff b sa69 32k 1f0000 - 1f7fff b sa70 32k 1f8000 - 1fffff c sa71 32k 200000 - 207fff c sa72 32k 208000 - 20ffff c sa73 32k 210000 - 217fff c sa74 32k 218000 - 21ffff c sa75 32k 220000 - 227fff c sa76 32k 228000 - 22ffff c sa77 32k 230000 - 237fff c sa78 32k 238000 - 23ffff c sa79 32k 240000 - 247fff c sa80 32k 248000 - 24ffff c sa81 32k 250000 - 257fff c sa82 32k 258000 - 25ffff c sa83 32k 260000 - 267fff c sa84 32k 268000 - 26ffff c sa85 32k 270000 - 277fff c sa86 32k 278000 - 27ffff c sa87 32k 280000 - 287fff c sa88 32k 288000 - 28ffff c sa89 32k 290000 - 297fff memory organization ? at49bn/bv6416 (continued) 6416 plane sector size (words) x16 address range (a21 - a0)
19 at49bn/bv6416(t) 2481c?flash?5/03 c sa90 32k 298000 - 29ffff c sa91 32k 2a0000 - 2a7fff c sa92 32k 2a8000 - 2affff c sa93 32k 2b0000 - 2b7fff c sa94 32k 2b8000 - 2bffff c sa95 32k 2c0000 - 2c7fff c sa96 32k 2c8000 - 2cffff c sa97 32k 2d0000 - 2d7fff c sa98 32k 2d8000 - 2dffff c sa99 32k 2e0000 - 2e7fff c sa100 32k 2e8000 - 2effff c sa101 32k 2f0000 - 2f7fff d sa102 32k 2f8000 - 2fffff d sa103 32k 300000 - 307fff d sa104 32k 308000 - 30ffff d sa105 32k 310000 - 317fff d sa106 32k 318000 - 31ffff d sa107 32k 320000 - 327fff d sa108 32k 328000 - 32ffff d sa109 32k 330000 - 337fff d sa110 32k 338000 - 33ffff d sa111 32k 340000 - 347fff d sa112 32k 348000 - 34ffff memory organization ? at49bn/bv6416 (continued) 6416 plane sector size (words) x16 address range (a21 - a0) d sa113 32k 350000 - 357fff d sa114 32k 358000 - 35ffff d sa115 32k 360000 - 367fff d sa116 32k 368000 - 36ffff d sa117 32k 370000 - 377fff d sa118 32k 378000 - 37ffff d sa119 32k 380000 - 387fff d sa120 32k 388000 - 38ffff d sa121 32k 390000 - 397fff d sa122 32k 398000 - 39ffff d sa123 32k 3a0000 - 3a7fff d sa124 32k 3a8000 - 3affff d sa125 32k 3b0000 - 3b7fff d sa126 32k 3b8000 - 3bffff d sa127 32k 3c0000 - 3c7fff d sa128 32k 3c8000 - 3cffff d sa129 32k 3d0000 - 3d7fff d sa130 32k 3d8000 - 3dffff d sa131 32k 3e0000 - 3e7fff d sa132 32k 3e8000 - 3effff d sa133 32k 3f0000 - 3f7fff d sa134 32k 3f8000 - 3fffff memory organization ? at49bn/bv6416 (continued) 6416 plane sector size (words) x16 address range (a21 - a0)
20 at49bn/bv6416(t) 2481c?flash?5/03 memory organization ? at49bn/bv6416t 6416t plane sector size (words) x16 address range (a21 - a0) d sa0 32k 00000 - 07fff d sa1 32k 08000 - 0ffff d sa2 32k 10000 - 17fff d sa3 32k 18000 - 1ffff d sa4 32k 20000 - 27fff d sa5 32k 28000 - 2ffff d sa6 32k 30000 - 37fff d sa7 32k 38000 - 3ffff d sa8 32k 40000 - 47fff d sa9 32k 48000 - 4ffff d sa10 32k 50000 - 57fff d sa11 32k 58000 - 5ffff d sa12 32k 60000 - 67fff d sa13 32k 68000 - 6ffff d sa14 32k 70000 - 77fff d sa15 32k 78000 - 7ffff d sa16 32k 80000 - 87fff d sa17 32k 88000 - 8ffff d sa18 32k 90000 - 97fff d sa19 32k 98000 - 9ffff d sa20 32k a0000 - a7fff d sa21 32k a8000 - affff d sa22 32k b0000 - b7fff d sa23 32k b8000 - bffff d sa24 32k c0000 - c7fff d sa25 32k c8000 - cffff d sa26 32k d0000 - d7fff d sa27 32k d8000 - dffff d sa28 32k e0000 - e7fff d sa29 32k e8000 - effff d sa30 32k f0000 - f7fff d sa31 32k f8000 - fffff c sa32 32k 100000 - 107fff c sa33 32k 108000 - 10ffff c sa34 32k 110000 - 117fff c sa35 32k 118000 - 11ffff c sa36 32k 120000 - 127fff c sa37 32k 128000 - 12ffff c sa38 32k 130000 - 137fff c sa39 32k 138000 - 13ffff c sa40 32k 140000 - 147fff c sa41 32k 148000 - 14ffff c sa42 32k 150000 - 157fff c sa43 32k 158000 - 15ffff c sa44 32k 160000 - 167fff c sa45 32k 168000 - 16ffff c sa46 32k 170000 - 177fff c sa47 32k 178000 - 17ffff c sa48 32k 180000 - 187fff c sa49 32k 188000 - 18ffff c sa50 32k 190000 - 197fff c sa51 32k 198000 - 19ffff c sa52 32k 1a0000 - 1a7fff c sa53 32k 1a8000 - 1affff c sa54 32k 1b0000 - 1b7fff c sa55 32k 1b8000 - 1bffff c sa56 32k 1c0000 - 1c7fff c sa57 32k 1c8000 - 1cffff c sa58 32k 1d0000 - 1d7fff c sa59 32k 1d8000 - 1dffff c sa60 32k 1e0000 - 1e7fff c sa61 32k 1e8000 - 1effff c sa62 32k 1f0000 - 1f7fff c sa63 32k 1f8000 - 1fffff b sa64 32k 200000 - 207fff b sa65 32k 208000 - 20ffff b sa66 32k 210000 - 217fff b sa67 32k 218000 - 21ffff b sa68 32k 220000 - 227fff b sa69 32k 228000 - 22ffff b sa70 32k 230000 - 237fff b sa71 32k 238000 - 23ffff b sa72 32k 240000 - 247fff b sa73 32k 248000 - 24ffff b sa74 32k 250000 - 257fff b sa75 32k 258000 - 25ffff b sa76 32k 260000 - 267fff b sa77 32k 268000 - 26ffff b sa78 32k 270000 - 277fff b sa79 32k 278000 - 27ffff b sa80 32k 280000 - 287fff b sa81 32k 288000 - 28ffff b sa82 32k 290000 - 297fff b sa83 32k 298000 -29ffff b sa84 32k 2a0000 - 2a7fff b sa85 32k 2a8000 - 2affff b sa86 32k 2b0000 - 2b7fff b sa87 32k 2b8000 - 2bffff b sa88 32k 2c0000 - 2c7fff b sa89 32k 2c8000 - 2cffff memory organization ? at49bn/bv6416t (continued) 6416t plane sector size (words) x16 address range (a21 - a0)
21 at49bn/bv6416(t) 2481c?flash?5/03 b sa90 32k 2d0000 - 2d7fff b sa91 32k 2d8000 - 2dffff b sa92 32k 2e0000 - 2e7fff b sa93 32k 2e8000 - 2effff b sa94 32k 2f0000 - 2f7fff b sa95 32k 2f8000 - 2fffff a sa96 32k 300000 - 307fff a sa97 32k 308000 - 30ffff a sa98 32k 310000 - 317fff a sa99 32k 318000 - 31ffff a sa100 32k 320000 - 327fff a sa101 32k 328000 - 32ffff a sa102 32k 330000 - 337fff a sa103 32k 338000 - 33ffff a sa104 32k 340000 - 347fff a sa105 32k 348000 - 34ffff a sa106 32k 350000 - 357fff a sa107 32k 358000 - 35ffff a sa108 32k 360000 - 367fff a sa109 32k 368000 - 36ffff a sa110 32k 370000 - 377fff a sa111 32k 378000 - 37ffff a sa112 32k 380000 - 387fff memory organization ? at49bn/bv6416t (continued) 6416t plane sector size (words) x16 address range (a21 - a0) a sa113 32k 388000 - 38ffff a sa114 32k 390000 - 397fff a sa115 32k 398000 - 39ffff a sa116 32k 3a0000 - 3a7fff a sa117 32k 3a8000 - 3affff a sa118 32k 3b0000 - 3b7fff a sa119 32k 3b8000 - 3bffff a sa120 32k 3c0000 - 3c7fff a sa121 32k 3c8000 - 3cffff a sa122 32k 3d0000 - 3d7fff a sa123 32k 3d8000 - 3dffff a sa124 32k 3e0000 - 3e7fff a sa125 32k 3e8000 - 3effff a sa126 32k 3f0000 - 3f7fff a sa127 4k 3f8000 - 3f8fff a sa128 4k 3f9000 - 3f9fff a sa129 4k 3fa000 - 3fafff a sa130 4k 3fb000 - 3fbfff a sa131 4k 3fc000 - 3fcfff a sa132 4k 3fd000 - 3fdfff a sa133 4k 3fe000 - 3fefff a sa134 4k 3ff000 - 3fffff memory organization ? at49bn/bv6416t (continued) 6416t plane sector size (words) x16 address range (a21 - a0)
22 at49bn/bv6416(t) 2481c?flash?5/03 notes: 1. x can be vil or vih. 2. refer to ac programming waveforms. 3. manufacturer code: 001fh; device code: 00d6h - at49bn6416/bv6416; 00d2h - AT49BN6416T/bv6416t. 4. see details under ?software product identification entry/exit? on page 32. 5. the vpp pin can be tied to v cc . for faster program/erase operations, v pp can be set to 12.0v 0.5v. 6. v ihpp (min) = 1.65v. 7. v ilpp (max) = 0.8v. dc and ac operating range at49bn/bv6416(t) - 70 at49bn/bv6416(t) - 85 operating temperature (case) industrial -40c - 85c -40c - 85c v cc power supply 2.7v - 3.6v 2.7v - 3.6v operating modes mode ce oe we reset v pp (5) ai i/o read v il v il v ih v ih xai d out burst read v il v il v ih v ih xai d out program/erase (3) v il v ih v il v ih v ihpp (6) ai d in standby/program inhibit v ih x (1) xv ih xx high z program inhibit xxv ih v ih x xv il xv ih x xxx x v ilpp (7) output disable x v ih xv ih xhigh z reset xxx v il xx high z product identification software (4) v ih a0 = v il , a1 - a21 = v il manufacturer code (3) a0 = v ih , a1 - a21 = v il device code (3)
23 at49bn/bv6416(t) 2481c?flash?5/03 note: 1. in the erase mode, i cc is 30 ma. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v i/o = 0v to v cc 1a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v cc 10 a i cc (1) v cc active current f = 66 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 66 mhz; i out = 0 ma 50 ma i ccrw v cc read while write current f = 66 mhz; i out = 0 ma 50 ma v il input low voltage 0.6 v v ih input high voltage v ccq - 0.6 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a; v ccq = 1.65v - 2.2v v ccq - 0.1 v i oh = -400 a; v ccq = 2.7v - 3.1v 2.4 ac driving levels 2.0v 0.6v 1.5v ac measurement level v 1.8k output pin 30 pf 1.3k ccq pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pf v in = 0v c out 812 pf v out = 0v
24 at49bn/bv6416(t) 2481c?flash?5/03 avd pulsed asynchronous read cycle waveform (1)(2) note: 1. after the high-to-low transition on avd , avd may remain low as long as the address is stable. 2. clk may be static high or static low. asynchronous read cycle waveform (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. avd and clk should be tied low. ac asynchronous read timing characteristics symbol parameter min max units t acc1 access, avd to data valid 70 ns t acc2 access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t ahav address hold from avd 9ns t avlp avd low pulse width 10 ns t avhp avd high pulse width 10 ns t aav address valid to avd 7ns t df ce , oe high to data float 25 ns t ro reset to output delay 150 ns t ce t acc2 t df t df t ahav t avlp t acc1 data valid ce i/o0-i/o15 a0 -a21 avd oe t aav t oe t avhp reset t ro (1) output valid i/o0 - i/o15 high z reset oe toe tce address valid tdf toh tacc2 tro ce a0 - a21 trc
25 at49bn/bv6416(t) 2481c?flash?5/03 page read cycle waveform 1 (1)(2) notes: 1. after the high-to-low transition on avd , avd may remain low as long as the page address is stable. 2. the diagram shown is for a four-word page read. for an eight-word page read a0 - a1 becomes a0 - a2 and a2 - a21 becomes a3 - a21. page read cycle waveform 2 (1)(2) notes: 1. avd may remain low as long as the page address is stable. 2. the diagram shown is for a four-word page read. for an eight-word page read a0 - a1 becomes a0 - a2 and a2 - a21 becomes a3 - a21. ac asynchronous read timing characteristics symbol parameter min max units t acc1 access, avd to data valid 70 ns t acc2 access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t ahav address hold from avd 9ns t avlp avd low pulse width 10 ns t avhp avd high pulse width 10 ns t aav address valid to avd 7ns t df ce , oe high to data float 25 ns t ro reset to output delay 150 ns t pa a page address access time 20 ns t ce t acc2 t df t df t ahav data valid ce i/o0-i/o15 a2 -a21 t aav t avlp t acc1 avd oe t oe t avhp reset t ro (1) t acc2 t ahav a0 -a1 t aav t pa a (2) (2) t ce t acc2 t df t df data valid ce i/o0-i/o15 a2 -a21 avd oe t oe reset t ro (1) t acc2 a0 -a1 t pa a (2) (2) v i l
26 at49bn/bv6416(t) 2481c?flash?5/03 burst read cycle waveform notes: 1. the rdy signal (solid line) shown is for a burst configuration register setting of b10 and b8 = 0. the rdy signal (dash ed line) shown is for a burst configuration setting of b10 = 1 and b8 = 0. 2. after the high-to-low transition on avd , avd may remain low. ac burst read timing characteristics symbol parameter min max units t clk clk period 15 ns t ckh clk high time 4 ns t ckl clk low time 4 ns t ckrt clk rise time 3.5 ns t ckft clk fall time 3.5 ns t ack address valid to clock 7 ns t avck avd low to clock 7 ns t ceck ce low to clock 7 ns t ckav clock to avd high 3 ns t qhck output hold from clock 3 ns t ahck address hold from clock 8 ns t ckry clock to rdy delay 13.0 ns t ceav ce setup to avd 7ns t aav address valid to avd 7ns t ahav address hold from avd 9ns t ckqv clk to data delay 13.0 ns t ceqz ce high to output high-z 10 ns d0 d127 d1 d128 ce i/o0-i/o15 a0-a21 avd clk oe t clk t ckh t ckl ... rdy t ceav t ce t ahav t aav d129 ... d126 ... t ceck t ahck t avck t ack t ckry t ckry ... t ckav t ckqv t ceqz t qhck (1) (2)
27 at49bn/bv6416(t) 2481c?flash?5/03 burst read waveform (clock latency of 4) note: 1. solid line reflects a b10 and b8 setting of 0 in the configuration register. dashed line reflects a b10 setting of 0 and b8 set- ting of 1 in the configuration register. four-word burst read waveform (clock latency of 4) valid d0 d127 d1 d128 ce a0-a21 i/o0-i/o15 avd clk oe rdy d129 ... d126 (1) a c d e f g b ... d0 d1 d2 d3 ce a0-a21 i/o0-i/o15 avd clk oe valid a c b
28 at49bn/bv6416(t) 2481c?flash?5/03 ac word load waveforms 1 we controlled (1) note: 1. after the high-to-low transition on avd , avd may remain low as long as the clk input does not toggle. ce controlled (1) note: 1. after the high-to-low transition on avd , avd may remain low as long as the clk input does not toggle. ac word load characteristics 1 symbol parameter min max units t as address, ce setup time to avd high 10 ns t ahav address hold time from avd high 9 ns t avlp avd low pulse width 10 ns t ds data setup time 15 ns t dh data hold time 0 ns t ceav ce setup to avd 10 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns t weav we high time to avd low 25 ns t ceav ce high time to avd low 25 ns t ds t weav t dh t as t ahav t avlp t wp data va l i d ce i/o0-i/o15 a0 -a21 avd we t ds t dh t as t ahav t avlp t wp data valid ce i/o0-i/o15 a0 -a21 avd we t ceav t ceav
29 at49bn/bv6416(t) 2481c?flash?5/03 ac word load waveforms 2 we controlled (1) note: 1. the clk input should not toggle. ce controlled (1) note: 1. the clk input should not toggle. ac word load characteristics 2 symbol parameter min max units t as address setup time to we and ce low 0 ns t ah address hold time 20 ns t ds data setup time 20 ns t dh data hold time 0 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns t ds t ah t dh t wp data va l i d ce i/o0-i/o15 a0 -a21 avd we t as v il t ds t dh t wp data valid ce i/o0-i/o15 a0 -a21 avd we t as v il t ah
30 at49bn/bv6416(t) 2481c?flash?5/03 program cycle waveforms sector, plane or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for plane or sector erase, the address depends on what plane or sector is to be erased. (see note 4 and 6 under command definitions on page 14.) 3. for chip erase, the data should be xx10h, for plane erase, the data should be xx20h, and for sector erase, the data should be xx30h 4. the waveforms shown above use the we controlled ac word load waveforms 1. program cycle characteristics symbol parameter min typ max units t bp word programming time (v pp = v cc )22s t bpvpp word programming time (v pp > 11.5v) 10 s t sec1 sector erase cycle time (4k word sectors) 100 ms t sec2 sector erase cycle time (32k word sectors) 500 ms t es erase suspend time 15 s t ps program suspend time 10 s input data xxaa ce we i/o0 -i/o15 xx55 xxa0 a0 -a21 avd addr 555 aaa 555 oe (1) oe (1) xxaa xxaa ce we i/o0 -i/o15 xx55 xx80 a0 -a21 avd 555 555 aaa 555 xx55 note3 aaa note2
31 at49bn/bv6416(t) 2481c?flash?5/03 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 24. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 24. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a21 we ce oe i/o7 toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
32 at49bn/bv6416(t) 2481c?flash?5/03 software product identification entry (1) load data aa to address 555 load data 55 to address aaa load data 90 to address xxx (7) enter product identification mode (2)(3)(5) software product identification exit (1)(6) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (h ex) address format: a11 - a0 (hex); a12 - a21 (don?t care). 2. a1 - a21 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh device code: 00d6h - at49bn6416/bv6416; 00d2h - AT49BN6416T/bv6416t. 6. either one of the product id exit commands can be used. 7. for the at49bn6416/bv6416: for the AT49BN6416T/bv6416t: xxx = 0xx555 status read from plane a xxx = 3xx555 status read from plane a xxx = 1xx555 status read from plane b xxx = 2xx555 status read from plane b xxx = 2xx555 status read from plane c xxx = 1xx555 status read from plane c xxx = 3xx555 status read from plane d xxx = 0xx555 status read from plane d if a read status has been entered for a plane, any read from this plane will be a status read while any read of another plane will be a memory read, either random or burst. program or erase operations cannot be performed while one of the planes is in the read status mode.
33 at49bn/bv6416(t) 2481c?flash?5/03 table 5. common flash interface definition for at49bn/bv6416(t) address at49bn/bv6416(t) comments 10h 0051h ?q? 11h 0052h ?r? 12h 0059h ?y? 13h 0002h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1ah 0000h 1bh 0027h vcc min write/erase 1ch 0031h vcc max write/erase 1dh 00b5h vpp min voltage 1eh 00c5h vpp max voltage 1fh 0004h typ word write ? 16 s 20h 0000h 21h 0009h typ block erase ? 500 ms 22h 0010h typ chip erase, 32m bytes ? 32,300 ms, 64m bytes ? 64,300 ms 23h 0004h max word write/typ time 24h 0000h n/a 25h 0003h max block erase/typ block erase 26h 0003h max chip erase/ typ chip erase 27h 0017h device size 28h 0001h x16 device 29h 0000h x16 device 2ah 0000h multiple byte write not supported 2bh 0000h multiple byte write not supported 2ch 0002h 2 regions, x = 2 2dh 007eh 64k bytes, 32m ? y = 62, 64m ? y = 126 2eh 0000h 64k bytes, 32m ? y = 62, 64m ? y = 126 2fh 0000h 64k bytes, z = 256 30h 0001h 64k bytes, z = 256 31h 0007h 8k bytes, y = 7 32h 0000h 8k bytes, y = 7 33h 0020h 8k bytes, z = 32 34h 0000h 8k bytes, z = 32
34 at49bn/bv6416(t) 2481c?flash?5/03 vendor specific extended query 41h 0050h ?p? 42h 0052h ?r? 43h 0049h ?i? 44h 0031h major version number, ascii 45h 0030h minor version number, ascii 46h 00bfh bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 0000h at49bn/bv6416t or 0001h at49bn/bv6416 bit 0 ? top (?0?) or bottom (?1?) boot block device undefined bits are ?0? 48h 0007h bit 0 ? 4 word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8 word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? continuos burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 0003h bit 0 ? 4 word page, 0 ? no, 1 ? yes bit 1 ? 8 word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 0080h location of protection register lock byte, the section's first byte 4bh 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 0003h # of bytes in the user prog section of prot register ? 2*n table 5. common flash interface definition for at49bn/bv6416(t) (continued) address at49bn/bv6416(t) comments
35 at49bn/bv6416(t) 2481c?flash?5/03 at49bv6416(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.01 at49bv6416-70ti 48t industrial (-40 to 85 c) 85 30 0.01 at49bv6416-85ti 48t industrial (-40 to 85 c) 70 30 0.01 at49bv6416t-70ti 48t industrial (-40 to 85 c) 85 30 0.01 at49bv6416t-85ti 48t industrial (-40 to 85 c) at49bn6416(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.01 at49bn6416-70ci 55c1 industrial (-40 to 85 c) 85 30 0.01 at49bn6416-85ci 55c1 industrial (-40 to 85 c) 70 30 0.01 AT49BN6416T-70ci 55c1 industrial (-40 to 85 c) 85 30 0.01 AT49BN6416T-85ci 55c1 industrial (-40 to 85 c) package type 55c1 55-ball, plastic chip-size ball grid array package (cbga) 48t 48-lead, plastic thin small outline package (tsop)
36 at49bn/bv6416(t) 2481c?flash?5/03 packaging information ? at49bn6416(t) 55c1 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 55c1 , 55-ball (8 x 7 array), 8 x 11 x 1.0 mm body, 0.75 mm ball pitch ceramic ball grid array package (cbga) a 55c1 3/20/02 0.12 c seating plane c 1.375 mm ref d e top view side view a 87 6 5 4 3 21 ?b 3.25 mm ref bottom view a a1 d1 e1 e e b c d e f g common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.00 a1 0.23 ? ? d 7.90 8.00 8.10 d1 5.25 typ e 10.90 11.00 11.10 e1 4.50 typ e 0.75 typ ? b 0.35 typ
37 at49bn/bv6416(t) 2481c?flash?5/03 packaging information ? at49bv6416(t) 48t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48t , 48-lead (12 x 20 mm package) plastic thin small outline package, type i (tsop) b 48t 10/18/01 pin 1 0o ~ 8o d1 d pin 1 identifier b e e a a2 c l gage plane seating plane l1 a1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation dd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 11.90 12.00 12.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. 2481c?flash?5/03 xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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