features ? improved versions of the uc3823/uc3825 pwms ? compatible with voltage or current-mode topologies ? practical operation at switching frequencies to 1mhz ? 50ns propagation delay to output ? high current dual totem pole outputs (2a peak) ? trimmed oscillator discharge current ? low 100 m a startup current ? pulse-by-pulse current limiting comparator ? latched overcurrent comparator with full cycle restart uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b high speed pwm controller description the uc3823a & b and the uc3825a & b family of pwm control ics are im- proved versions of the standard uc3823 & uc3825 family. performance en- hancements have been made to several of the circuit blocks. error amplifier gain bandwidth product is 12mhz while input offset voltage is 2mv. current limit threshold is guaranteed to a tolerance of 5%. oscillator discharge current is spec- ified at 10ma for accurate dead time control. frequency accuracy is improved to 6%. startup supply current, typically 100 m a, is ideal for off-line applications. the output drivers are redesigned to actively sink current during uvlo at no expense to the startup current specification. in addition each output is capable of 2a peak currents during transitions. functional improvements have also been implemented in this family. the uc3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2v. the overcurrent comparator sets a latch that ensures full discharge of the soft start capacitor before allowing a restart. while the fault latch is set, the outputs are in the low state. in the event of continuous faults, the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. the uc3825 clock pin has be- come clk/leb. this pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. * note: 1823a,b version toggles q and q are always low 9/95 block diagram continued udg-95101
2 the uc3825a,b has dual alternating outputs and the same pin configuration of the uc3825. the uc3823a,b outputs op- erate in phase with duty cycles from zero to less than 100%. the pin configuration of the uc3823a,b is the same as the uc3823 except pin 11 is now an output pin instead of the ref- erence pin to the current limit comparator. a version parts have uvlo thresholds identical to the original uc3823/25. the b versions have uvlo thresholds of 16 and 10v, in- tended for ease of use in off-line applications. consult application note u-128 for detailed technical and ap- plications information. contact the factory for further pack- aging and availability information. uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b connection diagrams supply voltage (vc, vcc) ....................................................22v output current, source or sink (pins outa, outb) dc ..................................................................................0.5a pulse (0.5 m s) ...................................................................2.2a power ground (pgnd) ...................................................... 0.2v analog inputs (inv, ni, ramp)................................................... - 0.3v to 7v (ilim, ss)............................................................. - 0.3v to 6v clock output current (clk/leb) ....................................... - 5ma error amplifier output current (eaout)..............................5ma soft start sink current (ss) ...............................................20ma oscillator charging current (rt)........................................ - 5ma power dissipation at t a = 60 c..............................................1w storage temperature range............................ - 65 c to + 150 c junction temperature....................................... - 55 c to + 150 c lead temperature (soldering, 10 sec.).............................300 c all currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. dil-16, soic-16, (top view) j or n package; dw package plcc-20, lcc-20, (top view) q, l packages device uvlo d max uc3823a 9.2v/8.4v < 100% uc3823b 16v/10v < 100% uc3825a 9.2v/8.4v < 50% uc3825b 16v/10v < 50% description (cont.) absolute maximum ratings electrical characteristics unless otherwise stated, these specifications apply for t a = - 55 c to + 125 c for the uc1823a,b and uc1825a,b; - 40 c to + 85 c for the uc2823a,b and uc2825a,b; 0 c to + 70 c for the uc3823a,b and uc3825a,b; rt = 3.65k, ct = 1nf, vcc = 12v, t a = t j . parameter test conditions min typ max units reference section output voltage t j = 25 c, io = 1ma 5.05 5.1 5.15 v line regulation 12 < vcc < 20v 2 15 mv load regulation 1ma < io < 10ma 5 20 mv total output variation line, load, temp 5.03 5.17 v temperature stability t min < t a < t max (note 1) 0.2 0.4 mv/ c output noise voltage 10hz < f < 10khz (note 1) 50 m vrms long term stability t j = 125 c, 1000 hours (note 1) 5 25 mv short circuit current vref = 0v 30 60 90 ma
3 parameter test conditions min typ max units oscillator section initial accuracy t j = 25 c (note 1) 375 400 425 khz total variation line, temperature (note 1) 350 450 khz voltage stability 12v < vcc < 20v 1 % temperature stability t min < t a < t max (note 1) 5 % initial accuracy rt = 6.6k, ct = 220pf t a = 25 c (note 1) 0.9 1 1.1 mhz total variation rt = 6.6k, ct = 220pf (note 1) 0.85 1.15 mhz clock out high 3.7 4 v clock out low 0 0.2 v ramp peak 2.6 2.8 3 v ramp valley 0.7 1 1.25 v ramp valley to peak 1.6 1.8 2 v oscillator discharge current rt = open, v ct = 2v 9 10 11 ma error amplifier section input offset voltage 210mv input bias current 0.6 3 m a input offset current 0.1 1 m a open loop gain 1v < vo < 4v 60 95 db cmrr 1.5v < v cm < 5.5v 75 95 db psrr 12v < vcc < 20v 85 110 db output sink current v eaout = 1v 1 2.5 ma output source current v eaout = 4v - 0.5 - 1.3 ma output high voltage i eaout =- 0.5ma 4.5 4.7 5 v output low voltage i eaout = 1ma 0 0.5 1 v gain bandwidth product f = 200khz 6 12 mhz slew rate (note 1) 6 9 v/ m s pwm comparator ramp bias current v ramp = 0v - 1 - 8 m a minimum duty cycle 0% maximum duty cycle 85 % leading edge blanking r = 2k, c = 470pf 300 375 450 ns leb resistor v clk / leb = 3v 8.5 10 11.5 kohm eaout zero d.c. threshold v ramp = 0v 1.1 1.25 1.4 v delay to output v eaout = 2.1v, v ramp = 0 to 2v step (note 1) 50 80 ns current limit/start sequence/fault section soft start charge current v ss = 2.5v 8 14 20 m a full soft start threshold 4.3 5 v restart discharge current v ss = 2.5v 100 250 350 m a restart threshold 0.3 0.5 v ilim bias current 0 < v ilim < 2v 15 m a current limit threshold 0.95 1 1.05 v uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b electrical characteristics (cont.) unless otherwise stated, these specifications apply for t a = - 55 c to + 125 c for the uc1823a,b and uc1825a,b; - 40 c to + 85 c for the uc2823a,b and uc2825a,b; 0 c to + 70 c for the uc3823a,b and uc3825a,b; rt = 3.65k, ct = 1nf, vcc = 12v, t a = t j .
4 parameter test conditions min typ max units current limit/start sequence/fault section (cont.) over current threshold 1.14 1.2 1.26 v ilim delay to output v ilim = 0 to 2v step (note 1) 50 80 ns output section output low saturation i out = 20ma 0.25 0.4 v i out = 200ma 1.2 2.2 v output high saturation i out = 20ma 1.9 2.9 v i out = 200ma 2 3 v uvlo output low saturation i o = 20ma 0.8 1.2 v rise/fall time c l = 1nf (note 1) 20 45 ns undervoltage lockout start threshold ucx823b and x825b only 16 17 v stop threshold ucx823b and x825b only 9 10 v uvlo hysteresis ucx823b and x825b only 5 6 7 v start threshold ucx823a and x825a only 8.4 9.2 9.6 v uvlo hysteresis ucx823a and x825a only 0.4 0.8 1.2 v supply current startup current vc = vcc = v th (start) - 0.5v 100 300 m a icc 28 36 ma uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b note 1: guaranteed by design. not 100% tested in production. electrical characteristics (cont.) unless otherwise stated, these specifications apply for t a = - 55 c to + 125 c for the uc1823a,b and uc1825a,b; - 40 c to + 85 c for the uc2823a,b and uc2825a,b; 0 c to + 70 c for the uc3823a,b and uc3825a,b; rt = 3.65k, ct = 1nf, vcc = 12v, t a = t j . oscillator the uc3823a,b/3825a,b oscillator is a saw tooth. the rising edge is governed by a current controlled by the rt pin and value of capacitance at the ct pin. the falling edge of the sawtooth sets dead time for the outputs. se- lection of rt should be done first, based on desired max- imum duty cycle. ct can then be chosen based on de- sired frequency, rt, and d max . the design equations are: rt = ct = recommended values for rt range from 1k to 100k. control of d max less than 70% is not recommended. (1.6 ? d max ) (rt ? f) 3v (10ma) (1 - d max ) applications information oscillator udg-95102
5 uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b applications information (cont.) maximum duty cycle vs r t curve oscillator frequency vs. r t and c t curve oscillator (cont.) leading edge blanking the uc3823a,b/3825a,b performs fixed frequency pulse width modulation control. the uc3823a,b outputs oper- ate together at the switching frequency and can vary from 0 to some value less than 100%. the uc3825a,b outputs are alternately controlled. during every other cycle, one output will be off. each output then, switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%. to limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. on the falling edge of the clock, the appropriate output(s) is driven high. the end of the pulse is controlled by the pwm comparator, current limit comparator, or the overcurrent comparator. normally the pwm comparator will sense a ramp cross- ing a control voltage (error amp output) and terminate the pulse. leading edge blanking (leb) causes the pwm comparator to be ignored for a fixed amount of time after the start of the pulse. this allows noise inherent with switched mode power conversion to be rejected. the pwm ramp input may not require any filtering as result of leading edge blanking. to program a leading edge blanking period, connect a capacitor, c, to clk/leb. the discharge time set by c and the internal 10k resistor will determine the blanked inter- val. the 10k resistor has a 10% tolerance. for more ac- curacy, an external 2k 1% resistor, r, can be added, re- sulting in an equivalent resistance of 1.66k with a tolerance of 2.4%. the design equation is: t leb = 0.5 ? (r | | 10k) ? c. values of r less than 2k should not be used leading edge blanking is also applied to the current limit comparator. after leb, if the ilim pin exceeds the one volt threshold, the pulse is terminated. the over current comparator, however, is not blanked. it will catch catas- trophic over current faults without a blanking delay. any time the ilim pin exceeds 1.2v, the fault latch will be set and the outputs driven low. for this reason, some noise filtering may be required on the ilim pin. leb operational waveforms udg-95103 udg-95104 udg-95105
6 uvlo, soft start and fault management soft start is programmed by a capacitor on the ss pin. at power up, ss is discharged. when ss is low, the error amp output is also forced low. as the internal 9 m a source charges the ss pin, the error amp output follows until closed loop regulation takes over. anytime ilim exceeds 1.2v, the fault latch will be set and the output pins will be driven low. the soft start cap is then discharged by a 250 m a current sink. no more output pulses are allowed until soft start is fully discharged, and ilim is below 1.2v. at this point the fault latch will be re- set and the chip will execute a soft start. should the fault latch be set during soft start, the outputs will be immediately terminated, but the soft start cap will not be discharged until it has been fully charged. this re- sults in a controlled hiccup interval for continuous fault con- ditions. uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b applications information (cont.) soft start and fault waveforms udg-95106 active low outputs during uvlo the uvlo function forces the outputs to be low and con- siders both vcc and vref before allowing the chip to operate. output v and i during uvlo simplified schematic pwm applications current mode voltage mode udg-95107 udg-95108 udg-95109 udg-95110
7 uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b synchronization the oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. program the free running frequency of the oscillator to be 10 to 15% slower than the desired synchronous frequency. the pulse width should be greater than 10ns and less than half the discharge time of the oscillator. the rising edge of the clk/leb pin can be used to generate a synchro- nizing pulse for other chips. note that, the clk/leb pin will no longer accept an incoming synchronizing signal. general oscillator synchronization operational waveforms two units applications information (cont.) high current outputs each totem pole output of the uc3823a,b and uc3825a,b can deliver a 2 amp peak current into a ca- pacitive load. the output can slew a 1000pf capacitor 15 volts in approximately 20 nanoseconds. separate col- lector supply (vc) and power ground (pgnd) pins help decouple the ic's analog circuitry from the high power gate drive noise. the use of 3 amp schottky diodes (1n5120, usd245 or equivalent) as shown in the figure from each output to both vc and pgnd are recom- mended. the diodes clamp the output swing to the sup- ply rails, necessary with any type of inductive/capacitive load, typical of a mosfet gate. schottky diodes must be used because a low forward voltage drop is required. do not use standard silicon diodes. although a "single ended" device, two output drivers are available on the uc3823a,b devices. these can be par- alleled by the use of a one-half ohm (noninductive) re- sistor connected in series with each output for a com- bined peak current of 4 amps. power mosfet drive circuit udg-95111 udg-95113 udg-95112 udg-95114
8 ground planes each output driver of these devices is capable of 2a peak currents. careful layout is essential for correct operation of the chip. a ground plane must be employed. a unique sec- tion of the ground plane must be designated for high di/dt currents associated with the output stages. this point is the power ground to which the pgnd pin is connected. power ground can be separated from the rest of the ground plane and connected at a single point, although this is not strictly necessary if the high di/dt paths are well understood and accounted for. vcc should be bypassed directly to power ground with a good high frequency capacitor. the sources uc1823a,b/1825a,b uc2823a,b/2825a,b uc3823a,b/3825a,b of the power mosfet should connect to power ground as should the return connection for input power to the sys- tem and the bulk input capacitor. the output should be clamped with a high current schottky diode to both vcc and pgnd. nothing else should be connected to power ground. vref should be bypassed directly to the signal portion of the ground plane with a good high frequency capaci- tor. low esr/esl ceramic 1 m f capacitors are recom- mended for both vcc and vref. all analog circuitry should likewise be bypassed to the signal ground plane. applications information (cont.) udg-95115 unitrode integrated circuits 7 continental blvd. merrimack, nh 03054 tel.(603) 424-2410 fax (603) 424-3460 grounding and bypass procedures should be followed. the use of a ground plane is highly recommended. open loop test circuit this test fixture is useful for exercising many of the uc3823a,b, uc3825a,b functions and measuring their specifications. as with any wideband circuit, careful udg-95116
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
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