1k x 8 registered prom cy7c235a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-04002 rev. ** revised march 4, 2002 35a features ? cmos for optimum speed/power high speed ? 18 ns address set-up ? 12 ns clock to output low power ? 495 mw (commercial) ? 660 mw (military) synchronous and asynchronous output enables on-chip edge-triggered registers programmable asynchronous registers (init ) eprom technology, 100% programmable slim, 300-mil, 24-pin plastic or hermetic dip or 28-pin lcc and plcc 5v 10% v cc , commercial and military ttl-compatible i/o direct replacement for bipolar proms capable of withstanding greater than 2001v static dis- charge functional description the cy7c235a is a high-performance 1024 word by 8 bit elec- trically programmable read only memory packaged in a slim 300-mil plastic or hermetic dip, 28-pin leadless chip carrier, or 28-pin plastic leaded chip carrier. the memory cells utilize proven eprom floating gate technology and byte-wide intelli- gent programming algorithms. the cy7c235a replaces bipolar devices pin for pin and offers the advantages of lower power, superior performance, and high programming yield. the eprom cell requires only 12.5v for the supervoltage, and low current requirements allow for gang programming. the eprom cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. each prom is also tested for ac performance to guarantee that the product will meet ac specification limits after customer pro- gramming. maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd v cc a 8 a 9 e init cp o 7 o 6 o 4 o 5 o 3 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 programmable array mul tiplexer column address row address 15 8-bit edge- register triggered o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 cp cp e s e e s 28 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 11 12 19 a 5 v cc gnd a 6 a 7 o 3 o 1 o 0 18 o 4 o 5 nc a 0 a 4 a 3 e nc nc nc init e s o 7 o 6 a 2 a 1 cp o 2 a 8 a 9 init initialize word programmable a 9 dip lcc/plcc to p v i e w to p v i e w address decoder logic block diagram pin configuration selection guide 7c235a-18 7c235a-25 7c235a-30 7c235a-40 minimum address set-up time (ns) 18 25 30 40 maximum clock to output (ns) 12 12 15 20 maximum operating current (ma) commercial 90 90 90 90 military 120 120 120
cy7c235a document #: 38-04002 rev. ** page 2 of 10 storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential (pin 24 to pin 12 for dip) .................................. ? 0.5v to +7.0v dc voltage applied to outputs in high z state .................................................... ? 0.5v to +7.0v dc input voltage .................................................? 3.0v to +7.0v dc program voltage (pins 7, 18, 20 for dip) ...............13.0v static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [1] ? 40 c to +85 c 5v 10% military [2] ? 55 c to +125 c 5v 10% electrical characteristics over operating range [3] parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma v in = v ih or v il 2.4 v v ol output low voltage v cc = min., i ol = 16 ma v in = v ih or v il 0.4 v v ih input high level guaranteed input logical high voltage for all inputs [4] 2.0 v v il input low level guaranteed input logical low voltage for all inputs [4] 0.8 v i ix input leakage current gnd < v in < v cc ? 10 +10 a v cd input clamp diode voltage note 5 i oz output leakage current gnd < v out < v cc output disabled [4] ? 10 +10 a i os output short circuit current v cc = max., v out = 0.0v [6] ? 20 ? 90 ma i cc power supply current i out = 0 ma, v cc = max. commercial 90 ma military 120 v pp programming supply voltage 12 13 v i pp programming supply current 50 ma v ihp input high programming voltage 3.0 v v ilp input low programming voltage 0.4 v capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc =5.0v 10 pf c out output capacitance 10 pf notes: 1. contact a cypress representative for industrial temperature range specifications. 2. t a is the ? instant on ? case temperature. 3. see the last page of this specification for group a subgroup testing information. 4. for devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measuremen t. 5. see introduction to cmos proms in this data book for general information on testing. 6. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds.
cy7c235a document #: 38-04002 rev. ** page 3 of 10 a operating modes the cy7c235a incorporates a d-type, master-slave register on chip, reducing the cost and size of pipelined micropro- grammed systems and applications where accessed prom data is stored temporarily in a register. additional flexibility is provided with synchronous (e s ) and asynchronous (e ) output enables and asynchronous initialization (init ). upon power-up, the synchronous enable (e s) flip-flop will be in the set condition causing the outputs (o 0 ? o 7 ) to be in the off or high-impedance state. data is read by applying the memory location to the address input (a 0 ? a 9 ) and a logic low to the enable (e s ) input. the stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. at the next low-to-high transition of the clock (cp), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (o 0 ? o 7 ), provided the asynchronous enable (e ) is also low. the outputs may be disabled at any time by switching the asynchronous enable (e ) to a logic high, and may be re- turned to the active state by switching the enable to a logic low. regardless of the condition of e , the outputs will go to the off or high-impedance state upon the next positive clock edge af- ter the synchronous enable (e s ) input is switched to a high level. if the synchronous enable pin is switched to a logic low, the subsequent positive clock edge will return the output to the active state if e is low. following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next low-to-high transition of the clock. this unique feature al- lows the cy7c235a decoders and sense amplifiers to access the next location while previously addressed data remains sta- ble on the outputs. system timing is simplified in that the on-chip edge-triggered register allows the prom clock to be derived directly from the system clock without introducing race conditions. the on-chip register timing requirements are similar to those of discrete registers available in the market. the cy7c235a has an asynchronous initialize input (init ). the initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophis- ticated functions such as a built-in ? jump start ? address. when activated the initialize control input causes the contents of a user programmed 1025th 8-bit word to be loaded into the on-chip register. each bit is programmable and the initialize function can be used to load any desired combination of 1s and 0s into the register. in the unprogrammed state, activating init will generate a register clear (all outputs low). if all the bits of the initialize word are programmed, activating init performs a register preset (all outputs high). applying a low to the init input causes an immediate load of the programmed initialize word into the master and slave flip-flops of the register, independent of all other inputs, includ- ing the clock (cp). the initialize data will appear at the device outputs after the outputs are enabled by bringing the asyn- chronous enable (e ) low. when power is applied the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impedance state. in order to enable the outputs, a clock must occur and the e s input pin must be low at least a set-up time prior to the clock low-to-high transition. the e input may then be used to enable the outputs. when the asynchronous initialize input, init , is low, the data in the initialize byte will be asynchronously loaded into the out- put register. it will not, however, appear on the output pins until they are enabled, as described in the preceding paragraph. ac test loads and waveforms [5] 3.0v 5v output r1 250 ? r2 167 ? 50 pf including jig and scope gnd 90% 10% 90% 10% 5ns 5 ns 5v output 5pf including jig and scope (b) high -z load output 2.0v equivalent to: th venin equivalent 100 ? r1 250 ? (a) normalload r2 167 ? all input pulses
cy7c235a document #: 38-04002 rev. ** page 4 of 10 switching waveforms [5] programming information programming support is available from cypress as well as from a number of third-party software vendors. for detailed programming information, including a listing of software pack- ages, please see the prom programming information located at the end of this section. programming algorithms can be ob- tained from any cypress representative. switching characteristics over operating range [3, 5] 7c235a-18 7c235a-25 7c235a-30 7c235a-40 parameter description min. max. min. max. min. max. min. max. unit t sa address set-up to clock high 18 25 30 40 ns t ha address hold from clock high 0 0 0 0 ns t co clock high to valid output 12 12 15 20 ns t pwc clock pulse width 12 12 15 20 ns t ses e s set-up to clock high 10 10 10 15 ns t hes e s hold from clock high 5 5 5 5 ns t di delay from init to valid output 20 25 25 35 ns t ri init recovery to clock high 15 20 20 20 ns t pwi init pulse width 15 20 20 25 ns t cos inactive to valid output from clock high [7] 15 20 20 25 ns t hzc inactive output from clock high [7] 15 20 20 25 ns t doe valid output from e low 15 20 20 25 ns t hze inactive output from e high 15 20 20 25 ns note: 7. applies only when the synchronous (e s ) function is used. t di t co t doe t hze t hzc t sa t ha t hes t ses c235a-7 t pwc t pwc t pwc t pwc t pwc t pwc t ha t co t cos o 0 ? o 7 a 0 ? a 10 init cp e s e t ri t pwi t hes t ses t hes t ses
cy7c235a document #: 38-04002 rev. ** page 5 of 10 table 1. mode selection pin function [8] read or output disable a 0 , a 3 ? a 9 a 1 a 2 cp e s e init o 7 ? o 0 mode other a 0 , a 3 ? a 9 a 1 a 2 pgm vfy e v pp d 7 ? d 0 read a 0 , a 3 ? a 9 a 1 a 2 x v il v il v ih o 7 ? o 0 output disable a 0 , a 3 ? a 9 a 1 a 2 x v ih x v ih high z output disable a 0 , a 3 ? a 9 a 1 a 2 x x v ih v ih high z initialize a 0 , a 3 ? a 9 a 1 a 2 x x v il v il init byte program a 0 , a 3 ? a 9 a 1 a 2 v ilp v ihp v ihp v pp d 7 ? d 0 program verify a 0 , a 3 ? a 9 a 1 a 2 v ihp v ilp v ihp v pp o 7 ? o 0 program inhibit a 0 , a 3 ? a 9 a 1 a 2 v ihp v ihp v ihp v pp high z intelligent program a 0 , a 3 ? a 9 a 1 a 2 v ilp v ihp v ihp v pp d 7 ? d 0 program initialize byte a 0 , a 3 ? a 9 v pp v ilp v ilp v ihp v ihp v pp d 7 ? d 0 blank check a 0 , a 3 ? a 9 a 1 a 2 v ihp v ilp v ihp v pp zeros note: 8. x = ? don ? t care ? but not to exceed v cc 5%. figure 1. programming pinouts. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 0 d 1 d 2 gnd v cc d 7 d 6 d 4 d 5 d 3 15 a 9 e v pp vfy pgm 28 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 11 12 19 a 5 v cc gnd a 6 a 7 d 3 d 1 d 0 18 d 4 d 5 nc a 0 a 4 a 3 a 8 nc nc d 7 d 6 a 2 a 1 d 2 e v pp vfy pgm nc a 9 dip lcc/plcc top view top view
cy7c235a document #: 38-04002 rev. ** page 6 of 10 typical dc and ac characteristics 1.4 1.6 1.0 0.8 4.0 4.5 5.0 5.5 6.0 ? 55 25 125 1.2 1.1 1.6 4.0 4.5 5.0 5.5 6.0 normalized clock-to-output time supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature ( c) supply voltage (v) clock to output time vs. v cc 0.6 1.2 1.6 1.4 1.2 1.0 0.8 ? 55 125 normalized set -up time ambient temperature ( c) clock to output time vs. temperature 150 175 125 75 50 25 0.0 1.0 2.0 3.0 output sink current (ma) 0 100 output voltage (v) output sink current vs. output voltage 1.0 0.9 0.8 normalized i cc normalized i cc v cc =5.0v t a =25 c t a =25 c 0.6 0.6 1.02 1.00 0.98 0.96 0.94 0.92 025 5075 clock period (ns) 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 100 0.0 1000 t a =25 c v cc =4.5v t a =25 c f= f max 25 0.88 normalized supply current vs. clock period 4.0 1.4 1.2 1.0 0.8 1.6 1.4 1.2 1.0 0.8 ? 55 125 normalized set-up 0.6 25 ambient temperature ( c) normalized set-up time vs. temperature 1.2 4.0 4.5 5.0 5.5 6.0 normalized clock-to-output time 0.4 supply voltage (v) normalized set-up time vs. supply voltage t a =25 c 1.0 0.8 0.6 c235a-10 normalized i cc 0.90 v cc =5.5v t a =25 c
cy7c235a document #: 38-04002 rev. ** page 7 of 10 military specifications group a subgroup testing ordering information [9] speed (ns) package name operating range t sa t co ordering code package type 18 12 CY7C235A-18DC d14 24-lead (300-mil) cerdip commercial cy7c235a-18jc j64 28-lead plastic leaded chip carrier cy7c235a-18pc p13 24-lead (300-mil) molded dip 25 12 cy7c235a-25dc d14 24-lead (300-mil) cerdip commercial cy7c235a-25jc j64 28-lead plastic leaded chip carrier cy7c235a-25pc p13 24-lead (300-mil) molded dip cy7c235a-25dmb d14 24-lead (300-mil) cerdip military cy7c235a-25lmb l64 28-square leadless chip carrier 30 15 cy7c235a-30dc d14 24-lead (300-mil) cerdip commercial cy7c235a-30jc j64 28-lead plastic leaded chip carrier cy7c235a-30pc p13 24-lead (300-mil) molded dip cy7c235a-30dmb d14 24-lead (300-mil) cerdip military cy7c235a-30lmb l64 28-square leadless chip carrier 40 20 cy7c235a-40dc d14 24-lead (300-mil) cerdip commercial cy7c235a-40jc j64 28-lead plastic leaded chip carrier cy7c235a-40pc p13 24-lead (300-mil) molded dip cy7c235a-40dmb d14 24-lead (300-mil) cerdip military cy7c235a-40lmb l64 28-square leadless chip carrier note: 9. most of the above products are available in industrial temperature range. contact a cypress representative for specifications and product availability. dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t sa 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t co 7, 8, 9, 10, 11
cy7c235a document #: 38-04002 rev. ** page 8 of 10 package diagrams 24-lead (300-mil) cerdip d14 mil-std-1835 d- 9 config.a 51-80031 28-lead plastic leaded chip carrier j64 51-85001-a
cy7c235a document #: 38-04002 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-square leadless chip carrier l64 mil-std-1835 c-4 51-80051 51-85013-a 24-lead (300-mil) molded dip p13/p13a
cy7c235a document #: 38-04002 rev. ** page 10 of 10 document title: cy7c235a 1k x 8 registered prom document number: 38-04002 rev. ecn no. issue date orig. of change description of change ** 113857 03/06/02 dsg change from spec number: 38-00229 to 38-04002
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