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june 1996 ? topswitch tips, techniques, and troubleshooting guide application note AN-14 dn-7: power factor correction using topswitch dn-8: simple bias supplies using the top200 dn-11: a low-cost, low part count topswitch supply dn-12: non-isolated flyback supplies using topswitch dn-14: constant current/constant power regulation circuits for topswitch dn-15: topswitch power supply for echelon plt-21 power line transceiver dn-16: dc to dc converters using topswitch for telecom and cablecom applications evaluation board is strongly recommended and will dramatically reduce design, breadboarding, and debugging time . for information on specific subjects including pc design, drain voltage clamping, and recommended transformer inductance, find the appropriate section in the table of contents on the next page. for problems encountered in working power supplies, refer directly to the troubleshooting guide. for technical questions not covered by any topswitch literature, fill out a copy of the topfax form given at the end of this application note and fax to power integrations, inc. answers to all common topswitch technical questions can be found in this application note, the topswitch data sheets, the topswitch design notes, and the topswitch reference design/evaluation board documentation. the fastest path to topswitch success is to read the topswitch data sheets, an-16 and this document carefully and completely before beginning the design . detailed information on specific application circuits can be found in the application notes, design notes and reference design/evaluation board documentation listed below. purchasing a reference design/ other design/application notes an-15: topswitch power supply design techniques for emi and safety an-16: topswitch flyback design methodology an-17: flyback transformer design for topswitch power supplies an-18: topswitch flyback transformer construction guide an-19: topswitch flyback power supply efficiency an-20: transient suppression techniques for topswitch power supplies reference design/evaluation board documentation st200: top200 reference design board 95 to 370 volt dc input; 5v, 5w output (replaced by rd1) st202a: top202 reference design board universal ac input; 7.5v, 15w output st204a: top204 reference design board universal ac input; 15v, 30w output rd-1: top210 reference design board 104 to 370 vdc input, 4w output rd-2: top210 reference design board 85 to 132 vac or 170 to 265 vac input; 8w output
AN-14 2 b 6/96 table of contents 1. troubleshooting guide.................................................................................................................................................................. 3 2. example power supply circuits 2.1 dc input, 5v, 5w, bias winding control using the top200............................................................................................... 7 2.2 universal input, 7.5v, 15w, optocoupler/zener control using the top202....................................................................... 8 2.3 universal input, 15v, 30w, optocoupler/tl431 control using the top204....................................................................... 9 3. drain clamping............................................................................................................................................................................ 10 4. pc layout 4.1 single point grounding......................................................................................................................................................... 11 4.2 ideal component placement................................................................................................................................................. 11 4.3 pc layout checklist..............................................................................................................................................................12 5. flyback power supply transformer 5.1 power and inductance ranges...................................................................................................................................................13 5.2 transformer turns ratio curves.......................................................................................................................................... 14 6. optimizing power supply efficiency.......................................................................................................................................... 15 7. thermal design............................................................................................................................................................................ 15 8. auto-restart................................................................................................................................................................................. 16 9. output overvoltage protection.................................................................................................................................................... 16 10. current to duty cycle conversion............................................................................................................................................ 17 11. minimum duty cycle operation............................................................................................................................................... 17 12. control loop 12.1 basic techniques................................................................................................................................................................ 17 12.2 enhanced bandwidth.......................................................................................................................................................... 18 13. emi 13.1 topswitch advantages....................................................................................................................................................... 19 13.2 emi filter topology........................................................................................................................................................... 19 14. soft start 14.1 optocoupler feedback......................................................................................................................................................... 20 14.2 bias winding feedback...................................................................................................................................................... 21 15. bench testing............................................................................................................................................................................ 21 16. optocoupler recommendations..................................................................................................................................................22 17. input undervoltage lockout circuitry 17.1 optocoupler feedback control........................................................................................................................................... 23 17.2 bias winding feedback control......................................................................................................................................... 24 18. doubler input for increased output power................................................................................................................................ 24 19. power factor correction (pfc)................................................................................................................................................. 25 topswitch topfax form ............................................................................................................................................................ 27
b 6/96 AN-14 3 general cause symptom what to do power supply does not start topswitch blows up at turn on or overload low efficiency switching currents trigger shutdown latch transformer primary zener clamp voltage too low secondary winding connected backwards failed output rectifier or clamp circuit high optocoupler current during start up triggers shutdown latch r3 exceeds 15 w (figure 3) insufficient clamping or high leakage inductance causes excessive drain-source voltage transformer primary clamp zener voltage too low causing high loss in clamp zener clamp circuit blocking diode is too slow or has low breakdown voltage rating output rectifier recovery too slow output rectifier breakdown voltage too low transformer primary inductance too low causing high rms currents topswitch current or power rating too low ? use kelvin (single point ground) connection for all capacitors connected to source pin (section 4.1) ? minimize length of source pin ? improve pc layout (section 4.2, 4.3) ? electrically isolate heat sink from circuit ? increase clamp zener voltage rating to 1.5 times reflected output voltage v or ? reverse connection on winding to match schematic dot polarity ? replace output rectifier, clamp zener, or clamp diode ? increase value of optical coupler led series resistor ? use optical coupler with ctr between 50% and 200% ? add resistor (270 w to 620 w ) in series with optocoupler emitter ? add 0.1 m f bypass capacitor across control and source pin (section 12.1) ? use zener diode/blocking diode clamp circuit across transformer primary (section 3) ? make sure zener voltage clamps drain voltage below breakdown (section 3) ? reduce transformer leakage inductance or v or ? increase clamp zener voltage rating to 1.5 times reflected output voltage v or ? use ultra fast recovery rectifier with at least 400 volt breakdown for top100 series and 600 volt breakdown for top200 series (section 3) ? use ultra fast recovery output rectifier ? increase breakdown voltage of output rectifier ? increase the transformer primary inductance ? increase the transformer turns ratio and primary inductance for higher duty cycle and lower peak current ? use higher power topswitch ? add or increase topswitch heatsink 1. troubleshooting guide
AN-14 4 b 6/96 general cause symptom what to do ? use zener clamp circuit across transformer primary (section 3) ? remove or reduce rc damping on primary or secondaries ? use ultra fast recovery output rectifiers ? add heat sink to output rectifier ? rewind transformer primary adding additional insulation between layers of primary winding to reduce capacitance (see an-18) ? reduce number of turns on primary ? increase clamp zener voltage rating to 1.5 times reflected output voltage v or ? reduce zener diode lead length ? increase pc trace width ? use ultra fast recovery output rectifiers ? use higher power rating zener ? place a 0.01 m f, 200v capacitor in parallel with zener diode ? rewind transformer for lower leakage inductance ? use ultra fast recovery rectifier with at least 400 volt breakdown for top100 series and 600 volt breakdown for top200 series (section 3) ? use ultra fast recovery output rectifier ? increase the transformer primary inductance ? increase the transformer turns ratio and primary inductance for higher duty cycle and lower peak current ? add or increase size of heat sink ? use topswitch with higher current or output power rating ? increase primary bias voltage (up to 30 volts) ? add minimum load resistor (section 11) turn-on drain current spike duration exceeds leading edge blanking due to: ? excessive clamp circuit capacitance ? excessive rc damper capacitance ? slow recovery rectifiers on output windings ? excessive transformer primary capacitance reflected output voltage exceeds zener diode voltage rating poor heat transfer slow recovery rectifiers on output windings clamp dissipation exceeds zener diode power rating high switching loss due to slow recovery clamp diode. high switching loss due to slow recovery output rectifier transformer primary inductance too low, causing high rms currents poor heat transfer current or power rating too low minimum duty cycle delivers more energy than light load can consume topswitch appears to operate at 50 khz (or lower subharmonic of 100 khz switching frequency) drain clamp zener diode is too hot topswitch too hot power supply output voltage increases at high input voltage and light load
b 6/96 AN-14 5 power supplies regulated with optical coupled feedback cause symptom what to do insufficient gain/phase margin due to: ? output has ( p -filter) filter adding additional phase shift to control loop. ? improper compensation ? optocoupler current transfer ratio (ctr) too high control loop is too slow control loop bandwidth too low input capacitor too small power supply oscillates output voltage turns on too fast or overshoots output voltage line frequency ripple too large ? connect optical coupler to the rectifier side of p section (section 12.1) ? increase resistor in series with optocoupler led (section 12.1) ? increase size of auto-restart/compensation capacitor across control and source pins ? increase or add resistor in series with auto-restart/ compensation capacitor (section 12.1) ? use optical coupler with ctr between 50% and 200% (section 16) ? increase control loop bandwidth ? add soft start capacitor (between 4.7 m f and 47 m f) across error amplifier output or zener diode (section 14) ? increase control loop bandwidth ? increase input capacitor power supplies regulated with bias winding feedback cause symptom what to do insufficient gain/phase margins control loop is too slow leakage inductance spike on bias winding discontinuous mode operation power supply oscillates output voltage turns on too fast or overshoots poor load regulation ? increase output capacitance ? increase size of auto-restart/compensation capacitor ? add or increase resistor r3 in series with auto-restart/ compensation capacitor (section 12.1) ? increase control loop bandwidth ? add rc soft start network (section 14) ? add resistor in series with bias winding to filter leakage inductance spike (see dn-8) ? change transformer winding order so that primary is first and bias winding is last ? on bias winding, use parallel, oversized diameter wire so bias winding completely covers width of bobbin ? redesign transformer for continuous mode operation
AN-14 6 b 6/96 power factor correction circuits cause symptom what to do drain voltage rings below source potential precompensation resistor value is not correct precompensation current waveform is being filtered output voltage ripple modulates duty cycle inductor value is too large and enters continuous mode at peak of rectified ac input voltage inductor value is too small and topswitch current limit reduces duty cycle precompensation resistor current disables auto-restart pfc stage does not start total harmonic distortion (thd) is greater than 10% pfc stage turns off with short interruption in ac power ? add fast recovery blocking diode in series with drain (section 19.1) ? adjust precompensation resistor until optimum thd has been obtained (see dn-7) ? reduce bypass capacitance on control pin to less than 4.7 m f ? add resistor (75 to 200 w ) between control pin bypass capacitor and auto-restart/compensation capacitor (r2 in figure 19) ? increase auto-restart/compensation capacitor to reject output voltage ripple ? decrease inductor value (see dn-7) ? increase inductor value (see dn-7) ? use topswitch with higher current limit ? add 2.7 k w to 6.8 k w resistor across c3 (figure 19) to shunt precompensation current from control pin (see dn-7)
b 6/96 AN-14 7 2. example power supply circuits the following three isolated power supplies will be used as examples in the text that follows. the st200 (figure 1) is a simple, absolute minimum part count 5v, 5w isolated bias supply using the top200 that operates from a high voltage dc bus. the st202a (figure 2) is a universal ac input, 7.5v, 15 watt power supply using the top202 and demonstrates low cost, optically coupled feedback control. the st204a (figure 3) is a universal ac input, 15v, 30 watt power supply using the top204 and features improved output voltage accuracy and regulation with optically coupled feedback control. 2.1 st200 general circuit description the st200 is a low-cost, dc input, isolated buck-boost or flyback switching power supply using the top200 integrated circuit. the circuit shown in figure 1 produces a 5 v, 5 w power supply that operates from 95 to 370 vdc input voltage. the 5 v output is indirectly sensed by the primary bias winding. the output voltage is determined by the topswitch control pin voltage (typically 5.7v), the voltage drops of rectifiers d2 and d3, and the turns ratio between the bias winding and output winding of t1. other output voltages are also possible by adjusting the transformer turns ratios. the high voltage dc bus is applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated high-voltage mosfet within the top200. d1 and vr1 clamp the voltage spike caused by transformer leakage inductance to a safe value and reduce ringing at the drain of u1. the power secondary winding is rectified and filtered by d2, c2, l1, and c3 to create the 5v output voltage. the bias winding is rectified and filtered by d3, r1 and c5 to create a bias voltage to the top200. c5 also filters internal mosfet gate drive charge current spikes on the control pin, determines the auto-restart frequency, and together with r1, compensates the control loop. pi-1267-010595 5 v rtn c5 47 m f u1 top200yai d2 1n5822 d3 1n4148 l1 (bead) c2 330 m f 25 v c3 150 m f 25 v t1 d1 uf4005 dc input vr1 1n4764 r1 22 w circuit performance: load regulation - ?.0% (10% to 100%) line regulation - ?.2% 95 to 370 v dc ripple voltage - ?5 mv drain source control figure 1. schematic diagram of the st200 minimum parts count 5v, 5w bias supply.
AN-14 8 b 6/96 2.2 st202a general circuit description the st202a is a low-cost, isolated buck-boost or flyback switching power supply using the top202 integrated circuit. the circuit shown in figure 2 produces a 7.5 v, 15 w power supply that operates from 85 to 265 vac input voltage. the 7.5 v output is directly sensed by optocoupler u2 and zener diode vr2. the output voltage is determined by the zener diode (vr2) voltage and the voltage drops across the optocoupler (u2) photodiode and resistor r1. other output voltages are also possible by adjusting the transformer turns ratios and value of zener diode vr2. ac power is rectified and filtered by br1 and c1 to create the high voltage dc bus applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated high-voltage mosfet within the top202. d1 and vr1 clamp the leading-edge voltage spike caused by transformer leakage inductance to a safe value and reduce ringing. the power secondary winding is rectified and filtered by d2, c2, l1, and c3 to create the 7.5 v output voltage. r2 and vr2 provide a slight pre-load on the 7.5 v output to improve load regulation at light loads. the bias winding is rectified and filtered by d3 and c4 to create a bias voltage to the top202. l2 and y1-safety capacitor c7 attenuate common-mode emission currents caused by high-voltage switching waveforms on the drain side of the primary winding and the primary to secondary capacitance. l2 and c6 attenuate differential-mode emission currents caused by the fundamental and harmonics of the trapezoidal or triangular primary current waveform. c5 filters internal mosfet gate drive charge current spikes on the control pin, determines the auto-restart frequency, and together with r1, compensates the control loop. figure 2. schematic diagram of the st202a power supply. pi-1699-112995 7.5 v rtn c5 47 m f d2 ug8bt d3 1n4148 r2 68 w vr2 1n5995b 6.2 v c3 120 m f 25 v t1 d1 uf4005 c2 680 m f 25 v vr1 p6ke150 circuit performance: line regulation - ?.5% (85-265 vac) load regulation - ?% (10-100%) ripple voltage - ?50 mv meets vde class b br1 400 v c1 33 m f 400 v r1 39 w u2 nec2501-h u1 top202yai drain source control c4 0.1 m f c7 1.0 nf y1 l1 3.3 m h f1 3.15 a j1 c6 0.1 m f l2 22 mh l n
b 6/96 AN-14 9 2.3 st204a general circuit description the st204a uses the top204yai integrated circuit to implement an isolated buck-boost or flyback switching power supply. figure 3 shows a power supply circuit delivering 30 w at 15 vdc from a universal ac input voltage of 85 to 265 vac. output voltage is directly sensed and accurately regulated by a secondary-referenced error amplifier. the error amplifier drives a current error signal through an optocoupler into the topswitch control pin to directly control topswitch duty cycle. output voltage can be fine-tuned by adjusting divider resistors r4 and r5. ac input voltage is rectified by br1 and filtered by c1 to create a high voltage dc bus ranging from 100 to 375 vdc. d1 and vr1 clamp leading edge voltage spikes and reduce ringing on the drain voltage waveform caused by leakage inductance. the t1 power secondary is rectified by d2 and filtered by c2 to generate dc output voltage. l1 and c3 provide additional filtering to reduce high frequency ripple voltage. r2 improves load regulation at light loads by pre-loading the output voltage. the t1 bias winding is rectified by d3 and filtered by c4 to create the topswitch bias voltage. l2 and y1-safety capacitor c7 attenuate common-mode emission currents caused by high-voltage switching waveforms on the drain side of the primary winding and the primary to secondary capacitance. l2 and c6 attenuate differential-mode emission currents caused by the fundamental and harmonics of the trapezoidal primary current waveform. c5 filters internal mosfet gate drive charge current spikes on the control pin, determines the auto-restart frequency, and together with r1, compensates the control loop. the tl431 shunt regulator (u3) integrates an accurate 2.5 v bandgap reference, op amp, and driver into a single device used as a secondary-referenced error amplifier. output voltage is sensed, divided by r4 and r5, and compared with the internal reference. c9 and r4 determine error amplifier frequency response. r1 limits led current and sets overall control loop dc gain. figure 3. schematic diagram of the st204a power supply 15 v rtn br1 400 v c1 47 m f 400 v c5 47 m f c4 0.1 m f u1 top204yai r3 6.2 w r2 200 w 1/2 w d2 mur610ct d3 1n4148 c2 1000 m f 35 v t1 d1 byv26c c7 1.0 nf y1 drain source control c3 120 m f 25 v u2 nec2501 u3 tl431 r4 49.9 k w r5 10 k w c9 0.1 m f r1 510 w vr1 p6ke200 l1 3.3 m h f1 3.15 a j1 c6 0.1 m f l2 33 mh l n circuit performance: line regulation - ?.2% (85-265 vac) load regulation - ?.2% (10-100%) ripple voltage - ?50 mv meets cispr-22 class b pi-1700-112995
AN-14 10 b 6/96 3. drain clamping transformer leakage inductance causes voltage spikes when the topswitch output mosfet turns off. these voltage spikes must be clamped to keep the topswitch drain voltage below the bv dss rating. the recommended clamp circuits shown in figures 2 and 3 consist of blocking diode d1 and zener diode vr1. voltage spikes are effectively clamped below the topswitch drain voltage rating. rcd clamp circuits are not recommended because clamping voltage varies with load current. rcd clamp circuits may allow the drain voltage to exceed the data sheet breakdown rating of topswitch during overload operation or during turn on with high line ac input voltage. d1 should be an ultra fast recovery, high voltage rectifier with a reverse recovery time t rr of less than 75 ns and breakdown voltage rating of 400v for top1xx series and 600v for top2xx series. zener diode vr1 must have sufficient power handling capability in both transient and steady state operation. vr1 should be selected such that clamp voltage is approximately 1.5 times higher than reflected output table 1. recommended blocking diodes (d1) and recommended clamp zener diodes (vr1). blocking diodes clamp zener diodes other clamp zener diode series that can be used include: 1.0 watt 1n476x (motorola) 1.5 watt bzy97 (philips, thomson, fagor) 3.25 watt bzt03 (philips, temic) 1.0 watt vrd z2xxu (ishizuka) 2 watt bz v47c (thomson) 5 watt 1n53xx (motorola, thomson) 1.3 watt bzx85c (thomson) 2.5 watt bzd23 (philips) 6 watt bzw03/d (temic) voltage v or . v or should be 60 v or less for top1xx devices and 135 v or less for top2xx devices. for all topswitch power and peak current levels, the low cost, 5 watt p6ke91- p6ke200 zener diode transient voltage suppressor series can be used and is available from motorola and sgs-thomson. transient voltage suppressor zener diode thermal impedance and steady state power dissipation capability depend heavily on lead diameter which should be between 0.037 and 0.043 inch. other manufacturers (including general instrument and fagor) make parts with identical part numbers but (due to smaller lead diameter) have lower effective thermal impedance and less steady state power dissipation capability. the 1.5 watt 1n5956 (200 v) zener diode is sufficient for lower power and lower peak drain current levels (below 600 ma) and are available from motorola. table 1 shows recommended blocking diodes (d1) and clamp zener diodes (vr1) for each topswitch . also shown are other zener diode families that can be used for clamp zener diode vr1. refer to an-16 for more information on reflected output voltage and clamping. general philips motorola instrument top100 byv26b mur140 uf4004 top101 byv26b mur140 top102 byv26b mur140 top103 byv26b top104 byv26b top200 byv26c mur160 uf4005 top201 byv26c mur160 uf4005 top202 byv26c mur160 top203 byv26c mur160 top214 byv26c top204 byv26c 115 vac universal doubled 115 input input or 230 vac input (v or 60v) (v or 135v) (v or 135v) p6ke91 p6ke91 p6ke91 p6ke91 p6ke91 1n5956 1n59536 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200 p6ke200
b 6/96 AN-14 11 4. pc layout 4.1 single point ground/kelvin source pin connections figure 4 shows how auto-restart/compensation capacitor c5 must be connected to the source pin using a single point ground or kelvin connection. proper layout prevents shutdown at turn on or instability due to high source pin switching currents. high voltage return to input capacitor c1 must be connected directly to the source pad with a separate trace and must not share the figure 4. recommended topswitch layout. c5 trace . bias/feedback return should also be connected directly to the source pad with a separate trace as shown. the source pin must be kept as short as possible . do not bend or extend the source pin . insert topswitch fully into the pc board as shown. extend and bend the drain pin if additional creepage distance on the pc board is necessary. 4.2 ideal component placement figure 5 shows ideal component placement and single sided pc trace connections for all critical power and emi components with the st204a schematic (figure 3) used for reference. pi-1697-120195 pc board kelvin-connected bypass capacitor and/or compensation network bias/feedback input bias/feedback return high-voltage return bend drain pin forward if needed for creepage drain source control do not bend source pin keep it short high voltage return bias winding return bypass capacitor d s c top view bias/feedback input c5 to c1 insert fully into pc board a checklist is provided on the next page which is useful for uncovering potential pc layout related problems in any topswitch power supply. figure 5. ideal placement for critical components. + pi-1334-012695 - c1 c5 r3 u2 c3 c2 t1 l1 c4 d1 c7 y1 + - + - - + - output connector vr1 d2 u1 + { loop length not critical jumper
AN-14 12 b 6/96 1) topswitch (u1), c1, and transformer t1 primary pins should be very close together to minimize pc trace length and loop area. the traces connecting these components have fast switching currents which cause common mode emi emissions. note topswitch alignment and right angle heat sink. 2) d1, vr1, and transformer t1 primary pins should be very close together to minimize pc trace length and loop area. traces connecting these components have fast switching currents which cause common mode emi emissions. 3) topswitch drain connection to t1 primary pins and clamp diode d1 must be very short because, in addition to fast switching currents, this trace also has high switching voltage which causes additional common mode emi emissions. 4) topswitch source pin should connect directly to c1 with no other traces connected to this trace segment. 5) y1-capacitor c7 should connect directly to the transformer t1 primary bias winding return and secondary output winding return pins with short, wide traces. 6) transformer t1 primary bias winding return should be connected directly to topswitch source pin. no other components should be connected to this trace segment because lightning surge test voltages induce noise voltage drops. 7) bias diode d3 should be as close as possible to transformer t1 bias winding pins. this placement minimizes anode trace length (which has high switching voltages) and maximizes length of the relatively quiet cathode trace. 8) cathode of d3 should connect directly to c4. no other components should be connected to this trace segment because lightning surge voltages and rectification current will induce noise voltage drops. c4 should then be connected through a pc trace and top side wire jumper to optocoupler u2. 9) capacitor c4 should be connected directly to topswitch source pin with no other traces connected to this trace segment. no other components should be connected to this trace segment because lightning surge test voltages will induce noise voltage drops. 10) capacitor c5 should be connected directly to topswitch source pin with no other traces connected to this trace segment. no other components should be connected to this trace segment because lightning surge test voltages will induce noise voltage drops. 11) output rectifier d2, c2, and transformer secondary pins should be very close together to minimize pc trace length and loop area. traces connecting these components have fast switching currents which cause common mode emi emissions. pc traces should be wide because peak currents are much higher than dc load current. 12) c3 should be close to the output connector and directly across the traces connecting to the output connector to minimize output switching noise. note that the pc traces run right through the capacitor lead pads and that no additional pc traces have been placed in series with c3. note also that pc traces in series with l1 and the pc trace connecting c2 and c3 can be narrower and longer because current flow is essentially dc. 13) heat sinks should be either connected only to topswitch tab or completely isolated from both topswitch tab and circuit. if the heat sink is connected elsewhere in circuit but isolated from topswitch tab, capacitance between topswitch tab and heat sink can resonate with circuit inductance causing high frequency ringing currents which may trigger topswitch shutdown latch. 4.3 pc layout checklist:
b 6/96 AN-14 13 5. flyback power supply transformer 5.1 power and inductance ranges nominal output power and primary inductance ranges are given in table 2 for each topswitch under the following ac input voltage conditions and transformer reflected output voltage v or . ? north america, japan, and taiwan (85 - 132 vac, 50/60 hz), v or = 60 v. ? universal input (85 - 265 vac, 50/60 hz), v or =135 v. ? europe and asia (195 - 265 vac, 50/60 hz), v or = 135 v. these output power ranges are rough guidelines intended only for initial topswitch selection and as a starting point for design. output power levels outside the given ranges can be used with proper attention to transformer design, heat sinking, and mechanical packaging. for more information, refer to an-16 for flyback power supply design guidelines. refer to an-17 for transformer design and an-18 for transformer construction guidelines. values in the table are based on the following assumptions: minimum available peak power (p peak ) is based on the trapezoidal, continuous mode drain current waveform shown in figure 6a and maximum primary inductance l max for each topswitch shown in table 2. ripple current to peak current ratio k rp is typically 0.4 for 100/115 vac or universal input and k rp is 0.6 for 230 vac input. p peak is the minimum peak power available at 90% of the minimum specified topswitch current limit (i limit ) and low line ac input voltage. continuous output power will approach p peak with infinite heat sinking. p max is based on empirical data with moderate heat sinking in continuous mode operation with l max for each topswitch shown in table 2. p min is based on empirical data with moderate heat sinking in discontinuous mode operation with the triangular drain current waveform shown in figure 6b and l min for each topswitch shown in table 2. input storage capacitor values: 3 m f per watt of output power for 100/115 or universal mains voltage (85 vac minimum) 1 m f per watt of output power for 230 vac mains voltage (195 vac minimum) 100/115 vac input, v or = 60 v, k rp = 0.4 part # suggested primary inductance ( m h) suggested output power (w) *p peak is the minimum available peak power at 90% of the minimum specified topswitch current limit (i limit ) and low line ac input voltage. table 2. recommended flyback power supply primary inductance and output power ranges. 230 vac input, v or =135 v, k rp = 0.6 universal input, v or = 135 v, k rp = 0.4 top100 top101 top102 top103 top104 top200 top201 top202 top203 top214 top204 top200 top201 top202 top203 top214 top204 p min 0 15 20 25 30 p nom 10 24 33 40 45 p max 19 33 45 55 60 *p peak 19 33 48 63 73 p min 0 10 15 20 25 30 p nom 6 16 23 28 34 40 p max 12 22 30 35 42 50 *p peak 13 27 40 48 61 73 p min 0 20 30 40 50 60 p nom 9 29 43 54 68 80 p max 18 37 55 67 84 100 *p peak 18 37 55 67 84 100 l max 1128 649 446 340 293 l max 3537 1703 1150 958 754 630 l max 3677 1789 1203 988 788 662 l min 504 357 268 214 179 l min 1963 1150 766 575 460 383 l min 2594 1418 946 709 567 473 for applications requiring high efficiency and low power loss, start with appropriate p max column to select the proper topswitch . then pick the transformer primary inductance from the l max column. for example, for a universal input and 22 watt output, start with the universal input table and p max column. the top201 will be the first choice. primary inductance is read from the l max column and found to be 1703 m h.
AN-14 14 b 6/96 applications requiring a small size transformer should start with the appropriate p min column to select the proper topswitch . then pick the transformer primary inductance from the l min column. for example: for a 115 vac input and 20 watt output, start with the 100/115 vac input table and p min column. the top102 is the first choice. primary inductance is read from the l min column and found to be 268 m h. p peak is critical for power supply applications with large peak loads such as disk drives, printers, and audio amplifiers. heat sinking and component temperature rise determines the length of time that topswitch can deliver peak power p peak . figure 6. current waveform shapes. pi-1903-061296 i p i r i p } i r } k rp = = 0.4 i r i p k rp = 1.0 drain current waveform shapes continuous mode (a) discontinuous mode (b) 5.2 transformer turns ratio curves the transformer turns ratio is determined from the low line minimum dc input voltage v min , output voltage v o , and reflected output voltage v or . v min depends on the energy storage input capacitance. a general rule is to use 3 m f/watt of output power for universal input or 100/115 vac applications figure 7. transformer turns ratio for various minimum dc input voltages and duty cycles. 20 40 0 015 10 5202530 output voltage (v) turns ratio pi-1904-061296 v or = 135 v v or = 60 v and 1 m f/watt of output power for 230 vac input applications. applications using doublers to get the higher effective dc voltage from a 100/115 vac input should use two series capacitors, each with a value of 2 m f/watt of output power. these capacitor guidelines result in a minimum v min of approximately 90 vdc for universal input or 100/115 vac applications and 240 vdc for 230 vac or doubler applications. applications using the top2xx series devices and operating from universal input voltage, 230 vac, or using a doubler from 100/115 vac should have a transformer designed for a reflected voltage v or of 135 v or less to limit peak drain voltage stress. applications using the top1xx series devices operating from 100/115 vac should design for a reflected output voltage v or of 60 v or less. some applications can benefit by designing for slightly lower reflected output voltage v or to reduce voltage stress when operating at high line. the transformer turns ratio is given below where n p is the primary number of turns, n s is the secondary number of turns, v or is the reflected output voltage, v o is the output voltage, and v d is the diode forward voltage. n n v vv p s or od = + turns ratio curves derived from the above equation are shown in figure 7 for reflected output voltages of 60 v and 135 v. v diode is assumed to be 0.7 v.
b 6/96 AN-14 15 6. optimizing power supply efficiency efficiency is typically greater than 80% for most topswitch power supplies above 10 watts. efficiency can be enhanced to as high as 90% with the following changes: design for higher output voltage (up to 30 volts). for example, if a choice is available between output voltages of 12 and 15 volts, the 15 volt design will have better efficiency. use schottky output rectifiers. universal input voltage operation will require a transformer designed for 135 v reflected output voltage v or to keep secondary voltage stress below schottky rectifier breakdown rating. increase transformer primary inductance for continuous mode operation to reduce topswitch rms current and conduction power loss. figure 6a shows the trapezoidal, continuous mode drain current waveform. the ripple current to peak current ratio (k rp ) has a practical lower limit of 0.4 (0.6 for 230 vac input). to maintain control loop stability when operating in the continuous mode, output capacitor size or compensation circuitry may need to change. reduce transformer leakage inductance with split primary winding. remove primary rc damping networks. a properly designed primary clamp circuit will reduce primary ringing so that a damping circuit is not necessary. remove secondary rc damping network. proper attention to pc board layout and selection of emi filter components may eliminate the need for the secondary rc damping network. choose higher current bridge rectifier diodes and common mode choke to reduce power losses due to input current. remove minimum load circuit if application allows. use higher power topswitch with lower r ds(on) . add heat sinks to topswitch and output rectifier d2. refer to an-19 for more information. 7. thermal design 7.1 heat sinking topswitch , clamp zener diode vr1, and output rectifier d2 are the critical power bearing components. temperature data should be taken on each of these three components at rated load current and input voltage in the mechanical package used for the actual application. excessive component temperature can be reduced by selecting components with higher rating, using mounting techniques with better heat transfer, or adding heat sinks. heat sinking topswitch is very simple. the to220 tab is simply attached directly to the heat sink using a screw, bolt, or clip. power supplies in plastic enclosures usually require a simple, non-safety-isolated, sheet metal stamped heat sink mounted along the edge of the pc board to transfer heat to the inside wall of the enclosure. in forced air applications, topswitch is also directly attached to a non-safety-isolated, free standing heat sink located in the moving air path. applications with metal chassis or cold plates require safety insulation beneath the topswitch tab. axial output rectifiers and zener diodes conduct heat through the mounting leads. thermal impedance can be reduced and power handling improved by mounting axial rectifiers with short leads to wide copper traces on the pc board. thermal impedance through each lead can be different if the die is bonded directly to one lead and connected to the other lead through a bonding wire. with vertical mounting, the lead with the lowest thermal impedance should be kept very short to minimize device junction temperature. a larger t0-220 style diode can also be used with the various heat sinks described above.
AN-14 16 b 6/96 8. auto-restart aluminum electrolytic auto-restart capacitor c5 determines the amount of time allowed for power supply start-up. when power is first applied, c5 charges to 5.7 volts before the topswitch mosfet is enabled and the power supply starts. the output voltage must become regulated before c5 discharges from 5.7 v to approximately 4.7 v or topswitch will disable the mosfet and enter the auto-restart mode. during auto-restart, c5 goes through 8 charge/discharge cycles before the topswitch mosfet is enabled again for another try. c5 may have a series resistor up to 100 w which has little effect on auto-restart. low dc input voltage (below 40 v) will cause the auto-restart time intervals to increase and auto-restart frequency to decrease. ac mains voltage is rectified and filtered resulting in a minimum high voltage dc bus of at least 85 vdc. during ac input voltage transients or dropout conditions, input storage capacitor c1 can discharge below 40 v which reduces topswitch 7.1 heat sinking (continued) the clamp zener diode must also be mounted with very short leads and wide copper traces for lowest thermal impedance. for example: the motorola 5 watt 1n5333b-1n5388b zener diode series has a primary thermal conduction path through the cathode lead which should be the shorter lead when vertically mounted. dissipation in clamp zener diode vr1 can also be minimized by reducing transformer leakage inductance. 7.2 thermally protecting entire power supply topswitch on-chip overtemperature protection will protect the entire power supply during overload conditions that are not severe enough to trigger auto-restart. clamp zener diode vr1 and output rectifier d2 must be selected and mounted to withstand overload conditions at high line input long enough for the topswitch junction temperature to reach the thermal shutdown temperature threshold. the output rectifier should have slightly better heat sinking compared with topswitch (u1) in most applications. for example, the 15 watt st202a power supply using the top202yai (figure 2) has no topswitch heat sink but has a small (0.8 inch x 0.8 inch, 40 mil thick), stamped copper plate style heat sink attached to the output rectifier. the 30 watt st204a power supply using the top204 (figure 3) has a topswitch heat sink (1.0 inch x 1.0 inch, 40 mils thick) and a larger heat sink (1.4 inch x 1.0 inch, 40 mils thick) on output rectifier d2. control pin charging current i c , increases charging time for auto-restart capacitor c5, and decreases the auto-restart frequency. short interruptions of ac power will cause topswitch to enter the 8-count auto-restart cycle before starting again if input energy storage capacitor c1 is not completely discharged and auto-restart capacitor c5 is not discharged below the control pin internal power up reset voltage threshold. a short delay due to auto-restart will be observed when starting after a short interruption in input power. the control pin voltage also has the 8 count, hysteretic auto- restart waveform whenever the output mosfet is disabled. this includes latching shutdown where the output mosfet has been latched off. when the internal shutdown latch is set, the hysteretic waveform on the control pin will continue until topswitch is reset by removing input power or shorting the control pin to the source pin. 9. output overvoltage protection figure 8 shows a discrete scr circuit which turns topswitch off when an overvoltage condition is sensed on the primary bias winding. this circuit latches externally and holds the control pin low. overvoltage latching occurs when the bias voltage exceeds the sum of the zener diode voltage and the npn transistor base-emitter voltage drop (0.7 v). figure 9 shows a diac (or silicon bi-directional switch) circuit which triggers the internal shutdown latch and turns topswitch off when an overvoltage condition causes the primary bias winding to exceed the diac trigger voltage. a zener diode can be used to limit the output voltage as shown in figure 10. if the optocoupler or secondary reference fails, regulation will default to the primary connected zener for output voltage control.
b 6/96 AN-14 17 10. current to duty cycle conversion topswitch is a voltage-mode device that produces a duty cycle inversely proportional to control pin current. topswitch is not a current-mode device. increasing control pin current will linearly decrease the duty cycle down to the minimum duty cycle value. further increases in control pin current will have no effect on the duty cycle until reaching the latched shutdown trigger current (i sd ) threshold at which point topswitch shuts down. 11. minimum duty cycle operation topswitch internal supply current remains constant and does not vary with duty cycle because of the minimum duty cycle dc min . in some cases, a small pre-load may be necessary to keep a lightly loaded or unloaded output voltage within the desired range due to dc min . shunt resistance or a zener diode with the proper power rating can simply be added across the output voltage to provide preload current. figure 2 shows how r2 and vr2 provide minimum loading for the st202a without adding a large power component. r2 is a small, 1/8 watt resistor which passes minimum load current through the existing 500 mw zener diode (vr2). figure 3 shows a variable minimum loading approach used on the st204a. r2 dissipates the most power when the power supply output is lightly loaded and the tl431 (u3) output is saturated low to decrease topswitch duty cycle. during normal operation, when wider duty cycles are necessary, topswitch control pin current is lower, tl431 output voltage is higher, r2 power dissipation is lower, and overall efficiency is improved. 12. control loop 12.1 basic techniques the topswitch control function has two poles and a zero. one pole is due to an internal rc filter with a typical corner frequency of 7 khz. this rc network filters switching noise but contributes little phase shift at normal crossover frequencies of 1 to 2 khz. auto-restart capacitor c5 (typically 47 m f) together with the control pin dynamic impedance (typically 15 w ) contributes the second pole of approximately 226 hz. c5 as shown in figure 11a has equivalent series resistance (typically 2 w ) which creates a zero at approximately 1.7 khz. this compensation method is used for power supplies operating in discontinuous mode or lightly continuous mode at duty cycles of 50% or less (such as the st202a in figure 2). additional series resistance r3 (between 2 w and 15 w ) can be added as shown in figure 11b to move the zero lower in frequency. this compensation method is used for power supplies operating in continuous mode (such as the st204a in figure 3). pi-1142a-081294 from secondary bias winding 47 m f 0.1 m f drain source control pi-1141a-081294 from secondary bias winding mbs4991 47 m f 1 m f 10 w drain source control pi-1140a-081294 from secondary bias winding 1n5231b 47 m f 0.1 m f 47 w drain source control figure 8. latching overvoltage protection using an scr. figure 9. latching overvoltage using a diac. figure 10. bias winding regulator to limit output voltage.
AN-14 18 b 6/96 12 control loop (continued) r3 can be increased beyond 15 w up to a maximum value of 100 w to eliminate the effect of auto-restart capacitor c5 from the control loop but bypass capacitor c10 must then be added as shown in figure 11c. this compensation method is good for power supplies with sophisticated, secondary side compensation schemes that do not require the dominant pole caused by auto- restart capacitor c5. r3 values beyond 100 w are not recommended because auto-restart timing intervals will decrease and auto-restart frequency will increase significantly. in optocoupler feedback (such as the st204a in figure 3 and the st202a in figure 2), series resistor r1 determines loop gain. the initial value of r1 is selected using the following "5% rule": with the power supply operating at nominal line and full load conditions, the average voltage across r1 should be approximately 5% of the output voltage. to help compensate the control loop, r1 can be increased above the 5% value to reduce loop gain. in optocoupler circuits which use a zener diode (such as the st202a circuit in figure 2), reducing r1 below the 5% value will improve load regulation but will also increase loop gain. stability can be examined with a step load change applied to the power supply output. a current step from 75% to 100% of rated output current is normally used. the voltage response is observed for settling time and damping. in primary bias power supplies, the bias voltage should be tested separately with a step load change of 25% (typically 1 ma). an lc postfilter effectively reduces output switching frequency ripple voltage and high frequency noise but can cause circuit instability due to additional phase shift. the st202a power supply (figure 2) shows the proper connection for simple figure 11. control pin compensation. pi-1277-011895 drain source control c5 47 m f drain source control c5 47 m f r3 2.0 w to 15 w (a) (b) (c) drain source control c5 47 m f c10 0.1 m f r3 15 w to 100 w . optocoupler circuits (to the rectifier side of l1). the st204a power supply (figure 3) shows the proper connection for accurate optocoupler circuits. the optocoupler is connected to the rectifier side of l1 but the resistor divider senses the voltage directly at the power supply output which makes load regulation independent of the dc resistance of l1. in this method, dc feedback comes directly from the output while ac feedback comes from before the postfilter to avoid additional phase shift. 12.2 topswitch circuit with enhanced bandwidth simple circuit improvements reduce output voltage line frequency ripple and improve transient response in topswitch power supplies using a tl431 shunt regulator and optocoupler for control loop feedback. figure 12 shows how the control circuitry of a typical topswitch power supply (such as the st204a reference design using the top204yai) can be easily modified to increase control loop gain and bandwidth which reduces output voltage line frequency ripple while also improving transient response. reducing capacitance c9 down to 0.01 m f improves tl431 frequency response. increasing r3 to 13 w improves loop phase margin. adding 100 k w resistor r6 as shown increases overall gain and also increases phase margin.
b 6/96 AN-14 19 pi-1567-092795 15 v rtn br1 400 v c1 47 m f 400 v c5 47 m f c4 0.1 m f u1 top204yai r3 13 w r2 200 w 1/2 w d2 mur610ct d3 1n4148 c2 1000 m f 35 v t1 1 9, 10 6,7 4 5 2 t1204 d1 byv26c c7 1.0 nf drain source control c3 120 m f 25 v u2 nec2501 u3 tl431 r5 10 k w r1 510 w vr1 p6ke200 l1 3.3 m h f1 3.15 a j1 c6 0.1 m f l2 33 mh l n circuit performance: line regulation - ?.2% (85-265 vac) load regulation - ?.2% (10-100%) ripple voltage ?0 mv meets cispr-22 class b c9 0.01 m f r4 49.9 k w r6 100 k w figure 12. schematic diagram of the st204a power supply with enhanced bandwidth and lower line frequency ripple voltage. 13. emi 13.1 topswitch advantages common mode emi is lower with topswitch because of the source connected tab and controlled turn-on. the topswitch thermal tab is connected to the quiet source of the output mosfet. the tab of discrete power mosfet transistors act as antennae, broadcasting common-mode emissions because the tab is connected to the drain which is switching at high frequency. the discrete mosfet common- mode emissions are even higher when a heat sink is added. the topswitch internal mosfet has a controlled turn-on characteristic which determines falling edge dv/dt (typically 50 ns) and further decreases common-mode emissions. discrete controller/mosfet solutions require extra components to properly tailor the turn-on fall time. drain trace length should be kept as short as possible to minimize radiated emi. 13.2 emi filter topology general emi filter topology is shown in both the st202a (figure 2) and st204a (figure 3) schematics. common mode emission currents are attenuated by common mode choke l2 and y1-capacitor c7. l2 and c6 attenuate difference mode emission currents due to the fundamental and harmonics of the trapezoidal or triangular current waveform flowing in the transformer primary, topswitch mosfet, and c1. figures 2 and 3 show a single reinforced insulation y1 safety capacitor c7 (murata de1110e102m act4k-kd, roederstein wkp102mcpe.ok or rifa part number pme294rb4100m), rated for direct connection between primary and secondary. when using standard y2-capacitors, two larger capacitors (typically 2200 pf) must be used in series to meet safety requirements. refer to an-15 for more information.
AN-14 20 b 6/96 14. soft start 14.1 optocoupler feedback soft start can be added to eliminate turn-on overshoot in optocoupler feedback applications with a 4.7 m f to 47 m f aluminum electrolytic capacitor (c ss ) placed across the shunt element as shown in figure 13. soft start capacitor c ss increases optocoupler current during turn-on to limit the duty cycle and slow down the rising output voltage. c ss has minimal effect on the control loop during normal operation. r2 discharges soft start capacitor c ss when input power is removed. figure 13. implementing soft start with optocoupler feedback. 7.5 v rtn d2 ug8bt r2 68 w vr2 1n5995b 6.2 v c3 120 m f 25 v c2 680 m f 25 v r1 39 w u2 nec2501-h l1 3.3 m h pi-1278-010494 15 v rtn r2 200 w 1/2 w d2 mur610ct c2 1000 m f 35 v c3 120 m f 25 v u2 tl431 r4 49.9 k w r5 10 k w c9 0.1 m f r1 510 w l1 3.3 m h c ss + c ss + (a) detail from st202a (b) detail from st204a
b 6/96 AN-14 21 14.2 bias winding feedback soft start can be implemented to eliminate turn-on overshoot in primary regulated feedback applications with the circuit shown in figure 14. soft start capacitor c ss increases topswitch pi-1290-121994 u1 pwr-top200yai vr2 22 v 5% r d 10 k w r1 22 w c4 0.1 m f c ss 10 m f drain source control c5 47 m f 25 v figure 14. implementing soft start with bias winding feedback pi-1126-041994 0.1 m f 47 m f 0-50 v 40 v topswitch 470 w 5 w s2 s1 470 w drain source control note: this test circuit is not applicable for current limit or output characteristic measurements. figure 15. topswitch general test circuit. 15. bench testing figure 15 shows a topswitch general test circuit for measuring most data sheet parameters. this test circuit is not applicable for current limit or output characteristic measurements. under some conditions, externally provided bias or supply current driven into the control pin from a low impedance source (<1 k w ) can stall topswitch in an auto-restart cycle indefinitely and prevent starting. shorting the control pin to the source pin will reset the shutdown latch within topswitch , which will then begin a normal start-up cycle. to avoid this problem when doing bench evaluation, it is recommended that power should be applied to the control pin before the drain voltage is applied. do not plug the topswitch device into a hot ic socket during test. capacitors mounted on the pc board may be charged and deliver a surge current into the low impedance control pin. this surge current may be sufficient to trigger the topswitch shutdown latch. control pin current during turn-on to limit the duty cycle and slow down the rising output voltage. resistor r d discharges c ss when the power supply is turned off.
AN-14 22 b 6/96 16. optocoupler recommendations optocouplers graded for minimum current transfer ratio (ctr) variation with minimum ctr above 50% and maximum ctr below 200% are recommended. ctr below 50% will require excessive photodiode currents to properly control topswitch duty cycle. ctr above 200% could trigger the topswitch shutdown latch during start up or load transients. the 5% rule for r1 selection (section 12.1) will compensate for nominal ctr value. table 3 lists many suitable optocouplers from various manufacturers. (isocom requires an "x" suffix for safety agency approved versions.) generic 4nxx series optocouplers (including 4n25, 4n26, etc.) are not recommended because ctr is uncontrolled. table 3: suggested optocouplers with ctr between 50 and 200. ctr(%) bvceo mfg cny17-2 63-125 70 v motorola, siemens, toshiba quality technologies, isocom cny17-3 100-200 70 v motorola, siemens, toshiba quality technologies, isocom sfh600-1 63-125 70 v siemens, isocom sfh600-2 100-200 70 v siemens, isocom pc702v2 63-125 70 v sharp pc702v3 100-200 70 v sharp pc714v1 80-160 35 v sharp pc110l1 50-125 35 v sharp pc112l2 80-200 70 v sharp cny17g-2 63-125 32 v temic cny17g-3 100-200 32 v temic moc8101 50-80 30 v motorola, isocom moc8102 73-117 30 v motorola, isocom moc8103 108-173 30 v motorola, isocom cny17f-2 63-125 70 v siemens, quality technologies, isocom cny17f-3 100-200 70 v siemens, quality technologies, isocom cny75a 63-125 90 v temic cny75b 100-200 90 v temic pc111l1 50-125 35 v sharp pc113l2 80-200 70 v sharp cny75ga 63-125 90 v temic cny75gb 100-200 90 v temic pc816a 80-160 70 v sharp pc817a 80-160 35 v sharp sfh 610a-2 63-125 70 v siemens sfh 610a-3 100-200 70 v siemens ps2501-h 80-160 40 v nec 6 pin dip 6 pin dip, 8 mm spacing 6 pin dip, no base connection 6 pin dip, no base connection, 8mm spacing 4 pin dip
b 6/96 AN-14 23 17. input undervoltage lockout circuitry 17.1 optocoupler feedback control figure 16 shows a circuit for implementing input undervoltage lockout with optocoupler feedback control. this circuit holds the control pin voltage (v c ) low through d5 and q1 until the voltage at the base of transistor q1 set by the r6-r7 voltage divider exceeds approximately 4.4 volts. this circuit prevents topswitch from starting until the dc input voltage v dc across c1 is high enough for regulation. when v dc is low, base current through r7 biases pnp transistor q1 on and holds the topswitch control voltage below the internal uv lockout threshold voltage (typically 4.7 volts). as v dc rises, the q1 base voltage will rise high enough to cut off q1 and allow the power supply to start. for example, for r6 of 1 m w , transistor base emitter voltage (v be ) and diode voltage (v d ) of 0.65 v, and v dc of 100 v, r7 is found to be 46.4 k w . during steady state operation, diode d5 is reverse biased and q1 may be on with current limited by r8. to minimize power dissipation, bias voltage v bias can be set to as low as 12 v or an optional resistor can be inserted between the emitter of q1 and v bias . when ac input voltage is removed, v dc decreases as c1 discharges until output voltage v o falls out of regulation and allows c5 to discharge. the discharge current through q1 and d5 is set by r8 to a value larger than the internal control pin charging current (i c ) to ensure that the control pin voltage will be pulled below the internal uv lockout threshold voltage to turn topswitch off. q1 continues to hold the control pin voltage low until ac input voltage is applied and v dc becomes high enough for the power supply to regulate again. rr vv v vvvv m cbed dc c be d 76 1 44 100 4 4 46 4 = -- -- - = - @ () . . . k w figure 16. input under voltage lockout circuitry for optocoupler feedback control. pi-1328-010495 u1 topswitch drain source control q1 2n2907a d5 c4 d3 d2 r8 1k w r6 1m w r7 46.4 k w v 0 c1 + v dc - d1 vr1 c5 v bias rtn
AN-14 24 b 6/96 17.2 bias winding feedback control figure 17 shows a circuit for implementing input undervoltage lockout with bias winding feedback control. this circuit holds the control pin voltage (v c ) low through q1 until the voltage at the cathode of d4 set by the r6-r7 voltage divider exceeds approximately 4.4 volts. this circuit prevents topswitch from starting until the dc input voltage v dc across c1 is high enough for regulation. when v dc is low, base current through d4 and r7 biases pnp transistor q1 on and holds the topswitch control voltage below the internal uv lockout threshold voltage (typically 4.7 volts). as v dc rises, the voltage at the cathode of d4 will rise high enough to cut off q1 and allow the power supply to start. use the equation from section 17.1. for example, for r6 of 1m w , transistor base emitter voltage (v be ) and diode voltage (v d ) of 0.65 v, and v dc 18. doubler input for increased output power figure 18 shows a voltage doubler circuit for generating a nominal 300 volt dc bus from 110 vac input. removing jumper j1 allows the circuit to operate as a full wave bridge rectifier from 230 vac input. both capacitors are rated for 200 to 250 volts dc with approximately 2 m f for each watt of output power. because of capacitor dc leakage current, balance resistors may be necessary to keep the voltage across each capacitor equal and within rating. for 100/110v only operation, d a , d b , r a and r b can be removed to reduce cost. pi-1327-010595 u1 topswitch drain source control q1 2n2907a d4 vr2 c4 d3 d2 r1 r8 1k w r6 1m w r7 46.4 k w v 0 c1 + v dc - d1 vr1 c5 rtn figure 17. input under voltage lockout circuitry for bias winding feedback control. pi-1281-010395 v dc high voltage return line neutral + + j1 d a d b r b r a figure 18. voltage doubler. of 100 v, r7 is found to be 46.4 k w . q1 is cut off during steady state operation and d4 prevents excessive reverse base emitter voltage. when ac input voltage is removed, v dc decreases as c1 discharges until output voltage v o falls out of regulation and allows c5 to discharge. the discharge current through q1 is set by r8 to a value larger than the internal control pin charging current (i c ) to ensure that the control pin voltage will be pulled below the internal uv lockout threshold voltage to turn topswitch off. q1 continues to hold the control pin voltage low until ac input voltage is applied and v dc becomes high enough for the power supply to regulate again.
b 6/96 AN-14 25 19. power factor correction (pfc) nominal output power ranges for pfc applications are given in table 4 for each topswitch . refer to dn-7 for recommended inductance and precompensation resistance values. 19.1 reverse drain voltage do not allow the drain voltage to ring below the source. add a fast recovery, high voltage (200 to 400 v) diode (d2 in figure 19) in series with the drain when using topswitch in a pfc circuit. negative voltages on the drain will forward bias the output mosfet body diode and trigger the internal shutdown latch. recycling input power or shorting the control pin to the source pin will be necessary to restart topswitch . 19.2 auto-restart in pfc applications, precompensation resistor r1 (figure 19) drives sufficient current into the control pin to overcome the discharge current and effectively stalls auto-restart. if the pfc circuit does not start the first time, an overload condition exists, or a short input power interruption occurs, topswitch will enter and stall in auto-restart. adding a parallel resistor between typically 2.7 k w and 6.8 k w across c3 provides an additional pfc output power part # 230/277 vac input top200 0 - 25 w top201 20 - 50 w top202 30-75 w top203 50 - 100 w top214 60 - 125 w top204 75 - 150 w pfc output power part # 110 vac input top100 0 - 30 w top101 25 - 50 w top102 35 - 70 w top103 45 - 90 w top104 55 - 110 w table 4. recommended pfc output power ranges. discharge path allowing the auto-restart circuit to function properly. c3 may have to be adjusted for proper auto-restart timing. 19.3 example power factor correction circuit the circuit shown in figure 19 operates from 230 vac input with typically 0.985 power factor and 8% total harmonic distortion (thd) while providing 65 watts of output power at 410 vdc. bridge rectifier br1 full wave rectifies the ac input voltage. l1, d1, c4, and topswitch make up the boost power stage. d2 prevents reverse current through the topswitch figure 19. schematic diagram of a 65w, 230 vac input boost power factor correction circuit utilizing the top202. pi-1423-040495 v o rtn d1 mur460 r1 200 k w 1/2 w r2 200 w r3 3 k w vr1 1n5386b vr2 1n5386b d2 1n4935 c1 220 nf c4 47 m f r8 430k 1/2w (bleeder resistor) c2 4.7 m f c3 220 m f r10 6.8 k w l1 500 m h ac in u1 top202yai drain source control typical performance: power factor = 0.985 thd = 8% d7 c9 220 nf d5 d6 d8 l2 33 mh f1 1 t1220 8
AN-14 26 b 6/96 19.3 example power factor correction circuit (continued) body diode. r1 generates a precompensation current proportional to the instantaneous rectified ac input voltage which directly varies the duty cycle. c2 filters high frequency switching currents while having no filtering effect on the line frequency precompensation current from the large filter capacitor c3 to prevent an averaging effect which would increase total harmonic distortion. c1 filters high frequency noise currents which could cause errors in the precompensation current. when the output voltage becomes regulated, series connected zener diodes vr1 and vr2 drive current into the topswitch control pin and directly control the duty cycle. c3 together with r3 perform low pass filtering on the feedback signal to prevent output line frequency ripple voltage from varying the duty cycle.
b 6/96 AN-14 27 japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohoma 2-chome, kohoku-ku yokohama-shi, kanagawa 222 japan phone: 81?(0)?45?471?1021 fax: 81?(0)?45?471?3717 asia & oceania for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 world headquarters power integrations, inc. 477 n. mathilda avenue sunnyvale, ca 94086 usa main: 408?523?9200 customer service: phone: 408?523?9265 fax: 408?523?9365 americas for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. pi logo and topswitch are registered trademarks of power integrations, inc. ?copyright 1994, power integrations, inc. 477 n. mathilda avenue, sunnyvale, ca 94086 applications hotline world wide 408?523?9260 applications fax americas 408?523?9361 europe/africa 44?(0)?1753?622?209 japan 81?(0)?45?471?3717 asia/oceania 408?523?9364 europe & africa power integrations (europe) ltd. mountbatten house fairacres windsor sl4 4le united kingdom phone: 44?(0)?1753?622?208 fax: 44?(0)?1753?622?209
AN-14 28 b 6/96 name ____________________________________ company ____________________________________ address ____________________________________ ____________________________________ telephone ____________________________________ fax ____________________________________ application ____________________________________ topswitch part number _______________________ quantity per month _______________________ ? to dramatically reduce topswitch design, breadboarding, and debugging time, we strongly recommend procuring a reference design/evaluation board. which reference design/evaluation board are you using now? __________________________________________________ for technical questions not answered by topswitch reference design/evaluation boards, documentation, and literature, please fill out this topfax form and fax with complete schematic and transformer or inductor documentation to power integrations, inc.. for best technical support, schematics must have component values. transformer or inductor documentation must have core part number, inductance, number of turns for each winding and construction information. topswitch topfax fax to: americas 408?523?9361 europe/africa 44?(0)?1753?622?209 japan 81?(0)?45?471?3717 asia/oceania 408?523?9364 topfax page 1 of ________ ____ schematic with component values ____ transformer documentation ____ inductor documentation ____ oscilloscope waveforms please indicate which of the following information is included with this topfax: other ___________________________________________ _________________________________________________ _________________________________________________ _________________________________________________ ac input voltage _____________ to ____________ dc input voltage _____________ to ____________ output power, steady state___________________________ output power, peak ___________________________ emi specification ___________________________ safety specification ___________________________ output steady state peak voltage output current output current 1) ________ _______ to _______ ________________ 2) ________ _______ to _______ ________________ 3) ________ _______ to _______ ________________ 4) ________ _______ to _______ ________________ please fill in application parameters:

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