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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad825 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 low-cost, general-purpose high-speed jfet amplifier connection diagrams 8-lead plastic soic (r) package 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect ad825 nc nc output +v s nc ?n +in ? s 16-lead plastic soic (r-16) package top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 nc = no connect nc nc nc input +input v s nc nc nc nc nc +v s output nc nc nc ad825 features high speed 41 mhz, C3 db bandwidth 125 v/ s slew rate 80 ns settling time input bias current of 20 pa and noise current of 10 fa/ hz input voltage noise of 12 nv/ hz fully specified power supplies: 5 v to 15 v low distortion: C76 db at 1 mhz high output drive capability drives unlimited capacitance load 50 ma min output current no phase reversal when input is at rail available in 8-lead soic applications ccd low distortion filters mixed gain stages audio amplifier photo detector interface adc input buffer dac output buffer product description the ad825 is a superbly optimized operatio nal amplifier for high speed, low cost, and dc parameters, m aking it ideally suited for a broad range of signal conditioning and data acquisition applications. the ac performance, gain, bandwidth, slew rate and drive capability are all very stable over temperature. the ad825 also maintains stable gain under varying load conditions. the unique input stage has ultralow input bias current and ultralow input c urrent noise. signals that go to e ither rail on this h igh perform ance input do not cause phase reversals at the output. these features make the ad825 a good choice as a buffer for mux outputs, creating minimal offset and gain errors. the ad825 is fully specified for operation with dual 5 v and 15 v supplies. this power supply flexibility, and the low sup- ply cu rrent of 6.5 ma with excellent ac characteristics under all su pply conditions, make the ad825 well suited for many demanding applications. figure 1. performance with rail-to-rail input signals
C2C rev. d ad825?pecifications (@ t a = 25 c, v s = 15 v unless otherwise noted) ad825a parameter conditions v s min typ max unit dynamic performance unity gain bandwidth 15 v 23 26 mhz bandwidth for 0.1 db flatness gain = +1 15 v 18 21 mhz C3 db bandwidth gain = +1 15 v 44 46 mhz slew rate r load = 1 k ? , g = 1 15 v 125 140 v/ s settling time to 0.1% 0 vC10 v step, a v = C1 15 v 150 180 ns settling time to 0.01% 0 vC10 v step, a v = C1 15 v 180 220 ns total harmonic distortion f c = 1 mhz, g = C1 15 v C77 db differential gain error ntsc 15 v 1.3 % (r load = 150 ? ) gain = +2 differential phase error ntsc 15 v 2.1 degrees (r load = 150 ? ) gain = +2 input offset voltage 15 v 1 2 mv t min to t max 5mv offset drift 10 v/ c input bias current 15 v 15 40 pa t min 5pa t max 700 pa input offset current 15 v 20 30 pa t min 5pa t max 440 pa open loop gain v out = 10 v 15 v r load = 1 k ? 70 76 db v out = 7.5 v 15 v r load = 1 k ? 70 76 db v out = 7.5 v 15 v r load = 150 ? 72 74 db (50 ma output) common-mode rejection v cm = 10 v 15 v 71 80 db input voltage noise f = 10 khz 15 v 12 nv/ hz input current noise f = 10 khz 15 v 10 fa/ hz input common-mode voltage range 15 v 13.5 v output voltage swing r load = 1 k ? 15 v 13 13.3 v r load = 500 ? 15 v 12.9 13.2 v output current 15 v 50 ma short-circuit current 15 v 100 ma input resistance 5 10 11 ? input capacitance 6pf output resistance open loop 8 ? power supply quiescent current 15 v 6.5 7.2 ma t min to t max 15 v 7.5 ma notes all limits are determined to be at least four standard deviations away from mean value. . specifications subject to change without notice.
C3C rev. d ad825 (@ t a = 25 c, v s = 5 v unless otherwise noted) ad825a parameter conditions v s min typ max unit dynamic performance unity gain bandwidth 5 v 18 21 mhz bandwidth for 0.1 db flatness gain = +1 5 v 8 10 mhz C3 db bandwidth gain = +1 5 v 34 37 mhz slew rate r load = 1 k ? , g = C1 5 v 115 130 v/ s settling time to 0.1% C2.5 v to +2.5 v 5 v 75 90 ns settling time to 0.01% C2.5 v to +2.5 v 5 v 90 110 ns total harmonic distortion f c = 1 mhz, g = C1 5 v C76 db differential gain error ntsc 5 v 1.2 % (r load = 150 ? ) gain = +2 differential phase error ntsc 5 v 1.4 degrees (r load = 150 ? ) gain = +2 input offset voltage 5 v 1 2 mv t min to t max 5mv offset drift 10 v/ c input bias current 5 v 10 30 pa t min 5pa t max 600 pa input offset current 5 v 15 25 pa t min 5pa offset current drift t max 280 pa open loop gain v out = 2.5 v 5 v r load = 500 ? 64 66 db r load = 150 ? 64 66 db common-mode rejection v cm = 2 v 5 v 69 80 db input voltage noise f = 10 khz 5 v 12 nv/ hz input current noise f = 10 khz 5 v 10 fa/ hz input common-mode voltage range 5 v 3.5 v output voltage swing r load = 500 ? 3.2 3.4 v r load = 150 ? 5 v 3.1 3.2 v output current 5 v 50 ma short-circuit current 5 v 80 ma input resistance 5 10 11 ? input capacitance 6pf output resistance open loop 8 ? power supply quiescent current 5 v 6.2 6.8 ma t min to t max 5 v 7.5 ma power supply rejection v s = 5 v to 15 v 76 88 db notes all limits are determined to be at least four standard deviations away from mean value. specifications subject to change without notice. specifications
ad825 C4C rev. d absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 small outline (r) . . . . . . . . . . . . . . . . see derating curves input voltage (common mode) . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . see derating curves storage temperature range (r, r-16) . . . . C65 c to +125 c operating temperature range . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead soic package: ja = 155 c/w 16-lead soic package: ja = 85 c/w ordering guide temperature package package model range description option ad825ar C40 c to +85 c 8-lead plastic soic so-8 ad825achips C40 c to +85 cdie ad825ar-reel C40 c to +85 c13 " tape and reel so-8 ad825ar-reel7 C40 c to +85 c7 " tape and reel so-8 ad825ar-16 C40 c to +85 c 16-lead plastic soic r-16 ad825ar-16-reel C40 c to +85 c13 " tape and reel r-16 AD825AR-16-REEL7 C40 c to +85 c7 " tape and reel r-16 pin configuration 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect ad825 nc nc output +v s nc in +in v s ambient temperature c 2.0 1.5 0 50 90 40 30 20 10 0 1020 30 506070 80 40 1.0 0.5 8-lead soic package t j = 150 c maximum power dissipation watts 2.5 16-lead soic package figure 2. maximum power dissipation vs. temperature caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad825 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad825 C5C rev. d typical performance characteristics r l = 150 r l = 1k supply voltage volts 20 20 018 2 output swing volts 4 6 8 10 12 14 16 15 0 5 10 15 10 5 tpc 1. output voltage swing vs. supply load resistance 0 100 output swing volts 15 0 5 10 15 10 5 200 300 400 500 600 700 800 900 1000 v s = 15v v s = 15v v s = 5v tpc 2. output voltage swing vs. load resistance supply voltage v 7.0 6.5 5.0 020 2 supply current ma 4 6 8 10 12 14 16 18 6.0 5.5 40 +25 +85 tpc 3. quiescent supply current vs. supply voltage for various temperatures frequency hz 100 1 0.01 100 10m 1k output impedance 10k 100k 1m 10 0.1 tpc 4. closed-loop output impedance vs. frequency temperature c 35 60 140 40 unity gain bandwidth mhz 20 0 20 40 80 100 120 30 15 10 5 0 25 20 20 40 60 80 phase margin c 60 bandwidth phase margin ,#.- 3 45 #*
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frequency hz 80 70 0 1k 100m 10k open-loop gain db 100k 1m 10m 60 50 10 40 30 20 open-loop phase degrees 180 135 90 45 0 v s = 15v v s = 5v tpc 6. open-loop gain and phase margin vs. frequency
ad825 C6C rev. d load resistance 80 75 60 100 10k 1k open-loop gain db 70 65 v s = 15v v s = 5v tpc 7. open-loop gain vs. load resistance frequency hz 10k 10m 100k psr db 1m 10 0 90 10 20 30 40 50 60 70 80 psrr +psrr tpc 8. power supply rejection vs. frequency frequency hz 10 10m 1k cmr db 100k 130 120 30 110 100 90 80 70 60 50 40 100 10k 1m v s = 15v v s = 5v tpc 9. common-mode rejection vs. frequency frequency hz 30 20 0 10k 100k output voltage volts p-p 1m 10m 10 r l = 1k r l = 150 tpc 10. large signal frequency response; g = +2 output swing 0 to v 200 80 0 10 10 8 settling time ns 64 2 0 2 4 6 8 180 100 60 20 140 120 40 160 0.01% 0.1% 0.01% 0.1% tpc 11. output swing and error vs. settling time frequency hz 50 55 85 100k 10m 1m distortion db 60 65 70 75 80 2nd 3rd tpc 12. harmonic distortion vs. frequency
ad825 C7C rev. d temperature c 100 60 140 40 slew rate v/ s 20 0 20 40 80 100 120 80 20 0 60 40 120 140 160 5v 15v 60 tpc 13. slew rate vs. temperature 1k 100k 10m 10k 1m v out v in v s 0.1db flatness 5v 10mhz 15v 21mhz frequency hz gain db 2 1 0 1 2 3 4 5 6 7 8 tpc 14. closed-loop gain vs. frequency, gain = +1 1k 100k 10m 10k 1m v out v in v s 0.1db flatness 5v 7.7mhz 15v 9.8mhz 1k 1k frequency hz gain db 2 1 0 1 2 3 4 5 6 7 8 tpc 15. closed-loop gain vs. frequency, gain = C1 +v s tektronix p6204 fet probe hp pulse (ls) or function (ss) generator 50 r l v out 0.01 f 10 f v s v in tektronix 7a24 preamp 0.01 f 10 f ad825 + tpc 16. noninverting amplifier connection tpc 17. noninverting large signal pulse response, r l = 1 k ? tpc 18. noninverting small signal pulse response, r l = 1 k ?
ad825 C8C rev. d tpc 19. noninverting large signal pulse response, r l = 150 ? tpc 20. noninverting small signal pulse response, r l = 150 ? +v s tektronix p6204 fet probe hp pulse generator 50 c l 1000pf v out 0.01 f 10 f v s v in tektronix 7a24 preamp 0.01 f 10 f ad825 r in 1k 1k + tpc 21. inverting amplifier connection tpc 22 . inverting large signal pulse response, r l = 1 k ? tpc 23. inverting small signal pulse response, r l = 1 k ?
ad825 C9C rev. d driving capacitive loads the internal compensation of the ad825, together with its high output current drive, permits excellent large signal performance while driving extremely high capacitive loads. +v s tektronix p6204 fet probe hp pulse generator 50 c l v out 0.01 f 10 f v s v in tektronix 7a24 preamp 0.01 f 10 f ad825 r in 1k 1k figure 3a. inverting amplifier driving a capacitive load input output figure 3b. inverting amplifier pulse response while driving a 400 pf capacitive load theory of operation the ad825 is a low cost, wide band, high performance fet input operational amplifier. with its unique input stage design, the ad825 assures no phase reversal even for inputs that exceed the power supply voltages, and its output stage is des igned to drive heavy capacitive or resistive load with small changes rela- tive to no load condition. the ad825 (figure 4) consists of common-drain common-base fet input stage driving a cascoded, common base matched npn gain stage. the output buffer stage uses emitter followers in a class ab amplifier that can deliver large current to the load while maintaining low levels of distortion. c f vneg vout vpos pos neg figure 4. simplified schematic the capacitor, c f , in the output stage, enables the ad825 to drive heavy capacitive load. for light load, the gain of the out- put buffer is close to unity, c f is bootstrapped and not much happens. as the capacitive load is increased, the gain of the output buffer is decreased and the bandwidth of the amplifier is reduced through a portion of c f adding to the dominant pole. as the capacitive load is further increased, the amplifiers band- width continues to drop, maintaining the stability of the ad825. input consideration the ad825 with its unique input stage assures no phase rever- sal for signals as large or even larger than the supply voltages. also, layout considerations of the input transistors assure func- tionality even with a large differential signal. the need for a low noise input stage calls for a larger fet transis- tor. one should consider the additional capacitance that is added to assure stability. when filters are designed with the ad825, one needs to consider the input capacitance (5 pfC6 pf) of the ad825 as part of the passive network. grounding and bypassing the ad825 is a low input bias current fet amplifier. its high frequency response makes it useful in applications such as photo diode interfaces, filters and audio circuits. when designing high frequency circuits, some special precautions are in order. cir cuits must be built with short interconnects, and resistances should have low inductive paths to ground. power supply leads should be bypassed to common as close as possible to the am plifier pins. ceramic capacitors of 0.1 f are recommended.
ad825 C10C rev. d second order low-pass filter a second order butterworth low-pass filter can be implemented using the ad825 as shown in figure 5. the extremely low bias currents of the ad825 allow the use of large resistor values, and consequently small capacitor values, without concern for devel- oping large offset errors. low current noise is another factor in permitting the use of large resistors without having to worry about the resultant voltage noise. with the values shown, the corner frequency will be 1 mhz. the equations for component selection are shown below. note that the noninverting input (and the inverting input) has an input capacitance of 6 pf. as a re sult, the calculated value of c1 (12 pf) is reduced to 6 pf. c 1 = 1.414 2 f cutoff r 1 c 2( farads ) = 0.707 2 f cutoff r 1 r 1 = r 2 = user selected typically 10 k ? to 100 k ? () a plot of the filter frequency response is shown in figure 6; better than 40 db of high frequency rejection is provided. ad825 c3 0.1 f +5v c4 0.1 f v out v in c2 6pf 5v c1 24pf r1 9.31k r2 9.31k figure 5. second order butterworth low-pass filter frequency hz 10k 100m 100k high frequency rejection db 1m 10m 0 10 20 30 40 50 60 70 80 figure 6. frequency response of second order butterworth filter
ad825 C11C rev. d outline dimensions dimensions shown in inches and (mm). 8-lead plastic soic (so-8) 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 16-lead plastic soic (r-16) seating plane 0.010 (0.25) 0.004 (0.10) 0.018 (0.46) 0.014 (0.36) 0.107 (2.72) 0.089 (2.26) 0.050 (1.27) bsc 16 9 8 1 0.419 (10.65) 0.404 (10.26) 0.299 (7.60) 0.291 (7.40) pin 1 0.413 (10.50) 0.398 (10.10) 0.015 (0.38) 0.007 (1.18) 0.364 (9.246) 0.344 (8.738) 0.045 (1.15) 0.020 (0.50)
C12C c00876cC0C2/01 (rev. d) printed in u.s.a. ad825 rev. d revision history location page changed from rev. c to rev. d. addition of 16-lead soic package (r-16) connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 addition to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 addition to ordering guide (r-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 addition of 16-lead soic package (r-16) outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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