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ramtron international corporation ? http://www.ramtron.com 1850 ramtron drive colorado springs ? mcu customer service: 1 - 800 - 943 - 4625, 1 - 514 - 871 - 2447, ext. 20 8 colorado , usa, 8092 1 ? 1 - 800 - 545 - fram, 1 - 719 - 4 81 - 7000 page 1 of 49 vrs51x5 7 0 /580 datasheet rev 1.2 versa 8051 mcus with 32/64kb overview the vrs51x570 and the vrs51x580 are low cost 8 - bit microcontrollers based on the standard 80c51 microcontroller family architecture. they are pin compatible and drop - in replacements for most 8051 mcus. ideal for a w ide range of applications requir ing large amounts of program / data memory , coupled with comprehensive peripheral support, the vrs51x570/580 devices include 32kb/64kb of flash memory, respectively, and 1kb of sram, 5 pwm output channels, a uart, three 16 - bit timers, a watch dog timer and power down features. these devices also include a fifth , 4 - bit , i/o port mapped into the ?no connect? pins of the standard 8051/52 package. this provides a total of 36 i/o s while maintaining compatibility with standard 80c51/ 52 pin outs. the vrs51x570 and vrs51x580 are available in plcc - 44 , qfp - 44 and dip - 40 packages in the industrial temperature range. the flash memory can be programmed using programmers from ramtron or other 3 rd party commercial programmer suppliers . f igure 1: vrs51 x 570 / vrs51 x 580 f unctional d iagram port 0 8051 processor port 3 port 2 port 1 pwm port 4 64 kb flash 2 interrupt inputs uart 1024 bytes of ram reset timer 0 timer 2 timer 1 power control watchdog timer address / data bus 8 8 8 8 4 5 feature set 80c51/80c52 pin compatible 12 clock periods per machine cycle 32 k b / 64 k b on - chip flash memory 1024 b ytes on - chip data ram 36 i/o lines: p0 - p 3 = 8 - bit, p4 = 4 - bit 5 - channel pwm on p1.3 to p1.7 full duplex serial port (uart) three 16 - bit timers/counters watch dog timer 8 - bit unsigned division / multiply bcd arithmetic direct and indirect addressing two levels of interrupt priority and nested in terrupts power saving modes code protection function operates at a clock frequency of up to 40 mhz low emi (inhibit ale) programming voltage: 12v industrial temperature range ( - 40c to +85c) 5v and 3v versions available (see ordering information.) f igure 2: vrs51 x 570 / vrs51 x 580 plcc and qfp p inout d iagrams pwm 3 / p 1 . 6 pwm 2 / p 1 . 5 reset pwm 4 / p 1 . 7 p 4 . 3 rxd / p 3 . 0 # int 0 / p 3 . 2 txd / p 3 . 1 t 0 / p 3 . 4 # int 1 / p 3 . 3 t 1 / p 3 . 5 # r d / p 3 . 7 # w r / p 3 . 6 x t a l 1 x t a l 2 p 4 . 0 v s s p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 1 1 p 2 . 2 / a 1 0 p 2 . 4 / a 1 2 p 2 . 6 / a 14 p 2 . 5 / a 13 # psen p 2 . 7 / a 15 p 4 . 1 ale p 0 . 7 / ad 7 # ea p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 4 / ad 4 p w m 0 / p 1 . 3 p w m 1 / p 1 . 4 t 2 e x / p 1 . 1 p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / a d 0 v d d p 0 . 2 / a d 2 p 0 . 1 / a d 1 p 0 . 3 / a d 3 1 vrs 5 1 x 570 / 580 plcc - 44 6 7 17 18 28 29 39 40 1 44 11 12 22 23 33 34 vrs 51 x 570 / 580 qfp - 44 p 2 . 6 / a 1 4 p 2 . 5 / a 1 3 # p s e n p 2 . 7 / a 1 5 p 4 . 1 a l e p 0 . 7 / a d 7 # e a p 0 . 5 / a d 5 p 0 . 6 / a d 6 p 0 . 4 / a d 4 # rd / p 3 . 7 # wr / p 3 . 6 xtal 1 xtal 2 p 4 . 0 vss p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 4 / a 12 p w m 3 / p 1 . 6 p w m 2 / p 1 . 5 r e s e t p w m 4 / p 1 . 7 p 4 . 3 r x d / p 3 . 0 # i n t 0 / p 3 . 2 t x d / p 3 . 1 t 0 / p 3 . 4 # i n t 1 / p 3 . 3 t 1 / p 3 . 5 pwm 0 / p 1 . 3 pwm 1 / p 1 . 4 t 2 ex / p 1 . 1 p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / ad 0 vdd p 0 . 2 / ad 2 p 0 . 1 / ad 1 p 0 . 3 / ad 3
vrs51x5 7 0 /580 ________________________________________________________________________________________________ www.ramtron.com page 2 of 49 pin descriptions for qfp - 44 t able 1: p in d escriptions for qfp - 44/ qfp - 44 name i/o function p wm2 o pwm channel 2 1 p1.5 i/o bit 5 of port 1 pwm3 o pwm channel 3 2 p1.6 i/o bit 6 of port 1 pwm4 o pwm channel 4 3 p1.7 i/o bit 7 of port 1 4 res i reset rxd i receive data 5 p3.0 i/o bit 0 of port 3 6 p4.3 i/o bit 3 of port 4 txd o trans mit data & 7 p3.1 i/o bit 1 of port 3 #int0 i external interrupt 0 8 p3.2 i/o bit 2 of port 3 #int1 i external interrupt 1 9 p3.3 i/o bit 3 of port 3 t0 i timer 0 10 p3.4 i/o bit 4 of port 3 t1 i timer 1 & 3 11 p3.5 i/o bit 5 of port #wr o ext. memory write 12 p3.6 i/o bit 6 of port 3 #rd o ext. memory read 13 p3.7 i/o bit 7 of port 3 14 xtal2 o oscillator/crystal output 15 xtal1 i oscillator/crystal in 16 vss - ground 17 p4.0 i/o bit 0 of p ort 4 p2.0 i/o bit 0 of port 2 18 a8 o bit 8 of external memory address p2.1 i/o bit 1 of port 2 19 a9 o bit 9 of external memory address p2.2 i/o bit 2 of port 2 20 a10 o bit 10 of external memory address p2.3 i/o bit 3 of port 2 & 21 a11 o bit 11 of external memory address p2. 4 i/o bit 4 of port 2 22 a12 o bit 12 of external memory address p2.5 i/o bit 5 of port 2 23 a13 o bit 13 of external memory address qfp - 44 name i/o function p2.6 i/o bit 6 of port 2 24 a14 o bit 14 of external memory address p2.7 i/o bit 7 of port 2 25 a15 o bit 15 of external memory address 26 #psen o program store enable 27 ale o address latch enable 28 p4.1 i/o bit 1 of port 4 29 #ea i external access p0.7 i/o bit 7 of port 0 30 ad7 i/o data/address bit 7 of external memory p0.6 i/o bit 6 of port 0 31 ad6 i/o data/address bit 6 of external memory p0.5 i/o bit 5 of port 0 32 ad5 i/o data/address bit 5 of external memory p0.4 i/o bit 4 of port 0 33 ad4 i/o data/address bit 4 of external memory p0.3 i/o bit 3 of port 0 34 ad3 i/o data/address bit 3 of external memory p0.2 i/o bit 2 of port 0 35 ad2 i/o data/address bit 2 of external memory p0. 1 i/o bit 1 of port 0 & data 36 ad1 i/o address bit 1 of external memory p0.0 i/o bit 0 of port 0 & data 37 ad0 i/o address bit 0 of external memory 38 vdd - vcc 39 p4.2 i/o bit 2 of port 4 t2 i timer 2 clock out 40 p1.0 i/o bit 0 of port 1 t2ex i timer 2 control 41 p1.1 i/o bit 1 of port 1 42 p1.2 i/o bit 2 of port 1 pwm0 o pwm channel 0 43 p1.3 i/o b it 3 of port 1 pwm1 o pwm channel 1 44 p1.4 i/o bit 4 of port 1 1 44 11 12 22 23 33 34 vrs 51 x 570 / 580 qfp - 44 p 2 . 6 / a 1 4 p 2 . 5 / a 1 3 # p s e n p 2 . 7 / a 1 5 p 4 . 1 a l e p 0 . 7 / a d 7 # e a p 0 . 5 / a d 5 p 0 . 6 / a d 6 p 0 . 4 / a d 4 # rd / p 3 . 7 # wr / p 3 . 6 xtal 1 xtal 2 p 4 . 0 vss p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 4 / a 12 p w m 3 / p 1 . 6 p w m 2 / p 1 . 5 r e s e t p w m 4 / p 1 . 7 p 4 . 3 r x d / p 3 . 0 # i n t 0 / p 3 . 2 t x d / p 3 . 1 t 0 / p 3 . 4 # i n t 1 / p 3 . 3 t 1 / p 3 . 5 pwm 0 / p 1 . 3 pwm 1 / p 1 . 4 t 2 ex / p 1 . 1 p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / ad 0 vdd p 0 . 2 / ad 2 p 0 . 1 / ad 1 p 0 . 3 / ad 3
vrs51x5 7 0 /580 ________________________________________________________________________________________________ www.ramtron.com page 3 of 49 pin descriptions for plcc - 44 t able 2: p in d escriptions for plcc - 44 plcc - 44 name i/o function 1 p4.2 i/o bit 2 of port 4 t2 i timer 2 clock out 2 p1.0 i/o bit 0 of port 1 t2ex i timer 2 control 3 p1.1 i/o bit 1 of port 1 4 p1.2 i/o bit 2 of port 1 pwm0 o pwm channel 0 5 p1.3 i/o bit 3 of port 1 pwm1 o pwm channel 1 6 p1.4 i/o bit 4 of port 1 pwm2 o pwm cha nnel 2 7 p1.5 i/o bit 5 of port 1 pwm3 o pwm channel 3 8 p1.6 i/o bit 6 of port 1 pwm4 o pwm channel 4 9 p1.7 i/o bit 7 of port 1 10 res i reset rxd i receive data 11 p3.0 i/o bit 0 of port 3 12 p4.3 i/o bit 3 of port 4 txd o transmit data & 13 p3.1 i/o bit 1 of port 3 #int0 i external interrupt 0 14 p3.2 i/o bit 2 of port 3 #int1 i external interrupt 1 15 p3.3 i/o bit 3 of port 3 t0 i timer 0 16 p3.4 i/o bit 4 of port 3 t1 i timer 1 & 3 17 p3.5 i/o bit 5 of port #wr o ext. me mory write 18 p3.6 i/o bit 6 of port 3 #rd o ext. memory read 19 p3.7 i/o bit 7 of port 3 20 xtal2 o oscillator/crystal output 21 xtal1 i oscillator/crystal in 22 vss - ground 23 p4.0 i/o bit 0 of p ort 4 plcc - 44 name i/o function p2.0 i/ o bit 0 of port 2 24 a8 o bit 8 of external memory address p2.1 i/o bit 1 of port 2 25 a9 o bit 9 of external memory address p2.2 i/o bit 2 of port 2 26 a10 o bit 10 of external memory address p2.3 i/o bit 3 of port 2 & 27 a11 o bit 11 of exter nal memory address p2.4 i/o bit 4 of port 2 28 a12 o bit 12 of external memory address p2.5 i/o bit 5 of port 2 29 a13 o bit 13 of external memory address p2.6 i/o bit 6 of port 2 30 a14 o bit 14 of external memory address p2.7 i/o bit 7 of p ort 2 31 a15 o bit 15 of external memory address 32 #psen o program store enable 33 ale o address latch enable 34 p4.1 i/o bit 1 of port 4 35 #ea i external access p0.7 i/o bit 7 of port 0 36 ad7 i/o data/address bit 7 of external memory p0.6 i /o bit 6 of port 0 37 ad6 i/o data/address bit 6 of external memory p0.5 i/o bit 5 of port 0 38 ad5 i/o data/address bit 5 of external memory p0.4 i/o bit 4 of port 0 39 ad4 i/o data/address bit 4 of external memory p0.3 i/o bit 3 of port 0 40 ad3 i/o data/address bit 3 of external memory p0.2 i/o bit 2 of port 0 41 ad2 i/o data/address bit 2 of external memory p0. 1 i/o bit 1 of port 0 & data 42 ad1 i/o address bit 1 of external memory p0.0 i/o bit 0 of port 0 & data 43 ad0 i/o addres s bit 0 of external memory 44 vdd - vcc pwm 3 / p 1 . 6 pwm 2 / p 1 . 5 reset pwm 4 / p 1 . 7 p 4 . 3 rxd / p 3 . 0 # int 0 / p 3 . 2 txd / p 3 . 1 t 0 / p 3 . 4 # int 1 / p 3 . 3 t 1 / p 3 . 5 # r d / p 3 . 7 # w r / p 3 . 6 x t a l 1 x t a l 2 p 4 . 0 v s s p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 1 1 p 2 . 2 / a 1 0 p 2 . 4 / a 1 2 p 2 . 6 / a 14 p 2 . 5 / a 13 # psen p 2 . 7 / a 15 p 4 . 1 ale p 0 . 7 / ad 7 # ea p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 4 / ad 4 p w m 0 / p 1 . 3 p w m 1 / p 1 . 4 t 2 e x / p 1 . 1 p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / a d 0 v d d p 0 . 2 / a d 2 p 0 . 1 / a d 1 p 0 . 3 / a d 3 1 vrs 51 x 570 / 580 plcc - 44 6 7 17 18 28 29 39 40
vrs51x5 7 0 /580 ________________________________________________________________________________________________ www.ramtron.com page 4 of 49 vrs51x570 ? vrs51x580 dip40 pin descriptions t able 3: vrs51 x 570 ? vrs51 x 580 p in d escriptions for dip40 package dip40 name i/o function t2 i timer 2 clock out 1 p1.0 i/o bit 0 of port 1 t2ex i timer 2 control 2 p1.1 i/o bit 1 of port 1 3 p1.2 i/o bit 2 of port 1 pwm0 o pwm channel 0 4 p1.3 i/o bit 3 of port 1 pwm1 o pwm channel 1 5 p1.4 i/o bit 4 of port 1 pwm2 o pwm channel 2 6 p1.5 i/o bit 5 of port 1 pwm3 o pwm channel 3 7 p1.6 i/o bit 6 of port 1 pwm4 o pwm channel 4 8 p1.7 i/o bit 7 of port 1 9 reset i reset rxd i receive data 10 p3.0 i/o bit 0 of port 3 txd o transmit data & 11 p3.1 i/o bit 1 of port 3 #int0 i external int errupt 0 12 p3.2 i/o bit 2 of port 3 #int1 i external interrupt 1 13 p3.3 i/o bit 3 of port 3 t0 i timer 0 14 p3.4 i/o bit 4 of port 3 t1 i timer 1 & 3 15 p3.5 i/o bit 5 of port #wr o ext. memory write 16 p3.6 i/o bit 6 of port 3 #rd o ext. memory read 17 p3.7 i/o bit 7 of port 3 18 xtal2 o oscillator/crystal output 19 xtal1 i oscillator/crystal in 20 vss - ground t 2 / p 1 . 0 t 2 ex / p 1 . 1 p 1 . 2 pwm 0 / p 1 . 3 pwm 1 / p 1 . 4 pwm 2 / p 1 . 5 pwm 3 / p 1 . 6 pwm 4 / p 1 . 7 reset rxd / p 3 . 0 txd / p 3 . 1 # int 0 / p 3 . 2 # int 1 / p 3 . 3 t 0 / p 3 . 4 t 1 / p 3 . 5 # wr / p 3 . 6 # rd / p 3 . 7 xtal 2 xtal 1 vss vrs 51 x 570 vrs 51 x 580 dip - 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vdd p 0 . 0 / ad 0 p 0 . 1 / ad 1 p 0 . 2 / ad 2 p 0 . 3 / ad 3 p 0 . 4 / ad 4 p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 7 / ad 7 # ea / vpp ale psen p 2 . 7 / a 15 p 2 . 6 / a 14 p 2 . 5 / a 13 p 2 . 4 / a 12 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 1 / a 9 p 2 . 0 / a 8 dip40 name i/o function p2.0 i/o bit 0 of port 2 21 a8 o bit 8 of external memory addr ess p2.1 i/o bit 1 of port 2 22 a9 o bit 9 of external memory address p2.2 i/o bit 2 of port 2 23 a10 o bit 10 of external memory address p2.3 i/o bit 3 of port 2 & 24 a11 o bit 11 of external memory address p2.4 i/o bit 4 of port 2 25 a12 o bit 12 of external memory address p2.5 i/o bit 5 of port 2 26 a13 o bit 13 of external memory address p2.6 i/o bit 6 of port 2 27 a14 o bit 14 of external memory address p2.7 i/o bit 7 of port 2 28 a15 o bit 15 of external memory address 29 #p sen o program store enable 30 ale o address latch enable 31 #ea / vpp i external access flash programming voltage input p0.7 i/o bit 7 of port 0 32 ad7 i/o data/address bit 7 of external memory p0.6 i/o bit 6 of port 0 33 ad6 i/o data/address bit 6 of external memory p0.5 i/o bit 5 of port 0 34 ad5 i/o data/address bit 5 of external memory p0.4 i/o bit 4 of port 0 35 ad4 i/o data/address bit 4 of external memory p0.3 i/o bit 3 of port 0 36 ad3 i/o data/address bit 3 of external memory p0.2 i/o bit 2 of port 0 37 ad2 i/o data/address bit 2 of external memory p0. 1 i/o bit 1 of port 0 & data 38 ad1 i/o address bit 1 of external memory p0.0 i/o bit 0 of port 0 & data 39 ad0 i/o address bit 0 of external memory 40 vdd - supply in put
vrs51x5 7 0 /580 ________________________________________________________________________________________________ www.ramtron.com page 5 of 49 instruction set the following tables describe the instruction set of the vrs51x570 and vrs51x580 devices. the instructions are functional and binary code compatible with industry standard 805 1s . t able 4: l egend for i nstructi on s et t able symbol function a accumulator rn register r0 - r7 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel two's complement offset byte bit direct bit address #data 8 - bit constant #data 16 16 - bit co nstant addr 16 16 - bit destination address addr 11 11 - bit destination address t able 5: vrs51 x 570 / vrs51 x 580 i nstruction s et mnemonic description size (bytes) instr. cycles arithmetic instructions add a, rn add register to a 1 1 add a, direct add direct byte to a 2 1 add a, @ri add data memory to a 1 1 add a, #data add immediate to a 2 1 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 1 addc a, @ri add data memory to a with carry 1 1 addc a, #data add immediate to a with carry 2 1 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 1 subb a, @ri subtract data mem from a with borrow 1 1 subb a, #data subtract immediate from a with borrow 2 1 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 1 inc @ri increment data memory 1 1 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 1 dec @ri decrement d ata memory 1 1 inc dptr increment data pointer 1 2 mul ab multiply a by b 1 4 div ab divide a by b 1 4 da a decimal adjust a 1 1 logical instructions anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 1 anl a, @ri and data memory to a 1 1 anl a, #data and immediate to a 2 1 anl direct, a and a to direct byte 2 1 anl direct, #data and immediate data to direct byte 3 2 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 1 orl a, @ri or data memory to a 1 1 orl a , #data or immediate to a 2 1 orl direct, a or a to direct byte 2 1 orl direct, #data or immediate data to direct byte 3 2 xrl a, rn exclusive - or register to a 1 1 xrl a, direct exclusive - or direct byte to a 2 1 xrl a, @ri exclusive - or data memory to a 1 1 xrl a, #data exclusive - or immediate to a 2 1 xrl direct, a exclusive - or a to direct byte 2 1 xrl direct, #data exclusive - or immediate to direct byte 3 2 clr a clear a 1 1 cpl a compliment a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 mnemonic description size (bytes) instr. cycles boolean instruction clr c clear carry bit 1 1 clr bit clear bit 2 1 setb c set carry bit to 1 1 1 setb bit set bit to 1 2 1 cpl c complement carry bit 1 1 cpl bit complement bit 2 1 anl c,bit logical and between carry and bit 2 2 anl c,#bit logical and between carry and not bit 2 2 orl c,bit logical orl between carry and bit 2 2 orl c,#bi t logical orl between carry and not bit 2 2 mov c,bit copy bit value into carry 2 1 mov bit,c copy carry value into bit 2 2 data transfer instructions mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 1 mov a, @ri move data memor y to a 1 1 mov a, #data move immediate to a 2 1 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 1 mov direct, a move a to direct byte 2 1 mov direct, rn move register to dire ct byte 2 2 mov direct, direct move direct byte to direct byte 3 2 mov direct, @ri move data memory to direct byte 2 2 mov direct, #data move immediate to direct byte 3 2 mov @ri, a move a to data memory 1 1 mov @ri, direct move direct byte to data me mory 2 2 mov @ri, #data move immediate to data memory 2 1 mov dptr, #data move immediate to data pointer 3 2 movc a, @a+dptr move code byte relative dptr to a 1 2 movc a, @a+pc move code byte relative pc to a 1 2 movx a, @ri move external data (a8) to a 1 2 movx a, @dptr move external data (a16) to a 1 2 movx @ri, a move a to external data (a8) 1 2 movx @dptr, a move a to external data (a16) 1 2 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchan ge a and register 1 1 xch a, direct exchange a and direct byte 2 1 xch a, @ri exchange a and data memory 1 1 xchd a, @ri exchange a and data memory nibble 1 1 branching instructions acall addr 11 absolute call to subroutine 2 2 lcall addr 16 long cal l to subroutine 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr 11 absolute jump unconditional 2 2 ljmp addr 16 long jump unconditional 3 2 sjmp rel short jump (relative address) 2 2 jc rel jump on carry = 1 2 2 jnc rel j ump on carry = 0 2 2 jb bit, rel jump on direct bit = 1 3 2 jnb bit, rel jump on direct bit = 0 3 2 jbc bit, rel jump on direct bit = 1 and clear 3 2 jmp @a+dptr jump indirect relative dptr 1 2 jz rel jump on accumulator = 0 2 2 jnz rel jump on accum ulator 1= 0 2 2 cjne a , direct, rel compare a, direct jne relative 3 2 cjne a, #d, rel compare a, immediate jne relative 3 2 cjne rn, #d, rel compare reg, immediate jne relative 3 2 cjne @ri, #d, rel compare ind, immediate jne relative 3 2 djnz rn, re l decrement register, jnz relative 2 2 djnz direct, rel decrement direct byte, jnz relative 3 2 miscellaneous instruction nop no operation 1 1 rn: any of the register r0 to r7 @ri: indirect addressing using register r0 or r1 #data: immediate data pro vided with instruction #data16: immediate data included with instruction bit: address at the bit level rel: relative address to program counter from +127 to ? 128 addr11: 11 - bit address range addr16: 16 - bit address range #d: immediate data supplied with in struction
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 6 of 49 special function registers (sfr) addresses 80h to ffh of the sfr address space can be accessed in direct addressing mode only. the following table lists the vrs51x570 and vrs51x580 special function registers. t able 6: s peci al f unction r egisters (sfr) sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - sp 81h - - - - - - - - dpl 82h - - - - - - - - dph 83h - - - - - - - - reserved 84h rcon 85h - - - - - - ram1 ram0 ******00b dbank 86h dbanke - - - dbk3 dbk2 dbk1 dbk0 0***0001b pcon 87h smod - - - gf1 gf0 pdown idle 00000000b tcon 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000b tmod 89h gate1 c/t1 m1.1 m0.1 gate0 c/t0 m1.0 m0.0 00000000b tl0 8ah - - - - - - - - tl1 8bh - - - - - - - - th0 8ch - - - - - - - - th1 8dh - - - - - - - - p1 90h - - - - - - - - wdtlock 97h 00000000b scon 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00000000b sbuf 99h - - - - - - - - pwmen 9bh pwm4e pwm3e pwm2e pwm1e pwm0e - - - 00000***b wdtcon 9fh wdte - wdclr - - wdps2 wdps1 wdps0 0*0**000b p2 a0h - - - - - - - - pwmcon a3h - - - - - - pdck1 pdck0 ******00b pwmd0 a4h pwmd0.4 pwmd0.3 pwmd0.2 pwmd0.1 pwmd0.0 np0.2 np0.1 np0.0 00000000b pwmd1 a5h pwmd1.4 pwmd 1.3 pwmd1.2 pwmd1.1 pwmd1.0 np1.2 np1.1 np1.0 00000000b pwmd2 a6h pwmd2.4 pwmd2.3 pwmd2.2 pwmd2.1 pwmd2.0 np2.2 np2.1 np2.0 00000000b pwmd3 a7h pwmd3.4 pwmd3.3 pwmd3.2 pwmd3.1 pwmd3.0 np3.2 np3.1 np3.0 00000000b ie a8h ea - et2 es et1 ex1 et0 ex0 000000 00b pwmd4 ach pwmd4.4 pwmd4.3 pwmd4.2 pwmd4.1 pwmd4.0 np4.2 np4.1 np4.0 00000000b p3 b0h - - - - - - - - ip b8h - - pt2 ps pt1 px1 pt0 px0 00000000b syscon bfh wdreset - - - - xrame alei 0*****00b t2con c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0 0000000b rcap2l cah - - - - - - - - 00000000b rcap2h cbh - - - - - - - - tl2 cch - - - - - - - - th2 cdh psw d0h cy ac f0 rs1 rs0 ov - p 00000000b p4 d8h - - - - p4.3 p4.2 p4.1 p4.0 ****1111b acc e0h - - - - - - - - b f0h - - - - - - - -
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 7 of 49 program memory structure program memory the vrs51x580 includes 64 kb of on - chip flash that can be used as general program memory. the flash memory size of the vrs51x570 is 32 kb . f igure 3: vrs51 x 580 / vrs51 x 570 i nternal p rogram m emory vrs 570 flash memory ( 32 k bytes ) 0000 h ffffh vrs 580 flash memory ( 64 k bytes ) 0000 h 7 fffh program status word register the psw register is a bit addressable that contains the status flags (cy, ac, ov, p), user flag (f0) and register bank select bits (rs1, rs0) of the 8051 processor. t able 7: p rogram s tatus w ord r egister (psw) - sfr do h 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov - p bit mnemonic description 7 cy carry bit 6 ac auxiliary carry bit from bit 3 to 4. 5 f0 user definer flag 4 rs1 r0 - r7 registers bank select bit 0 3 rs0 r0 - r7 registers bank select bit 1 2 ov overflow flag 1 - - 0 p parity flag rs1 rs0 active bank address 0 0 0 00h - 07h 0 1 1 08h - 0fh 1 0 2 10h - 17h 1 1 3 18 - 1fh data pointer the vrs51x570 and vrs51x580 have one 16 - bit data pointer (dptr) . the dptr i s accessed via two sfr addresses: dpl located at address 82h and dph located at address 83h. data memory the vrs51x580 and vrs51x570 have a total of 1k b of on - chip ram with a 256 byte subset of this block mapped as the internal memory structure of a stand ard 8052 . t he remaining 768 byte sub - block can be accessed using external memory addressing via movx instruction . f igure 4: vrs51 x 570 / vrs51 x 580 ram m emory upper 128 bytes ( i ndirect addressing only ) lower 128 bytes ( can be accessed in indirect and direct addressing mode ) sfr ( d irect addressing only ) externally mapped 768 bytes ram ( can by accessed by direct external addressing mode , using the movx instruction ) ( xrame = 1 ) 02 ff 0000 ff 80 7 f 00 by default, after reset, the externally mapped block of 768 b ytes of ram i s disabled and can be enabled by setting the xrame bit of the syscon register located at address bfh in the sfr space . lower 128 bytes (00h to 7fh, bank 0 & bank 1) the lower 128 bytes of data memory (from 00h to 7fh) is summa rized as follows : address range 00h to 7fh can be accessed in direct and indirect addressing modes. address range 00h to 1fh includes r0 - r7 registers area. address range 20h to 2fh is bit addressable. address range 30h to 7fh is not bit addressable and can be used as general - purpose storage.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 8 of 49 upper 128 bytes (80h to ffh, bank 2 & bank 3) the upper 128 bytes of the data memory ranging from 80h to ffh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. f igure 5: vrs51 x 570 / vrs51 x 580 i nternal lower 256 bytes ram s tructure registers bank 0 r7 - r0 registers bank 1 r7 - r0 registers bank 2 r7 - r0 registers bank 3 r7 - r0 80 bytes of general purpose ram 00h 08h 10h 18h 20h 07 06 05 04 03 02 01 00 0f 0e 0d 0c 0b 0a 09 08 77 76 75 74 73 72 71 70 7f 7e 7d 7c 7b 7a 79 78 30h 128 bytes of indirect access ram (sp, r0,r1) 80h 7fh ffh 2fh sfr area direct or bit access only ffh 85 84 83 82 81 80 p0 sp dpl dph expanded ram access using the movx @dptr instruction (0000 - 02ff, bank4 - bank15) the 768 bytes of the expanded ram data memory occupy addresses 0000h to 02ffh. this block can be accessed using external direct addressing (i.e. using the movx instruction) or by using bank mapping direct addressing . note that when accessing addresses above 02ffh, the vrs51x570 / vrs51x580 devices will access off - chip memory in the external memory space using the external memory control signal s . expanded ram control register the 768 bytes of expanded ram can also be accessed using the movx @rn instruction (where n = 0,1). t he scope of this instruction is limited to a data range of 256 bytes and therefore the internal ram control register rcon should be used to select which 256 byte block will be accessed ed by the movx @rn instruction ( configuring by bits ram0 and ram1 ) . the default setting of the ram1 and ram0 bits i s 00 (page 0). each page has 256 bytes. t able 8: i nternal ram c ontrol r egister (rcon) - sfr 85 h 7 6 5 4 3 2 1 0 unused ram1 ram0 bit mnemonic description 7 unused - 6 unused - 5 unused - 4 unused - 3 unused - 2 unused - 1 ram1 0 ram0 these two bits are used with rn of instruction movx @rn, n=1,0 for mapping (see section on extended 768 bytes) ram1, ram0 mapped area 00 000h - 0ffh 01 100h - 1ffh 10 200h - 2ffh 11 xy00h - xyff* * externally generated example: suppose that ram1, ram0 are set to 0 and 1 respectively and rn has a value of 45h. performing movx @rn, a , (where n is 0 or 1) allows the user to transfer the value of a to the expanded ram at address 145h (page 1). n ote that when both ram1, ram0 are set to 1, the va lue of p2 defines the upper byte and rn defines the lower byte of the external address . in this case the device will access off - chip memory in the external memory space using the external memory control signals , off chip peripherals can therefore be mappe d in to the ?p2value?00h to ?p2value?ffh address range.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 9 of 49 data bank control register the dbank register allows the user to enable the data bank select function and map the entire content of the ram memory in the range of 40h to 7fh for applications that wou ld require direct addressing of the expanded ram content. the data bank select function is activated by setting the data bank select enable bit (dbank s e) to 1 (s etting this bit to zero disables this function ) . the four least significant bits of this regis ter control the mapping of the entire 1 k byte on - chip ram space into the 40h - 7fh range. t able 9: d ata b ank c ontrol r egister (dbank) ? sfr 86 h 7 6 5 4 3 2 1 0 dbanke unused dbk3 dbk2 dbk1 dbk0 bit mnemonic description 7 dbankse d ata bank select enable bit dbanke=1, data bank select enabled dbanke=0, data bank select disabled 6 unused - 5 unused - 4 unused - 3 dbk3 2 dbk2 1 dbk1 0 dbk0 allows the mapping of the 1k ram into the 040h - 07fh ram space. w indowed access to all the 1k b on - chip ram in the range of 40h - 7fh is described in the following table. t able 10: b ank mapping direct a ddressing mode dbk3 dbk2 dbk1 bso 040h~07fh mapping address note 0 0 0 0 000h - 03fh lower 128 byte s ram 0 0 0 1 040h - 07fh lower 128 byte s ram 0 0 1 0 080h - 0bfh upper 128 byte s ram 0 0 1 1 0c0h - 0ffh upper 128 byte s ram 0 1 0 0 0000h - 003fh on - chip externally mapped 768 byte s ram 0 1 0 1 0040h - 007fh on - chip externally mapped 768 byte s ram 0 1 1 0 0080h - 00bfh on - chip ex ternally mapped 768 byte s ram 0 1 1 1 00c0h - 00ffh on - chip externally mapped 768 byte s ram 1 0 0 0 0100h - 013fh on - chip externally mapped 768 byte s ram 1 0 0 1 0140h - 017fh on - chip externally mapped 768 byte s ram 1 0 1 0 0180h - 01bfh on - chip externally map ped 768 byte s ram 1 0 1 1 01c0h - 01ffh on - chip externally mapped 768 byte s ram 1 1 0 0 0200h - 023fh on - chip externally mapped 768 byte s ram 1 1 0 1 0240h - 027fh on - chip externally mapped 768 byte s ram 1 1 1 0 0280h - 02bfh on - chip externally mapped 768 byte s ram 1 1 1 1 02c0h - 02ffh on - chip externally mapped 768 byte s ram example: user writes #55h to 203h address: mov dbank, #8ch ;set bank mapping 40h - 07fh to ;0200h - 023fh mov a, #55h ;store #55h to a mov 43h, a ;write #55h to 0203h ;address
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 10 of 49 des cription of peripherals system control register the following table describes the system control register (syscon) . the wdreset bit (7) indicates whether a reset was due to the watch dog timer overflow . when set to 1, the xrame bit allows the user to en able the on - chip expanded 768 bytes of ram. by default, upon reset, the xrame bit is set to 0. b it 0 of the syscon register is the ale output inhibit bit. setting this bit to 1 will inhibit the fosc/6 clock signal output to the ale pin. t able 11: s ystem c ontrol r egister (syscon) ? sfr bf h 7 6 5 4 3 2 1 0 wdreset unused xrame alei bit mnemonic description 7 wdreset this is the watch dog timer reset bit. it will be set to 1 when the reset signal generated by wdt overflows. 6 unus ed - 5 unused - 4 unused - 3 unused - 2 unused - 1 xrame 768 byte on - chip enable bit 0 alei ale output inhibit bit, which is used to reduce emi. power control register the vrs51x570 / vrs51x580 devices provide two power saving modes: idle and power do wn. these two modes serve to reduce the power consumption of the device. in idle mode, the processor is stopped but the oscillator continues to run. the content of the ram, i/o state and sfr registers are maintained and the timer and external interrupts ar e left operational. the processor will be woken up when an external event, triggering an interrupt, occurs. in power down mode, the oscillator and peripherals are disabled . the contents of the ram and the sfr registers, however, are maintained the mi nimum vcc in power down mode is 2v these power saving modes are controlled by the pdown and idle bits of the pcon register at address 87h. t able 12: p ower c ontrol r egister (pcon) - sfr 87 h 7 6 5 4 3 2 1 0 unused ram1 ram0 bit mnemo nic description 7 smod 1: double the baud rate of the serial port frequency that was generated by timer 1. 0: normal serial port baud rate generated by timer 1. 6 5 4 3 gf1 general purpose flag 2 gf0 general purpose flag 1 pdown power down mo de control bit 0 idle idle mode control bit
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 11 of 49 input/output ports the vrs51x570 and vrs51x580 have a total of 36 bi - directional i/o lines grouped in to four 8 - bit i/o ports and one 4 - bit i/o port. these i/os can be individually configured as input s or outpu t s . with the exception of the p0 i/os, which are of the open drain type, each i/o is made of a transistor connected to ground and a weak pull - up resistor. writing a 0 in a given i/o port bit register will activate the transistor connected to vss and br ing the i/o to a low level. writing a 1 into a given i/o port bit register de - activates the transistor between the pin and ground. in this case the pull - up resistor will bring the corresponding pin to a high level. to use a given i/o as an input, a 1 m ust be written into its associated port register bit. by default, upon reset all i/os are configured as inputs. general structure of an i/o port the following elements establish the link between the core unit and the pins of the microcontroller: special function register (same name as port) output stage amplifier (the structure of this element varies with its auxiliary function) from the following figure, one can see that the d flip - flop stores the value received from the internal bus after receiving a write signal from the core. also, note that the q output of the flip - flop can be linked to the internal bus by executing a read instruction. this is how one would read the content of the register. it is also possible to link the value of the pin to the in ternal bus. this is done by the ?read pin? instruction. in short, the user may read the value of the register or the pin. f igure 6: i nternal s tructure of o ne of the e ight i/o p ort l ines d flip-flop output stage q q ic pin read register internal bus write to register read pin structu re of the p1, p2, p3 and p4 the following figure provides a general idea of the structure of the p1, p2, p3 and p4 ports. note that the intermediary logic that connects the output of the register and the output stage together is not shown because this l ogic varies with the auxiliary function of each port. f igure 7: g eneral s tructure of the o utput s tage of p1, p2 and p3 d flip-flop q q ic pin read register internal bus write to register read pin vcc pull-up network x1 each line may be used independently as a logical input or output. when used as an input, as mentioned earlier, the corresponding port register bit must be high. structure of port 0 the internal structure of p0 is shown below. the auxiliary function of this port requires a particular logic.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 12 of 49 as opposed to the other ports, p0 is trul y bi - directional. in other words, when used as an input, it is considered to be in a floating logical state (high impedance state). this arises from the absence of the internal pull - up resistance. the pull - up resistance is actually replaced by a transistor that is only used when the port is configured to access the external memory/data bus (ea=0). when used as an i/o port, p0 acts as an open drain port and the use of an external pull - up resistor is likely to be required for most applications. f igure 8: p ort p0? s particular structu re d flip-flop q q ic pin read register internal bus write to register read pin x1 control address a0/a7 vcc when p0 is used as an external memory bus input (for a movx instruction, for example), the outputs of the register are automatically forced to 1. port p0 and p2 as addre ss and data bus the output stage may receive data from two sources the outputs of register p0 or the bus address itself multiplexed with the data bus for p0. the outputs of the p2 register or the high byte (a8 through a15) of the bus address for the p2 port. f igure 9: p2 p ort s tructure d flip-flop q q ic pin read register internal bus write to register read pin vcc pull-up network x1 control address when the ports are used as an address or data bus, the special function registers p0 and p2 are disconnected from the output stage. the 8 - bits of the p0 register are forced to 1 and the content of the p2 register remains constant. auxiliary port1 functions the port1 i/o pins are shared with the pwm outputs, timer 2 ext and t2 inputs as shown below: pin mnemonic function p1.0 t2 timer 2 counter input p1.1 t2ex time r2 auxiliary input p1.2 p1.3 pwm0 pwm0 output p1.4 pwm1 pwm1 output p1.5 pwm2 pwm2 output p1.6 pwm3 pwm3 output p1.7 pwm4 pwm4 output
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 13 of 49 auxiliary p3 port functions the port3 i/o pins are shared with the uart interface, int0 and int1 interrupts, t imer 0 and timer 1 inputs and finally the #wr and #rd lines when external memory access is performed. f igure 10: p3 p ort s tructure d flip-flop q q ic pin read register internal bus write to register read pin x1 vcc auxiliary function: input auxiliary function: output the following table describes the auxiliary function of the port 3 i /o pins. t able 13: p3 a uxiliary f unction t able pin mnemonic function p3.0 rxd serial port: receive data in asynchronous mode. input and output data in synchronous mode. p3.1 txd serial port: transmit data in asynchronous mode. output clock value in synchronous mode. p3.2 int0 external interrupt 0 timer 0 control input p3.3 int1 external interrupt 1 timer 1 control input p3.4 t0 timer 0 counter input p3.5 t1 timer 1 counter input p3.6 wr write signal for external memory p3.7 rd read signal for external memory port4 port4 has four pins and its port address is located at 0d8h. t able 14: p ort 4 (p4) - sfr d8 h 7 6 5 4 3 2 1 0 unused p4.3 p4.2 p4.1 p4.0 bit mnemonic description 7 unused - 6 unuse d - 5 unused - 4 unused - 3 p4.3 2 p4.2 1 p4.1 0 p4.0 used to output the setting to pins p4.3, p4.2, p4.1, p4.0 respectively. port4 uses the pins that n ormally appear as no - connect s (n/c) on standard 8051 b y default the port4 pin s are configure d as input s and internally pulled ? up, and therefore the vrs51x570 and vrs51x580 devices can be safely used in existing 80 c 51/80 c 52 designs where the corresponding pins have been left unconnected. in the case of an existing design where a pin corresponding to the port4 i/o is grounded, a small current will flow through the p4 pull - up resistor. in the case where those pins would be connected to vcc, care must be taken to avoid writing into the p4 register. software particularities concerning the ports s ome instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. these instructions are called read - modify - write instructions. a list of these instructions may be fo und in the table below. upon execution of these instructions, the content of the port register (at least 1 bit) is modified. the other read instructions take the present state of the input into account. for example, the instruction anl p3, #01h obtains th e value in the p3 register; performs the desired logic operation with the constant 01h, and recopies the result into the p3 register. when users want to take the present state of the inputs into
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 14 of 49 account, they must first read these states and perform an and operation between the read value and the constant. mov a, p3; state of the inputs in the accumulator anl a, #01; and operation between p3 and 01h when the port is used as an output, the register contains information on the state of the output pins. meas uring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. the functions shown below take the value of the register rather than that of the pin. t able 15: l ist of i nstructions that r ead and m odify the p ort u sing r egister v alues instruction function anl logical and ex: anl p0, a orl logical or ex: orl p2, #01110000b xrl exclusive or ex: xrl p1, a jbc jump if the bit of the port is set to 0 c pl complement one bit of the port inc increment the port register by 1 dec decrement the port register by 1 djnz decrement by 1 and jump if the result is not equal to 0 mov p., c copy the held bit c to the port clr p.x set the port bit to 0 setb p.x set the port bit to 1 port operation timing writing to a port (output) when an operation results in a modification of the content in a port register, the new value is placed at the output of the d flip - flop during the t12 period of the last machine cycle that the instruction needed to execute. it is important to note, however, that the output stage only samples the output of the registers on the p1 phase of each period. it follows that the new value only appears at the output after the t12 period of the following machine cycle. reading a port (input) the reading of an i/o pin takes place: during t9 cycle for p0, p1 during t10 cycle for p2, p3 when the ports are configured as i/os (see figure 25). in order to be sampled, the signal duration present on th e i/o inputs must be longer than fosc/12. i/o ports driving capability the maximum allowable continuous current that the device can sink on an i/o port is defined by the following maximum sink current on one given i/o 10ma maximum total sink current fo r p0 26ma maximum total sink current for p1, 2, 3 15ma maximum total sink current on all i/o 70ma on the vrs51x580 , the port4 output buffers can sink up to 20ma, allowing direct driving of led displays. it is not recommended to exceed the sink current outlined in the above table. doing so is likely to make the low - level output voltage exceed the device?s specification and it is likely to affect the device?s reliability. the vrs51x570 / vrs51x580 i/o port s are not designed to source current.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 15 of 49 timers both the vrs51x570 / vrs51x580 include three 16 - bit timers: t0, t1 and t2. the timers can operate in two specific modes: event counting mode timer mode when operating in counting mode, the counter is incremented each time an external event, such as a tra nsition in the logical state of the timer input (t0, t1, t2 input), is detected. when operating in timer mode, the counter is incremented by the microcontroller?s direct clock pulse or by a divided version of this pulse. timer 0 and timer 1 timers 0 and 1 have four modes of operation. these modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. timer 1 can also be used as a baud rate generator to generate communication freque ncies for the serial interface. timer 1 and timer 0 are configured by the tmod and tcon registers. t able 16: t imer m ode c ontrol r egister (tmod) ? sfr 89 h 7 6 5 4 3 2 1 0 gate c/t m1 m0 gate c/t m1.0 m0.0 bit mnemonic description 7 gate1 1: enables external gate control (pin int1 for counter 1). when int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on the t1in input pin. 6 c/t1 selects timer or counter operation (timer 1). 1 = a c ounter operation is performed 0 = the corresponding register will function as a timer. 5 m1.1 selects mode for timer/counter 1 4 m0.1 selects mode for timer/counter 1 3 gate0 if set, enables external gate control (pin int0 for counter 0). when int0 is h igh, and trx bit is set (see tcon register), a counter is incremented every falling edge on the t0in input pin. 2 c/t0 selects timer or counter operation (timer 0). 1 = a counter operation is performed 0 = the corresponding register will function as a ti mer. 1 m1.0 selects mode for timer/counter 0. 0 m0.0 selects mode for timer/counter 0. the table below summarizes the four modes of operation of timers 0 and 1. the timer - operating mode is selected by the bits m1 and m0 of the tmod register. t able 17: t imer /c ounter m ode d escription s ummary m1 m0 mode function 0 0 mode 0 13 - bit counter 0 1 mode 1 16 - bit counter 1 0 mode 2 8 - bit auto - reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented e very machine cycle. when tlx overflows, the value of thx is copied to tlx. 1 1 mode 3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 16 of 49 timer 0/ timer 1 counter / timer functions timing function when operating as a timer, the counter is automatic ally incremented at every system cycle (fosc/12) . a flag is raised in the event that an overflow occurs and the counter acquires a value of zero. these flags (tf0 and tf1) are located in the tcon register. t able 18: t imer 0 and 1 c ont rol r egister (tcon) ? sfr 88 h 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit mnemonic description 7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware on timer/counter overflow. cleared by hardware when pro cessor vectors to interrupt routine. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt r outine. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on or off. 3 ie1 interrupt edge flag. set by hardware when external interrupt edge is detected. cleared when interrupt processed. 2 it1 interrupt 1 type control bit. se t/cleared by software to specify falling edge/low level triggered external interrupts. 1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge is detected. cleared when interrupt processed. 0 it0 interrupt 0 type control bit. set/cleare d by software to specify falling edge/low level triggered external interrupts. counting function when operating as a counter, the timer?s register is incremented at every falling edge of the t0, t1 and t2 signals located at the input of the timer. in thi s case, the signal is sampled at the t10 phase of each machine cycle for timer 0, timer 1 and t9 for timer 2. when the sampler sees a high immediately followed by a low in the next machine cycle, the counter is incremented. two system cycles are required t o detect and record an event. this reduces the counting frequency by a factor of 24 (24 times less than the oscillator?s frequency). operating modes the user may change the operating mode by varying the m1 and m0 bits of the tmod sfr. mode 0 a schematic representation of this mode of operation can be found below in figure 1 1 . from the figure, we notice that the timer operates as an 8 - bit counter preceded by a divide - by - 32 prescaler composed of the 5lsb of tl1. the register of the counter is configured to be 13 bits long. when an overflow causes the value of the register to roll over to 0, the tfx interrupt signal goes to 1. the count value is validated as soon as trx goes to 1 and the gate bit is 0, or when intx is 1. f igure 11: t i mer /c ounter 1 m ode 0: 13 - b it c ounter clk 12 t1pin c/t =0 c/t =1 tr1 gate int1 pin 0 1 0 7 4 mode 0 mode 1 0 7 tl1 tf1 int th1 clk control mode 1 mode 1 is almost identical to mode 0. they differ in that, in mode 1, the counter uses the full 16 bits and has no prescaler. mode 2 in this mode, the register of the timer is con figured as an 8 - bit automatically re - loadable counter. in mode 2, it is the lower byte tlx that is used as the counter. in the event of a counter overflow, the tfx flag is set to 1 and the value contained in thx, which is preset by software, is reloaded in to the tlx counter. the value of thx remains unchanged.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 17 of 49 f igure 12: t imer /c ounter 1 m ode 2: 8 - bit a utomatic r eload 12 t1 pin c/t =0 c/t=1 tr1 gate 0 1 0 7 th1 clk tf1 int 0 7 int0 pin tl1 control reload mode 3 in mode 3, timer 1 is blocked as if its control bit, tr1, was set to 0. in t his mode, timer 0?s registers tl0 and th0 are configured as two separate 8 - bit counters. also, the tl0 counter uses timer 0?s control bits c/t, gate, tr0, int0, tf0 and the th0 counter is held in timer mode (counting machine cycles) and gains control over tr1 and tf1 from timer 1. at this point, th0 controls the timer 1 interrupt. f igure 13: t imer /c ounter 0 m ode 3 clk 12 t0pin c/t =0 c/t =1 tr0 gate int0 pin 0 1 0 7 tl0 tf0 clk control interrupt 0 7 th0 tf1 clk control interrupt tr1
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 18 of 49 timer 2 timer 2 of the vrs51x570 / vrs51x580 devices is a 16 - bit timer/counter. similar to timers 0 and 1, timer 2 can operate either as an event counter or as a timer. the user may switch functions by writing to the c/t2 bit located in the t2con special function register. timer 2 has three operating modes: ?auto - load? ?capture?, and ?baud r ate generator?. the t2con sfr configures the modes of operation of timer 2. the following table describes each bit in the t2con special function register. t able 19: t imer 2 c ontrol r egister (t2con) ? sfr c8 h 7 6 5 4 3 2 1 0 tf2 exf2 rc lk tclk exen2 tr2 c/t2 cp/rl2 bit mnemonic description 7 tf2 timer 2 overflow flag: set by an overflow of timer 2 and must be cleared by software. tf2 will not be set when either rclk =1 or tclk =1. 6 exf2 timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on t2ex and exen2=1. when timer 2 is enabled, exf=1 will cause the cpu to vector to the timer 2 interrupt routine. note that exf2 must be cleared by software. 5 rclk serial port receive c lock source. 1: causes serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. 0: causes timer 1 overflow to be used for the serial port receive clock. 4 tclk serial port transmit clock. 1: causes serial port to use timer 2 ove rflow pulses for its transmit clock in modes 1 and 3. 0: causes timer 1 overflow to be used for the serial port transmit clock. 3 exen2 timer 2 external mode enable. 1: allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. 0: causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2. 1: start timer 2 0: stop timer 2 1 c/t2 timer or counter select (timer 2) 1: external event counter falling edge tri ggered. 0: internal timer (osc/12) 0 cp/rl2 capture/reload select. 1: capture of timer 2 value into rcap2h, rcap2l is performed if exen2=1 and a negative transitions occurs on the t2ex pin. the capture mode requires rclk and tclk to be 0. 0: auto - relo ad reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2=1. when either rck =1 or tclk =1, this bit is ignored and the timer is forced to auto - reload on timer 2 overflow. as shown below, there are different possible combinations of control bits that may be used for the mode selection of timer 2. t able 20: t imer 2 m ode s election b its rclk + tclk cp/rl2 tr2 mode 0 0 1 16 - bit auto - reload mode 0 1 1 16 - bit capture mode 1 x 1 baud rate generator mod e x x 0 off the details of each mode are described as follows . capture mode in capture mode the exen2 bit value defines if the external transition on the t2ex pin will be able to trigger the capture of the timer value. when exen2 = 0, timer 2 acts as a 16 - bit timer or counter, which, upon overflowing, will set bit tf2 (timer 2 overflow bit). this overflow can be used to generate an interrupt. f igure 14: t imer 2 in c apture m ode f osc 12 timer counter c/t2 0 1 t2 pin tr2 t2 ex pin 0 7 0 7 0 7 0 7 timer 2 interrupt exf2 exen2 rcap2l rcap2h tl2 th2 tf2
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 19 of 49 when exen2 = 1, the above still applies. a ddition ally , it is possible to allow a 1 to 0 transition at the t2ex input to cause the current value stored in the timer 2 registers (tl2 and th2) to be captured by the rcap2l and rcap2h registers. furthermore, the transition at t2e x causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. note that both exf2 and tf2 share the same interrupt vector. auto - reload mode in this mode, there are also two options. the user may choose either option by writing to bit exen2 in t2con. if exen2 = 0, when timer 2 rolls over, it not only sets tf2, but also causes the timer 2 registers to be reloaded with the 16 - bit value in the rcap2l and rcap2h registers previously initialised. in this mode, timer 2 can be used as a bau d rate generator source for the serial port. if exen2=1, then timer 2 still performs the above operation, but a 1 to 0 transition at the external t2ex input will also trigger an anticipated reload of the timer 2 with the value stored in rcap2l, rcap2h and set exf2. f igure 15: t imer 2 in auto - reload mode f osc 12 timer counter c/t2 0 1 t2 pin tr2 t2 ex pin 0 7 0 7 0 7 0 7 timer 2 interrupt exf2 exen2 rcap2l rcap2h tl2 th2 tf2 baud rate generator mode the baud rate generator mode is activated when rclk is set to 1 and/or tclk is set to 1. this mode will be described in the se rial port section. f igure 16: t imer 2 in automatic b aud g enerator m ode f osc 2 timer counter c/t2 0 1 t2 pin tr2 t2 ex pin 0 7 0 7 0 7 0 7 exf2 exen2 rcap2l rcap2h tl2 th2 2 16 16 smod 0 1 timer 1 overflow 0 1 0 1 tclk rclk tx clock rx clock timer 2 interrupt request
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 20 of 49 serial port the serial port included in the vrs51x570 and the vrs51x580 can operate in full duplex; in other words, it can transmi t and receive data simultaneously. this occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. the serial por t receive is buffered, which means that it can begin reception of a byte even if the one previously received byte has not been retrieved from the receive register by the processor. however, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. the sbuf register provides access to the transmit and receive registers of the serial port. reading from the sbuf register will access the receive register, while a write to the sbuf loads the transmit register. serial port control register the scon (serial port control) register contains control and status information, and includes the 9 th data bit for transmit/receive (tb8/rb8 if required), mode selection bits and se rial port interrupt bits (ti and ri). t able 21: s erial p ort c ontrol r egister (scon) ? sfr 98 h 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri bit mnemonic description 7 sm0 bit to select mode of operation (see table below) 6 sm 1 bit to select mode of operation (see table below) 5 sm2 multiprocessor communication is possible in modes 2 and 3. in modes 2 or 3 if sm2 is set to 1, ri will not be activated if the received 9 th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri wil l not be activated if a valid stop bit was not received. 4 ren serial reception enable bit this bit must be set by software and cleared by software. 1: serial reception enabled 0: serial reception disabled 3 tb8 9 th data bit transmitted in modes 2 and 3 this bit must be set by software and cleared by software. 2 rb8 9 th data bit received in modes 2 and 3. in mode 1, if sm2 = 0 , rb8 is the stop bit that was received. in mode 0, this bit is not used. this bit must be cleared by software. 1 ti transmissi on interrupt flag. automatically set to 1 when: the 8 th bit has been sent in mode 0. automatically set to 1 when the stop bit has been sent in the other modes. this bit must be cleared by software. 0 ri reception interrupt flag automatically set to 1 w hen: the 8 th bit has been received in mode 0. automatically set to 1 when the stop bit has been sent in the other modes (see sm2 exception). this bit must be cleared by software. t able 22: s erial p ort m odes of o peration sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart f osc /64 or f osc /32 1 1 3 9 - bit uart variable modes of operation the vrs51x570 / vrs51x580 devices serial port can operate in four different modes. in all fou r modes, a transmission is initiated by an instruction that uses the sbuf sfr as a destination register. in mode 0, reception is initiated by setting ri to 0 and ren to 1. an incoming start bit initiates reception in the other modes provided that ren is se t to 1. the following paragraphs describe the four modes.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 21 of 49 mode 0 in this mode, the serial data exits and enters through the rxd pin. txd is used to output the shift clock. the signal is composed of 8 data bits starting with the lsb. the baud rate in this mode is 1/12 the oscillator frequency. f igure 17: s erial p ort m ode 0 b lock d iagram transmission in mode 0 any instruction that uses sbuf as a destination register may initiate a transmission. the ?write to sbuf? signal also loa ds a 1 into the 9 th position of the transmit shift register and tells the tx control block to begin a transmission. the internal timing is such that one full machine cycle will elapse between a write to sbuf instruction and the activation of send. the se nd signal enables the output of the shift register to the alternate output function line of p3.0 and enables shift clock to the alternate output function line of p3.1. shift clock is high during t11, t12 and t1, t2 and t3, t4 of every machine cycle and low during t5, t6, t7, t8, t9 and t10. at t12 of every machine cycle in which send is active and the contents of the transmit shift register are shifted to the right by one position. zeros come in from the left as data bits shift out to the right. the tx con trol block sends its final shift and deactivates send while setting t1 after one condition is fulfilled: when the msb of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9 th position is just to the lef t of the msb; and all positions to the left of that contain zeros. once these conditions are met, the deactivation of send and the setting of t1 occur at t1 of the 10 th machine cycle after the ?write to sbuf? pulse. reception in mode 0 when ren and r1 are set to 1 and 0 respectively, reception is initiated. the bits 11111110 are written to the receive shift register at t12 of the next machine cycle by the rx control unit. in the following phase, the rx control unit will activate receive. shift clock to th e alternate output function line of p3.1 is enabled by receive. at every machine cycle, shift clock makes transitions at t5 and t11. the contents of the receive shift register are shifted one position to the left at t12 of every machine in which receive is active. the value that comes in from the right is the value that was sampled at the p3.0 pin at t10 of the same machine cycle. 1?s are shifted out to the left as data bits are shifted in from the right. the rx control block is flagged to do one last shif t and load sbuf when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock shift send rx control unit ri ti 1 1 1 1 1 1 1 0 rx clock start shift receive shift register sbuf internal bus read sbuf ren ri rxd p3.0 input function rxd p3.0 txd p3.1 shift clock fosc/12 serial port interrupt shift rxd p3.0
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 22 of 49 mode 1 for an operation in mode 1, 10 bits are transmitted through txd or received through rxd. the transactions a re composed of: a start bit (low); 8 data bits (lsb first) and one stop bit (high). the reception is completed once the stop bit sets the rb8 flag in the scon register. either timer 1 or timer 2 controls the baud rate in this mode. the following diagram s hows the serial port structure when configured in mode 1. f igure 18: s erial p ort m ode 1 and 3 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 timer 2 overflow timer 1 overflow rclk tclk smod 0 1 0 1 0 1 load sbuf shift txd transmission in mode 1 transmission is initiated by any instruction that makes use of sbuf as a destination register. the 9 th bit position of the transmit shift register is loaded by the ?write to sbuf? signal. this event also flags the tx control unit that a transmission has been requested. it is after the next rollover in the divide - by - 16 count er when transmission actually begins at t1 of the machine cycle. it follows that the bit times are synchronized to the divide - by - 16 counter and not to the ?write to sbuf? signal. when a transmission begins, it places the start bit at txd. data transmissio n is activated one bit time later. this activation enables the output bit of the transmit shift register to txd. one bit time after that, the first shift pulse occurs. in this mode, zeros are clocked in from the left as data bits are shifted out to the rig ht. when the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9 th position is to the immediate left of the msb, and all positions to the left of that contain zeros. this conditi on flags the tx control unit to shift one more time. reception in mode 1 a o ne to zero transition at rxd initiate s reception. it is for this reason that rxd is sampled at a rate of 16 multiplied by the baud rate that has been established. when a transitio n is detected, 1ffh is written into the input shift register and the divide - by - 16 counter is immediately reset. the divide - by - 16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. in total, there are 16 states i n the counter. during the 7 th , 8 th and 9 th counter states of each bit time; the bit detector samples the value of rxd. the accepted value is the value that was seen in at least two of the three samples. the purpose of doing this is for noise rejection. if the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. all false start bits are rejected by doing this. if the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. for a receive operation, the data bits come in from the right as 1?s shift out on the left. as soon as the start bit arrives at the leftmost position in the shift register, (9 - bit register), it tells the rx control block to perform one last shift operation: to set ri and to load sbuf and rb8. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the fi nal shift pulse is generated: - either sm2 = 0 or the received stop bit = 1 - ri = 0
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 23 of 49 if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. if one of these conditions is not met, the received frame is comp letely lost. at this time, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition in rxd. mode 2 in mode 2 a total of 11 bits are transmitted through txd or received through rxd. the transactions are comp osed of: a start bit (low), 8 data bits (lsb first), a programmable 9 th data bit, and one stop bit (high). for transmission, the 9 th data bit comes from the tb8 bit of scon. for example, the parity bit p in the psw could be moved into tb8. in the case o f receive, the 9 th data bit is automatically written into rb8 of the scon register. in mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. f igure 19: s erial p ort m ode 2 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock control start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 fosc/2 smod 0 1 load sbuf shift txd stop sample mode 3 in mode 3, 11 bits are transmitted through txd or received through rxd. the transactions are composed of: a start bit (low), 8 data bits (lsb first), a programmable 9 th data bit, and one stop bit (high). mode 3 is identical to mod e 2 in all respects but one: the baud rate. either timer 1 or timer 2 generates the baud rate in mode 3. f igure 20: s erial p ort m ode 3 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 timer 2 overflow timer 1 overflow rclk tclk smod 0 1 0 1 0 1 load sbuf shift txd sample
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 24 of 49 mode 2 and 3: additional information as mentioned prev iously , for an operation in these modes, 11 bits are transmitted through txd or received through rxd. the signal comprises: a logical low start bit, 8 data bits (lsb first), a programmable 9 th data bit, and one logical high stop bit. on transmit, (tb8 in scon) can be assigned the value of 0 or 1. on receive; the 9 th data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from either timer 1 or ti mer 2 depending on the states of tclk and rclk. transmission in mode 2 and mode 3 the transmission is initiated by any instruction that makes use of sbuf as the destination register. the 9 th bit position of the transmit shift register is loaded by the ?w rite to sbuf? signal. this event also informs the tx control unit that a transmission has been requested. after the next rollover in the divide - by - 16 counter, a transmission actually begins at t1 of the machine cycle. it follows that the bit times are sync hronized to the divide - by - 16 counter and not to the ?write to sbuf? signal, as in the previous mode. transmissions begin when the send signal is activated, which places the start bit at txd. data is activated one bit time later. this activation enables th e output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a stop bit (1) into the 9 th bit position of the shift register to txd. thereafter, only zeros are clocked in. thus, as data bi ts shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition signals to the tx control unit to shift one more time and set ti, while de - activating send. this occurs at the 11 th divide - by - 16 rollover after ?write to sbuf?. reception in mode 2 and mode 3 one to zero transitions at rxd initiate reception. it is for this reason that rxd is sam pled at a rate of 16 multiplied by the baud rate that has been established. when a transition is detected, the 1ffh is written into the input shift register and the divide - by - 16 counter is immediately reset. during the 7 th , 8 th and 9 th counter states of each bit time; the bit detector samples the value of rxd. the accepted value is the value that was seen in at least two of the three samples. if the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. if the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. for a receive operation, the data bits come in from the right as 1?s shift o ut on the left. as soon as the start bit arrives at the leftmost position in the shift register (9 - bit register), it tells the rx control block to do one more shift, to set ri, and to load sbuf and rb8. the signal to set ri and to load sbuf and rb8 will be generated if, and only if, the following conditions are satisfied at the instance when the final shift pulse is generated: - either sm2 = 0 or the received 9 th bit is equal to 1 - ri = 0 if both conditions are met, the 9 th data bit received goes into r b8, and the first 8 data bits go into sbuf. if one of these conditions is not met, the received frame is completely lost. one bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the r xd input. please note that the value of the received stop bit is unrelated to sbuf, rb8 or ri.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 25 of 49 uart baud rates calculation in mode 0, the baud rate is fixed and can be represented by the following formula: in mode 2, the baud rate depends on t he value of the smod bit in the pcon sfr. from the formula below, we can see that if smod = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. the timer 1 and/or timer 2 overflow rate determines the baud rates in mode s 1 and 3. generating baud rate s with timer 1 when timer 1 functions as a baud rate generator, the baud rate in modes 1 and 3 are determined by the timer 1 overflow rate. timer 1 must be configured as an 8 - bit timer (tl1) with auto - reload with th1 value when an overflow occurs (mode 2). in this application, the timer 1 interrupt should be disabled. the two following formulas can be used to calculate the baud rate and the reload value to be written in to the th1 register. the value to wr ite into the th1 register is defined by the following formula: it is possible to use timer 1 in 16 - bit mode to generate the baud rate for the serial port. to do this, leave the timer 1 interrupt enabled, configure the timer to run as a 16 - bit timer (high nibble of tmod = 0001b), and use the timer 1 interrupt to perform a 16 - bit software reload. this can achieve very low baud rates. generating baud rates with timer 2 timer 2 is often preferred to generate the baud rate, as it can be easily configure d to operate as a 16 - bit timer with auto - reload . this allows for much better resolution than using timer 1 in 8 - bit auto - reload mode. the baud rate using timer 2 is defined as: the timer can be configured as either a timer or a counter in any of its 3 running modes. in most typical application, it is configured as a timer (c/t2 is set to 0). to make the timer 2 operate as a baud rate generator the tclk and rclk bits of the t2con register must be set to 1. the baud rate generator mode is simila r to the auto - reload mode in that an overflow in th2 causes the timer 2 registers to be reloaded with the 16 - bit value in registers rcap2h and rcap2l, which are preset by software. however, when timer 2 is configured as a baud rate generator, its clock sou rce is osc/2. mode 0 baud rate = oscillator frequency 12 mode 2 baud rate = 2 smod x (o scillator frequency) 64 mode 1, 3 baud rate = 2 smod x fosc 32 x 12(256 ? th1) th1 = 256 - 2 smod x fosc 32 x 12x (baud rate) mode 1, 3 baud rate = 2 smod x timer 1 overflow rate 32 mode 1, 3 baud rate = timer 2 overflow rate 16
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 26 of 49 the following formula can be used to calculate the baud rate in modes 1 and 3 using the timer 2: the formula below is used to define the reload value to put into the rcap2h, rcap2l registers to achieve a given baud rate. in th e above formula, rcap2h and rcap2l are the content of rcap2h and rcap2l taken as a 16 - bit unsigned integer. note that a rollover in th2 does not set tf2, and will not generate an interrupt and b ecause of this, the timer 2 interrupt does not have to be dis abled when timer 2 is configured in baud rate generator mode. also, if exen2 is set, a 1 - to - 0 transition in t2ex will set exf2 but will not cause a reload from rcap2x to tx2. therefore, when timer 2 is used as a baud rate generator, t2ex can be used as an extra external interrupt. furthermore, when timer 2 is running (tr2 is set to 1) as a timer in baud rate generator mode, the user should not try to read or write to th2 or tl2. when operating under these conditions, the timer is being incremented every st ate time and the results of a read or write command may be inaccurate. the rcap2 registers, however, may be read but should not be written to, because a write may overlap a reload operation and generate write and/or reload errors. in this case, before acc essing the timer 2 or rcap2 registers, be sure to turn the timer off by clearing tr2. modes 1, 3 baud rate = oscillator frequency 32x[65536 ? (rcap2h, r cap2l)] (rcap2h, rcap2l) = 65536 - fosc 32x[baud rate]
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 27 of 49 pulse width modulation (pwm) the vrs51x570 and vrs51x580 devices include a pulse width modulation (pwm) module that has five 8 - bit channels. each channel uses an 8 - bit pwm data register (pwmd) to set the number of continuous pulses within a pwm frame cycle. pwm function description each 8 - bit pwm channel is composed of an 8 - bit register that consists of a 5 - bit pwm (5 msbs) and a 3 - bit (lsbs) narrow pulse generator (np ). the 5 - bit pwm determines the duty cycle of the output. the 3 - bit npx generates and inserts narrow pulses among the pwm frame made of 8 cycles. the number of pulses generated is equal to the number programmed in to the 3 - bit np. the np is used to genera te an equivalent 8 - bit resolution pwm type dac with a reasonably high repetition rate through a 5 - bit pwm clock speed. the pdck [1:0] setting of the pwmcon (a3h) register is used to derive the pwm clock from fosc. the pwm output cycle frame re petition rate (frequency) is calculated using the following formula: pwm registers - p1 con, pwmcon, pwmr pwm registers - port1 configuration register t able 23: p ort 1 c onfiguration r egister (pwme, $9b) 7 6 5 4 pwm4e pwm 3e pwm2e pwm1e 3 2 1 0 pwm0e unused bit mnemonic description 7 pwm4e 6 pwm3e 5 pwm2e 4 pwm1e 3 pwm0e when bit is set to one, the corresponding pwm pin is active as a pwm function. when the bit is cleared, the corresponding pwm pin is active as an i/o pin. these five bits are cleared upon reset. [2:0] unused - pwm registers - pwm control register the following table describes the pwm control register signals . t able 24: pwm c ontrol r egister (pwmcon) ? sfr a3 h 7 6 5 4 3 2 1 0 unused pdck1 pdck0 bit mnemonic description [7:2] unused - 1 pdck1 input clock frequency divider bit 1 0 pdck0 input clock frequency divider bit 0 the following table describes the relationship between the values of pdck1/pdck0 and the value of the divider. numerical values of the corresponding frequencies are also provided. pdck1 pdcko divider pwm clock, fosc=12mhz pwm clock, fosc=25mhz 0 0 2 6 mhz 12.5 mhz 0 1 4 3 mhz 6.25 mhz 1 0 8 1.5 mhz 3.12 mhz 1 1 16 0.75 mhz 1.56 mhz pwm clock = f osc 2 (pdck [1:0] +1) pwm frame = f osc 32 x 2 (pdck [1:0] +1) or simply pwm frame = pwm clock 32
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 28 of 49 pwm data registers the following tables describe the pwm data register bits . the 5 most significant bits of the pwmdx registers determine the duty cycle of the pwm output waveform. the three least significant bits of the pwmdx registers control a system that will insert short pulses into the pwm frame cycle. the number of narrow pulses inserted during pwm frame cycle is proportional to the value written into the 3 least significant bit s of the pwmdx register. the net result of this system is that the a verage pwm output will have an equivalent resolution of 8 - bit s . t able 25: pwm d ata r egister 0 (pwmd0) ? sfr a4 h 7 6 5 4 pwmd0.4 pwmd0.3 pwmd0.2 pwmd0.1 3 2 1 0 pwmd0.0 np0.2 np0.1 np0.0 bit mnemonic description 7 pwmd0.4] contents of pwm data register 0 bit 4 6 pwmd0.3 contents of pwm data register 0 bit 3 5 pwmd0.2 contents of pwm data register 0 bit 2 4 pwmd0.1 contents of pwm data register 0 bit 1 3 pwmd0.0 contents of pwm data register 0 bit 0 2 np0.2 1 np0.1 0 np0.0 inserts narro w pulses in a 8 - pwm - cycle frame t able 26: pwm d ata r egister 1 (pwmd1) ? sfr a5 h 7 6 5 4 pwmd1.4 pwmd1.3 pwmd1.2 pwmd1.1 3 2 1 0 pwmd1.0 np1.2 np1.1 np1.0 bit mnemonic description 7 pwmd1.4 contents of pwm data register 1 bit 4 6 pwmd1.3 contents of pwm data register 1 bit 3 5 pwmd1.2 contents of pwm data register 1 bit 2 4 pwmd1.1 contents of pwm data register 1 bit 1 3 pwmd1.0 contents of pwm data register 1 bit 0 2 np1.2 1 np1.1 0 np1.0 inserts narrow pulses in a 8 - pwm - cycle frame t able 27: pwm d ata r egister 2 (pwmd2) ? sfr a6 h 7 6 5 4 pwmd2.4 pwmd2.3 pwmd2.2 pwmd2.1 3 2 1 0 pwmd2.0 np2.2 np2.1 np2.0 bit mnemonic description 7 pwmd2.4 contents of pwm data reg ister 2 bit 4 6 pwmd2.3 contents of pwm data register 2 bit 3 5 pwmd2.2 contents of pwm data register 2 bit 2 4 pwmd2.1 contents of pwm data register 2 bit 1 3 pwmd2.0 contents of pwm data register 2 bit 0 2 np2.2 1 np2.1 0 np2.0 inserts narrow pulses in a 8 - pwm - cycl e frame t able 28: pwm d ata r egister 3 (pwmd1) ? sfr a7 h 7 6 5 4 pwmd3.4 pwmd3.3 pwmd3.2 pwmd3.1 3 2 1 0 pwmd3.0 np3.2 np3.1 np3.0 bit mnemonic description 7 pwmd3.4 contents of pwm data register 3 bit 4 6 pwmd3.3 contents of pwm data register 3 bit 3 5 pwmd3.2 contents of pwm data register 3 bit 2 4 pwmd3.1 contents of pwm data register 3 bit 1 3 pwmd3.0 contents of pwm data register 3 bit 0 2 np3.2 1 n p3.1 0 np3.0 inserts narrow pulses in a 8 - pwm - cycle frame t able 29: pwm d ata r egister 4 (pwmd1) ? sfr ac h 7 6 5 4 pwmd4.4 pwmd4.3 pwmd4.2 pwmd4.1 3 2 1 0 pwmd4.0 np4.2 np4.1 np4.0 bit mnemonic description 7 pwmd4.4 contents of pwm data register 4 bit 4 6 pwmd4.3 contents of pwm data register 4 bit 3 5 pwmd4.2 contents of pwm data register 4 bit 2 4 pwmd4.1 contents of pwm data register 4 bit 1 3 pwmd4.0 contents of pwm data register 4 bit 0 2 np4.2 1 np4.1 0 np4. 0 inserts narrow pulses in a 8 - pwm - cycle frame the following table shows the number of extra short pulses inserted in an 8 - pwm cycles frame when we vary the np number. n = np [4:0][2:0] number of pwm cycles inserted in an 8 - cycle frame 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
vrs51x5 7 0 /580 ____________________ __________________________________________________________________________ www.ramtron.com page 29 of 49 exa mple of pwm timing mov pwmd0 #83h ; pwmd04:0]=10h (=16t high, 16t low), np02:0] = 3 mov pwme, #08h ; enable p1.3 as pwm output pin f igure 21: pwm t iming d iagram 32t 32t 32t 32t 32t 32t 32t 32t 1t 1t 1t 16 16 16 16 16 1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame 6th cycle frame 7th cycle frame 8th cycle frame (narrow pulse inserted by np0[2:0]=3) spwm clock= 1/t= fosc / 2^(pdck+1) the spwm output cycle frame frequency = spwm clock/32 = [fosc/2^(pdck+1)]/32 if fosc = 20mhz, pdck[1:0] of spwwc = #03h, then pwm clock = 20mhz/2^4 = 20mhz/16 = 1.25mhz. pwm output cycle frame frequency = (20mhz/2^4)/32 = 39.1 khz.
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 30 of 49 interrupts the vrs51x570 and vrs51x580 have 8 interrupt sources (9 if we include the wdt) and 7 interrupt vectors (including reset) used for handl ing . the interrupt s are enabled via the ie register shown below: t able 30: ien0 i nterrupt e nable r egister ? sfr a8 h 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit mnemonic description 7 ea disables all interrupts 0: n o interrupt acknowledgment 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit. 6 - reserved 5 et2 timer 2 interrupt enable bit 4 es serial port interrupt enable bit 3 et1 timer 1 interrupt enable bit 2 ex1 external interrupt 1 enable bit 1 et0 timer 0 interrupt enable bit 0 ex0 external interrupt 0 enable bit the following figure illustrates the various interrupt sources on the vrs51x570 / vrs51x580 . f igure 22: i nterrupt s ou rces ie0 it0 int0 tf0 ie1 it1 int1 tf1 t1 ri tf2 exf2 interrupt sources interrupt vectors the following table specifies each interrupt source, its flag and its vector address. t able 31: i nterrupt v ector c orresponding f lags ans v ector a ddress interrupt source flag vector address reset (+ wdt) wdreset 0000h int0 ie0 0003h timer 0 tf0 000bh int1 ie1 0013h timer 1 tf1 001bh serial port ri+ti 0023h timer 2 tf2+exf2 002bh external interrupts the vrs51x570 and vrs51x580 have two external interrupt inputs ( int0 and int1 ) . these interrupt lines are shared with p3.2 and p3.3. the bits it0 and it1 of the tcon register determine whether the external interrupts are level or edge sensitive. if itx = 1, the interrupt will be raised when a 1 to 0 transition occurs at the in terrupt pin. for the interrupt to be noticed by the processor the duration of the sum high and low condition must be at least equal to 12 oscillator cycles. if itx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. the state of the external interrupt, when enabled, can be monitored using the flags, ie0 and ie1 of the tcon register that are set when the interrupt condition occurs. in the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. if the interrupt is configured as level sensitive, then the interrupt flag must be cleared by the software.
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 31 of 49 timer 0 and timer 1 interrupt both timer 0 and timer 1 can be configured to generate an i nterrupt when a rollover of the timer/counter occurs (except timer 0 in mode 3). the tf0 and tf1 flags serve to monitor timer overflow occurring from timer 0 and timer 1. these interrupt flags are automatically cleared when the interrupt is serviced. tim er 2 interrupt a timer 2 interrupt can occur if tf2 and/or exf2 flags are set to 1 and if the timer 2 interrupt is enabled. the tf2 flag is set when a rollover of the timer 2 counter/timer occurs. the exf2 flag can be set by a 1 to 0 transition on the t2ex pin by the software. note that neither flag is cleared by the hardware upon execution of the interrupt service routine. the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt. these flag bits will have to be cleared by the software. every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. in other words, pending interrupts can be cancelled and interrupts can be g enerated by the software. serial port interrupt the serial port can generate an interrupt upon byte reception or once the byte transmission is completed. those two conditions share the same interrupt vector and it is up to the user developed interrupt s ervice routine software to ascertain the cause of the interrupt by looking at the serial interrupt flags ri and ti. note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. the software must clear these flags. execution of an interrupt when the processor receives an interrupt request, an automatic jump to the desired subroutine occurs. this jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address o f the next instruction on the stack. an internal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. an interrupt subroutine must always end with the reti instruction. this instruction allows users to retri eve the return address placed on the stack. the reti instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. interrupt enable and interrupt priority when the vrs51x570 / vrs51x580 device is initialized, all interrupt sources are inhibited by the bits of the ie register being reset to 0. it is necessary to start by enabling the interrupt sources that the application requires. this is achieved by setting bits in the ie register, as discussed pr eviously. this register is part of the bit addressable internal ram. for this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. all interrupts can be inhibited by setting ea to 0. the order in which interrupts are serviced is shown in the following table: t able 32: i nterrupt n atural p riority interrupt source reset + wdt (highest priority) ie0 tf0 ie1 tf1 ri+ti tf2+exf2 (lowest priority)
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 32 of 49 modif ying the interrupt order of priority the vrs51x570 / vrs51x580 devices allows the user to modify the natural priority of the interrupts. one may modify the order by programming the bits in the ip (interrupt priority) register. when any bit in this register is set to 1, it gives the corresponding source a greater priority than interrupts coming from sources that don?t have their corresponding ip bit set to 1. the ip register is represented in the table below. t able 33: ip i nterrupt p rior ity r egister ? sfr b8 h 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit mnemonic description 7 - 6 - 5 pt2 gives timer 2 interrupt higher priority 4 ps gives serial port interrupt higher priority 3 pt1 gives timer 1 interrupt higher priority 2 px1 gives int1 interrupt higher priority 1 pt0 gives timer 0 interrupt higher priority 0 px0 gives int0 interrupt higher priority watch dog timer the watch dog timer (wdt) is a 16 - bit free - running counter that generates a reset signal if the counter ov erflows. the wdt is useful for systems that are susceptible to noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways. the wdt function gives the user software a recovery mechanism from abnormal so ftware conditions. the watch dog timer of the vrs51x570 and vrs51x580 devices is driven by an auxiliary rc oscillator having an operating frequency of about 250khz. this makes the wdt operation independent of the processor oscillator operation. to enable the wdt, the user must set bit 7 (wdte) of the wdtcon register to 1. once wdte has been set to 1, the 16 - bit counter will start to count with the selected time base source clock configured in wdps2~wdps0. the watch dog timer will generate a reset signal i f an overflow has taken place. the wdte bit will be cleared to 0 automatically when the device is reset by either the hardware or a wdt reset. once the wdt is enabled, the user software must clear it periodically. in the case where the wdt is not cleared , its overflow will trigger a reset of the device. the user should check the wdreset bit of the syscon register whenever an unpredicted reset has taken place. the wdt timeout delay can be adjusted by configuring the clock divider input for the time base so urce clock of the wdt. to select the divider value, bit2 - bit0 (wdps2~wdps0) of the watch dog timer control register (wdtcon) should be set accordingly. clearing the wdt is accomplished by setting the clr bit of the wdtcon to 1. this action will clear the c ontents of the 16 - bit counter and force it to restart. watch dog timer registers three registers of the vrs51x570 / vrs51x580 devices are associated with the watch dog timer: wdtcon, the wdtlock and the syscon registers. the wdtcon register allows the user t o enable the wdt, to clear the counter and to divide the clock source. the wdreset bit of the syscon register indicates whether the watch dog timer has caused the device reset. t able 34: w atchdog t imer r egisters : wdtcon ? sfr 9f h 7 6 5 4 3 2 1 0 wdte unused wdclr unused wdtps [2:0] bit mnemonic description 7 wdte watch dog timer enable bit 6 unused - 5 wdclr watch dog timer counter clear bit [4:3] unused - 2 1 0 wdps [2:0] watchdog timer clock source divider
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 33 of 49 the tab le below provides examples of watch dog timeout period s the user will obtain for different values of the wdpsx bits of the watch dog timer register. t able 35: w atch d og t imer period vs . wdwdps [2:0] bit wdps [2:0] wdt timeout (ms) 0 00 2 001 4.1 010 8.2 011 16.4 100 32.7 101 65.5 110 131 111 262 accessing the wdtcon register by default and as a protection feature, the wdtcon register is read only. this feature is in place to prevent inadvertent ly writing to this register. the wdtlock register is located at sfr address 97h. in order to be able to perform a write operation to the wdtcon register, two consecutive write operations to the wdtlock register must first be performe d. . t able 36: w atchdog t imer l ock r egisters : wdtlock ? sfr 97 h 7 6 5 4 3 2 1 0 wdtlock [7:0] to enable write operations into the wdtcon register: you must perform the two following operations: mov wdtlock, #01eh mov wdtlock, #0e1h ?at this point, write operations are allowed t o the wdtcon register such as watch dog timer configuration or watch dog timer clear operations. to disable any further write operations to the wdtcon register, you must then perform the two following operations: mov wdtlock, #0e1h mov wdtlock, #01eh the system control register the system control register is used to monitor the status of the watch dog timer, enabling the operation of the 768 bytes of expanded ram and inhibiting the address latch enable signal output. t able 37: t he s ystem c ontrol r egister (syscon) ? sfr bf h 7 6 5 4 3 2 1 0 wdreset unused xrame alei bit mnemonic description 7 wdreset watch dog timer reset status bit [6:3] unused - 2 unused - 1 xrame 0 alei 1: enable electromagnetic interference reducer 0: d isable electromagnetic interference reducer the wdreset bit of the syscon register is the watch dog timer reset bit. it will be set to 1 when a reset signal is generated by the wdt overflow. the user should check the wdreset bit state if a reset has taken place in application where the watchdog timer is activated reduced emi function the vrs51x570 and vrs51x580 devices can also be set up to reduce its emi (electromagnetic interference) by setting bit 0 (alei) of the syscon register to 1. this function will inhibit the fosc/6hz clock signal output to the ale pin.
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 34 of 49 crystal consideration the crystal connected to the vrs51x570 / vrs51x580 oscillator input should be of a parallel type, operating in fundamental mode. the following table shows the value of capaci tors and feedback resistor that must be used at different operating frequencies. xtal 3mhz 6mhz 12mhz 16mhz 25mhz c1 30 pf 30 pf 30 pf 30 pf 15 pf c2 30 pf 30 pf 30 pf 30 pf 15 pf r open open open open 62ko note: oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. crystals or ceramic resonator characteristics vary from one manufacturer to the other. the user should check the specific crystal or ceramic resonator technical literature available or contact the manufacturer to select the appropriate values for the external components. vrs 51 x 570 vrs 51 x 580 xtal 1 xtal 2 xtal r c 1 c 2
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 35 of 49 operating conditions t able 38: o perating c onditions symbol description min. typ. max. unit remarks ta operating temperature - 40 25 85 oc ambient temperature operating ts storage temperature - 55 25 155 oc vcc5v supply voltage 4.5 5.0 5.5 v 5 volts devices vcc3v supply voltage 3.0 3.3 3.6 v 3.3 volts devices 25 mhz for 5v & 3.3v application dc characteristics t able 39: dc c haracteristics a mbient t emperature = - 40c to 85c, 3.0v to 5.5v symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0 ,1,2,3,4,#ea - 0.5 0.8 v vil2 input low voltage res, xtal1 0 0 . 8 v vih1 input high voltage port 0,1,2,3,4,#ea 2.0 vcc+0.5 v vi h2 input high voltage res, xtal1 70% vcc vcc+0.5 v vol1 output low voltage port 0, ale, #psen 0.45 v iol=3.2ma vol2 output low voltage port 1,2,3,4 0.45 v iol=1.6ma 2.4 v ioh= - 800ua (vcc = 5v) voh1 output high voltage port 0 90% vcc v ioh= - 80ua 2.4 v ioh= - 60ua (vcc = 5v) voh2 output high voltage port 1,2,3,4,ale,#psen 90% vcc v ioh= - 10ua iil logical 0 input current port 1,2,3,4 - 75 ua vin=0.45v itl logical transition current port 1,2,3,4 - 650 ua vin=2.ov ili input leakage current port 0, #ea + 10 ua 0.45v vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 36 of 49 ac characteristics t able 40: ac c haracteristics fosc 16 variable fosc symbol parameter valid c ycle min. type max. min. type max. unit t lhll ale pulse width rd/wrt 115 2xt - 10 ns t avll address valid to ale low rd/wrt 43 t - 20 ns t llax address hold after ale low rd/wrt 53 t - 10 ns t lliv ale low to valid instruction in rd 240 4xt - 10 ns t llpl ale low to #psen low rd 53 t - 10 ns t plph #psen pulse width rd 173 3xt - 15 ns t pliv #psen low to valid instruction in rd 177 3xt - 10 ns t pxix instruction hold after #psen rd 0 0 ns t pxiz instruction float after #psen rd 87 t + 25 ns t avi v address to valid instruction in rd 292 5xt - 20 ns t plaz #psen low to address float rd 10 10 ns t rlrh #rd pulse width rd 365 6xt - 10 ns t wlwh #wr pulse width wrt 365 6xt - 10 ns t rldv #rd low to valid data in rd 302 5xt - 10 ns t rhdx data hold after #rd rd 0 0 ns t rhdz data float after #rd rd 145 2xt + 20 ns t lldv ale low to valid data in rd 590 8xt - 10 ns t avdv address to valid d ata in rd 542 9xt - 20 ns t llyl ale low to #wr high or #rd low rd/wrt 178 197 3xt - 10 3xt + 10 ns t avyl address valid to #wr or #rd low rd/wrt 230 4xt - 20 ns t qvwh data valid to #wr high wrt 403 7xt - 35 ns t qvwx data valid to #wr transition wrt 38 t - 25 ns t whqx data hold after #wr wrt 73 t + 10 ns t rlaz #rd low to address float rd 5 ns t yalh #w r or #rd high to ale high rd/wrt 53 72 t - 10 t+10 ns t chcl clock fall time ns t clcx clock low time ns t clch clock rise time ns t chcx clock high time ns t,tc lcl clock period 63 1/fosc ns
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 37 of 49 data memory read cycle timing the following timing diagram shows what occurs at each signal during a data memory read cycle. f igu re 25: d ata m emory r ead c ycle t iming t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #rd port2 port0 address a15-a8 inst in a7-a0 float data in float address or float 7 8 1 2 5 3 3 4 6 float
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 38 of 49 program memory read cycle timing the following timing diagram shows what occurs at each signal during a program memory read cycle. f igure 26: p rogram m emory r ead c ycle t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #rd,#wr port2 port0 float a7-a0 float float float float a7-a0 inst in inst in address a15-a8 address a15-a8 1 2 5 7 3 3 4 6 8
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 39 of 49 data memory write cycle timing the following timing diagram shows what occurs at each signal during a data memory write cycle. f igure 27: d ata m emory w rite c ycle t iming t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #wr port2 port0 address a15-a8 inst in a7-a0 data out address or float 1 5 float 2 2 3 6 4
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 40 of 49 i/o port timing the following timing diagram shows what occurs during i/o port timing. f igure 28: i/o p orts t iming t7 t8 t9 t10 t11 t12 t1 t2 t3 t4 t5 t6 t7 t8 sampled sampled sampled current data next data x1 inputs p0,p1 inputs p2,p3 output by mov px, src rxd at serial port shift clock mode 0
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 41 of 49 external clock timing f igure 29: t iming r equirement of e xternal c lock (vss= 0.0v is assumed ) tclcl tchcx tclch tchcl tclcx 70% vdd 20% vdd-0.1v vdd - 0.5v 0.45v external program memory read cycle the following timing diagram shows what occurs at each signal during an external program memory read cycle. f igure 30: e xternal p rogram m emory r ead c ycle tplph tpxix tpxiz instruction in a0-a7 a8-a15 p2.0-p2.7 or ab-a15 from dph a0-a7 tllpl tlhll tavll tllax tplaz tpliv taviv #psen ale port 0 port2
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 42 of 49 external data memory read cycle the following timing diagram shows what occurs at each signal during an external data memory read cycle. f igure 31: e xternal d ata m emory r ead c ycle tlldv tllyl trlrh trlaz a0-a7 from ri or dpl tavll tllax tavyl tavdv p2.0-p2.7 or a8 -a15 from dph a8-a15 from pch data in trhdx trhdz a0-a7 from pcl instrl in trldv tyhlh #psen ale #rd port 0 port 2
vrs51x5 7 0 /580 _______________________________________________________________________________________ _______ www.ramtron.com page 43 of 49 external data memory write cycle the following timing diagram shows what occurs at each signal during an external data memory write cycle. f igure 32: e xternal d ata m emory w rite c ycle #psen twlwh tllyl tlhll tavll tllax tqvwx tqvwh twhqx tyhlh tavyl ale #wr port 0 port 2 p2.0-p2.7 or a8-a15 from dph data out a0-a7 from ri or dpl a8-a15 from pch a0-a7 from pcl instrl in . plastic chip carrier (plcc)
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 44 of 4 9 vrs 51 x 570 vrs 51 x 580 plcc - 44 d hd e he gd e c b1 b note: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion /intrusion. 3. controlling dimension: inch 4. general appearance spec should be based on final visual inspection spec.
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 45 of 49 ge y a2 a1 a l t able 41: d imensions of plcc - 44 c hip c arrier dimension in inch dimens ion in mm symbol minimal/maximal minimal/maximal a - /0.185 - /4.70 al 0.020/ - 0.51/ a2 0.145/0.155 3.68/3.94 bl 0.026/0.032 0.66/0.81 b 0.016/0.022 0.41/0.56 c 0.008/0.014 0.20/0.36 d 0.648/0.658 16.46/16.71 e 0.648/0.658 16.46/16.71 e 0.050 bsc 1. 27 bsc gd 0.590/0.630 14.99/16.00 ge 0.590/0.630 14.99/16.00 hd 0.680/0.700 17.27/17.78 he 0.680/0.700 17.27/17.78 l 0.090/0.110 2.29/2.79 ? - /0.004 - /0.10 ?y / /
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 46 of 49 quad flat package (qfp) vrs 5 1 x 570 vrs 51 x 580 qfp - 44 e 2 e 1 e d 2 d 1 d e seating plane c e1 note: 1. dimensions d1 and e1 do not include mold protrusion. 2. allowance protrusion is 0.25mm per side. 3. dimensions d1 and e1 do not include mold mismatch and are determined datum plane. 4. dimension b does not include dambar protrusion. 5. allowance dambar protru sion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the lead foot. 3 gage plane 0.25mm r1 2 r2
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 47 of 49 l c l1 s s b a a1 a2 t able 42: d imensions of qfp - 44 c hip c arrier d imension in in. dimension in mm symbol minimal/maximal minimal/maximal a - /0.100 - /2.55 al 0.006/0.014 0.15/0.35 a2 0.071 / 0.087 1.80/2.20 b 0.012/0.018 0.30/0.45 c 0.004 / 0.009 0.09/0.20 d 0.520 bsc 13.20 bsc d1 0.394 bsc 10.00 bsc d2 0.315 8.0 0 e 0.520 bsc 13.20 bsc e1 0.394 bsc 10.00 bsc e2 0.315 8.00 e 0.031 bsc 0.80 bsc l 0.029 / 0.041 0.73/1.03 l1 0.063 1.60 r1 0.005/ - 0.13/ - r2 0.005/0.012 0.13/0.30 s 0.008/ - 0.20/ - 0 0 /7 as left ? 1 0 / - as left ? 2 10 ref as left ? 3 7 ref as left ?c 0.004 0.10
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 48 of 49 ordering information device number structure vrs51x570 ordering options device number flash size ram size package option voltage temperature frequency VRS51C570 - 40 - l 32kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - l 32kb 1kb plcc - 44 3.0v to 3.6v - 40c to +85c 25mhz VRS51C570 - 40 - q 32kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - q 32kb 1kb qfp - 44 3 .0v to 3.6v - 40c to +85c 25mhz VRS51C570 - 40 - p 32kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - p 32kb 1kb dip - 40 3.0v to 3.6v - 40c to +85c 25mhz VRS51C570 - 40 - lg 32kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - lg 32kb 1 kb plcc - 44 3.0v to 3.6v - 40c to +85c 25mhz VRS51C570 - 40 - qg 32kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - qg 32kb 1kb qfp - 44 3.0v to 3.6v - 40c to +85c 25mhz VRS51C570 - 40 - pg 32kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz vrs51l570 - 25 - pg 32kb 1kb dip - 40 3.0v to 3.6v - 40c to +85c 25mhz
vrs51x5 7 0 /580 ______________________________________________________________________________________________ www.ramtron.com page 49 of 49 vrs51x580 ordering options device number flash size ram size package option voltage temperature frequency vrs51c580 - 40 - l 64kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 25 - l 64kb 1kb plcc - 44 3.0v to 3.6v - 40c to +85c 25mhz vrs51c580 - 40 - q 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 25 - q 64kb 1kb qfp - 44 3.0v to 3.6v - 40c to +85c 25mhz vrs51c580 - 40 - p 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 2 5 - p 64kb 1kb dip - 40 3.0v to 3.6v - 40c to +85c 25mhz vrs51c580 - 40 - lg 64kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 25 - lg 64kb 1kb plcc - 44 3.0v to 3.6v - 40c to +85c 25mhz vrs51c580 - 40 - qg 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 25 - qg 64kb 1kb qfp - 44 3.0v to 3.6v - 40c to +85c 25mhz vrs51c580 - 40 - pg 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz vrs51l580 - 25 - pg 64kb 1kb dip - 40 3.0v to 3.6v - 40c to +85c 25mhz disclaimers r ight to make change - ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. customers should obtain the most current and relevant information before placing orders. use in applications - ramtron assumes no responsi bility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. customers are responsible for product design and applications using ramtron parts. ramtron assumes no liability for applications assistance or customer product design. life support ? ramtron products are not designed for use in life support systems or devices. ramtron customers using or selling ramtron products for use in such applications do so at their own risk and agree to fully indemnify ramtron for any damages resulting from such applications

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