h anbit hm d4m144d9wg url:www.hbe.co.kr - 1 - hanbit electronics co.,lt d. rev.1.0.(august.2002) general description the HMD4M144D9WG is a 4mbit x 144bit dynamic ram high - density memory module. the module consists of eight cmos 4mx16bit drams in 50 - pin tsop packages and one cmos 4m x 16bit dram in 50pin tsop package mounted on a 200 - pin, d ouble - sided, fr - 4 - printed circuit board. a 0.1uf or 4.7uf decoupling capacitor is mounted on the printed circuit board for each dram components. the module is a dual in - line memory module with edge connections and is intended for mounting in to 200 - pin edg e connector sockets. all module components may be powered from a single 5v dc power supply and all inputs and outputs are ttl - compatible. features option s marking w access times : 50, 60 ns w timing w high - density 64mbyte design 50ns access - 5 w part identification 60ns access - 6 - HMD4M144D9WG (4k cycles/64ms ref, gold) w packages w single +5v 0.5v power supply 200 - pin dimm d w jedec standard pinout w ecc mode operation w ttl compatible inputs and output performance range speed t rac t cac t rc t pc - 5 50ns 13ns 90ns 35ns - 6 60ns 15ns 110ns 40ns pin names pin name function pin name function pin name function ba0 - ba11 address input bras row address strobe vss ground dq0 - dq143 data in/out bcas1,bcas2 column address strobe nc no connection bw e read/write enable vcc powe r(+5v) 64mbyte(4mx144) 200 - pin ecc m ode 4k ref. dimm design 5v part no. hm d4m144d9wg
h anbit hm d4m144d9wg url:www.hbe.co.kr - 2 - hanbit electronics co.,lt d. rev.1.0.(august.2002) pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vss 35 dq1 4 69 dq2 9 101 vss 135 vss 169 dq94 2 vss 36 dq50 70 dq 65 102 vss 136 vss 170 dq130 3 dq0 37 dq15 71 dq30 103 b a6 137 dq80 171 dq95 4 dq 36 38 dq51 72 dq66 104 ba7 138 dq 116 172 dq131 5 dq1 39 dq16 73 d q31 105 ba8 139 dq81 173 dq96 6 dq37 40 dq52 74 dq67 106 ba9 140 dq117 174 dq132 7 dq2 41 dq17 75 dq32 107 ba10 141 d q 8 2 175 dq97 8 dq38 42 dq53 76 dq68 108 ba11 142 dq118 176 dq133 9 dq3 43 dq18 77 dq33 109 nc 143 dq83 177 dq98 10 dq39 44 dq54 78 dq69 110 / b we 144 dq119 178 dq134 11 dq4 45 dq19 79 d q34 111 nc 145 dq84 179 dq99 12 dq40 46 dq55 80 dq70 112 nc 146 dq120 180 dq135 13 dq5 47 dq20 81 vcc 113 vss 147 dq85 181 dq100 14 dq41 48 dq56 82 vcc 11 4 vss 148 dq121 182 dq136 15 dq6 49 vcc 83 d q35 115 vss 149 dq86 183 vcc 16 dq42 50 vcc 84 dq71 116 vss 150 dq122 184 vcc 17 vcc 51 dq21 85 /bcas1 117 d q 7 2 151 vcc 185 dq101 18 vcc 52 dq57 86 /bcas2 118 d q 1 08 152 vcc 186 dq137 19 dq 7 53 dq22 87 / bras 119 vcc 153 dq8 7 187 dq102 20 dq 43 54 dq58 88 nc 120 vcc 154 dq 123 188 dq138 21 dq8 55 dq23 89 nc 121 dq73 155 d q 8 8 189 dq103 22 dq44 56 dq59 90 nc 122 dq109 156 dq124 190 dq139 23 dq9 57 dq24 91 nc 123 dq74 157 dq89 191 dq104 24 dq45 58 dq 60 92 nc 12 4 dq110 158 dq125 192 dq140 25 dq10 59 dq25 93 ba0 125 dq75 159 dq90 193 dq105 26 dq46 60 dq61 94 ba1 126 dq111 160 dq126 194 dq141 27 dq11 61 dq26 95 ba2 127 dq76 161 dq91 195 dq106 28 dq47 62 dq62 96 ba3 128 dq112 162 dq127 196 dq142 29 dq12 63 dq27 97 ba4 129 dq77 163 dq92 197 dq107 30 dq48 64 dq63 98 ba5 130 dq113 164 dq128 198 dq143 31 dq13 65 vss 99 vss 131 dq78 165 dq93 199 vss 32 dq 49 66 vss 100 vss 132 dq114 166 dq129 200 vss 33 vss 67 dq2 8 133 dq79 167 vss 34 vss 68 dq64 134 dq115 168 vss p in assignment 200pin dimm top view
h anbit hm d4m144d9wg url:www.hbe.co.kr - 3 - hanbit electronics co.,lt d. rev.1.0.(august.2002) functional block dia gram dq0 - dq15 dq16 - dq31 dq32 - dq47 dq48 - dq63 dq64 - dq79 dq80 - dq95 dq96 - dq111 dq112 - dq127 dq128 - dq143 /cas /ras dq0 - 15 /oe w a0 - a11 u 1 /cas /ras dq16 - 32 /oe w a0 - a11 u 2 /cas /ras dq32 - 47 /oe w a0 - a11 u 10 /cas /ras dq48 - 63 /oe w a0 - a11 u 9 /cas /ras dq80 - 95 /oe w a0 - a11 u4 /cas /ras dq96 - 111 /oe w a0 - a11 u5 /cas /ras dq112 - 127 /oe w a0 - a11 u 7 /cas /ras dq128 - 143 /oe w a0 - a11 u 6 /cas1 /cas2 /ras dq63 - 79 /oe w a0 - a11 u 3 /cas2 /ras / cas1 a0 - a11 vcc vss 0.1uf or 4.7uf capacitor for each dram /we
h anbit hm d4m144d9wg url:www.hbe.co.kr - 4 - hanbit electronics co.,lt d. rev.1.0.(august.2002) absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 9 w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as deta iled in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics symbol speed min max units - 5 - 396 ma i cc1 - 6 - 366 ma i cc2 don't care - 12 ma - 5 - 396 ma i cc3 - 6 - 366 ma - 5 - 396 ma i cc4 - 6 - 366 ma i cc5 don't care - 6 ma - 5 - 990 ma i cc6 - 6 - 900 ma 74fct162244 a /ras /cas1 /cas2 /we /ba /bras /bcas1 /bcas2 /bw e
h anbit hm d4m144d9wg url:www.hbe.co.kr - 5 - hanbit electronics co.,lt d. rev.1.0.(august.2002) i l(l) - 60 40 m a i o(l) - 5 5 m a v oh 2.4 - v v ol - 0.4 v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current (/ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note: i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a11 ) c in1 - 65 pf input capacitance (/w e ) c in2 - 80 pf input capacitance (/ras0) c in3 - 50 pf input capacitance (/cas1 - /cas2) c in4 - 40 pf input/output capacitance (dq0 - 31) c dq1 - 20 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1 ,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 110 130 ns access time from /ras t rac 50 60 ns access time from /cas t cac 15 20 ns access time from column address t aa 30 35 ns /cas to output in low - z t clz 0 0 ns output buffer turn - off delay t off 0 15 0 20 ns transition time (rise and fall) t t 3 50 3 50 ns
h anbit hm d4m144d9wg url:www.hbe.co.kr - 6 - hanbit electronics co.,lt d. rev.1.0.(august.2002) /ras precharge time t rp 40 50 ns /ras pulse width t ras 60 10k 70 10k ns /ras hold time t rsh 15 20 ns /cas hold time t csh 60 70 n s /cas pulse width t cas 15 10k 20 10k ns /ras to /cas delay time t rcd 20 45 20 50 ns /ras to column address delay time t rad 15 30 15 35 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 15 15 ns column address hold referenced to /ras t ar 50 55 ns column address to /ras lead time t ral 30 35 ns read command set - up time t rcs 0 0 ns read command hold r eferenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 15 15 ns write command hold referenced to /ras t wcr 50 55 ns write command pulse width t wp 15 15 ns write command to /ras lead time t rwl 15 20 ns write command to /cas lead time t cwl 15 20 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 15 15 ns data - in hold referenced to /ras t dhr 50 55 ns refresh period t ref 16 16 ns write command set - up time t wcs 0 0 ns / cas setup time (c - b - r refresh) t csr 10 10 ns
h anbit hm d4m144d9wg url:www.hbe.co.kr - 7 - hanbit electronics co.,lt d. rev.1.0.(august.2002) /cas hold time (c - b - r refresh) t chr 15 15 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 35 40 ns fast page mode cycle time t pc 40 45 ns /cas precharge time ( fast page) t cp 10 10 ns /ras pulse width (fast page ) t rasp 60 100k 70 100k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 30 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition tim es are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference po int only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd anf t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early wr ite cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the cas leading edge in early write cycles and to the w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa .
h anbit hm d4m144d9wg url:www.hbe.co.kr - 8 - hanbit electronics co.,lt d. rev.1.0.(august.2002) 0.25 mm max min 2.54 mm 1.27 gold : 1.04 0. 10 mm solder:0.914 0.10mm packaging informatio n o r dering information part number density org. package component number vcc mode speed HMD4M144D9WG - 5 64mbyte x 144 200 pin - dmm 9ea 5v ecc 50ns hmd4m14 4d9wg - 6 64mbyte x 144 200 pin - dimm 9ea 5v ecc 60ns max 7.68 mm 1.29 0.08 mm 10.25 mm 143.60 mm 130.81 6.35 mm r1.57 10 mm 6.39 mm 2. 05 18.52 mm 6.45 mm 136.70 mm r1.57 mm r 3.18 051 3.45 mm
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