Part Number Hot Search : 
RF081 SDA294D STPS8L30 S18LA ST16600 MAX8563 080207R0 3SK0270
Product Description
Full Text Search
 

To Download NTD4404N Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
  ? semiconductor components industries, llc, 2004 december, 2004 ? rev. 5 1 publication order number: NTD4404N/d NTD4404N power mosfet 85 amps, 24 volts n-channel dpak features ? planar hd3e process for fast switching performance ? low r ds(on) to minimize conduction loss ? low c iss to minimize driver loss ? low gate charge ? pb?free packages are available maximum ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain?to?source voltage v dss 24 v dc gate?to?source voltage ? continuous v gs 20 v dc thermal resistance ? junction?to?case total power dissipation @ t c = 25 c drain current ? continuous @ t c = 25 c, limited by package ? continuous @ t a = 25 c, limited by wires ? single pulse (t p 10  s) r  jc p d i d i d i dm 1.6 78.1 85 32 96 c/w w a a a thermal resistance, junction?to?ambient (note 1) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r  ja p d i d 52 2.4 16 c/w w a thermal resistance, junction?to?ambient (note 2) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r  ja p d i d 100 1.25 12 c/w w a operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 23 v dc , v gs = 10 v dc , i l = 13.4 a pk , l = 1 mh, r g = 25  ) e as 90 mj maximum lead temperature for soldering purposes, 1/8 in from case for 10 seconds t l 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. when surface mounted to an fr4 board using 1 inch pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using minimum recommended pad size, (cu area 0.412 in 2 ). 85 amperes, 24 volts r ds(on) = 4.23 m  (min) r ds(on) = 5.17 m  (max) marking diagrams & pin assignments y = year ww = work week 4404n = specific device code dpak case 369c style 2 d s g n?channel 1 3 2 4 straight lead dpak?3 case 369d style 2 yww 44 04n 4 1 gate 2 drain 3 source 4 drain 13 2 1 2 3 4 1 2 3 4 yww 44 04n see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information http://onsemi.com
NTD4404N http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) characteristics symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 3) (v gs = 0 v dc , i d = 250  a dc ) temperature coefficient (positive) v (br)dss 24 ? 28 20.5 ? ? v dc mv/ c zero gate voltage drain current (v ds = 20 v dc , v gs = 0 v dc ) (v ds = 20 v dc , v gs = 0 v dc , t j = 150 c) i dss ? ? ? ? 1.5 10  a dc gate?body leakage current (v gs = 20 v dc , v ds = 0 v dc ) i gss ? ? 100 na dc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250  a dc ) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.5 4.0 2.0 ? v dc mv/ c static drain?to?source on?resistance (note 3) (v gs = 10 v dc , i d = 20 a dc ) r ds(on) 4.23 ? 5.17 m  forward transconductance (note 3) (v ds = 10 v dc , i d = 15 a dc ) g fs ? 38 ? mhos dynamic characteristics input capacitance (v 20 v v 0v c iss ? 2050 ? pf output capacitance (v ds = 20 v dc , v gs = 0 v, f = 1 mhz ) c oss ? 871 ? transfer capacitance f = 1 mhz) c rss ? 359 ? switching characteristics (note 4) turn?on delay time t d(on) ? 6.3 ? ns rise time (v gs = 10 v dc , v dd = 10 v dc , t r ? 77 ? turn?off delay time (v gs 10 v dc , v dd 10 v dc , i d = 30 a dc , r g = 3  ) t d(off) ? 25 ? fall time t f ? 12 ? gate charge (v 5v i 10 a q t ? 17.7 ? nc g (v gs = 5 v dc , i d = 10 a dc , v ds = 10 v dc ) ( note 3 ) q 1 ? 2.6 ? v ds = 10 v d c ) (note 3) q 2 ? 7.1 ? source?drain diode characteristics forward on?volta g e v s d v dc forward on?voltage (i s = 10 a dc , v gs = 0 v dc ) (note 3) (i 10 a v 0v t 125 c) v sd ? 0.78 063 1.0 v d c (i s 10 a dc , v gs 0 v dc ) (note 3) (i s = 10 a dc , v gs = 0 v dc , t j = 125 c) ? 0.78 0.63 1.0 ? reverse recovery time t rr ? 37.5 ? ns y (i s = 20 a dc , v gs = 0 v dc , t a ? 16.8 ? (i s 20 a dc , v gs 0 v dc , di s /dt = 100 a/  s) (note 3) t b ? 20.7 ? reverse recovery stored charge q rr ? 0.027 ?  c 3. pulse test: pulse width 300  s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures. ordering information device package shipping 2 NTD4404N dpak 75 units / rail NTD4404Ng dpak (pb?free) 75 units / rail NTD4404Nt4 dpak 2500 / tape & reel NTD4404Nt4g dpak (pb?free) 2500 / tape & reel NTD4404N1 dpak?3, straight lead 75 units / rail NTD4404N1g dpak?3, straight lead (pb?free) 75 units / rail 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NTD4404N http://onsemi.com 3 3 v 10 v 0 0.018 40 0.014 0.006 0.002 160 1.6 1.2 1.4 1.0 0.8 0.6 10,000 100,000 010 40 4 2 v ds , drain?to?source voltage (volts) i d , drain current (amps) 0 v gs , gate?to?source voltage (volts) figure 1. on?region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.018 40 0.010 0.006 0.002 80 figure 3. on?resistance versus drain current and temperature i d , drain current (amps) figure 4. on?resistance versus drain current and temperature i d , drain current (amps) r ds(on) , drain?to?source resistance (  ) r ds(on) , drain?to?source resistance (  ) figure 5. on?resistance variation with temperature t j , junction temperature ( c) figure 6. drain?to?source leakage current versus voltage v ds , drain?to?source voltage (volts) r ds(on) , drain?to?source resistance (normalized) i dss , leakage (na) ?50 50 25 0 ?25 75 125 100 23 015 10 25 5 6 v ds 10 v t j = 25 c t j = ?55 c t j = 125 c v gs = 10 v v gs = 4.5 v 150 v gs = 0 v i d = 40 a v gs = 10 v 80 v gs = 4 v t j = 25 c t j = ?55 c t j = 125 c t j = 150 c t j = 125 c 40 0 160 80 45 t j = 25 c t j = ?55 c 20 100 6 v 3.2 v 5 v 1.8 6 1000 8 120 1 0 120 120 160 0.014 t j = 125 c 80 0.010 120 2.8 v 2.6 v 2.4 v 4.4 v 3.4 v 3.6 v 3.8 v 160
NTD4404N http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals (  t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. c rss 10 0 10 15 20 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 4800 1600 0 v gs v ds 2400 800 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 3200 4000 v gs figure 8. gate?to?source and drain?to?source voltage versus total charge v gs , gate?to?source voltage (volts) 0 2 0 q g , total gate charge (nc) 6 4 12 48 i d = 10 a t j = 25 c q 2 q 1 q t 20 16
NTD4404N http://onsemi.com 5 80 0 0 drain?to?source diode characteristics v sd , source?to?drain voltage (volts) i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v figure 10. diode forward voltage versus current 100 0.2 0.4 1. 0 10 20 30 t r t d(off) t d(on) t f 10 v ds = 10 v i d = 40 a v gs = 10 v 0.6 0.8 40 60 50 t j = 25 c 70 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance ? general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10  s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r  jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain?to?source voltage (volts) 1 100 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs = 20 v single pulse t c = 25 c 1 ms 100  s 10 ms dc 10  s
NTD4404N http://onsemi.com 6 figure 12. thermal response 10 0.1 0.01 0.00001 0.0001 r(t) , effective transient thermal resistance (normalized) t, time (s) 1 0.001 0.01 0.1 1 10 normalized to r  jc at steady state 10 0.1 0.01 0.00001 0.0001 r(t) , effective transient thermal response (normalized) t, time (s) 1 0.001 0.01 0.1 1 10 100 1000 figure 13. thermal response normalized to r  ja at steady state, 1 square cu pad, cu area 1.127 in 2 , 3 x 3 inch fr4 board
NTD4404N http://onsemi.com 7 package dimensions dpak case 369c issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243  mm inches  scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 2: pin 1. gate 2. drain 3. source 4. drain
NTD4404N http://onsemi.com 8 package dimensions dpak?3 case 369d?01 issue b 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NTD4404N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.


▲Up To Search▲   

 
Price & Availability of NTD4404N

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X