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16-bit, 8-channel serial output sampling analog-to-digital converter features pin for pin with ads7844 single supply: 2.7v to 5v 8-channel single-ended or 4-channel differential input up to 100khz conversion rate 84db sinad serial interface qsop-20 and ssop-20 packages applications data acquisition test and measurement equipment industrial process control personal digital assistants battery-powered systems description the ads8344 is an 8-channel, 16-bit, sampling analog-to-digital (a/d) converter with a synchronous serial interface. typical power dissipation is 10mw at a 100khz throughput rate and a +5v supply. the reference voltage (v ref ) can be varied between 500mv and v cc , providing a corresponding input voltage range of 0v to v ref . the device includes a shutdown mode which reduces power dissipation to under 15 w. the ads8344 is guaranteed down to 2.7v operation. low power, high speed, and an on-board multiplexer make the ads8344 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data log- gers, and measurement equipment. the serial interface also provides low-cost isolation for remote data acquisition. the ads8344 is available in a qsop-20 or ssop-20 package and is guaranteed over the ?0 c to +85 c temperature range. cdac sar comparator 8-channel multiplexer serial interface and control ch4 ch5 ch6 ch7 com v ref cs shdn d in d out busy dclk ch0 ch1 ch2 ch3 ads8344 a d s 8 3 4 4 ads8344 sbas139c ? may 2001 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ads8344 2 sbas139b minimum relative maximum specification package accuracy gain error temperature drawing ordering transport product (lsb) (%) range package number number (1) media ads8344e 8 0.05 ? 40 c to +85 c qsop-20 349 ads8344e rails " " " " " " ads8344e/2k5 tape and reel ads8344n " " " ssop-20 334 ads8344n rails " " " " " " ads8344n/1k tape and reel ads8344eb 6 0.024 ? 40 c to +85 c qsop-20 349 ads8344eb rails " " " " " " ads8344eb/2k5 tape and reel ads8344nb " " " ssop-20 334 ads8344nb rails " " " " " " ads8344nb/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 de vices per reel). ordering 2500 pieces of ? ads8344e/2k5 ? will get a single 2500-piece tape and reel. package/ordering information absolute maximum ratings (1) +v cc to gnd ........................................................................ ? 0.3v to +6v analog inputs to gnd ............................................ ? 0.3v to +v cc + 0.3v digital inputs to gnd ........................................................... ? 0.3v to +6v power dissipation .......................................................................... 250mw maximum junction temperature ................................................... +150 c operating temperature range ........................................ ? 40 c to +85 c storage temperature range ......................................... ? 65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. pin configuration top view ssop pin descriptions pin name description 1 ch0 analog input channel 0. 2 ch1 analog input channel 1. 3 ch2 analog input channel 2. 4 ch3 analog input channel 3. 5 ch4 analog input channel 4. 6 ch5 analog input channel 5. 7 ch6 analog input channel 6. 8 ch7 analog input channel 7. 9 com ground reference for analog inputs. sets zero code voltage in single ended mode. connect this pin to ground or ground reference point. 10 shdn shutdown. when low, the device enters a very low-power shutdown mode. 11 v ref voltage reference input. see specification table for ranges. 12 +v cc power supply, 2.7v to 5v. 13 gnd ground. 14 gnd ground. 15 d out serial data output. data is shifted on the falling edge of dclk. this output is high impedance when cs is high. 16 busy busy output. busy goes low when the d in control bits are being read and also when the device is converting. the output is high impedance when cs is high. 17 d in serial data input. if cs is low, data is latched on rising edge of d clk . 18 cs chip select input. active low. data will not be clocked into d in unless cs is low. when cs is high, d out is high impedance. 19 dclk external clock input. the clock speed determines the conversion rate by the equation f dclk = 24 f sample . 20 +v cc power supply. 1 2 3 4 5 6 7 8 9 10 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com shdn +v cc dclk cs d in busy d out gnd gnd +v cc v ref 20 19 18 17 16 15 14 13 12 11 ads8344 electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ads8344 3 sbas139b electrical characteristics: +5v at t a = ? 40 c to +85 c, +v cc = +5v, v ref = +5v, f sample = 100khz, and f clk = 24 f sample = 2.4mhz, unless otherwise noted. ads8344e, n ads8344eb, nb parameter conditions min typ max min typ max units resolution 16 ? bits analog input full-scale input span positive input - negative input 0 v ref ?? v absolute input range positive input ? 0.2 +v cc + 0.2 ?? v negative input ? 0.2 +1.25 ?? v capacitance 25 ? pf leakage current 1 ? a system performance no missing codes 14 15 bits integral linearity error 86lsb offset error 2 1mv offset error match 1.2 4 ?? lsb (1) gain error 0.05 0.024 % gain error match 1.0 4 ?? lsb noise 20 ? vrms power-supply rejection +4.75v < v cc < 5.25v 3 ? lsb (1) sampling dynamics conversion time 16 ? clk cycles acquisition time 4.5 ? clk cycles throughput rate 100 ? khz multiplexer settling time 500 ? ns aperture delay 30 ? ns aperture jitter 100 ? ps internal clock frequency shdn = v dd 2.4 ? mhz external clock frequency 0.024 2.4 ?? mhz data transfer only 0 2.4 ?? mhz dynamic characteristics total harmonic distortion (2) v in = 5vp-p at 10khz ? 90 ? db signal-to-(noise + distortion) v in = 5vp-p at 10khz 86 ? db spurious free dynamic range v in = 5vp-p at 10khz 92 ? db channel-to-channel isolation v in = 5vp-p at 10khz 100 ? db reference input range 0.5 +v cc ?? v resistance dclk static 5 ? g ? input current 40 100 ?? a f sample = 12.5khz 2.5 ? a dclk static 0.001 3 ?? a digital input/output logic family cmos ? logic levels v ih | i ih | +5 a 3.0 5.5 ?? v v il | i il | +5 a ? 0.3 +0.8 ?? v v oh i oh = ? 250 a 3.5 ? v v ol i ol = 250 a 0.4 ? v data format straight binary ? power-supply requirements +v cc specified performance 4.75 5.25 ?? v quiescent current 1.5 2.0 ? ma f sample = 100khz 300 ? a power-down mode (3) , cs = +v cc 3 ? a power dissipation 7.5 10 ? mw temperature range specified performance ? 40 +85 ?? c ? same specifications as ads8344e. notes: (1) lsb means least significant bit. with v ref equal to +5.0v, one lsb is 76 v. (2) first nine harmonics of the test frequency. (3) auto power-down mode (pd1 = pd0 = 0) active or shdn = gnd.
ads8344 4 sbas139b electrical characteristics: +2.7v at t a = ? 40 c to +85 c, +v cc = +2.7v, v ref = +2.7v, f sample = 100khz, and f clk = 24 f sample = 2.4mhz, unless otherwise noted. ads8344e, n ads8344eb, nb ? same specifications as ads8344e. notes: (1) lsb means least significant bit. with v ref equal to +2.5v, one lsb is 38 v. (2) first nine harmonics of the test frequency. (3) auto power-down mode (pd1 = pd0 = 0) active or shdn = gnd. parameter conditions min typ max min typ max units resolution 16 ? bits analog input full-scale input span positive input - negative input 0 v ref ?? v absolute input range positive input ? 0.2 +v cc + 0.2 ?? v negative input ? 0.2 +0.2 ?? v capacitance 25 ? pf leakage current 1 ? a system performance no missing codes 14 15 bits integral linearity error 12 8 lsb offset error 1 0.5 mv offset error match 1.2 4 ?? lsb gain error 0.05 0.0024 % of fsr gain error match 14 ?? lsb noise 20 ? vrms power-supply rejection +2.7 < v cc < +3.3v 3 ? lsb (1) sampling dynamics conversion time 16 ? clk cycles acquisition time 4.5 ? clk cycles throughput rate 100 ? khz multiplexer settling time 500 ? ns aperture delay 30 ? ns aperture jitter 100 ? ps internal clock frequency shdn = v dd 2.4 ? mhz external clock frequency 0.024 2.4 mhz when used with internal clock 0.024 2.0 ?? mhz data transfer only 0 2.4 ?? mhz dynamic characteristics total harmonic distortion (2) v in = 2.5vp-p at 1khz ? 90 ? db signal-to-(noise + distortion) v in = 2.5vp-p at 1khz 86 ? db spurious free dynamic range v in = 2.5vp-p at 1khz 92 ? db channel-to-channel isolation v in = 2.5vp-p at 10khz 100 ? db reference input range 0.5 +v cc ?? v resistance dclk static 5 ? g ? input current 13 40 ?? a f sample = 12.5khz 2.5 ? a dclk static 0.001 3 ?? a digital input/output logic family cmos ? logic levels v ih | i ih | +5 a+v cc 0.7 5.5 ?? v v il | i il | +5 a ? 0.3 +0.8 ?? v v oh i oh = ? 250 a+v cc 0.8 ? v v ol i ol = 250 a 0.4 ? v data format straight binary ? power-supply requirements +v cc specified performance 2.7 3.6 ?? v quiescent current 1.2 1.85 ?? ma f sample = 100khz 220 ? a power-down mode (3) , cs = +v cc 3 ? a power dissipation 3.2 5 ? mw temperature range specified performance ? 40 +85 ?? c
ads8344 5 sbas139b typical characteristics: +5v at t a = +25 c, +v cc = +5v, v ref = +5v, f sample = 100khz, and f dclk = 24 f sample = 2.4mhz, unless otherwise noted. 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 frequency spectrum (4096 point fft; f in = 1.001khz, ? 0.2db) 0 1020304050 frequency (khz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 frequency spectrum (4096 point fft; f in = 9.985khz, ? 0.2db) 0 1020304050 frequency (khz) amplitude (db) signal-to-noise ratio and signal-to- (noise+distortion) vs input frequency 10 1 100 frequency (khz) snr and sinad (db) 100 90 80 70 60 sinad snr spurious free dynamic range and total harmonic distortion vs input frequency 10 1 100 frequency (khz) sfdr (db) thd (db) 100 90 80 70 60 ? 100 ? 90 ? 80 ? 70 ? 60 thd (1) sfdr note: (1) first nine harmonics of the input frequency change in signal-to-(noise+distortion) vs temperature ? 40 ? 25 0 20 50 75 100 temperature ( c) delta from +25 c (db) 0.2 0.0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 0.4 f in = 9.985khz, ? 0.2db effective number of bits vs input frequency 10 1 100 frequency (khz) effective number of bits 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0
ads8344 6 sbas139b typical characteristics: +5v (cont.) at t a = +25 c, +v cc = +5v, v ref = +5v, f sample = 100khz, and f dclk = 24 f sample = 2.4mhz, unless otherwise noted. output code 2 1 0 ? 1 ? 2 ? 3 ? 4 integral linearity error vs code 8000 h c000 h ffff h 0000 h 4000 h ile (lsb) output code 3 2 1 0 ? 1 ? 2 ? 3 differential linearity error vs code 8000 h c000 h ffff h 0000 h 4000 h dle (lsb)
ads8344 7 sbas139b typical characteristics: +2.7v at t a = +25 c, +v cc = +2.7v, v ref = +2.7v, f sample = 100khz, and f dclk = 24 f sample = 2.4mhz, unless otherwise noted. 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 frequency spectrum (4096 point fft; f in = 1.001khz, ? 0.2db) 0 1020304050 frequency (khz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 frequency spectrum (4096 point fft; f in = 9.985khz, ? 0.2db) 0 1020304050 frequency (khz) amplitude (db) signal-to-noise ratio and signal-to- (noise+distortion) vs input frequency 10 1 100 frequency (khz) snr and sinad (db) 100 90 80 70 60 50 sinad snr spurious free dynamic range and total harmonic distortion vs input frequency 10 1 100 frequency (khz) sfdr (db) thd (1) sfdr 100 90 80 70 60 50 thd (db) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 note: (1) first nine harmonics of the input frequency effective number of bits vs input frequency 10 1 100 frequency (khz) effective number of bits 15 14 13 12 11 10 9 8 change in signal-to-(noise+distortion) vs temperature ? 40 ? 25 0 20 50 75 100 temperature ( c) delta from +25 c (db) 2.0 1.5 1.0 0.5 0.0 ? 0.5 ? 1.0 ? 1.5 ? 2.0 f in = 9.985khz, ? 0.2db
ads8344 8 sbas139b typical characteristics: +2.7v (cont.) at t a = +25 c, +v cc = +2.7v, v ref = +2.7v, f sample = 100khz, and f dclk = 24 f sample = 2.4mhz, unless otherwise noted. output code 3 2 1 0 ? 1 ? 2 ? 3 integral linearity error vs code 8000 h c000 h ffff h 0000 h 4000 h ile (lsb) output code 3 2 1 0 ? 1 ? 2 ? 3 differential linearity error vs code 8000 h c000 h ffff h 0000 h 4000 h dle (lsb) supply current vs +v ss 2.5 3.0 3.5 4.0 4.5 5.0 +v ss (v) supply current (ma) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 f sample = 100khz, v ref = +v ss
ads8344 9 sbas139b theory of operation the ads8344 is a classic successive approximation register (sar) analog-to-digital (a/d) converter. the ar- chitecture is based on capacitive redistribution which inher- ently includes a sample/hold function. the converter is fabricated on a 0.6 s cmos process. the basic operation of the ads8344 is shown in figure 1. the device requires an external reference and an external clock. it operates from a single supply of 2.7v to 5.25v. the external reference can be any voltage between 500mv and +v cc . the value of the reference voltage directly sets the input range of the converter. the average reference input current depends on the conversion rate of the ads8344. the analog input to the converter is differential and is provided via an eight-channel multiplexer. the input can be provided in reference to a voltage on the com pin (which is generally ground) or differentially by using four of the eight input channels (ch0 - ch7). the particular configura- tion is selectable via the digital interface. a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 00 0+in ? in 00 1 +in ? in 01 0 +in ? in 01 1 +in ? in 10 0 ? in +in 10 1 ? in +in 11 0 ? in +in 11 1 ? in +in table ii. differential channel control (sgl/dif low). table i. single-ended channel selection (sgl/dif high). figure 1. basic operation of the ads8344. a2 a1 a0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 00 0+in ? in 10 0 +in ? in 00 1 +in ? in 10 1 +in ? in 01 0 +in ? in 11 0 +in ? in 01 1 +in ? in 11 1 +in ? in analog input see figure 2 for a block diagram of the input multiplexer on the ads8344. the differential input of the converter is derived from one of the eight inputs in reference to the com pin, or four of the eight inputs. table i and table ii show the relationship between the a2, a1, a0, and sgl/dif control bits and the configuration of the analog multiplexer. the control bits are provided serially via the d in pin (see the digital interface section of this data sheet for more details). when the converter enters the hold mode, the voltage difference between the +in and ?n inputs is captured on the internal capacitor array (see figure 2). the voltage on the ?n input is limited between ?.2v and 1.25v, allowing the input to reject small signals which are common to both the +in and ?n input. the +in input has a range of ?.2v to +v cc + 0.2v. the input current on the analog inputs depends on the conver- sion rate of the device. during the sample period, the source must charge the internal sampling capacitor (typically 25pf). after the capacitor has been fully charged, there is no further input current. the rate of charge transfer from the analog source to the converter is a function of conversion rate. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com shdn 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 +v cc dclk cs d in busy d out gnd gnd +v cc v ref serial/conversion clock chip select serial data in serial data out +2.7v to +5v 1 f to 10 f ads8344 single-ended or differential analog inputs 1 f to 10 f 0.1 f
ads8344 10 sbas139b reference input the external reference sets the analog input range. the ads8344 will operate with a reference in the range of 100mv to +v cc . keep in mind that the analog input is the difference between the +in input and the ?n input, as shown in figure 2. for example, in the single-ended mode, a 1.25v reference with the com pin grounded, the selected input channel (ch0 - ch7) will properly digitize a signal in the range of 0v to 1.25v. if the com pin is connected to 0.5v, the input range on the selected channel is 0.5v to 1.75v. there are several critical items concerning the reference input and its wide-voltage range. as the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. this is often referred to as the lsb figure 2. simplified diagram of the analog input. converter +in ? in ch0 ch1 ch2 ch3 a2-a0 (shown 00o b ) (1) sgl/dif (shown high) ch4 ch5 ch6 ch7 com note: (1) see truth tables, table i and table ii for address coding. (least significant bit) size and is equal to the reference voltage divided by 65536. any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference voltage is reduced. for example, if the offset of a given converter is 2lsbs with a 2.5v reference, then it will typically be 10lsbs with a 0.5v reference. in each case, the actual offset of the device is the same, 76.3 v. likewise, the noise or uncertainty of the digitized output will increase with lower lsb size. with a reference voltage of 500mv, the lsb size is 7.6 v. this level is below the internal noise of the device. as a result, the digital output code will not be stable and will vary around a mean value by a number of lsbs. the distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. with a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. because the lsb size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. the voltage into the v ref input is not buffered and directly drives the capacitor digital-to-analog converter (cdac) portion of the ads8344. typically, the input current is 13 a with a 2.5v reference. this value will vary by microamps depending on the result of the conversion. the reference current diminishes directly with both conversion rate and reference voltage. as the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. digital interface the ads8344 has a four-wire serial interface compatible with several microprocessor families (note that the digital inputs are over-voltage tolerant up to +5.5v, regardless of +v cc ). figure 3 shows the typical operation of the ads8344 digital interface. most microprocessors communicate using 8-bit transfers; the ads8344 can complete a conversion with three such transfers, for a total of 24 clock cycles on the dclk input, provided the timing is as shown in figure 3. figure 3. conversion timing, 24-clocks per conversion, 8-bit bus interface. no dclk delay required with dedicated serial port. t acq acquire idle conversion 1 dclk cs 81 15 d out busy (msb) (start) (lsb) a2 s d in a1 a0 sgl/ dif pd1 pd0 14131211109 8 7654321 0 zero filled... 81 8 acquire idle conversion 181 15 (msb) (start) a2 sa1a0 sgl/ dif pd1 pd0 14
ads8344 11 sbas139b the first eight clock cycles are used to provide the control byte via the d in pin. when the converter has enough information about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. after four more clock cycles, the control byte is complete and the converter enters the conversion mode. at this point, the input sample/hold goes into the hold mode. the next sixteen clock cycles accomplish the actual a/d conversion. control byte see figure 3 for placement and order of the control bits within the control byte. tables iii and iv give detailed information about these bits. the first bit, the ??bit, must always be high and indicates the start of the control byte. the ads8344 will ignore inputs on the d in pin until the start bit is detected. the next three bits (a2-a0) select the active input channel or channels of the input multiplexer (see tables i and ii and figure 2). the sgl/dif-bit controls the multiplexer input mode: ei- ther in single-ended mode, where the selected input channel is referenced to the com pin, or in differential mode, where the two selected inputs provide a differential input. bit 7 bit 0 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) sa2a1a0 ? sgl/dif pd1 pd0 table iii. order of the control bits in the control byte. table iv. descriptions of the control bits within the control byte. bit name description 7 s start bit. control byte starts with first high bit on d in . 6 - 4 a2 - a0 channel select bits. along with the sgl/dif bit, these bits control the setting of the multiplexer input, as detailed in tables i and ii. 2 sgl/dif single-ended/differential select bit. along with bits a2 - a0, this bit controls the setting of the multiplexer input, as detailed in tables i and ii. 1 - 0 pd1 - pd0 power-down mode select bits. see table v for details. pd1 pd0 description 0 0 power-down between conversions. when each conversion is finished, the converter enters a low-power mode. at the start of the next conver- sion, the device instantly powers up to full power. there is no need for additional delays to assure full operation and the very first conversion is valid. 1 0 internal clock mode. 0 1 reserved for future use. 1 1 no power-down between conversions, device al- ways powered. table v. power-down selection. figure 4. detailed timing diagram. pd0 t bdv t dh t ch t cl t ds t css t dv t bd t bd t tr t btr t d0 t csh dclk cs 15 d out busy d in 14 see tables i and ii and figure 2 for more information. the last two bits (pd1 - pd0) select the power-down mode and clock mode, as shown in table v. if both pd1 and pd0 are high, the device is always powered up. if both pd1 and pd0 are low, the device enters a power-down mode between conversions. when a new conversion is initiated, the device will resume normal operation instantly?o delay is needed to allow the device to power up and the very first conversion will be valid. clock modes the ads8344 can be used with an external serial clock or an internal clock to perform the successive-approximation con- version. in both clock modes, the external clock shifts data in and out of the device. internal clock mode is selected when pd1 is high and pd0 is low. if the user decides to switch from one clock mode to the other, an extra conversion cycle will be required before the ads8344 can switch to the new mode. the extra cycle is required because the pd0 and pd1 control bits need to be written to the ads8344 prior to the change in clock modes. note: it is recommended that the customer write to the pd1 and pd0 registers prior to the first conversion in order to insure that the proper clock mode is selected. external clock mode in external clock mode, the external clock not only shifts data in and out of the ads8344, it also controls the a/d conversion steps. busy will go high for one clock period after the last bit of the control byte is shifted in. successive-approximation bit decisions are made and appear at d out on each of the next 16 s dclk falling edges (see figure 3). figure 4 shows the busy timing in external clock mode.
ads8344 12 sbas139b symbol description min typ max units t acq acquisition time 1.5 s t ds d in valid prior to dclk rising 100 ns t dh d in hold after dclk high 10 ns t do dclk falling to d out valid 200 ns t dv cs falling to d out enabled 200 ns t tr cs rising to d out disabled 200 ns t css cs falling to first dclk rising 100 ns t csh cs rising to dclk ignored 0 ns t ch dclk high 200 ns t cl dclk low 200 ns t bd dclk falling to busy rising 200 ns t bdv cs falling to busy enabled 200 ns t btr cs rising to busy disabled 200 ns table vi. timing specifications (+v cc = +2.7v to 3.6v, t a = ?0 c to +85 c, c load = 50pf). since one clock cycle of the serial clock is consumed with busy going high (while the msb decision is being made), 16 additional clocks must be given to clock out all 16 bits of data; thus, one conversion takes a minimum of 25 clock cycles to fully read the data. since most microproces- sors communicate in 8-bit transfers, this means that an additional transfer must be made to capture the lsb. there are two ways of handling this requirement. one is where the beginning of the next control byte appears at the same time the lsb is being clocked out of the ads8344 (see figure 3). this method allows for maximum throughput and 24 clock cycles per conversion. the other method is shown in figure 5, which uses 32 clock cycles per conversion; the last seven clock cycles simply shift out zeros on the d out line. busy and d out go into a high-impedance state when cs goes high; after the next cs falling edge, busy will go low. internal clock mode in internal clock mode, the ads8344 generates its own conversion clock internally. this relieves the microproces- sor from having to generate the sar conversion clock and allows the conversion result to be read back at the processor? convenience, at any clock rate from 0mhz to 2.0mhz. busy goes low at the start of a conversion and then returns high when the conversion is complete. during the conversion, busy will remain low for a maximum of 8 s. also, during the conversion, dclk should remain low to achieve the best noise performance. the conversion result is stored in an internal register; the data may be clocked out of this register any time after the conversion is complete. t acq acquire idle conversion 1 d clk cs 81 15 d out busy (msb) (start) (lsb) a2 s d in a1 a0 sgl/ dif pd1 pd0 14131211109 8 7654321 0 81 8 idle 18 zero filled... if cs is low when busy goes low following a conver- sion, the next falling edge of the external serial clock will write out the msb on the d out line. the remaining bits (d14-d0) will be clocked out on each successive clock cycle following the msb. if cs is high when busy goes low then the d out line will remain in tri-state until cs goes low, as shown in figure 6. cs does not need to remain low once a conversion has started. note that busy is not tri-stated when cs goes high in internal clock mode. data can be shifted in and out of the ads8344 at clock rates exceeding 2.4mhz, provided that the minimum acquisition time t acq , is kept above 1.7 s. digital timing figure 4 and tables vi and vii provide detailed timing for the digital interface of the ads8344. t acq acquire idle conversion 1 d clk cs 8 9 1011121314151617181920212223242526272829303132 15 d out busy (msb) (start) (lsb) a2 s d in a1 a0 sgl/ dif pd1 pd0 14131211109 8 7654321 0 zero f illed... figure 5. external clock mode, 32 clocks per conversion. figure 6. internal clock mode timing.
ads8344 13 sbas139b symbol description min typ max units t acq acquisition time 1.7 s t ds d in valid prior to dclk rising 50 ns t dh d in hold after dclk high 10 ns t do dclk falling to d out valid 100 ns t dv cs falling to d out enabled 70 ns t tr cs rising to d out disabled 70 ns t css cs falling to first dclk rising 50 ns t csh cs rising to dclk ignored 0 ns t ch dclk high 150 ns t cl dclk low 150 ns t bd dclk falling to busy rising 100 ns t bdv cs falling to busy enabled 70 ns t btr cs rising to busy disabled 70 ns figure 7. ideal input voltages and output codes. table vii. timing specifications (+v cc = +4.75v to +5.25v, t a = ?0 c to +85 c, c load = 50pf). output code 0v fs = full-scale voltage = v ref 1 lsb = v ref /65,536 fs ? 1 lsb 11...111 11...110 11...101 00...010 00...001 00...000 1 lsb note: (1) voltage at converter input, after multiplexer: +in ? ( ? in). (see figure 2.) input voltage (1) (v) data format the ads8344 output data is in straight binary format, as shown in figure 7. this figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. power dissipation there are three power modes for the ads8344: full-power (pd1 - pd0 = 11b), auto power-down (pd1 - pd0 = 00b), and shutdown (shdn low). the effects of these modes varies depending on how the ads8344 is being operated. for example, at full conversion rate and 24-clocks per conversion, there is very little difference between full-power mode and auto power-down; a shutdown will not lower power dissipation. when operating at full-speed and 24-clocks per conversion (see figure 3), the ads8344 spends most of its time acquiring or converting. there is little time for auto power-down, assuming that this mode is active. thus, the difference between full-power mode and auto power-down is negligible. if the conversion rate is decreased by simply slowing the frequency of the dclk input, the two modes remain approximately equal. however, if the dclk fre- quency is kept at the maximum rate during a conversion, but conversions are simply done less often, then the difference between the two modes is dramatic. in the latter case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). if dclk is active and cs is low while the ads8344 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. the power can be reduced to a minimum by keeping cs high. operating the ads8344 in auto power-down mode will result in the lowest power dissipation, and there is no conversion time ?enalty?on power-up. the very first conversion will be valid. shdn can be used to force an immediate power-down. noise the noise floor of the ads8344 itself is extremely low, as shown in figures 8 thru 11, and is much lower than compet- ing a/d converters. the ads8344 was tested at both 5v and 2.7v, and in both the internal and external clock modes. a low-level dc input was applied to the analog-input pins and the converter was put through 5,000 conversions. the digital output of the a/d converter will vary in output code due to the internal noise of the ads8344. this is true for all 16-bit sar-type a/d converters. using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. the 1 , 2 , and 3 distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. the transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the 3 distribution, or 99.7%, of all codes. statistically, up to 3 codes could fall outside the distribution when executing 1,000 conversions. the ads8344, with < 3 output codes for the 3 distribution, will yield a < 0.5lsb transition noise at 5v operation. remember, to achieve this low-noise per- formance, the peak-to-peak noise of the input signal and reference must be < 50 v. figure 8. histogram of 5,000 conversions of a dc input at the code transition, 5v operation external clock mode. code 4561 242 00 197 7ffe 7ffd 8001 8000 7fff
ads8344 14 sbas139b figure 9. histogram of 5,000 conversions of a dc input at the code center, 5v operation internal clock mode. code 4507 251 00 242 7ffe 7ffd 8001 8000 7fff figure 10. histogram of 5,000 conversions of a dc input at the code transition, 2.7v operation external clock mode. figure 11. histogram of 5,000 conversions of a dc input at the code center, 2.7v operation internal clock mode. code 3511 721 666 50 52 7ffe 7ffd 8001 8000 7fff code 2868 1137 858 78 59 7ffe 7ffd 8001 8000 7fff sion results will reduce the transition noise by 1/2 to 0.25 lsbs. averaging should only be used for input signals with frequencies near dc. for ac signals, a digital filter can be used to low-pass filter and decimate the output codes. this works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio will improve 3db. layout for optimum performance, care should be taken with the physical layout of the ads8344 circuitry. this is particu- larly true if the reference voltage is low and/or the conver- sion rate is high. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connec- tions, and digital inputs that occur just prior to latching the output of the analog comparator. thus, during any single conversion for an n-bit sar converter, there are n ?in- dows?in which large external transient voltages can easily affect the conversion result. such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. the error can change if the external event changes in time with respect to the dclk input. with this in mind, power to the ads8344 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 f to 10 f capacitor and a 5 ? or 10 ? series resistor may be used to low-pass filter a noisy supply. the reference should be similarly bypassed with a 0.1 f capacitor. again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. if the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). the ads8344 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of dclk during a conversion). the ads8344 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high-frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50hz or 60hz) can be difficult to remove. the gnd pin should be connected to a clean ground point. in many cases, this will be the ?nalog?ground. avoid connections which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power-supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. averaging the noise of the a/d converter can be compensated by averaging the digital codes. by averaging conversion results, transition noise will be reduced by a factor of 1/ n, where n is the number of averages. for example, averaging 4 conver-
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