65 real time clock module specifications (characteristics) absolute max. rating operating range frequency characteristics and current consumption characteristics electrical characteristics external dimensions terminal connection rtc-72421 (unit: mm) 23.1 max. 3.3 min. 0.2 min. 6.8 max. 4.2 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 rtc72421 a epson 5053c rtc72423 a epson 6150 (v dd ) and v dd are to have the same level of voltage . do not connect it to any external terminals. nc is not connected internally. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 rtc-72421 rtc-72423 rtc-72423 0.05 min. 2.8 max. 7.62 0.25 2.5 16.3 max. 7.9 12.2 max. 0.2 1.0 0.3 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 std. p cs 0 ale a 0 a 1 a 2 a 3 rd gnd wr d 3 d 2 d 1 d 0 cs 1 ( v dd ) ( v dd ) v dd 72423 std. p cs 0 nc ale a 0 nc a 1 nc a 2 a 3 rd gnd wr d 3 d 2 d 1 nc nc d 0 cs 1 nc ( v dd ) ( v dd ) v dd 72421 90 to 105 0 to 10 4-bit real time clock module rtc-72421 / 72423 ? builtin crystal unit allows adjustment-free efficient operation. ? ale input terminal available for 8048, 8051, and 8085 series. ? 12/24h clock switchover function and automatic leap year setting. ? interrupt masking. ? 30 second adjustment function. ? low current consumption and features a backup function. item power source voltage input and output voltage storage temperature soldering condition symbol v dd v i/o t stg t sol condition ta=25?c ta=25?c rtc-72421 rtc-72423 rtc-72421 rtc-72423 specifications -0.3 to 7.0 gnd -0.3 to v dd +0.3 -55 to +85 -55 to +125 under 260?c within 10 sec. (lead part) (package should be less than 150?c) twice at under 260?c within 10 sec. or under 230?c within 3 min. unit v ?c item operating voltage operating temperature data holding voltage csi data holding time operation restoring time symbol v dd t opr v dh t cdr t r condition rtc-72421 rtc-72423 refer to the data holding timing specifications 4.5 to 5.5 -10 to 70 -40 to 85 2.0 to 5.5 2.0 min. unit v ?c v s item frequency tolerance frequency temperature characteristics aging shock resistance current consumption symbol d f/fo fa s.r. i dd1 i dd2 ta=25?c v dd =5v 72421 a 72421 b 72423 a 72423 condition three drops on a hard board from 75 cm or 3000g x 0.3ms x 1/2 sine wave x 3 directions cs 1 =0v exclude input/ output current v dd =5v v dd =2v specifications 10 50 20 50 +10/-120 5 max. 10 max. 10 max. 5 max. unit ppm ppm/y ppm a item h input voltage (1) l input voltage (1) input leak current (1) input leak current (2) l output voltage (1) h output voltage l output voltage (2) off leak current input capacity h input voltage (2) l input voltage (2) symbol v ih1 v il1 i lk1 i lk2 v ol1 v oh v ol2 i offlk c 1 v ih2 v il2 condition v 1 =v dd /0v i ol =2.5ma i oh = -400a i ol =2.5ma v 1 =v dd /0v input frequency 1 mhz v dd = 2 to 5.5v min. 2.2 2.4 4/5 v dd typ. 10 20 max. 0.8 1 10 0.4 0.4 10 1/5 v dd unit v a v a pf v applicable terminal all inputs other than cs 1 input other than d 0 to d 3 d 0 to d 3 std.p input other than d 0 to d 3 d 0 to d 3 cs 1 -10 to +70?c (25?c reference temperature) v dd =5v, ta=25?c, first year actual size
66 real time clock module cs 1 v ih ( cs1 ) v ih v ih v ih v ih v ih v ih v ih v il v il v il v ih v il v il v il v ih ( cs1 ) t su ( cs1 ) t su ( a-ale ) t h ( ale-a ) t su ( ale-w ) t su ( d-w ) t su ( w-ale ) t su ( r-ale ) t w ( ale ) cs 0 ale wr a 0 to a 3 d 0 to d 3 t h ( cs1 ) t h ( w-d ) t w ( w ) cs 1 cs 1 cs 0 or wr not occurred cs 1 v ih ( cs1 ) 1/5v dd v dd 4v 4v v ih 2 v ih 2 v il 2 v il 2 t cdr t r v ih v ih v oh v ol v oh v ol v ih v ih v ih v il v il v ih v il v il v il v il v ih ( cs1 ) t su ( cs1 ) t su ( a-ale ) t h ( ale-a ) t su ( ale-r ) t pzv ( r-q ) t pvz ( r-q ) t su ( r-ale ) t rnc ( r ) t w ( ale ) cs 0 ale rd a 0 to a 3 d 0 to d 3 t h ( cs1 ) 2 to 4v data storage mode interface possible with external terminals interface possible with the external terminals osc divider read write control address latch data bus buffer address decoder rd wr cs 1 ale cs 0 a 0 d 0 d 1 d 2 d 3 a 1 a 2 a 3 std? 64 h z rest stop 30adj busy hold carry per sec. carry per min. carry per hour 4 4 4 4 4 irqflag 24 /12 seconds minutes hours days months years week sec 1 sec 10 min 1 min 10 hou 1 hou 10 day 1 day 10 mon 1 mon 10 yea 1 yea 10 reg d reg e reg f register table switching characteristics ( with ale ) read mode ( with ale ) write mode ( with ale ) data holding timing block diagram ( v dd = 5v 0.5v ) 0=??level,1=??level, rest = reset itrpt/ stnd=interrupt/standard 1 ) bit does not exist. 2 ) please mask am/pm bit with 10's of hours operations. 3 ) busy is read only. irq can only. irq can only be set low (??. 4 ) 5 ) test bit should be ?? ( please connect ale to v dd if the microprocessor does not have an ale output. ) * 0 1 2 3 4 5 6 7 8 9 a b c d e f a 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 a 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 s 1 s 10 mi 1 mi 10 h 1 h 10 d 1 d 10 mo 1 mo 10 y 1 y 10 w reg d reg e reg f d 3 s 8 * mi 8 * h 8 * d 8 * mo 8 * y 8 y 80 * 30 sec. adj t 1 test d 2 s 4 s 40 mi 4 mi 40 h 4 pm/am d 4 * mo 4 * y 4 y 40 w 4 irq flag t 0 24/12 d 1 s 2 s 20 mi 2 mi 20 h 2 h 20 d 2 d 20 mo 2 * y 2 y 20 w 2 busy itrpt /stnd stop d 0 s 1 s 10 mi 1 mi 10 h 1 h 10 d 1 d 10 mo 1 mo 10 y 1 y 10 w 1 hold mask rest count value 0 to 9 0 to 5 0 to 9 0 to 5 0 to 9 0 to 2 or 0 to 1 0 to 9 0 to 3 0 to 9 0 to 1 0 to 9 0 to 6 ----- remarks 1- second digit register 10- second digit register 1- minute digit register 10- minute digit register 1- hour digit register pm/am,10- hours digit register 1- day digit register 10 -day digit register 1- month digit register 10- month digit register 1- year digit register 10- year digit register week register control register d control register e control register f item cs 1 setup time address setup time before ale address hold time after ale ale pulse width ale setup time before write ale setup time before read ale setup time after write ale setup time after read write pulse width data delay time after read data hold time after read data setup time before write data hold time after write cs 1 hold time read/write recovery time symbol t su (cs1) t su (a-ale) t h (ale-a) t w (ale) t su (ale-w) t su (ale-r) t su (w-ale) t su (r-ale) t w (w) t pzv (r-q) t pvz (r-q) t su (d-w) t h (w-d) t h (cs1) t rec (r/w) condition c l =150pf min. 1000 50 50 80 0 0 50 50 120 ---- 0 80 10 1000 200 max. ---- 120 70 ---- unit ns address register data bit 1 0 pm/am pm am itrpt/stnd itrpt stnd 24/12 24 12 data
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