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1 features ? utilizes the avr ? risc architecture avr ? high-performance and low-power risc architecture ? 121 powerful instructions ? most single clock cycle execution ? 32 x 8 general-purpose working registers + peripheral control registers ? up to 6 mips throughput at 6 mhz data and nonvolatile program memory ? 128k bytes of in-system programmable flash endurance: 1,000 write/erase cycles ? 4k bytes internal sram ? 4k bytes of in-system programmable eeprom endurance: 100,000 write/erase cycles ? programming lock for flash program and eeprom data security ? spi interface for in-system programming peripheral features ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator ? programmable serial uart ? master/slave spi serial interface ? real-time counter (rtc) with separate oscillator ? two 8-bit timer/counters with separate prescaler and pwm ? expanded 16-bit timer/counter system with separate prescaler, compare, capture modes and dual 8-, 9-, or 10-bit pwm ? programmable watchdog timer with on-chip oscillator ? 8-channel, 10-bit adc special microcontroller features ? low-power idle, power-save and power-down modes ? software selectable clock frequency ? external and internal interrupt sources specifications ? low-power, high-speed cmos process technology ? fully static operation power consumption at 4 mhz, 3v, 25 c ? active: 5.5 ma ? idle mode: 1.6 ma ? power-down mode: < 1 a i/o and packages ? 32 programmable i/o lines, 8 output lines, 8 input lines ? 64-lead tqfp operating voltages ? 2.7 - 3.6v for ATMEGA103L ? 4.0 - 5.5v for atmega103 speed grades ? 0 - 4 mhz for ATMEGA103L ? 0 - 6 mhz for atmega103 8-bit microcontroller with 128k bytes in-system programmable flash atmega103(l) summary rev. 0945gs?09/01 n o t e: thi s i s a summary d ocume n t . a comp l e t e d ocumen t i s ava ila ble on ou r we b site at www.atmel.com .
2 atmega103(l) 0945gs?09/01 pin configuration tqfp pc0 (a8) vcc gnd (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref agnd avcc 32 52 53 31 54 29 55 30 28 56 27 57 26 58 25 59 24 60 61 23 61 62 22 62 63 20 21 63 64 64 1 51 2 50 3 49 4 48 5 47 6 46 7 45 8 44 9 43 10 42 11 41 12 40 13 39 14 38 15 37 16 36 17 35 18 34 19 33 (pdi/rxd) pe0 (pdo/txd) pe1 pen (ac+) pe2 (ac-) pe3 (int4) pe4 (int5) pe5 (int6) pe6 (int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc0/pwm0) pb4 pb7 (oc2/pwm2) tosc2 (oc1b/pwm1b) pb6 tosc1 (oc1a/pwm1a) pb5 pc1 (a9) wr pd7 (t2) pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15) pa7 (ad7) ale pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) (ad0) pa0 (ad1) pa1 (ad2) pa2 rd pd6 (t1) pd5 pd4 (ic1) pd3 (int3) pd2 (int2) pd1 (int1) pd0 (int0) xtal1 xtal2 reset gnd vcc index corner
3 atmega103(l) 0945gs?09/01 description the atmega103(l) is a low-power, cmos, 8-bit microcontroller based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the atmega103(l) achieves throughputs approaching 1 mips per mhz, allowing the sys- tem designer to optimize power consumption versus processing speed. the avr core is based on an enhanced risc architecture that combines a rich instruc- tion set with 32 general-purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architec- ture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega103(l) provides the following features: 128k bytes of in-system program- mable flash, 4k bytes eeprom, 4k bytes sram, 32 general-purpose i/o lines, 8 input lines, 8 output lines, 32 general-purpose working registers, real-time counter (rtc), 4 flexible timer/counters with compare modes and pwm, uart, programmable watchdog timer with internal oscillator, an spi serial port and 3 software-selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next inter- rupt or hardware reset. in power-save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the device is manufactured using atmel?s high-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory programmer. by combining an 8-bit risc cpu with a large array of isp flash on a monolithic chip, the atmel atmega103(l) is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. the atmega103(l) avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, in- circuit emulators and evaluation kits.
4 atmega103(l) 0945gs?09/01 block diagram figure 1. the atmega103(l) block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portc data register portd programming logic timing and control oscillator oscillator interrupt unit eeprom spi uart status register z y x alu portb driver/buffers porte driver/buffers porta driver/buffers portf buffers analog mux adc portd driver/buffers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 reset vcc vcc agnd gnd gnd aref tosc2 tosc1 xtal1 xtal1 control lines + - analog comp ara tor pd0 - pd7 pc0 - pc7 pen ale wr rd 8-bit data bus avcc
5 atmega103(l) 0945gs ? 09/01 pin descriptions vcc supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port. port pins can provide internal pull-up resistors (selected for each bit). the port a output buffers can sink 20 ma and can drive led dis- plays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. port a serves as multiplexed address/data bus when using external sram. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors. the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low, will source current if the pull-up resistors are activated. port b also serves the functions of various special features. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c (pc7..pc0) port c is an 8-bit output port. the port c output buffers can sink 20 ma. port c also serves as address output when using external sram. since port c is an output only port, the port c pins are not tri-stated when a reset condi- tion becomes active. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. port d also serves the functions of various special features. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors. the port e output buffers can sink 20 ma. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. port e also serves the functions of various special features. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running port f (pf7..pf0) port f is an 8-bit input port. port f also serves as the analog inputs for the adc. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier.
6 atmega103(l) 0945gs ? 09/01 tosc1 input to the inverting timer/counter oscillator amplifier. tosc2 output from the inverting timer/counter oscillator amplifier. wr external sram write strobe rd external sram read strobe ale ale is the address latch enable used when the external memory is enabled. the ale strobe is used to latch the low-order address (8 bits) into an address latch during the first access cycle, and the ad0-7 pins are used for data during the second access cycle. avcc supply voltage for port f, including adc. the pin must be connected to vcc when not used for the adc. see ? adc noise canceling techniques ? on page 74 for details when using the adc. aref aref is the analog reference input for the adc converter. for adc operations, a volt- age in the range agnd to avcc must be applied to this pin. agnd if the board has a separate analog ground plane, this pin should be connected to this ground plane. otherwise, connect to gnd. pen pen is a programming enable pin for the serial programming mode. by holding this pin low during a power-on reset, the device will enter the serial programming mode. pen has no function during normal operation.
7 atmega103(l) 0945gs ? 09/01 note: for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical ? 1 ? to them. note that the cbi and sbi instruc- tions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the c bi and sbi instructions work with registers $00 to $1f only. register summary address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 page $3f ($5f) sreg i t h s v n z c page 19 $3e ($5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 20 $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 20 $3c ($5c) xdiv xdiven xdiv6 xdiv5 xdiv4 xdiv3 xdiv2 xdiv1 xdiv0 page 22 $3b ($5b) rampz ? ? ? ? ? ? ? rampz0 page 20 $3a ($5a) eicr isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 29 $39 ($59) eimsk int7 int6 int5 int4 int3 int2 int1 int0 page 28 $38 ($58) eifr intf7 intf6 intf5 intf4 ? ? ? ? page 29 $37 ($57) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 ocie0 toie0 page 30 $36 ($56) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 ocf0 tov0 page 31 $35 ($55) mcucr sre srw se sm1 sm0 ? ? ? page 21 $34 ($54) mcusr ? ? ? ? ? ? extrf porf page 27 $33 ($53) tccr0 ? pwm0 com01 com00 ctc0 cs02 cs01 cs00 page 37 $32 ($52) tcnt0 timer/counter0 (8-bit) page 38 $31 ($51) ocr0 timer/counter0 output compare register page 39 $30 ($50) assr ? ? ? ? as0 tcn0ub ocr0ub tcr0ub page 40 $2f ($4f) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?pwm11pwm10 page 45 $2e ($4e) tccr1b icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 page 46 $2d ($4d) tcnt1h timer/counter1 ? counter register high byte page 47 $2c ($4c) tcnt1l timer/counter1 ? counter register low byte page 47 $2b ($4b) ocr1ah timer/counter1 ? output compare register a high byte page 47 $2a ($4a) ocr1al timer/counter1 ? output compare register a low byte page 47 $29 ($49) ocr1bh timer/counter1 ? output compare register b high byte page 48 $28 ($48) ocr1bl timer/counter1 ? output compare register b low byte page 48 $27 ($47) icr1h timer/counter1 ? input capture register high byte page 48 $26 ($46) icr1l timer/counter1 ? input capture register low byte page 48 $25 ($45) tccr2 ? pwm2 com21 com20 ctc2 cs22 cs21 cs20 page 37 $24 ($44) tcnt2 timer/counter2 (8-bit) page 38 $23 ($43) ocr2 timer/counter2 output compare register page 39 $21 ($47) wdtcr ? ? ? wdtoe wde wdp2 wdp1 wdp0 page 51 $1f ($3f) eearh ? ? ? ? eear11 eear10 eear9 eear8 page 53 $1e ($3e) eearl eeprom address register l page 53 $1d ($3d) eedr eeprom data register page 53 $1c ($3c) eecr ? ? ? ? eerie eemwe eewe eere page 53 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 79 $1a ($3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 79 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 79 $18 ($38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 81 $17 ($37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 81 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 81 $15 ($35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 87 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 88 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 88 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 88 $0f ($2f) spdr spi data register page 60 $0e ($2e) spsr spif wcol ? ? ? ? ? ? page 59 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 page 58 $0c ($2c) udr uart i/o data register page 64 $0b ($2b) usr rxc txc udre fe or ? ? ? page 64 $0a ($2a) ucr rxcie txcie udrie rxen txen chr9 rxb8 txb8 page 65 $09 ($29) ubrr uart baud rate register page 67 $08 ($28) acsr acd ? aco aci acie acic acis1 acis0 page 68 $07 ($27) admux ? ? ? ? ? mux2 mux1 mux0 page 73 $06 ($26) adcsr aden adsc ? adif adie adps2 adps1 adps0 page 73 $05 ($25) adch ? ? ? ? ? ? adc9 adc8 page 74 $04 ($24) adcl adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 page 74 $03 ($23) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 page 92 $02 ($22) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 92 $01 ($21) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 page 92 $00 ($20) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 page 96
8 atmega103(l) 0945gs ? 09/01 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd, rr compare rd - rr z,n,v,c,h 1 cpc rd, rr compare with carry rd - rr - c z,n,v,c,h 1 cpi rd, k compare register with immediate rd - k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc = pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc = pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v = 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v = 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions elpm extended load program memory r0 (z + rampz) none 3 mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1
9 atmega103(l) 0945gs ? 09/01 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-increment rd (x), x x + 1 none 2 ld rd, -x load indirect and pre-decrement x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-increment rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-decrement y y - 1, rd (y) none 2 ldd rd, y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-increment rd (z), z z + 1 none 2 ld rd, -z load indirect and pre-decrement z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-increment (x) rr, x x + 1 none 2 st -x, rr store indirect and pre-decrement x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-increment (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-decrement y y - 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-increment (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-decrement z z - 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1none2 cbi p, b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) = c, rd(n+1) rd(n), c = rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) = c, rd(n) rd(n+1), c = rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) = rd(7..4), rd(7..4) = rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wd timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks
10 atmega103(l) 0945gs ? 09/01 ordering information speed (mhz) power supply ordering code package operation range 4 2.7 - 3.6v ATMEGA103L-4ac 64a commercial (0 c to 70 c) ATMEGA103L-4ai 64a industrial (-40 c to 85 c) 6 4.0 - 5.5v atmega103-6ac 64a commercial (0 c to 70 c) atmega103-6ai 64a industrial (-40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp)
11 atmega103(l) 0945gs ? 09/01 packaging information 64a pin 1 id 0.80(0.0315) bsc 16.25(0.640) sq sq 15.75(0.620) 0.45(0.018) 0.30(0.012) 14.10(0.555) 13.90(0.547) 0.15(0.006) 0.05(0.002 ) 0.75(0.030) 0.45(0.018) 0.20(0.008) 0.09(0.004) pin 1 64-lead, thin (1.0 mm) plastic quad flat package (tqfp), 14x14mm body, 2.0mm footprint, 0.8mm pitch. dimensions in millimeters and (inches)* jedec standard ms-026 aeb *controlliing dimension: millimeter 0?~7? 1.20 (0.047) max rev. a 04/11/2001
? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the companys standard warranty which is detailed in atmels terms and conditions located on the companys web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmels products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel product operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-7658-3000 fax (33) 4-7658-3480 atmel heilbronn theresienstrasse 2 pob 3535 d-74025 heilbronn, germany tel (49) 71 31 67 25 94 fax (49) 71 31 67 24 23 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 0 2 40 18 18 18 fax (33) 0 2 40 18 19 60 atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-357-000 fax (44) 1355-242-743 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. at m e l and avr are the registered trademarks of atmel. other terms and product names may be the trademarks of others. 0945gs09/01/xm

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