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low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 17 http://www.cypress.com approved product c9811x2 product features ? intel?s 810 clock solution ? 3 copies of cpu clock (cpu[0:1] and cpu_itp) ? 9 copies of sdram clock (sdram[0:7] and dclk) ? 8 copies of pci clock ? 2 copies of 3v66 clock ? 2 copies of apic clock, synchronous to pci clock ? 1 ref clock ? 2 usb clocks (non ssc) ? power down feature ? spread spectrum support ? smbus support for turning off unused clocks ? 56 pin ssop package block diagram fig.1 frequency table (mhz) sel1 sel0 cpu sdram pci 0 0 tri-state tri-state tri-state 0 1 test mode (see table2) 1 0 66.6 100 33.3 1 1 100 100 33.3 table 1 note: the following clocks remain fixed frequencies except in test mode. 3v66=66.6mhz, usb/dot=48mhz, ref=14.318mhz and ioapic=16.6 or 33.3mhz depending on power up selection. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 xin vdd sel1 xout vss vss 3v660 3v661 vdd pci0_ich pci1 pci2 vss pci4 vss vdd pci3 pci5 pci6 vdd vdda vssa vss vdd dclk vss sdram7 sdram6 sdram5 vdd vss sdram2 vdd sdram0 vss cpu2_itp cpu1 sdram4 sdram3 sdram1 vss vddc cpu0 vddi ioapic1 ioapic0 vss pci7 c9811x2 25 26 27 asel/ref usb0 usb1 28 vdd sel0 sdata sclk pd# 49 50 51 52 53 54 55 56 vddc vdds vdd vdd vddi vdd vdd pll1 rin i2c-clk i2c-data apic s1 pwr_dwn# s0 cpu sdram 66m pci pll2 rin 48 pd# i2c-clk i2c-data 300k 36pf 36pf x b u f 3 9 2 8 2 1 1 xin xout cpu(0:2) sdram(0:7), dclk 3v66(0:1) pci(0:7) ioapic(0:1) sdata sclk pd# sel0 sel1 usb (0:1) ref
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 17 http://www.cypress.com approved product c9811x2 pin description pin no. pin name pwr i/o type description 1 asel/ref vdd i/o 3.3v 14.318 mhz clock output. this pin also serves as the select strap for ioapic clock frequency. if strapped low during power up, ioapic clocks run at pci/2 (16.6 mhz). if not strapped, it runs at 33 mhz. this pin has a 50k internal pull-up (+/- 20k). 3 xin vdd i osc1 14.318mhz crystal input 4 xout vdd o 14.318mhz crystal output 11, 12, 13, 15, 16, 18, 19, 20 pci0/ich pci(1..7) vdd o 3.3v pci clock outputs 7, 8 3v66(0,1) vdd o 3.3v fixed 66.6 mhz clock outputs 25, 26 usb (0:1) vdd o 3.3v fixed 48 mhz clock outputs 28, 29 sel(0,1) vdd i 3.3v lvttl compatible inputs for logic selection. has an internal pull-up (typ. 250k ? ) 30 sdata vdd i i 2 c compatible sdata input. has an internal pull-up (>100k ? ) 31 sclk vdd i i 2 c compatible sclk input. has an internal pull-up (>100k ? ) 32 pd# vdd i 3.3v lvttl compatible input. device enters powerdown mode when held low. has an internal pull-up (>100k ? ) 34 dclk vdd o 3.3v output running 100mhz 36, 37, 39, 40, 42, 43, 45, 46 sdram(7..0) vdds o 3.3v output running 100mhz. all sdram outputs can be turned off through smbus. 49, 50, 52 cpu(2)_itp, cpu(1,0) vddc o 2.5v host bus clock outputs. 66 or 100mhz depending on state of sel0 and sel1 pins. 54, 55 ioapic(1,0) vddi o 2.5v clock outputs running rising edge synchronous with the pci clock frequency. 16.67 mhz or 33.3 mhz dependent on power up strapping of ref (pin 1). 2, 9, 10, 21, 27 vdd - 3.3v power supply 22 vdda - p analog circuitry 3.3v power supply 23 vssa - p analog circuitry power supply ground pins. 51, 53 vddc, vddi - p 2.5v power supply ? s 5, 6,14, 17, 24, 35, 41, 47, 48, 56 vss - p - common ground pins. 33, 38, 44 vdds - p - 3.3v power support for sdram clock output drivers. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 17 http://www.cypress.com approved product c9811x2 test mode function test mode functionality sel1 sel0 cpu sdram 3v66 pci 48 mhz ref ioapic 01tclk 2tclk 2tclk 3tclk 6tclk 2 tclk tclk 6 table 2 note : tclk is a test clock over driven on the xin input during test mode. power management functions power management on this device is controlled by a single pin, pd# (pin32). when pd# is high (default) the device is in running and all signals are active. when pd# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3v and 2.5v except for vdda/pin 22) may be removed. when in power down, all outputs are synchronously stopped in a low state (see fig.2 below), all pll ? s are shut off, and the crystal oscillator is disabled. when the device is shutdown the i 2 c function is also disabled. power management timing pd# pci(1:6) cpu(1:3) fig.2 power management current pd# , sel[1..0] (cpu clock) maximum 2.5 volt current consumption (vdd2.5 =2.625) maximum 3.3 volt current consumption (vdd3.3 = 3.465 v) 0xx (power down) 100 a 200 a 110 (66mhz) 70 ma 280 ma 111 (100mhz) 100 ma 280 ma table 3 when exiting the power down mode, the designer must supply power to the vdd pins first, a minimum of 200ms before releasing the pd# pin high.
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 17 http://www.cypress.com approved product c9811x2 clock synchronization and phase alignment this device incorporates ioapic clock synchronization. with this feature, the ioapic clocks are derived from the cpu clock. the ioapic clock lags the cpu clock by the specified 1.5 to 3.5 nsec. figure 3 shows the relationship between the cpu and ioapic clocks. device clock phase relationships fig.3 0ns 10ns 20ns 30ns 40ns 66mhz 100mhz cpu clock sdram clock 3v66 clock pci clock 100mhz 66mhz 33mhz cpu clock 1.5~3.5ns sync 7.5ns 5ns 5ns 2.5ns ioapic clock 33mhz
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 17 http://www.cypress.com approved product c9811x2 power on bi-directional pins power up condition: pin1 is a power up bi-directional pin and is used for selecting the ioapic frequency in page 1, table 1. during power-up of the device, this pin is in input mode (see fig 4, below), therefore; it is considered input select pins internal to the ic. after a settling time, the selection data is latch into the internal control register and this pin becomes a clock output. if strapped low the ioapic clock is set to ? of the pci frequency (16.6 mhz). if strapped high ioapic is 33.3 mhz. - hi-z inputs toggle outputs ower supply amp select data is latched into register then pin becomes a ref clock output signal ref / sel2 (pin 1) vdd rail strapping resistor options: the power up bi-directional pins have a large value pull- up each (250k ?) , therefore, a selection ? 1 ? is the default. if the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external pull-up (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig.5a and b. fig. 5a represents an additional pull up resistor 50k ? connected from the pin to the power line, which allows a faster pull to a high level. if a selection ? 0 ? is desired, then a jumper is placed on jp1 to a 5k ? resistor as implemented as shown in fig.5a. please note the selection resistors (rup and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 5b represent a single resistor 10k ? connected to a 3-way jumper, jp2. when a ? 1 ? selection is desired, a jumper is placed between leads1 and 3. when a ? 0 ? selection is desired, a jumper is placed between leads 1 and 2. load load fig. 5a fig. 5b vdd vdd rup 10k rd imi c9811x2 bidirectional jp1 jumper jp2 3 w ay jumper rsel 10k rd imi c9811x2 bidirectional rdn 10k see description 1 2 3 fig.4
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 17 http://www.cypress.com approved product c9811x2 2-wire smbus control interface the 2-wire control interface implements a write slave only interface according to smbus specification. (see fig. 7 / p. 8). sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. 100 kbits/second (standard mode) data transfer is supported. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is an 8-bit address. w#=0 in write mode. the device will respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. data is transferred msb first at a max rate of 100kbits/s. the device will not respond to any other control interface conditions, and previously set control registers are retained. smbus test circuitry fig.6 note: buffer is 7407 with vcc @ 5.0 v 2.2 k device under test sdata datain sclk dataout clock + 5v + 5v + 5v 2.2 k 2.2 k
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 17 http://www.cypress.com approved product c9811x2 serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up. following the acknowledge of the address byte, two additional bytes must be sent: 1) ? command code ? byte, and 2) ? byte count ? byte. although the data (bits) in these two bytes are considered ? don ? t care ? ; they must be sent and will be acknowledged. after the command code and the count bytes have been acknowledged, the sequence described below (byte 0, byte 1, and byte2) will be valid and acknowledged. byte 0: cpu clock register (1=enable, 0=disable, default=07) bit @pup pin# description 7 0 - reserved 6 0 - reserved 5 0 - reserved 4 0 - reserved 3 0 - spread spectrum mode 2 1 26 usb1 1 1 25 usb0 0 1 49 cpu2_itp byte 2: pci clock register (1=enable, 0=disable, default=fe) bit @pup pin# description 71 20pci7 61 19pci6 51 18pci5 41 16pci4 31 15pci3 21 13pci2 11 12pci1 0 0 - reserved byte 1: sdram clock register (1=enable, 0=disable, default=ff) bit @pup pin# description 7 1 36 sdram7 6 1 37 sdram6 5 1 39 sdram5 4 1 40 sdram4 3 1 42 sdram3 2 1 43 sdram2 1 1 45 sdram1 0 1 46 sdram0 byte 3: reserved register (default=00) byte 4: reserved register (default=00) byte 5: sscg control register (default=00) bit @pup pin# description 7 0 - spread mode (0=down, 1=center) 6 0 - ref. table 4 5 0 - ref. table 4 4 0 - reserved 3 0 - reserved 2 0 - reserved 1 0 - reserved 0 0 - reserved
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 17 http://www.cypress.com approved product c9811x2 0 8 lsb 1 88 command byte (don ? tcare) ack 1 count byte (don ? tcare) ack 10 0 ack sclk ack sdata ack msb byte 0 (valid data) 1 byte n (last valid data) 0 8 continued sdata is output pin stop condition continued start condition sdata is input pin figure 7 smbus communications waveforms test and measurement condition fig.8 - - 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc 0.4v 2.0v 1.25v 2.5v 0v 2.5v signals tdc tr tf probe output under test load cap - -
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 9 of 17 http://www.cypress.com approved product c9811x2 spread spectrum clock generation (sscg) spread spectrum is a modulation technique applied here for maximum efficiency in minimizing electro-magnetic interference radiation generated from repetitive digital signals mainly clocks. a clock accumulates em energy at the center frequency it is generating. spread spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. this technique is achieved by modulating the clock down from (fig.9a) or around the center (fig.9b) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). in this device, spread spectrum is enabled by setting smbus byte0, bit3 = 1. the default of the device at power up keeps the spread spectrum disabled, it is therefore, important to have smbus accessibility to turn- on the spread spectrum function. once the spread spectrum is enabled, the spread bandwidth option is selected by sst(0:2) in smbus byte 5, bits 5, 6 & 7 following tables 4a, and 4b below. in down spread mode the center frequency is shifted down from its rested (non-spread) value by ? of the total spread %. (ex.: assuming the center frequency is 100mhz in non-spread mode; when down spread of ? 0.5% is enabled, the center frequency shifts to 99.75mhz.). in center spread mode, the center frequency remains the same as in the non-spread mode. down spread center spread fig.9a fig.9b spread spectrum selection tables i2c byte5 bit[7:5] center frequency (mhz) spread % 100 66/100 0.25 101 66/100 0.35 110 66/100 0.5 111 66/100 0.7 table 4a i2c byte5 bit[7:5] center frequency (mhz) spread % 000 66/100 - 0.5 001 66/100 - 0.7 010 66/100 - 1.0 011 66/100 - 1.5 table 4b
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 10 of 17 http://www.cypress.com approved product c9811x2 maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65 o c to + 150 o c operating temperature: 0 o c to +85 o c maximum esd protection 2kv maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 11 of 17 http://www.cypress.com approved product c9811x2 ac parameters 66 mhz host 100 mhz host symbol parameter min max min max units notes tperiod host/cpu clk period 15.0 15.5 10.0 10.5 ns 2,7 thigh host/cpu clk high time 5.2 - 3.0 - ns 3 tlow host/cpu clk low time 5.0 - 2.8 - ns 4 edge rate rising edge rate 1.0 4.0 1.0 4.0 v/ns edge rate failing edge rate 1.0 4.0 1.0 4.0 v/ns t rise host/cpu clk rise time 0.4 1.6 0.4 1.6 ns 1 t fall host/cpu clk fall time 0.4 1.6 0.4 1.6 ns 1 tperiod ioapic 33 mhz clk period 30.0 - 30.0 - ns 2,7 thigh ioapic 33 mhz clk high time 12.0 - 12.0 - ns 3 tlow ioapic 33 mhz clk low time 12.0 - 12.0 - ns 4 edge rate rising edge rate 1.0 4.0 1.0 4.0 v/ns edge rate failing edge rate 1.0 4.0 1.0 4.0 v/ns t rise ioapic 33 mhz clk rise time 0.4 1.6 0.4 1.6 ns 1 t fall ioapic 33 mhz clk fall time 0.4 1.6 0.4 1.6 ns 1 tperiod ioapic 16.67 mhz clk period 60.0 64.0 60.00 64.0 ns 2,7 thigh ioapic 16.67 mhz clk high time 25.5 - 25.5 - ns 3 tlow ioapic 16.67 mhz clk low time 25.3 - 25.3 - ns 4 edge rate rising edge rate 1.0 4.0 1.0 4.0 v/ns edge rate failing edge rate 1.0 4.0 1.0 4.0 v/ns t rise ioapic 16.67 mhz clk rise time 0.4 1.6 0.4 1.6 ns 1 t fall ioapic 16.67 mhz clk fall time 0.4 1.6 0.4 1.6 ns 1 tperiod 3v66 clk period 15.0 16.0 15.0 16.0 ns 2,7 thigh 3v66 clk high time 5.25 - 5.25 - ns 3 tlow 3v66 clk low time 5.05 - 5.05 - ns 4 edge rate rising edge rate 1.0 4.0 1.0 4.0 v/ns edge rate failing edge rate 1.0 4.0 1.0 4.0 v/ns t rise 3v66 clk rise time 0.5 2.0 0.5 2.0 ns 1 t fall 3v66 clk fall time 0.5 2.0 0.5 2.0 ns 1
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 12 of 17 http://www.cypress.com approved product c9811x2 ac parameters (cont.) 66 mhz host 100 mhz host symbol parameter min max min max units notes tperiod pci clk period (and 33 mhz ioapic) 30.00 - 30.0 - ns 2,7 thigh pci clk high time (& 33 mhz ioapic) 12.0 - 12.0 - ns 3 tlow pci clk low time (& 33 mhz ioapic) 12.0 - 12.0 - ns 4 edge rate rising edge rate 1.0 4.0 1.0 4.0 v/ns edge rate failing edge rate 1.0 4.0 1.0 4.0 v/ns t rise pci clk rise time (& 33 mhz ioapic) 0.5 2.0 0.5 2.0 ns 1 t fall pci clk fall time (& 33 mhz ioapic) 0.5 2.0 0.5 2.0 ns 1 tperiod sdram clk period 10.0 10.5 10.0 10.5 ns 2,7 thigh sdram clk high time 3.0 - 3.0 - ns 3 tlow sdram clk low time 2.8 - 2.8 - ns 4 edge rate rising edge rate 1.5 4.0 1.5 4.0 v/ns edge rate failing edge rate 1.5 4.0 1.5 4.0 v/ns t rise sdram clk rise time 0.4 1.6 0.4 1.6 ns 1 t fall sdram clk fall time 0.4 1.6 0.4 1.6 ns 1 tjc-c 48 mhz clock cycle to cycle jitter - 500 - 500 ps 2 tpzl,tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns tplz,tpzh output disable delay (all outputs) 1.0 10.0 1.0 10.00 ns tstable all clock stabilization from power-up 3 3 ms 5 notes: 1. output drivers must have monotonic rise/fall times through the specified vol/voh levels. 2. period, jitter, offset and skew measured on rising edge @ 1.25v for 2.5v clocks and @ 1.5v for 3.3v clocks. 3. thigh is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 4. tlow is measured at 0.4v for all outputs. 5. the time specified is measured from when vddq achieves its nominal operating level (typical condition vddq = 3.3v) the frequency output is stable and operating within specification. 6. trise and tfall are measured as a transition through the threshold region vol = 0.4v and voh = 2.0v 7. the average period over any 1 us period of time must be greater than the minimum specified period.
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 13 of 17 http://www.cypress.com approved product c9811x2 output buffer characteristics buffer characteristics for cpu characteristic symbol min typ max units conditions pull-up current ioh 1 13 - - ma vout =vddc - 0.5v pull-up current ioh 2 25 - - ma vout = 1.2 v pull-down current iol 1 11 - - ma vout = 0.4 v pull-down current iol 1 25 - - ma vout = 1.2 v dynamic output impedance z0 13.5 45 ? rise time min between 0.4 and 2.0 v tr 0.4 - - ns 20pf load fall time max between 0.4 and 2.0 v tf - - 1.6 ns 20pf load buffer characteristics for pci and 3v66 characteristic symbol min typ max units conditions pull-up current ioh 1 14 - - ma vout =vddc ? 0.5v pull-up current ioh 2 35 - - ma vout = 1. 5 v pull-down current iol 1 13 - - ma vout = 0.4 v pull-down current iol 1 40 - - ma vout = 1.5 v dynamic output impedance z0 12 55 ? rise time min between 0.4 and 2.4 v tr 0.5 - - ns 30pf load fall time max between 0.4 and 2.4 v tf - - 2.0 ns 30pf load buffer characteristic s for usb (0:1) and ref characteristic symbol min typ max units conditions pull-up current ioh 1 6 - - ma vout =vdd - 1.0 v pull-up current ioh 2 15 - - ma vout = 1. 5 v pull-down current iol 1 6 - - ma vout = 0.4 v pull-down current iol 1 22 - - ma vout = 1.5 v dynamic output impedance z0 20 60 ? rise time min between 0.4 and 2.4 v tr 0.4 - - ns 20pf load fall time max between 0.4 and 2.4 v tf - - 4.0 ns 20pf load
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 14 of 17 http://www.cypress.com approved product c9811x2 output buffer characteristics (cont.) buffer characteristics for ioapic characteristic symbol min typ max units conditions pull-up current ioh 1 13 - - ma vout =vddi - 0.5v pull-up current ioh 2 25 - - ma vout = 1. 0 v pull-down current iol 1 11 - - ma vout = 0.4 v pull-down current iol 1 25 - - ma vout = 1.4 v dynamic output impedance z0 13.5 45 ? rise time min between 0.4 and 2.0 v tr 1.0 - - ns 20pf load fall time max between 0.4 and 2.0 v tf - - 1.6 ns 20pf load buffer characteristics for sdram characteristic symbol min typ max units conditions pull-up current ioh 1 19 - - ma vout =vdd - 1. 0 v pull-up current ioh 2 62 - - ma vout = 1. 4 v pull-down current iol 1 18 - - ma vout = 0.4 v pull-down current iol 1 59 - - ma vout = 1.5 v dynamic output impedance z0 10 24 ? rise time min between 0.4 and 2.4 v tr 0.4 - - ns 30pf load fall time max between 0.4 and 2.4 v tf - - 1.33 ns 30pf load vdd=vdds=3.3v 5%, vddc=vddi=2.5 5%, ta=0 to 70 o c
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 15 of 17 http://www.cypress.com approved product c9811x2 suggested crystal oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant, note 1 load capacitance cl - 18 - pf the crystal ? s rated load. note 1 effective series resistance (esr) r1 - 40 - ohms note 1 power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystal ? s internal package capacitance (total) note1: for best performance and accurate center frequencies of this device, it is recommended but not mandatory that the chosen crystal meets these specifications for maximum accuracy, the total circuit loading capacitance should be equal to cl. this loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations device pin capacitance: cxtal = 36pf in order to meet the specification for cl = 18 p f following the formula: then the board trace capacitance between xin and the crystal should be no more than 2pf. (same is applicable to the trace between xout and the crystal) in this case the total capacitance from the crystal to xin will be 36pf. similarly the total capacitance between the crystal a nd xout will be 36pf. hence using the above formula: xout xin xout xin l c c xc c c + = pf pf pf pf pfx c l 18 36 36 36 36 = + =
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 16 of 17 http://www.cypress.com approved product c9811x2 package drawing and dimensions 56 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.088 0.090 0.092 2.24 2.29 2.34 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 - 0.010 0.127 - 0.254 d .720 .725 .730 18.29 18.42 18.54 e 0.292 0.296 0.299 7.42 7.52 7.59 e 0.025 bsc 0.635 bsc h 0.400 0.406 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 l 0.024 0.032 0.040 0.61 0.81 1.02 a0 o 5 o 8 o 0 o 5 o 8 o x 0.085 0.093 0.100 2.16 2.36 2.54 ordering information part number package type production flow C9811X2AYB 56 pin ssop commercial, 0 to 70 o c marking: example: cypress c9811x2 date code, lot # C9811X2AYB flow b = commercial, 0 to 70 o c package y = ssop revision device number notice cypress semiconductor corporation reserves the right to change or modify the information contained in this data sheet, without notice cypress semiconductor corporation does not assume any liability arising out of the application or use of any product or circuit described herein. cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others cypress semiconductor corporation does not authorize its products for use as critical components in life-support systems or critical medical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user. b e a a 1 a 2 e a l c d h
low emi clock generator for intel ? 810 chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07052 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 17 of 17 http://www.cypress.com approved product c9811x2 document title: c9811x2 low emi clock generator for intel ? 810 chipset systems document number: 38-07052 rev. ecn no. issue date orig. of change description of change ** 107060 06/11/01 ika convert from imi to cypress

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