 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| te ch tm t81l0006a/b tm technology inc. reserves the right p. 1 publication date: aug. 2005 to change products or specifications without notice. revsion : b mcu 8-bit a/d type mcu 1. features compatible with mcs-51 embedded 8k bytes otp rom 128 x 8-bit internal ram 15/19 programmable i/o lines for 20/24-pin package two 16-bit timer/counter & one 16-bit timer two external interrupt input (only one input for 20-pin package) two channel pwm (only one channel pwm for 20-pin package) driving capability up to 40 ma embedded 1k bits eeprom (for t81l0006b only) programmable serial uart interface low power idle & power-down modes watch-dog timer on-chip crystal & rc oscillator (selected by bonding option) internal power-on reset and external reset supported 8-channel 8-bit a/d converter sop20/dip20 & sop24/dip24 package 3.3v operating voltage eeporm interface low voltage reset 2. applications meter household appliances controller handwriting board charger sport devices other controller (automotive, toy?) 3. general description the t81l0006a/b is 8-bit microcontroller designed and developed with low power and high speed cmos technology. it contains a 8k bytes otp rom, a 128 8 ram, an 8-channels 8-bit a/d converter, 15/19 i/o lines, a watchdog timer, two 16-bit counter/timers, a seven source, two-priority level nested interrupt structure, two channel pulsed-width modulator (pwm), a full duplex uart, and an on-chip oscillator and clock circuits. in addition, the t81l0006a/b has two selectable modes of power reduction-idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. 4. order information part number oscillator type eeprom package t81l0006a-ak rc none 24-pin dip t81l0006a-bk crystal none 24-pin dip t81l0006a-ck rc none 20-pin dip t81l0006a-dk crystal none 20-pin dip t81l0006a-ad rc none 24-pin sop t81l0006a-bd crystal none 24-pin sop t81l0006a-cd rc none 20-pin sop t81l0006a-dd crystal none 20-pin sop t81l0006b-ak rc embedded 24-pin dip t81l0006b-bk crystal embedded 24-pin dip T81L0006B-AD rc embedded 24-pin sop t81l0006b-bd crystal embedded 24-pin sop
te ch tm t81l0006a/b tm technology inc. reserves the right p. 2 publication date: aug. 2005 to change products or specifications without notice. revsion : b 5. block diagram port 1 drivers ram addr. register ram port 1 latch otp rom b register acc stack pointer tmp2 tmp1 alu psw interrupt, serial port, and timer block timing & control instruction register port 3 latch port 3 drivers program address register buffer pc incrementer program counter dptr p1.0 -p1.7 p3.0 -p3.7 rst osc wdt pwm port 2 drivers adc port 2 latch p2.0 p2.3 p2.1 xtal2 xtal1 eeprom interface eeprom te ch tm t81l0006a/b tm technology inc. reserves the right p. 3 publication date: aug. 2005 to change products or specifications without notice. revsion : b 6. pin configuration (txd) p3.1 (rxd) p3.0 (adi0) p1.0 1 2 3 22 24 23 (t1) p3.5 (t0) p3.4 osc-r 19 21 20 stop rst/vpp vcc 16 18 17 p2.1 (vref) p3.7 (pwm2) p2.0 13 15 14 (pwm1) p3.6 (int0) p3.2 (adi7) p1.7 (int1) p3.3 (adi1) p1.1 gnd 4 5 6 (adi2) p1.2 p2.3 (adi3) p1.3 7 8 9 (adi5) p1.5 (adi4) p1.4 (adi6) p1.6 10 11 12 dip-24/sop-24 for rc oscillator t81l0006a-ak/ t81l0006a-ad t81l0006b-ak/ T81L0006B-AD (txd) p3.1 (rxd) p3.0 (adi0) p1.0 1 2 3 22 24 23 (t1) p3.5 (t0) p3.4 xin 19 21 20 xout rst/vpp vcc 16 18 17 p2.1 (vref) p3.7 (pwm2) p2.0 13 15 14 (pwm1) p3.6 (int0) p3.2 (adi7) p1.7 (int1) p3.3 (adi1) p1.1 gnd 4 5 6 (adi2) p1.2 p2.3 (adi3) p1.3 7 8 9 (adi5) p1.5 (adi4) p1.4 (adi6) p1.6 10 11 12 dip-24/sop-24 for crystal oscillator t81l0006a-bk/ t81l0006a-bd t81l0006b-bk/ t81l0006b-bd (txd) p3.1 (rxd) p3.0 (adi0) p1.0 1 2 3 (t1) p3.5 (t0) p3.4 osc-r 19 20 stop rst/vpp vcc 16 18 17 (vref) p3.7 13 15 14 (pwm1) p3.6 (int0) p3.2 (adi7) p1.7 (adi1) p1.1 gnd 4 5 6 (adi2) p1.2 (adi3) p1.3 7 8 9 (adi5) p1.5 (adi4) p1.4 (adi6) p1.6 10 11 12 dip-20/sop-20 for rc oscillator t81l0006a-ck/ t81l0006a-cd (txd) p3.1 (rxd) p3.0 (adi0) p1.0 1 2 3 (t1) p3.5 (t0) p3.4 xin 19 20 xout rst/vpp vcc 16 18 17 (vref) p3.7 13 15 14 (pwm1) p3.6 (int0) p3.2 (adi7) p1.7 (adi1) p1.1 gnd 4 5 6 (adi2) p1.2 (adi3) p1.3 7 8 9 (adi5) p1.5 (adi4) p1.4 (adi6) p1.6 10 11 12 dip-20/sop-20 for crystal oscillator t81l0006a-dk/ t81l0006a-dd te ch tm t81l0006a/b tm technology inc. reserves the right p. 4 publication date: aug. 2005 to change products or specifications without notice. revsion : b 7. pin description 8. temperature limit ratings parameter rating units operating temperature range -40 to +85 c storage temperature range -55 to +125 c number (24-pin) number (20-pin) name type description 1 1 p3.0/(rxd) i/o general-purpose i/o pin (default) or serial input port. 2 2 p3.1/(txd) i/o general-purpose i/o pin (default) or serial output port. 3 3 p1.0/(adi0) i/o general-purpose i/o pin (default) or adc input channel 0. 4 4 p1.1/(adi1) i/o general-purpose i/o pin (default) or adc input channel 1. 5 - p3.3/(int1) i/o general-purpose i/o pin (default) or external interrupt source 1. 6 5 gnd ground 7 - p2.3 i/o general-purpose i/o pin. 8 6 p1.2/(adi2) i/o general-purpose i/o pin (default) or adc input channel 2. 9 7 p1.3/(adi3) i/o general-purpose i/o pin (default) or adc input channel 3. 10 8 p1.4/(adi4) i/o general-purpose i/o pin (default) or adc input channel 4. 11 9 p1.5/(adi5) i/o general-purpose i/o pin (default) or adc input channel 5. 12 10 p1.6/(adi6) i/o general-purpose i/o pin (default) or adc input channel 6. 13 11 p1.7/(adi7) i/o general-purpose i/o pin (default) or adc input channel 7. 14 12 p3.2/(int0) i/o general-purpose i/o pin (default) or external interrupt source 0. 15 13 p3.6/(pwm1) i/o general-purpose i/o pin (default) or pwm signal output channel 1. 16 - p2.0/(pwm2) i/o general-purpose i/o pin (default) or pwm signal output channel 2. 17 14 p3.7/(vref) i/o general-purpose i/o pin (default) or external reference voltage input pin for adc. 18 - p2.1 i/o general-purpose i/o pin. 19 15 vcc 3.3v power supply. 20 16 rst/vpp i reset signal input or programming supply voltage input. 21 17 xout/(stop) o crystal oscillator output terminal or stop rc oscillator network. 22 18 xin/(osc-r) i crystal oscillator input terminal or rc oscillator external resister connect pin. 23 19 p3.4/(t0) i/o general-purpose i/o pin (default) or timer 0 external input pin. 24 20 p3.5/(t1) i/o general-purpose i/o pin (default) or timer 1 external input pin. te ch tm t81l0006a/b tm technology inc. reserves the right p. 5 publication date: aug. 2005 to change products or specifications without notice. revsion : b 9. electrical characteristics d.c characteristics symbol parameter conditions min typ max units v cc operating voltage 25c 3.0 3.3 3.6 v i cc operating current no load, adc disable vcc=3.3v - 6 - ma i pd power-down current no load, vcc=3.3v 1 ua i adc only adc enable, others disable no load - 120 - ua v adc adc input voltage range 0 - v ref v v ref v ref input voltage range 2 - v cc v v ih hi-level input voltage v out >=v voh(min.) v out <=v vol(min.) 2.1 - - v v il low-level input voltage v out >=v voh(min.) v out <=v vol(min.) - - 0.6 v i oh =-7ua 2.9 i oh =-45ua 2.4 i oh =-70ua 1.9 i oh =-12ma** 2.4 v oh hi-level output voltage v cc =min. v i =v ih or v il i oh =-20ma** 1.9 - - v i ol =12ma 0.2 i ol =25ma 0.4 v ol 1 * low-level output voltage v cc =min. v i =v ih or v il i ol =40ma - - 0.6 v i ol =4ma 0.2 i ol =12ma 0.4 v ol 2 ** low-level output voltage v cc =min. v i =v ih or v il i ol =20ma 0.6 v note : * for pwm pins (p3.6/pwm1 and p2.0/pwm2). ** for high driving current mode. a.c characteristics symbol parameter conditions min typ max units f sys1 system clock 1 (crystal osc) v cc =3.3v - 12 24 mhz f sys2 system clock 2 (rc osc) v cc =3.3v - 12 - mhz f adc adc clock frequency - 125 - khz t act adc conversion time - 128 us t res external reset high pulse width - 10 - system cycle t pos power on start up time - 20 - ms t lhll ale pulse width 127 - - ns t avll address valid to ale low 43 - - ns t llax address hold after ale low 48 - - ns t lliv ale low to valid instruction in - - 233 ns t llpl ale low to psen low 43 - - ns t plph psen pulse width 205 - - ns t pliv psen low to valid instruction in - - 145 ns t aviv address to valid instruction in - - 312 ns t rlrh rd pulse width 400 - - ns t wlwh wr pulse width 400 - ns t rldv rd low to valid data in - - 252 ns t lldv ale low to valid data in - - 517 ns t avdv address to valid data in - - 585 ns t llwl ale low to rd or wr low 200 - 300 ns t avwl address to rd or wr low 203 - - ns t whlh rd or wr high to ale high 43 - 123 ns te ch tm t81l0006a/b tm technology inc. reserves the right p. 6 publication date: aug. 2005 to change products or specifications without notice. revsion : b 10. function description 10.1 reset for power on reset only for power on reset and external reset 10.2 oscillation rc oscillator crystal oscillator t81l0006a/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p30 p31 p10 p11 p33 vss p23 p12 p13 p14 p15 p16 p17 p32 p36 p20 p37 p21 vcc rst xout xin p34 p35 vcc t81l0006a/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p30 p31 p10 p11 p33 vss p23 p12 p13 p14 p15 p16 p17 p32 p36 p20 p37 p21 vcc rst xout xin p34 p35 8.2k 51k t81l0006a/b-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p30 p31 p10 p11 p33 vss p23 p12 p13 p14 p15 p16 p17 p32 p36 p20 p37 p21 vcc rst stop oscr p34 p35 t81l0006a/b-b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p30 p31 p10 p11 p33 vss p23 p12 p13 p14 p15 p16 p17 p32 p36 p20 p37 p21 vcc rst xout xin p34 p35 22p 2.2m y1 22p te ch tm t81l0006a/b tm technology inc. reserves the right p. 7 publication date: aug. 2005 to change products or specifications without notice. revsion : b 10.3 special function register f8h f0h b e8h e0h acc d8h d0h psw c8h t2con t2mod rcap2l rcap2h tl2 th2 c0h b8h ip b0h p3 a8h ie a0h p2 98h scon sbuf 90h p1 88h tcon tmod tl0 tl1 th0 th1 80h p0* sp dpl dph wdrel pcon *note: p0:internal still keeping, but for pad dominate, no external pin assignment accumulator : acc acc is the accumulator register. the mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as a. b register : b the b register is used during multiply and divide operations. for other instructions it can be treated as another scratch pad register. program status word : psw the psw register contains program status information as detailed in cy ac f0 rs1 rs0 ov -- p bit symbol function psw.7 cy carry flag. psw.6 ac auxiliary carry flag. (for bcd operations.) psw.5 f0 flag 0. (available to the user for general purposes.) psw.4 rs1 register bank select control bit 1. set/cleared by software to determine working register bank. (see note. ) psw.3 rs0 register bank select control bit 0. set/cleared by software to determine working register bank. (see note. ) psw.2 ov overflow flag. psw.1 ? user-definable flag. psw.0 p parity flag. set/cleared by hardware each instruction cycle to indicate an odd/even number of ?one? bits in the accumulator, i.e., even parity. note : the contents of (rs1, rs0) enable the working register banks as follows: (0,0)? bank 0 (00h?07h) (0,1)? bank 1 (08h?0fh) (1,0)? bank 2 (10h?17h) (1,1)? bank 3 (18h?17h) te ch tm t81l0006a/b tm technology inc. reserves the right p. 8 publication date: aug. 2005 to change products or specifications without notice. revsion : b stack pointer : sp the stack pointer register is 8 bits wide. it is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at locations 08h. data pointer (dptr) : dph & dpl the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). its intended function is to hold a 16-bit address. it may be manipulated as a 16-bit register or as two independent 8-bit registers. ports 1.0~1.7 & 2.0,2.1,2.3 & 3.0~3.7 all ports are the sfr latches, respectively. writing a one to a bit of a port sfr (p1 or p2 or p3) causes the corresponding port output pin to switch high. writing a zero causes the port output pin to switch low. when used as an input, the external state of a port pin will be held in the port sfr (i.e., if the external state of a pin is low, the corresponding p ort sfr bit will contain a ?0?; if it is high, the bit will contain a ?1?). serial data buffer : sbuf the serial buffer is actually two separate registers, a transmit buffer and a receive buffer. when data is moved to sbuf, it goes to the transmit buffer and is held for serial transmission. (moving a byte to sbuf is what initiates the transmission.) when data is moved from sbuf, it comes from the receive buffer. timer registers : th0, tl0, th1, tl1,th2,tl2 register pairs (th0, tl0) and (th1, tl1) and (th2, tl2) are 16-bit counting registers for timer/counters 0 and timer1and timer2, respectively. . control register : ip, ie, tmod, tcon, scon, pcon special function registers ip, ie, tmod, tcon, scon, and pcon contain control and status bits for the interrupt system, the timer/counters, and the serial port. they are described in later sections. standard serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn?t been read by the time reception of the second byte is complete, one of the bytes will be lost.) the ser ial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destinatio n register. reception is initiated in mode 0 by the condition ri = ?0? and ren = ?1?. reception is initiated in the other modes by the incoming start bit if ren = ?1?. te ch tm t81l0006a/b tm technology inc. reserves the right p. 9 publication date: aug. 2005 to change products or specifications without notice. revsion : b multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9 th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = ?1?. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is ?1? in an address byte and ?0? in a data byte. with sm2 = ?1?, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren?t being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, in mode 1 can be used to check the validity of the stop bit. in mode 1 reception, if sm2 = ?1?, the receive interrupt will not active unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 11. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial por t interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12. the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = ?0? (which is the value on reset), the baud rate is 1/64 the oscillator frequency. if smod = ?1?, the baud rate is 1/32 the oscillator frequency. mode 2 baud rate =2 smod /64* (oscillator frequency) in the t81l0006a/b, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. scon msb lsb sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc / 12 0 1 1 8-bit uart variable 1 0 2 9-bit uart uart f osc /64 or f osc /32 1 1 3 9-bit uart variable using timer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate =2 smod /32* (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer 1 itself can be configured for either ?timer? or ?counter? operation, and in any of its 3 running modes. in the most typical applications, it is configured for ?timer? operatio n, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate =2 smod *(oscillator frequency)/ 32/12 / [256 _ (th1)] one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. using timer 2 to generate baud rates timer2 is selected as the baudrate generator by setting tclk and/or rclk in t2con register as followed. t2con ( address : c8h) msb lsb tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 t2con.7: tf2 timer2 overflow flag set by timer2 overflow and must be cleared by software. tf2 will not be set when either rclk=1 or tclk=1. t2con.6: exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2=1. when timer2 interrupt is enabled, exf2=1 will cause the cpu to vector to the timer2 interrupt routine. exf2 must be cleared by software. t2con.5: rclk receive clock flag. when set, cause the serial port to use timer2 overflow pulses for its receive clock in te ch tm t81l0006a/b tm technology inc. reserves the right p. 10 publication date: aug. 2005 to change products or specifications without notice. revsion : b mode 1 and 3. rclk=0 causes timer1 overflow to be used for the receive clock t2con.4: tclk transmit clock flag. when set, cause the serial port to use timer2 overflow pulses for its transmit clock in mode 1 and 3. tclk=0 causes timer1 overflow to be used for the transmit clock t2con.3: exen2 timer2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer2 is not being used to clock the serial port. exen2=0 causes timer2 to ignore events at t2ex. t2con.2: start/stop control for timer2. a logic 1 starts the timer t2con.1: timer or counter select. (timer 2) , 0 as internal timer t2con.0: capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2=1. when cleared, auto reloads will occur either with timer2 overflow or negative transitions at t2ex when exen2=1. when either rclk=1 or tclk=1, this bit is ignored and the timer is forced to auto-reload on timer2 overflow. note then the baudrates for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer2 into its baudrate generator mode. the baudrate generator mode is similar to the auto reload mode, in that a rollover is th2 causes the timer2 registers to be reload with the 16 bit value in registers rcap2h and rcap2l, which are preset by software given by the formula. baudrate= (timer2 overflow rate)/16 =(oscillator frequency) / (32*(65536-(rcap2h,rcap2l))) serial interface timing diagram s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 ale d0 d1 d2 d3 d4 d5 d6 d7 rxd txd d0 d1 d2 d3 d4 d5 d6 d7 rxd txd receive shift write to scon, clear ri ri receive write to sbuf send shift serial port mode 0 transmit te ch tm t81l0006a/b tm technology inc. reserves the right p. 11 publication date: aug. 2005 to change products or specifications without notice. revsion : b tx clock d0 d1 d2 d3 d4 d5 d6 d7 txd ti shift ri receive write to sbuf send shift serial port mode 1 transmit stop bit data start bit rx clock d0 d1 d2 d3 d4 d5 d6 d7 rxd stop bit start bit tx clock d0 d1 d2 d3 d4 d5 d6 d7 txd ti shift ri receive write to sbuf send shift serial port mode 2 transmit stop bit data start bit rx clock d0 d1 d2 d3 d4 d5 d6 d7 rxd stop bit start bit tb8 tb8 te ch tm t81l0006a/b tm technology inc. reserves the right p. 12 publication date: aug. 2005 to change products or specifications without notice. revsion : b interrupt enable register : ie msb lsb ea wdt et2 es et1 ex1 et0 ex0 ea ie.7 disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. wdt ie.6 watchdog timer refresh flag. et2 ie.5 enable or disable the timer 2 overflow interrupt. es ie.4 enable or disable the serial port interrupt. et1 ie.3 enable or disable the timer 1 overflow interrupt. ex1 ie.2 enable or disable external interrupt 1. (see note ) et0 ie.1 enable or disable the timer 0 overflow interrupt. ex0 ie.0 enable or disable external interrupt 0. note : if a/d converter interrupts enabled, ex1 interrupt function will be replaced. tx clock d0 d1 d2 d3 d4 d5 d6 d7 txd ti shift ri receive write to sbuf send shift serial port mode 3 transmit stop bit data start bit rx clock d0 d1 d2 d3 d4 d5 d6 d7 rxd stop bit start bit tb8 tb8 te ch tm t81l0006a/b tm technology inc. reserves the right p. 13 publication date: aug. 2005 to change products or specifications without notice. revsion : b watchdog timer the watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. after an external reset the watchdog timer is disabled and all registers are set to zeros. watchdog timer structure the watchdog consists of 16-bit counter wdt , reload register wdtrel , prescalers by 2 and by 16 and control logic. where wdtl=00h while start up. figure watchdog block diagram start procedure there are one way to start the watchdog. a programmer can start the watchdog as refreshing procedure. once the watchdog is started it cannot be stopped unless rst signal becomes active. when wdt registers enters the state 7ffch, asynchronous wdts signal will become active. the signal wdts sets the bit 6 in ip0 register and requests reset state. the wdts is cleared either by rst signal or change of the state of the wdt timer. procedure: load wdtrel value set ?wdt? set ?swdt? in 12 instruction cycles. refreshing the watchdog timer the watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. this requirement imposes obligation on the programmer to issue two followed instructions. the first instruction sets wdt and the second one swdt . the maximum allowed delay between settings of the wdt and swdt is 12 instruction cycles. while this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt is automatically reset. the procedure is as ?start procedure? before. te ch tm t81l0006a/b tm technology inc. reserves the right p. 14 publication date: aug. 2005 to change products or specifications without notice. revsion : b special function registers a) interrupt enable 0 register (ien0) the ien0 register (address : a8) msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 the ien0 bit functions bit symbol function ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set directly before swdt is set to prevent an unintentional refresh of the watchdog timer. the wdt is reset by hardware 12 instruction cycles after it has been set. note: other bits are not used to watchdog control b) interrupt enable 1 register (ien1) the ien1 register (address : b8) msb lsb - swdt pt2 ps pt1 px1 pt0 px0 the ien1 bit functions bit symbol function ien1.6 swdt watchdog timer start refresh flag. set to active/refresh the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. bit swdt is reset by hardware 12 instruction cycles after it has been set. pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. ie. watch dog timer status flag. set by hardware when the watchdog timer was started. d) watchdog timer reload register (wdtrel) the wdtrel register ( address : 86 ) msb lsb 7 6 5 4 3 2 1 0 the wdtrel bit functions bit symbol function wdtrel.7 7 prescaler select bit. when set, the watchdog is clocked through an additional divide-by-16 prescaler wdtrel.6 t0 wdtrel.0 6-0 seven bit reload value for the high-byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt the wdtrel register can be loaded and read any time te ch tm t81l0006a/b tm technology inc. reserves the right p. 15 publication date: aug. 2005 to change products or specifications without notice. revsion : b wdt reset a high on reset pin or watchdog reset request for two clock cycles while the oscillator is running resets the device. diagram b) watchdog timer reset 7ffbh 7ffch 0000h figure watchdog reset timing **note : clk: external clock input tclk: clock period wdt: watchdog timer registers wdts: watchdog timer status flag reset: external reset input rst: internally generated reset signal reset time formula reset time=(7ffch-wdth.wdtl)*presc*48/clockfrequency while presc=16 if wdtrel.7=1, presc=1 if wdtrel.7=0. for example if you use frequency clock=12mhz, wdtrel=10111111b which means wdtrel.7=1 and wdth=3fh then reset time= (7ffch-3f00h)*48/12m=66544 us te ch tm t81l0006a/b tm technology inc. reserves the right p. 16 publication date: aug. 2005 to change products or specifications without notice. revsion : b 10.4 external register table ( for a/d converter , pwm, eeprom & lvr) note : * lvr (low voltage reset) address : 802bh, read/write msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 lvr[7] lvr[6] pwm control register2 lvr[7] : if lvr[7] write ?1?, low voltage reset function enable. default is ?0?, low voltage reset function disable. lvr[6] : if lvr[6] write ?1?= 2.1v reset. if lvr[6] write ?0?= 2.8v reset. default is ?0?= 2.8v reset. ** port i/o high driving set if write ?0? = set i/o to high driving current mode. if write ?1? = set i/o to normal driving current mode. default is set ?1?. port 3 high driving address : 8030h msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 port3.7 port3.6 port3.5 port3.4 port3.3 port3.2 port3.1 port3.0 port 2 high driving address : 8031h msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 port2.3 port2.1 port2.0 port 1 high driving address : 8032h msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 port1.7 port1.6 port1.5 port1.4 port1.3 port1.2 port1.1 port1.0 register address (a15?a5-a0) hex name comments 100? 0010 0000 8020h adm a/d control & status 100? 0010 0001 8021h adr a/d clock prescaler and a/d value lsb 100? 0010 0010 8022h adb a/d value msb 100? 0010 1010 802ah ade a/d converter channel enable 100? 0010 0101 8025h pwmc1 pwm control register1 100? 0010 1011 802bh pwmc2 pwm control register2 and lvr(low voltage reset)* 100? 0010 0110 8026h pwm1 pwm1 value 100? 0010 0111 8027h pwm2 pwm2 value 100? 00101000 8028h spicon eeprom control & setup (for t81l0006b only) 100? 0010 1001 8029h opcode eeprom opcode (for t81l0006b only) 100? 0010 1110 802eh dataw_h eeprom write high byte (for t81l0006b only) 100? 0010 1111 802fh dataw_l eeprom write low byte (for t81l0006b only) 100? 0010 1100 802ch datar_h eeprom read high byte (for t81l0006b only) 100? 0010 1101 802dh dataw_l eeprom read high byte (for t81l0006b only) 100? 0011 0000 8030h port3 hds port3 i/o high driving set** 100? 0011 0001 8031h port2 hds port2 i/o high driving set** 100? 0011 0010 8032h port1 hds port1 i/o high driving set** te ch tm t81l0006a/b tm technology inc. reserves the right p. 17 publication date: aug. 2005 to change products or specifications without notice. revsion : b 10.5 a/d converter the data acquisition component is an 8-bit analog-to-digital converter, 8-channel multiplexer and microcontroller compatible control logic. the 8-bit a/d converter uses successive approximation conversion technique. the 8-channel multiplexer can directly access any of 8-single-ended analog signals. the device eliminates the need for external zero and full-scale adjustments. the design of the component has been optimized by incorporating the most desirable aspects of several a/d conversion techniques. the component offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. these features make this device ideally suitable from process and machine control to consumer applications. a/d converter register control adenb disable all a/d converter input channels: 0-disable, 1-enable if adenb=0, all input channel will be closed. if adenb =1, each input channels is individually enabled or disabled by setting or clearing ench7~ench0 enable bits. adi a/d interrupt bit: 0-disable, 1-enable if adi=1, external interrupt 1 will be inhibited. a/d converter interrupt function will in place of external interrupt 1 function. ads a/d start bit: 0-stop, 1-start eoc a/d status bit: 0- busy, 1-end of converting and clear ads bit chs2: chs0 --- channel select adps2: adps0 ---a/d clock divider, input frequency = f osc /3 adps2:1:0 dividers ratio fad: fosc/12 000 1:1 001 1:2 010 1:4 011 1:8 100 1:16 101 1:32 110 1:64 111 1:128 adb7 ~adb0--- 8-bit adc converting data ench7 ~ench0 --- adc individual input channel enable bit: 0-disable, 1-enable default r/w r/w r r/w - r/w r/w r/w adm 00100000 adenb ads eoc adi - chs2 chs1 chs0 default - r/w r/w r/w - - - - adr x010xxxx - adps2 adps1 adps0 - - - - default r r r r r r r r adb xxxxxxxx adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 default r/w r/w r/w r/w r/w r/w r/w r/w ade 00000000 ench7 ench6 ench5 ench4 ench3 ench2 ench1 ench0 te ch tm t81l0006a/b tm technology inc. reserves the right p. 18 publication date: aug. 2005 to change products or specifications without notice. revsion : b a/d converter conversion flow a/d converter timing diagram 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 16 rb adclk ads chs[2:0] an[7:0] eoc pcha d[7:0] 10 adclk < time < 16 adclk 16 adclk 5 adclk 1.5 adclk set adenb=1 set ench7~ench0 (enable individually channel ) set chs[2:0] register bit ( chose adc in p ut channel ) when set (ads register )bit=1, and then (eoc register) bit will b e turn low. microcontroller generate ads signal pulse to adc. 1?adclk te ch tm t81l0006a/b tm technology inc. reserves the right p. 20 publication date: aug. 2005 to change products or specifications without notice. revsion : b 10.7 eeprom interface (for t81l0006b only) the eeprom interface timing is fully compatible with 93c46. to access or send data from/to t81l0006b , 6 registers are going to be controlled. eeprom register control default -- -- -- -- -- b2: r/w b1: r/w b0: r/w spicon 00h -- -- -- -- -- epdiv1 epdiv0 epst w opcode 00h - - - - - - - dataw_h dataw_l 00h datar_h dataw_l 00h spicon: msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 epdiv1 epdiv0 epst epst: start eeprom timing. ?1? to start and will be auto cleared after timing finish. epdiv[1..0]: divide input clock into eeprom system clock. 10: divide by 64 01: divide by 32 else: divide by 16 opcode msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 op code address instruction set op code address input data read 10 a5-a0 wen (write enable) 00 11xxxx write 01 a5-a0 d15-d0 wrall (write all registers) 00 01xxxx d15-d0 wds (write disable) 00 00xxxx erase 11 a5-a0 eral 00 10xxxx te ch tm t81l0006a/b tm technology inc. reserves the right p. 21 publication date: aug. 2005 to change products or specifications without notice. revsion : b 11. i/o ports port1 port 1 is an 8-bit bi-directional i/o port with internal pull-ups. port 1 output buffers can sink/source four external ttl device inputs. when port 1 pins are written as 1?s, these pins are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current because of the internal pull-ups. port 1 also serves the analog signal input of a/d converter, as listed below: p1.0 adi0 (analog input signal channel 0) p1.1 adi1 (analog input signal channel 1) p1.2 adi2 (analog input signal channel 2) p1.3 adi3 (analog input signal channel 3) p1.4 adi4 (analog input signal channel 4) p1.5 adi5 (analog input signal channel 5) p1.6 adi6 (analog input signal channel 6) p1.7 adi7 (analog input signal channel 7) port2.0, 2.1, 2.3 port2.0, 2.1, 2.3 are a bi-directional i/o port with internal pull-ups. port2.0, 2.1, 2.3 output buffers can sink/source four external ttl device inputs. when port2.0, 2.1, 2.3 pins are written as 1?s, these pins are pulled high by the internal pull-ups and can be used as inputs. as inputs, port2.0, 2.1, 2.3 pins that are externally being pulled low will source current because o f the internal pull-ups. port 2.0 also serves the output signal of pwm 2. port 3 port 3 is an 8-bit bi-directional i/o port with internal pull-ups. port 3 output buffers can sink/source four external ttl device inputs. when port 3 pins are written as 1?s, these pins are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the internal pull-ups. port 3 also serves the functions of various special features, as listed below: p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 pwm1 (pwm 1 signal output) p3.7 vref (external reference voltage input for adc) |
Price & Availability of T81L0006B-AD
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |