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ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 1 dr021-0a 08/11/2001 document title 256kx16 bit dynamic ram with fast page mode revision history revision no history draft date remark 0a initial draft august 11,2001 the attached datasheets are provided by icsi. integrated circuit solution inc reserve the right to change the specifications a nd products. icsi will answer to your questions about device. if you have any questions, please contact the icsi offices.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 2 integrated circuit solution inc. dr021-0a 08/11/2001 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. features ? fast access and cycle time ? ttl compatible inputs and outputs ? refresh interval: 512 cycles/8 ms ? refresh mode: ras -only, cas -before- ras (cbr), hidden ? self refresh mode: 512 cycles/64 ms (s version only) ? jedec standard pinout ? single power supply: ? 5v 10% (ic41c16257) ? 3.3v 10% (ic41lv16257) ? byte write and byte read operation via two cas ? available in 40-pin soj and tsop-2 description the icsi ic41c16257 and the ic41lv16257 are 262,144 x 16-bit high-performance cmos dynamic random access memory. fast page mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. the byte write control, of upper and lower byte, makes these devices ideal for use in 16-, 32-bit wide data bus systems. these features make the ic41c16257 and the ic41lv16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. the ic41c16257 and the ic41lv16257 are packaged in a 40-pin, 400mil soj and tsop-2. 256k x 16 (4-mbit) dynamic ram with fast page mode pin descriptions a0-a8 address inputs i/o0-i/o15 data inputs/outputs we write enable oe output enable ras row address strobe ucas upper column address strobe lcas lower column address strobe vcc power gnd ground nc no connection 40-pin soj pin configurations 40-pin tsop-2 key timing parameters parameter -35 -50 -60 unit max. ras access time (t rac )355060ns max. cas access time (t cac )101415ns max. column address access time (t aa )182530ns min. fast page mode cycle time (t pc )122025ns min. read/write cycle time (t rc ) 60 90 110 ns
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 3 dr021-0a 08/11/2001 functional block diagram
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 4 integrated circuit solution inc. dr021-0a 08/11/2001 truth table function ras ras ras ras ras lcas lcas lcas lcas lcas ucas ucas ucas ucas ucas we we we we we oe oe oe oe oe address t r /t c i/o standby h h h x x x high-z read: word l l l h l row/col d out read: lower byte l l h h l row/col lower byte, d out upper byte, high-z read: upper byte l h l h l row/col lower byte, high-z upper byte, d out write: word (early write) l l l l x row/col d in write: lower byte (early write) l l h l x row/col lower byte, d in upper byte, high-z write: upper byte (early write) l h l l x row/col lower byte, high-z upper byte, d in read-write (1,2) lllh ll h row/col d out , d in hidden refresh 2) read l h l l l h l row/col d out write l h l l l l x row/col d out ras -only refresh l h h x x row/na high-z cbr refresh (3) h l l l x x x high-z notes: 1. these write cycles may also be byte write cycles (either lcas or ucas active). 2. these read cycles may also be byte read cycles (either lcas or ucas active). 3. at least one of the two cas signals must be active ( lcas or ucas ).
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 5 dr021-0a 08/11/2001 functional description the ic41c16257 and the ic41lv16257 are cmos drams optimized for high-speed bandwidth, low-power applications. during read or write cycles, each bit is uniquely addressed through the 18 address bits. these are entered nine bits (a0-a8) at a time. the row address is latched by the row address strobe ( ras ). the column address is latched by the column address strobe ( cas ). ras is used to latch the first nine bits and cas is used to latch the latter nine bits. the ic41c16257 and the ic41lv16257 have two cas controls, lcas and ucas . the lcas and ucas inputs internally generate a cas signal functioning in an identical manner to the single cas input on the other 256k x 16 drams. the key difference is that each cas controls its corresponding i/o tristate logic (in conjunction with oe and we and ras ). lcas controls i/o0 - i/o7 and ucas controls i/o8 - i/o15. the ic41c16257/ic41lv16257 cas function is determined by the first cas ( lcas or ucas ) transitioning low and the last transitioning back high. the two cas controls give the ic41c16257 both byte read and byte write cycle capabilities. memory cycle a memory cycle is initiated by bringing ras low and it is terminated by returning both ras and cas high. to ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time specified by t ar . data out becomes valid only when t rac , t aa , t cac and t oe are all satisfied. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we , whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs last. refresh cycle to retain data, 512 refresh cycles are required in each 8 ms period. there are two ways to refresh the memory: 1. by clocking each of the 512 row addresses (a0 through a8) with ras at least once every 8 ms. any read, write, read-modify-write or ras -only cycle refreshes the ad- dressed row. 2. using a cas -before- ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before- ras refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. self refresh cycle (1) the self refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 64 ms. i.e., 125 s per row when using distributed cbr refreshes. the feature also allows the user the choice of a fully static, low power data retention mode. the optional self refresh feature is initiated by performing a cbr refresh cycle and holding ras low for the specified t rass . the self refresh mode is terminated by driving ras high for a minimum time of t rps . this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras low-to-high transition. if the dram controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras -only or burst refresh sequence, all 512 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. power-on after application of the v cc supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a ras signal). during power-on, it is recommended that ras track with v cc or be held at a valid v ih to avoid current surges. note: 1.self refresh is for sversion only.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 6 integrated circuit solution inc. dr021-0a 08/11/2001 absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v ?1.0 to +7.0 v 3.3v ?0.5 to +4.6 v v cc supply voltage 5v ?1.0 to +7.0 v 3.3v ?0.5 to +4.6 v i out output current 50 ma p d power dicsipation 1 w t a operation temperature com. 0 to +70 o c ind. -40 to +85 o c t stg storage temperature ?55 to +125 o c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd) symbol parameter min. typ. max. unit v cc supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v v ih input high voltage 5v 2.4 ? v cc + 1.0 v 3.3v 2.0 ? v cc + 0.3 v v il input low voltage 5v ?1.0 ? 0.8 v 3.3v ?0.3 ? 0.8 v t a ambient temperature com. 0 ? 70 o c ind. ?40 ? 85 o c capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a8 5 pf c in 2 input capacitance: ras , ucas , lcas , we , oe 7pf c io data input/output capacitance: i/o0-i/o15 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 o c, f = 1 mhz, v cc = 5.0v + 10%, or v cc = 3.3v + 10%.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 7 dr021-0a 08/11/2001 electrical characteristics (1) (recommended operation conditions unless otherwise noted.) symbol parameter test condition speed min. max. unit i il input leakage current any input 0v v in vcc ?10 10 a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) ?10 10 a 0v v out vcc v oh output high voltage level i oh = ?2.5 ma 2.4 ? v v ol output low voltage level i ol = +2.1 ma ? 0.4 v i cc 1 stand-by current: ttl ras , lcas , ucas v ih com. 5v ? 2 ma ind. 5v ? 3 ma i cc 1 stand-by current: ttl ras , lcas , ucas v ih com. 3.3v ? 1 ma ind. 3.3v ? 2 ma i cc 2 stand-by current: cmos ras , lcas , ucas v cc ? 0.2v 5v ? 1 ma i cc 2 stand-by current: cmos ras , lcas , ucas v cc ? 0.2v 3.3v ? 0.5 ma i cc 3 operating current: ras , lcas , ucas , -35 ? 230 ma random read/write (2,3,4) address cycling, t rc = t rc (min.) -50 ? 180 average power supply current -60 ? 170 i cc 4 operating current: ras = v il , lcas , ucas , -35 ? 220 ma fast page mode (2,3,4) cycling t pc = t pc (min.) -50 ? 170 average power supply current -60 ? 160 i cc 5 refresh current: ras cycling, lcas , ucas v ih -35 ? 230 ma ras -only (2,3) t rc = t rc (min.) -50 ? 180 average power supply current -60 ? 170 i cc 6 refresh current: ras , lcas , ucas cycling -35 ? 230 ma cbr (2,3,5) t rc = t rc (min.) -50 ? 180 average power supply current -60 ? 170 i ccs self refresh current (6) self refresh mode 5v ? 300 a 3.3v ? 300 a notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras -only or cbr) before proper device operation is assured.the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specified values are obtained with minimum cycle time and the output open. 4. column-address is changed once each fast page cycle. 5. enables on-chip refresh and address counters. 6. i ccs is for s version only.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 8 integrated circuit solution inc. dr021-0a 08/11/2001 ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -35 -50 -60 symbol parameter min. max. min. max. min. max. units t rc random read or write cycle time 60 ?90? 110 ? ns t rac access time from ras (6, 7) ? 35 ?50 ? 60 ns t cac access time from cas (6, 8, 15) ? 10 ?14 ? 15 ns t aa access time from column-address (6) ? 18 ?25 ? 30 ns t ras ras pulse width 35 10k 50 10k 60 10k ns t rp ras precharge time 20 ? 30 ? 40 ? ns t cas cas pulse width (26) 6 10k 8 10k 10 10k ns t cp cas precharge time (9, 25) 5 ? 8 ? 10 ? ns t csh cas hold time (21) 35 ? 50 ? 60 ? ns t rcd ras to cas delay time (10, 20) 11 28 19 36 20 45 ns t asr row-address setup time 0 ? 0 ? 0 ? ns t rah row-address hold time 6 ? 8 ? 10 ? ns t asc column-address setup time (20) 0 ? 0 ? 0 ? ns t cah column-address hold time (20) 6 ? 8 ? 10 ? ns t ar column-address hold time 30 ? 40 ? 40 ? ns (referenced to ras ) t rad ras to column-address delay time (11) 12 20 14 25 15 30 ns t ral column-address to ras lead time 18 ? 25 ? 30 ? ns t rpc ras to cas precharge time 0 ?0? 0 ? ns t rsh ras hold time (27) 8 ? 14 ? 15 ? ns t clz cas to output in low-z (15, 29) 3 ? 3 ? 3 ? ns t crp cas to ras precharge time (21) 5 ? 5 ? 5 ? ns t od output disable time (19, 28, 29) 315 315 315 ns t oe output enable time (15, 16) ? 10 ? 15 ? 15 ns t oes oe low to cas high setup time 5 ? 5 ? 5 ? ns t rcs read command setup time (17, 20) 0 ? 0 ? 0 ? ns t rrh read command hold time 0 ? 0 ? 0 ? ns (referenced to ras ) (12) t rch read command hold time 0 ? 0 ? 0 ? ns (referenced to cas ) (12, 17, 21) t wch write command hold time (17, 27) 5 ? 8 ? 10 ? ns t wcr write command hold time 30 ? 40 ? 50 ? ns (referenced to ras ) (17) t wp write command pulse width (17) 5 ? 8 ? 10 ? ns t rwl write command to ras lead time (17) 8 ? 14 ? 15 ? ns t cwl write command to cas lead time (17, 21) 8 ? 14 ? 15 ? ns t wcs write command setup time (14, 17, 20) 0 ? 0 ? 0 ? ns t dhr data-in hold time (referenced to ras )30 ? 40 ? 45 ? ns (continued)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 9 dr021-0a 08/11/2001 ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -35 -50 -60 symbol parameter min. max. min. max. min. max. units t ach column-address setup time to cas 15 ? 15 ? 15 ? ns precharge during write cycle t oeh oe hold time from we during 8 ? 10 ? 15 ? ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0 ? 0 ? 0 ? ns t dh data-in hold time (15, 22) 6 ? 8 ? 10 ? ns t rwc read-modify-write cycle time 80 ? 125 ? 140 ? ns t rwd ras to we delay time during 45 ? 70 ? 80 ? ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 25 ? 34 ? 36 ? ns t awd column-address to we delay time (14) 30 ? 42 ? 49 ? ns t pc fast page mode read or write 12 ? 20 ? 25 ? ns cycle time (24) t rasp fast page mode ras pulse width 35 100k 50 100k 60 100k ns t cpa access time from cas precharge (15) ? 21 ?27 ? 34 ns t prwc fast page mode read-write cycle time (24) 40 ? 47 ? 56 ? ns t off output buffer turn-off delay from 3 15 3 15 3 15 ns cas or ras (13,15,19, 29) t clch last cas going low to first cas 10 ? 10 ? 10 ? ns returning high (23) t csr cas setup time (cbr refresh) (30, 20) 8 ? 10 ? 10 ? ns t chr cas hold time (cbr refresh) (30, 21) 8 ? 10 ? 10 ? ns t ord oe setup time prior to ras during 0 ? 0 ? 0 ? ns hidden refresh cycle t ref refresh period (512 cycles) ? 8 ? 8 ? 8ms t t transition time (rise or fall) (2, 3) 150 150 150 ns ac test conditions output load: two ttl loads and 50 pf (vcc = 5.0v 10%) one ttl load and 50 pf (vcc = 3.3v 10%) input timing reference levels: v ih = 2.4v, v il = 0.8v (vcc = 5.0v 10%); v ih = 2.0v, v il = 0.8v (vcc = 3.3v 10%) output timing reference levels: v oh = 2.0v, v ol = 0.8v (vcc = 5v 10%, 3.3v 10%)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 10 integrated circuit solution inc. dr021-0a 08/11/2001 notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t rcd t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd t rcd (max). 9. if cas is low at the falling edge of ras , data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input, i/o0-i/o7 by lcas and i/o8-i/o15 by ucas . 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defined as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. the first cas edge to transition low. 21. the last cas edge to transition high. 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. last falling cas edge to first rising cas edge. 24. last rising cas edge to next cycle?s last rising cas edge. 25. last rising cas edge to first falling cas edge. 26. each cas must meet minimum pulse width. 27. last cas to go low. 28. i/os controlled, regardless ucas and lcas . 29. the 3 ns minimum is a parameter guaranteed by design. 30. enables on-chip refresh and address counters.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 11 dr021-0a 08/11/2001 read cycle note: 1. t off is referenced from rising edge of ras or cas , whichever occurs last.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 12 integrated circuit solution inc. dr021-0a 08/11/2001 read write cycle (late write and read-modify-write cycles)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 13 dr021-0a 08/11/2001 early write cycle ( oe = don't care)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 14 integrated circuit solution inc. dr021-0a 08/11/2001 fast page mode read cycle
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 15 dr021-0a 08/11/2001 fast page mode read write cycle (late write and read-modify-write cycles)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 16 integrated circuit solution inc. dr021-0a 08/11/2001 fast page mode early write cycle ac waveforms ras ras ras ras ras -only refresh cycle ( oe , we = don't care)
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 17 dr021-0a 08/11/2001 cbr refresh cycle (addresses; we , oe = don't care) hidden refresh cycle (1) ( we = high; oe = low) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t off is referenced from rising edge of ras or cas , whichever occurs last.
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 18 integrated circuit solution inc. dr021-0a 08/11/2001 self refresh cycle (addresses : we and oe = don't care) timing parameters -35 -50 -60 symbol min. max. min. max. min. max. units t chd 8? 10? 10? ns t cp 5? 9? 9? ns t csr 8? 10? 10? ns t rass 100 ? 100 ? 100 ? s t rp 20 ? 30 ? 40 ? ns t rps 64 ? 84 ? 104 ? ns t rpc 5? 5? 5? ns
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s integrated circuit solution inc. 19 dr021-0a 08/11/2001 ordering information ic41lv16257s commercial range: 0 c to 70 c speed (ns) order part no. package 35 ic41lv16257s-35k 400mil soj ic41lv16257s-35t 400mil tsop-2 50 ic41lv16257s-50k 400mil soj ic41lv16257s-50t 400mil tsop-2 60 is41lv16257s-60k 400mil soj ic41lv16257s-60t 400mil tsop-2 industrial range: -40 c to 85 c speed (ns) order part no. package 35 ic41lv16257s-35ki 400mil soj ic41lv16257s-35ti 400mil tsop-2 50 ic41lv16257s-50ki 400mil soj ic41lv16257s-50ti 400mil tsop-2 60 ic41lv16257s-60ki 400mil soj ic41lv16257s-60ti 400mil tsop-2 ordering information ic41c16257s commercial range: 0 c to 70 c speed (ns) order part no. package 35 ic41c16257s-35k 400mil soj IC41C16257S-35T 400mil tsop-2 50 ic41c16257s-50k 400mil soj ic41c16257s-50t 400mil tsop-2 60 ic41c16257s-60k 400mil soj ic41c16257s-60t 400mil tsop-2 industrial range: -40 c to 85 c speed (ns) order part no. package 35 ic41c16257s-35ki 400mil soj IC41C16257S-35Ti 400mil tsop-2 50 ic41c16257s-50ki 400mil soj ic41c16257s-50ti 400mil tsop-2 60 ic41c16257s-60ki 400mil soj ic41c16257s-60ti 400mil tsop-2 ordering information ic41lv16257 commercial range: 0 c to 70 c speed (ns) order part no. package 35 ic41lv16257-35k 400mil soj ic41lv16257-35t 400mil tsop-2 50 ic41lv16257-50k 400mil soj ic41lv16257-50t 400mil tsop-2 60 is41lv16257-60k 400mil soj ic41lv16257-60t 400mil tsop-2 industrial range: -40 c to 85 c speed (ns) order part no. package 35 ic41lv16257-35ki 400mil soj ic41lv16257-35ti 400mil tsop-2 50 ic41lv16257-50ki 400mil soj ic41lv16257-50ti 400mil tsop-2 60 ic41lv16257-60ki 400mil soj ic41lv16257-60ti 400mil tsop-2 ordering information ic41c16257 commercial range: 0 c to 70 c speed (ns) order part no. package 35 ic41c16257-35k 400mil soj ic41c16257-35t 400mil tsop-2 50 ic41c16257-50k 400mil soj ic41c16257-50t 400mil tsop-2 60 ic41c16257-60k 400mil soj ic41c16257-60t 400mil tsop-2 industrial range: -40 c to 85 c speed (ns) order part no. package 35 ic41c16257-35ki 400mil soj ic41c16257-35ti 400mil tsop-2 50 ic41c16257-50ki 400mil soj ic41c16257-50ti 400mil tsop-2 60 ic41c16257-60ki 400mil soj ic41c16257-60ti 400mil tsop-2
ic41c16257/ic41c16257s ic41lv16257/ic41lv16257s 20 integrated circuit solution inc. dr021-0a 08/11/2001 integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw

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