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hm51w16400 series hm51w17400 series 16 m fp dram (4-mword 4-bit) 4 k refresh/2 k refresh ade-203-649e (z) rev. 5.0 nov. 1997 description the hitachi hm51w16400 series, hm51w17400 series are cmos dynamic rams organized 4,194,304- word 4-bit. they employ the most advanced 0.5 m m cmos technology for high performance and low power. the hm51w16400 series, hm51w17400 series offer fast page mode as a high speed access mode. they have package variations of standard 300-mil 26-pin plastic soj and standard 300-mil 26-pin plastic tsop. features single 3.3 v ( 0.3 v) access time: 60 ns/70 ns (max) power dissipation ? active mode : 288mw/252 mw (max) (hm51w16400 series) : 324 mw/288 mw (max) (hm51w17400 series) ? standby mode : 7.2 mw (max) : 0.36 mw (max) (l-version) fast page mode capability long refresh period ? 4096 refresh cycles : 64 ms (hm51w16400 series) : 128 ms (l-version) ? 2048 refresh cycles : 32 ms (hm51w17400 series) : 128 ms (l-version) 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh (l-version) battery backup operation (l-version) test function
hm51w16400 series, hm51w17400 2 ? 16-bit parallel test mode ordering information type no. access time package hm51w16400s-6 hm51w16400s-7 60 ns 70 ns 300-mil 26-pin plastic soj (cp-26/24db) hm51w16400ls-6 hm51w16400ls-7 60 ns 70 ns hm51w17400s-6 hm51w17400s-7 60 ns 70 ns hm51w17400ls-6 hm51w17400ls-7 60 ns 70 ns hm51w16400ts-6 hm51w16400ts-7 60 ns 70 ns 300-mil 26-pin plastic tsop ii (ttp-26/24da) hm51w16400lts-6 hm51w16400lts-7 60 ns 70 ns hm51w17400ts-6 HM51W17400TS-7 60 ns 70 ns hm51w17400lts-6 hm51w17400lts-7 60 ns 70 ns
hm51w16400 series, hm51w17400 3 pin arrangement 26 25 24 23 22 21 19 18 17 16 15 14 1 2 3 4 5 6 8 9 10 11 12 13 v cc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 v cc v cc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 v cc v i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss ss v i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss ss 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 hm51w16400s/ls series hm51w16400ts/lts series (top view) (top view) pin description pin name function a0 to a11 address input row/refresh address column address a0 to a11 a0 to a9 i/o1 to i/o4 data input/data output ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground
hm51w16400 series, hm51w17400 4 pin arrangement 26 25 24 23 22 21 19 18 17 16 15 14 1 2 3 4 5 6 8 9 10 11 12 13 v cc i/o1 i/o2 we ras nc a10 a0 a1 a2 a3 v cc v i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss ss v cc i/o1 i/o2 we ras nc a10 a0 a1 a2 a3 v cc v i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss ss 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 hm51w17400s/ls series hm51w17400ts/lts series (top view) (top view) pin description pin name function a0 to a10 address input row/refresh address column address a0 to a10 a0 to a10 i/o1 to i/o4 data input/data output ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection
hm51w16400 series, hm51w17400 5 block diagram (hm51w16400 series) timing and control column address buffers row address buffers i/o buffers ? ? ? ? ? ? a0 a1 to a9 a11 i/o1 to i/o4 a10 ras cas we oe column decoder row decoder 4m array 4m array 4m array 4m array
hm51w16400 series, hm51w17400 6 block diagram (hm51w17400 series) timing and control column address buffers row address buffers i/o buffers ? ? ? ? ? ? a0 a1 to a10 i/o1 to i/o4 ras cas we oe column decoder row decoder 4m array 4m array 4m array 4m array
hm51w16400 series, hm51w17400 7 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( +4.6 v (max)) v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss .
hm51w16400 series, hm51w17400 8 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w16400 series) hm51w16400 -6 -7 parameter symbol min max min max unit test conditions operating current* 1 , * 2 i cc1 80 70 ma t rc = min standby current i cc2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z standby current (l-version) i cc2 100 100 m a cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 80 70 ma t rc = min standby current* 1 i cc5 5 5 ma ras = v ih cas = v il dout = enable cas -before- ras refresh current i cc6 80 70 ma t rc = min fast page mode current* 1, * 3 i cc7 70 60 ma t pc = min battery backup current (standby with cbr refresh) (l-version) i cc10 300 300 m a cmos interface dout = high-z, cbr refresh: t rc = 31.3 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 200 200 m a cmos interface ras , cas 0.2 v dout = high-z input leakage current i li C 10 10 C 10 10 m a 0 v vin 4.6 v output leakage current i lo C 10 10 C 10 10 m a 0 v vin 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C 2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes : 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih .
hm51w16400 series, hm51w17400 9 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w17400 series) hm51w17400 -6 -7 parameter symbol min max min max unit test conditions operating current* 1 , * 2 i cc1 90 80 ma t rc = min standby current i cc2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z standby current (l-version) i cc2 100 100 m a cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 90 80 ma t rc = min standby current* 1 i cc5 5 5 ma ras = v ih cas = v il dout = enable cas -before- ras refresh current i cc6 90 80 ma t rc = min fast page mode current* 1, * 3 i cc7 80 70 ma t pc = min battery backup current (standby with cbr refresh) (l-version) i cc10 300 300 m a cmos interface dout = high-z, cbr refresh: t rc = 62.5 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 200 200 m a cmos interface ras , cas 0.2 v dout = high-z input leakage current i li C 10 10 C 10 10 m a 0 v vin 4.6 v output leakage current i lo C 10 10 C 10 10 m a 0 v vin 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C 2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes : 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih .
hm51w16400 series, hm51w17400 10 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5pf1 input capacitance (clocks) c i2 7pf1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
hm51w16400 series, hm51w17400 11 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) * 1, * 2, * 18, * 19 test conditions input rise and fall time: 5 ns input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes random read or write cycle time t rc 110 130 ns ras precharge time t rp 40 50 ns cas precharge time t cp 10 10 ns ras pulse width t ras 60 10000 70 10000 ns cas pulse width t cas 15 10000 18 10000 ns row address setup time t asr 00ns row address hold time t rah 10 10 ns column address setup time t asc 00ns column address hold time t cah 10 15 ns ras to cas delay time t rcd 20 45 20 52 ns 3 ras to column address delay time t rad 15 30 15 35 ns 4 ras hold time t rsh 15 18 ns cas hold time t csh 60 70 ns cas to ras precharge time t crp 55ns oe to din delay time t oed 15 18 ns 5 oe delay time from din t dzo 00ns6 cas delay time from din t dzc 00ns6 transition time (rise and fall) t t 3 50 3 50 ns 7
hm51w16400 series, hm51w17400 12 read cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes access time from ras t rac 60 70 ns 8, 9, 20 access time from cas t cac 15 18 ns 9, 10, 17, 20 access time from address t aa 30 35 ns 9, 11, 17, 20 access time from oe t oea 15 18 ns 9, 20 read command setup time t rcs 00ns read command hold time to cas t rch 00ns12 read command hold time to ras t rrh 00ns12 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 30 35 ns cas to output in low-z t clz 00ns output data hold time t oh 33ns output data hold time from oe t oho 33ns output buffer turn-off time t off 15 15 ns 13 output buffer turn-off to oe t oez 15 15 ns 13 cas to din delay time t cdd 15 18 ns 5 write cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes write command setup time t wcs 00ns14 write command hold time t wch 10 15 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 15 18 ns write command to cas lead time t cwl 15 18 ns data-in setup time t ds 00ns15 data-in hold time t dh 10 15 ns 15
hm51w16400 series, hm51w17400 13 read-modify-write cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes read-modify-write cycle time t rwc 155 181 ns ras to we delay time t rwd 85 98 ns 14 cas to we delay time t cwd 40 46 ns 14 column address to we delay time t awd 55 63 ns 14 oe hold time from we t oeh 15 18 ns refresh cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 55ns cas hold time (cbr refresh cycle) t chr 10 10 ns we setup time (cbr refresh cycle) t wrp 00ns we hold time (cbr refresh cycle) t wrh 10 10 ns ras precharge to cas hold time t rpc 55ns fast page mode cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes fast page mode cycle time t pc 40 45 ns fast page mode ras pulse width t rasp 100000 100000 ns 16 access time from cas precharge t cpa 35 40 ns 9, 17, 20 ras hold time from cas precharge t cprh 35 40 ns
hm51w16400 series, hm51w17400 14 fast page mode read-modify-write cycle hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes fast page mode read-modify-write cycle time t prwc 85 96 ns we delay time from cas precharge t cpw 60 68 ns 14 test mode cycle * 19 hm51w16400/hm51w17400 -6 -7 parameter symbol min max min max unit notes test mode we setup time t wts 00ns test mode we hold time t wth 10 10 ns refresh (hm51w16400 series) parameter symbol max unit notes refresh t ref 64 ms 4096 cycles refresh (l-version) t ref 128 ms 4096 cycles refresh (hm51w17400 series) parameter symbol max unit notes refresh period t ref 32 ms 2048 cycles refresh period (l-version) t ref 128 ms 2048 cycles
hm51w16400 series, hm51w17400 15 self refresh mode (l-version) hm51w16400l/hm51w17400l -6 -7 parameter symbol min max min max unit notes ras pulse width (self refresh) t rass 100 100 m s 21, 22, 23, 24 ras precharge time (self refresh) t rps 110 130 ns cas hold time (self refresh) t chs C50 C50 ns notes: 1. ac measurements assume t t = 5 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. (v oh = 2.0 v, v ol = 0.8 v) 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. these parameters are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in fast page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. the 16m dram offers a 16-bit time saving parallel test mode. address ca0 and ca1 for the 4m 4 are dont care during test mode. test mode is set by performing a we -and- cas -before- ras (wcbr) cycle. in 16-bit parallel test mode, data is written into 4 bits in parallel at each i/o (i/o1 to i/o4) and read out from each i/o.
hm51w16400 series, hm51w17400 16 if 4 bits of each i/o are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. if they are not equal, data output pin is a low state, then the device has failed. refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. to get out of test mode and enter a normal operation mode, perform either a regular cas - before- ras refresh cycle or ras -only refresh cycle. 20. in a test mode read cycle, the value of t rac , t aa , t cac and t cpa is delayed by 2 ns to 5 ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass > 100 m s, then ras precharge time should use t rps instead of t rp . 22. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed with in 15.6 m s immediately after exiting from and before entering into self refresh mode. 23. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 4096 or 2048 cycles (4096 cycles: hm51w16400 series, 2048 cycles: hm51w 17400 series) of distributed cbr refresh with 15.6 m s interval should be executed with in 64 or 32 ms (64 ms: hm51w16400 series, 32 ms: hm51w17400 series) immediately after exiting from and before entering into the self refresh mode. 24. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm51w16400 series, hm51w17400 17 timing waveforms * 25 read cycle ras cas address we dout oe din t rc t ras t rp t csh t crp t rcd t rsh t cas t t t rad t ral t cal t asc t cah t asr row column t rah t rcs t rch t rrh t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez
hm51w16400 series, hm51w17400 18 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hm51w16400 series, hm51w17400 19 delayed write cycle * 18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t clz t oez high-z din high-z invalid dout read-modify-write cycle * 18
hm51w16400 series, hm51w17400 20 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas
hm51w16400 series, hm51w17400 21 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off
hm51w16400 series, hm51w17400 22 cas -before- ras refresh cycle ras cas we address dout high-z t off t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
hm51w16400 series, hm51w17400 23 hidden refresh cycle din oe dout we address cas ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t rcs t cdd t dzc dzo t oed t oez t oho t off t oh t cac t aa t rac t clz t dout column row oea t high-z t wrh t rrh t wrp t wrh t wrp
hm51w16400 series, hm51w17400 24 fast page mode read cycle we din oe dout address cas ras t rasp t cprh t rp t t t csh t rcd t cas t cp t cas t pc t rsh t cp t cas t crp t ral t cal t cah asc t t asc t t cal t cal t asc t t rad t asr t rah tt rch t rch tt t rrh t rch t cdd high-z t dzc t cdd t dzc t cdd t dzc high-z high-z t dzo t oed t oed t dzo tt oed t oh t aa t oh t aa t oh t cpa t cpa t rac t aa t oea t oea t oea t oho t oho t oho t cac t clz t oez t off t cac t clz t oez t off t cac t clz t oez t off dout n dout 2 dout 1 row column 1 column 2 column n cah cah rcs rcs rcs dzo
hm51w16400 series, hm51w17400 25 fast page mode early write cycle * t wcs wcs (min) ras cas address we din dout t rasp t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n
hm51w16400 series, hm51w17400 26 fast page mode delayed write cycle * 18 we din oe dout address cas ras t rasp t rp t crp t rsh t cas t pc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z
hm51w16400 series, hm51w17400 27 fast page mode read-modify-write cycle * 18 we din oe dout address cas ras t rasp t crp t cp t prwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh
hm51w16400 series, hm51w17400 28 test mode cycle * 19 cbr or ras-only refresh ras cas we set cycle** test mode cycle *,** reset cycle normal mode ** * address, din, oe: h or l test mode set cycle @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? cas we address dout ras t rc t rp t ras t rp t chr t csr t rpc t rpc t crp t t t cp t wts t wth t cp t off high-z
hm51w16400 series, hm51w17400 29 self refresh cycle (l-version)* 21, * 22, * 23, * 24 ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off high-z cas wrp t wrh t we
hm51w16400 series, hm51w17400 30 package dimensions hm51w16400s/ls series hm51w17400s/ls series (cp-26/24db) 16.90 17.27 max 0.74 7.62 0.13 8.51 0.13 26 14 113 0.10 0.43 0.10 3.50 0.26 19 21 8 6 2.65 0.12 1.30 max 0.80 +0.25 ?.17 2.54 1.27 hitachi code jedec eiaj weight (reference value) cp-26/24db conforms conforms 0.8 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension 6.79 + 0.19 ?0.18
hm51w16400 series, hm51w17400 31 hm51w16400ts/lts series hm51w17400ts/lts series (ttp-26/24da) 17.14 17.54 max 26 14 113 1.27 0.21 0.42 0.08 1.20 max 0.10 7.62 9.22 0.20 0.145 0.05 0.13 0.05 0 ?5 0.50 0.10 m 1.15 max 0.68 19 21 68 0.80 hitachi code jedec eiaj weight (reference value) ttp-26/24da conforms ? 0.30 g 0.40 0.06 0.125 0.04 2.54 unit: mm dimension including the plating thickness base material dimension
hm51w16400 series, hm51w17400 32 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm51w16400 series, hm51w17400 33 revision record rev. date contents of modification drawn by approved by 1.0 oct. 14, 1996 initial issue y. kasama m. mishima 2.0 nov. 14, 1996 addition of hm51w16400-5 series addition of hm51w17400-5 series power dissipation (active) 396/360 mw(max) to 360/324/288 mw (max) (hm51w17400 series) dc characteristics (hm51w17400 series) i cc1 max: 110/100 ma to 100/90/80 ma i cc3 max: 110/100 ma to 100/90/80 ma i cc6 max: 110/100 ma to 100/90/80 ma y. kasama y. matsuno 3.0 feb. 27, 1997 ac characteristics t rrh min: 5/5/5 ns to 0/0/0 ns y. kasama y. matsuno 4.0 jun. 12, 1997 deletion of hm51w16400/hm51w17400-5 series y. kasama y. matsuno 5.0 nov. 1997 change of subtitle

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