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1 of 38 071800 special features digital thermometer measures temperature from as low as -40 c to +85 c in 0.5 c increments temperature conversion accuracy = 1 c from as low as -20 c to +70 c real-time clock/calendar in bcd format counts seconds, minutes, hours, date, month, day of the week, and year with leap year compensation; y2k compliant real-time clock accuracy = 2 minutes per month from 0 c to 45 c programmable temperature-high and temperature-low alarm trip points automatically wakes up and measures temperature at user-programmable intervals from 1 to 255 minutes logs up to 2048 consecutive temperature measurements in read-only nonvolatile memory records a long-term temperature histogram with 2 c resolution (63 bins) records time stamp and duration when temperature leaves the range specified by the trip points 4096 bits of general-purpose read/write nonvolatile memory 256-bit scratchpad ensures integrity of data transfer overdrive mode boosts communication speed to 142 kbits per second memory partitioned into 256-bit pages for packetizing data on-chip 16-bit crc generator to safeguard data read operations common ibutton features digital identification and information by momentary contact f5 microcan ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan ? chip-based data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to host with a single digital signal at 16.3 kbits per second ? standard 16 mm diameter and 1-wire ? protocol ensure compatibility with ibutton device family ? button shape is self-aligning with cup- shaped probes ? durable stainless steel case engraved with registration number withstands harsh environments ? easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ? meets ul#913 (4 th edit.); intrinsically safe apparatus: approved under entity concept for use in class i, division 1, group a, b, c and d locations (application pending) ds1921l-f5x thermochron ibutton tm preliminary, rev date 12/15/1999 data ground 0.36 0.51 5.89 c 1993 yyww registered rr 89 21 xxx000fbc52 16.25 17.35 preliminary www.dalsemi.com
ds1921l-f5x 2 of 38 examples of accessories ds9096p self-stick adhesive pad ds9101 multi-purpose clip ds9093ra mounting lock ring ds9093a snap-in fob ds9092 ibutton probe ordering information part number range of accurate operations packaging ds1921l-f51 -10 c to +85 c f5, microcan ds1921l-f52 -20 c to +85 c f5, microcan DS1921L-F53 -30 c to +85 c f5, microcan ibutton description the ds1921l-f5x thermochron ibuttons are rugged, self-sufficient systems that, once setup for a mission, measure temperature and record the result in a protected memory section. the recording is done at a user-defined rate, both as a direct storage of temperature values at incrementing memory addresses as well as in the form of a histogram. up to 2048 temperature values taken at equidistant intervals ranging from 1 to 255 minutes can be stored. the histogram provides 63 data bins for a resolution of 2 c. each bin is implemented as a 16-bit binary counter that is incremented if the value of a temperature measurement falls into the range of the bin. if the temperature leaves a user-programmable range, the ds1921 will also record when this happened, for how long the temperature stayed outside the permitted range, and if the temperature was too high or too low. a total of 24 such events can be recorded, 12 for exceeding each temperature limit. additional read/write non-volatile memory independent of the memory used for temperature logging offers a simple solution to storing and retrieving information pertaining to the object to which the ds1921 is associated. data is transferred serially via the 1-wire protocol, which requires only a single data lead and a ground return and which allows the device to be accessed with minimal hardware. the scratchpad is an additional memory area that acts as a buffer when writing to the read/write memory and to the special function registers required to mission the device. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to memory. this process ensures data integrity when modifying the memory. a 48-bit serial number is factory-lasered into each ds1921 to provide a guaranteed unique identity which allows for absolute traceability. the durable microcan package is highly resistant to environmental hazards such as dirt, moisture, and shock. its compact, coin-shaped profile is self-aligning with mating receptacles, allowing the ds1921 to be easily used by human operators. accessories permit the ds1921 to be mounted on almost any surface, including containers, pallets and bags. application the ds1921 thermochron ibutton is an ideal device to monitor the temperature of any object it is attached to or shipped with, such as perishable goods or containers of temperature sensitive chemicals. using tmex, the read/write nonvolatile memory can store an electronic copy of shipping information, date of manufacture and other important data written as clear as well as encrypted files. the unique registration number and a non-resettable counter that increments with each new mission provide traceability and evidence in case of tampering with the device.
ds1921l-f5x 3 of 38 overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds1921. the ds1921 has seven main data components: 1) 64-bit lasered rom, 2) 256-bit scratchpad, 3) 4096-bit sram, 4) 256-bit of timekeeping, control and counter registers, 5) 2048 bytes of data-logging memory, 6) 128 bytes of histogram memory, and 7) 96 bytes of event/duration recording memory. except for the rom and the scratchpad, all other memory is arranged in a single linear address space. all memory reserved for logging purposes, the counter registers and several other registers are read-only for the user. the timekeeping and control registers are write-protected while the device is programmed for a mission. the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first provide one of the seven rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) conditional search rom, 5) skip rom, 6) overdrive-skip rom or 7) overdrive-match rom. upon completion of an over-drive rom command byte executed at standard speed, the device will enter overdrive mode, where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions become accessible and the master may provide any one of the seven memory function commands. the protocol for these memory function commands is described in figure 7. all data is read and written least significant bit first. parasite power the block diagram (figure 1) shows the parasite-powered circuitry. this circuitry ?steals? power whenever the i/o input is high. i/o will provide sufficient power as long as the specified timing and voltage requirements are met. the advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved; and 2) if the lithium is exhausted for any reason, the rom may still be read normally. 64-bit lasered rom each ds1921 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3). the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic redundancy check is available in the book of ds19xx ibutton standards. the shift register bits are initialized to 0. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all 0s.
ds1921l-f5x 4 of 38 ds1921 block diagram figure 1 256-bit scratchpad 1-w rom control function 64-bit rom lasered parasite- circuitry powered memory function control 1-wire port 32.768 khz oscillator & counters internal control reg. sram timekeeping, holding registers control & counter 4096-bit alarm time stamp and duration logging memory histogram memory temperature logging memory temperature sensor control logic timekeeping & 3v lithium hierarchical structure for 1-wire protocol figure 2 1-wire bus other devices ds1921 bus master ds1921 specific memory function commands (see figure 7) write scratchpad copy scratchpad read scratchpad read memory read memory with crc 256-bit scratchpad 256-bit scratchpad 4096-bit sram all memory all memory or registers 1-wire rom function commands (see figure 9) command level: available commands: read rom match rom search rom skip rom data field affected: 64-bit rom 64-bit rom 64-bit rom n/a overdrive skip rom overdrive match rom n/a 64-bit rom conditional search rom 64-bit rom, cond. search settings, device status clear memory convert temperature address 20dh to 17ffh address 211h
ds1921l-f5x 5 of 38 64-bit lasered rom figure 3 msb lsb 8-bit crc code 48-bit serial number 8-bit family code (21h) msb lsb msb lsb msb lsb the most significant 12 bits of the 48-bit serial number are being used in the ds1921l-f5x thermochron product series to identify both the lower limit and the range of accurate operations, as described in rom encoding vs. range of accurate operations in the last section of this document. software developers may use this coding mechanism to automatically determine the validity of sampled temperature values based on the content of this 12-bit field. 1-wire crc generator figure 4 input polynomial = x 8 x 5 x 4 + + + 1 xor xor xor 1st stage 2nd stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage x 7 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 8 memory the memory map in figure 5a shows a 32-byte page called the scratchpad and additional 32-byte pages assigned to various purposes. the 4096-bit sram make up pages 0 through 15 of the ds1921. the timekeeping, control and counter registers fill page 16 (register page, figure 5b). pages 17 to 19 are assigned to storing the alarm time stamps and durations. the temperature histogram bins begin at page 64 and use up four pages. the temperature logging memory covers pages 128 to 191. memory pages 20 to 63, 68 to 127 and 192 to 255 are reserved for future extensions. the scratchpad is an additional page that acts as a buffer when writing to the sram memory or the timekeeping, control and counter registers. the memory pages 17 and higher are read-only for the user. they are written to or erased solely under supervision of the on-chip control logic. timekeeping the real-time clock/alarm and calendar information is accessed by reading/ writing the appropriate bytes in the register page (figure 5b, address 200h to 206h). note that some bits are set to 0. these bits will always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the bcd format (binary-coded decimal). real-time clock/calendar the real-time clock of the ds1921 can run in either 12-hour or 24-hour mode. bit 6 of the hours register (address 202h) is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic 1 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20 - 23 hours). to distinguish between the days of the week the ds1921 includes a counter with a range from 1 to 7. the assignment of counter value to the day of week is arbitrary. typically the number 1 is assigned to a sunday (u.s. standard) or to a monday (european standard).
ds1921l-f5x 6 of 38 the calendar logic is designed to automatically compensate for leap years. for every year value that is either 00 or a multiple of 4 the device will add a 29 th of february. this will work correctly up to (but not including) the year 2100. the ds1921 is year 2000-compliant. bit 7 (cent) of the months register at address 205h serves as a century flag. when the year register rolls over from (19)99 to (20)00 the century flag will toggle. it is recommended to write the century bit to a 0 when setting the real-time clock to a time/date before the year 2000. real-time clock alarms the ds1921 also contains a real-time clock alarm function. the alarm registers are located in registers 207h to 20ah. the most significant bit of each of the alarm registers is a mask bit (see table 1). when all of the mask bits are logic 0, an alarm will occur once per week when the values stored in timekeeping registers 200h to 203h match the values stored in the time of day alarm registers. any alarm will set the timer alarm flag (taf) in the device's status register (address 214h). the bus master may set the search conditions (address 20eh) to identify devices with timer alarms by means of the conditional search function (see rom function commands). time of day alarm bits table 1 alarm register mask bits (bit 7) ms mm mh md 1 1 1 1 alarm once per second. 0 1 1 1 alarm when seconds match (once per minute). 0 0 1 1 alarm when minutes and seconds match (once every hour). 0 0 0 1 alarm when hours, minutes and seconds match (once every day). 0 0 0 0 alarm when day, hours, minutes and seconds match (once every week). temperature conversion the temperature sensor of the ds1921 can accurately measure temperatures from as low as -40c to +85c in 0.5c increments. temperature readings are represented in a single byte as an unsigned binary number (table 2). the possible values range from 00000000 (for -40c) to 1111 1010 (for +85c). with t[7..0] representing the decimal equivalent of the binary temperature reading the temperature value is calculated as ( c) = t[7..0] / 2 - 40 this formula is valid for converting temperature readings stored in the temperature logging memory as well as for data read from the temperature read-out register (address 211h). to specify the high and low temperature alarm thresholds this formula needs to be resolved to t[7..0] = 2 x ( c = ) = + = 80 a value of 23c, for example, thus translates into 126, which is then written as a binary pattern of 01111110 to the temperature alarm register. the value of -20c, as another example, is represented as 00101000.
ds1921l-f5x 7 of 38 temperatures below -40c will be recorded as 00000000 (=-40c) [1] . temperatures higher than +85c will be recorded as 111111010 (=85c). temperature data byte format table 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t7 t6 t5 t4 t3 t2 t1 t0 ds1921 memory map figure 5a 32-byte intermediate storage scratchpad address 0000h to 001fh 32-byte final storage nv ram page 0 0020h to 01ffh final storage nv ram page 1 to page 15 0200h to 021fh 32-byte register page page 16 00220h to 027fh alarm time stamps and durations page 17 to page 19 0280h to 07ffh (reserved for future extensions) page 20 - 63 0800h to 087fh temperature histogram page 64 to page 67 0880h to 0fffh (reserved for future extensions) page 68 - 127 1000h to 17ffh temperature logging memory (64 pages) page 128 to page 191 1800h to 1fffh (reserved for future extensions) page 192 - 255
ds1921l-f5x 8 of 38 ds1921 register page figure 5b addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function 200 0 10 seconds single seconds 201 0 10 minutes single minutes 202 0 12/24 10 h. a/p 10h. single hours 203 0 0 0 0 0 day of week 204 0 0 10 date single date 205 cent 0 0 10 m. single months 206 10 years single years real-time clock registers 207 ms 10 seconds alarm single seconds alarm 208 mm 10 minutes alarm single minutes alarm 209 mh 12/24 10 ha. a/p 10 h. alm. single hours alarm 20a md 0 0 0 0 day of week alarm real-time clock alarm 20b low temperature threshold 20c high temperature threshold temperature alarm 20d number of minutes between temperature conversions sample rate 20e eosc mclre 0 em ro tls ths tas control 20f 0 0 0 0 0000 210 0 0 0 0 0000 (no function) 211 temperature read out (forced conversion) temperature 212 low byte 213 high byte mission start delay 214 tcb memclr mip sip 0 tlf thf taf status 215 0 10 minutes single minutes 216 0 12/24 10 h. a/p 10h. single hours 217 0 0 10 date single date 218 unused * 0 0 10 m. single months mission time stamp 219 10 years single years 21a low byte 21b medium byte 21c high byte mission samples counter 21d low byte 21e medium byte 21f high byte device samples counter address registers figure 6 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 1) pf e4 e3 e2 e1 e0 1) this bit will always be 0. * this bit maybe used in the future to represent the century as does the cent bit of the rtc registers. see end note 11 for an example of program logic that works with both the current and future versions of thermochrons.
ds1921l-f5x 9 of 38 temperature logging and histogram once setup for a mission, the ds1921 logs the temperature measurements simultaneously byte after byte in the temperature logging memory as well as in histogram form in the histogram memory. the temperature logging memory is able to store 2048 temperature values measured at equidistant time points. the time/date stamp of when the device was setup for a mission is stored as mission time stamp in the register page, addresses 215h to 219h. the first temperature value of a mission is written to address location 1000h of the temperature logging memory, the second value to address location 1001h and so on. with the starting time point and the interval between temperature measurements known, one can exactly reconstruct the time and date each measurement was taken. there are two alternatives to the way the ds1921 will behave after the 2048 bytes of temperature logging memory is filled with data. the user can program the device to either stop any further recording or overwrite the previously recorded data (enable ?rollover?), one byte at a time, starting again at address 1000h for the 2049 th temperature value. the contents of the mission samples counter (addresses 21ah to 21ch) in conjunction with the sample rate and the mission time stamp will then allow reconstructing the time points of all values stored in the temperature logging memory. this gives the exact temperature history over time for the latest 2048 measurements taken. all earlier measurements cannot be reconstructed. regardless of enabling the rollover, these values indirectly show up in the temperature histogram. for the temperature histogram, the ds1921 provides 63 bins that begin at memory address 0800h. each bin consists of a 16-bit, non-rolling-over binary counter that is incremented each time a temperature value acquired during a mission falls into the range of the bin. the least significant byte of each bin is stored at the lower address. bin 1 begins at memory address 0800h, bin 2 at 0802h, and so on up to 087ch for bin 63. after a temperature conversion is completed the number of the bin to be updated is determined by cutting off the two least significant bits of the binary temperature value. thus bin 1 will be updated with every temperature reading from -40 c or lower to -38.5 c. bin 2 is associated with the range of -38.0 c to - 36.5 c and so on 1 . bin 63, finally, counts temperature values of +84 c and higher. since each data bin is 2 bytes it can increment up to 65535 times. if more samples for a given data bin are measured, the data bin will remain at its maximum value. with the fastest sample rate of one sample every minute, this is sufficient for up to 45 days if all temperature readings fall into the same bin. temperature alarm logging for some applications it may be essential to not only record temperature over time and the temperature histogram, but also record when exactly the temperature has exceeded a predefined tolerance band and for how long the temperature stayed outside the desirable range. the ds1921 is able to provide this information, too. the tolerance band is specified by means of the temperature alarm registers, addresses 20bh and 20ch in the register page. one can set a high and a low temperature threshold. see section ?temperature conversion? for the data format the temperature has to be written in. as long as the temperature values stay within the tolerance band, i.e., are higher than the low threshold and lower than the high threshold, the ds1921 will not record any temperature alarm. if the temperature during a mission reaches or exceeds either threshold, the ds1921 will generate an alarm and set either the temperature high flag (thf) or the temperature low flag (tlf) in the status register (address 214h). in addition, the device generates a time stamp of when the alarm occurred and begins recording the duration of the alarming condition. 1 the temperature and histogram logs are meaningful only when the temperature values are within the stated range of accurate operations, as shown in the ordering information table.
ds1921l-f5x 10 of 38 the device stores a time stamp as a copy of the mission samples counter when the alarm occurred. the least significant byte is stored at the lower address. one address higher than a time stamp the ds1921 maintains a 1-byte duration counter that stores the number of times the temperature was found to be beyond the threshold. if this counter has reached its limit after 255 consecutive temperature readings and the temperature has not yet returned to within the tolerance band, the device will issue another time stamp at the next higher address and open another counter to record the duration. if the temperature returns to normal before the counter has reached its limit, the duration counter of the particular time stamp will not increment any further. should the temperature again cross this threshold, another time stamp will be recorded and its associated counter will increment with each temperature reading outside the tolerance band. this algorithm is implemented for the low as well as for the high temperature threshold. time stamps and durations where the temperature leaves the tolerance band to the low (cold) side are stored in the address range 0220h to 024fh (48 bytes). the memory address range 0250h to 027fh (48 bytes) is reserved for time stamps and duration where the temperature leaves the tolerance band to the high (hot) side. this allocation allows recording 24 individual alarm events and periods (12 periods for too hot and 12 for too cold). the date and time of each of these periods can be determined from the mission time stamp and the time distance between each temperature reading. devices with temperature alarms can be identified by the bus master by means of the conditional search function (see "rom function commands") if the search conditions (address 20eh) are set accordingly. control/status register the ds1921 is set up for its operation by writing appropriate data to its special function registers that are located in the register page. several functions that are controlled by a single bit only are combined into a single byte called control register (address 20eh). this register can be read and written. if the device is programmed for a mission, writing to the control register or any other writable register (addresses 200 to 213h) will at the first attempt end the mission , but not overwrite any settings. every subsequent write attempt, however, will change the register contents. in the same way as the control register is used to control single-bit functions, the status register provides a read-out for single-bit status information. the status register is located at address 214h and is read-only, except for bit 5 (mip). write accesses to any other register/counter in the address range of 215h and higher are ignored. they do not have any effect on the status or behavior of the device. control register (address 20eh) bit 0 tas timer alarm search if this bit is 1, the device will respond to a conditional search command if during a mission a timer alarm has occurred. since a timer alarm cannot be disabled, the taf flag usually reads 1 during a mission. therefore it may be advisable to set the tas bit to a 0, in most cases. bit 1 ths temperature high alarm search if this bit is 1, the device will respond to a conditional search command if during a mission the temperature has reached or is higher than the high temperature threshold.
ds1921l-f5x 11 of 38 bit 2 tls temperature low alarm search if this bit is 1, the device will respond to a conditional search command if during a mission the temperature has reached or is lower than the low temperature threshold. bit 3 ro rollover enable/disable this bit controls whether the temperature logging memory is overwritten with new data or whether data logging is stopped once the memory is filled with data during a mission. setting this bit to a 1 enables the rollover and data logging continues at the beginning overwriting previously collected data. clearing this bit to a 0 disables the rollover and no further temperature values will be stored in the temperature logging memory once it is filled with data. bit 4 em enable mission this bit controls whether the ds1921 will begin a mission as soon as the sample rate is written. to enable the device for a mission, this bit must be 0. bit 5 0 0 (no function, reads always 0) bit 6 mclre memory clear enable this bit needs to be set to a logic 1 to enable the clear memory function which is invoked as a memory function command. the time-stamp, histogram and logging memory as well as the mission time stamp, mission samples counter, mission start delay and sample rate will be cleared only if the clear memory command is issued with the next access to the device . the mclre bit will return to 0 as the next memory function command is executed. bit 7 eosc enable oscillator this bit controls the crystal oscillator of the real-time clock. when set to a logic 0, the oscillator will start operation. when written to a logic 1, the oscillator will stop and the device is in a low-power data retention mode. this bit must be 0 for normal operation. status register (address 214h) bit 0 taf timer alarm flag if this bit reads 1 a real-time clock alarm has occurred (see section timekeeping for details). the timer alarm flag is cleared by writing this bit to a logic 0. since the timer alarm cannot be disabled, the taf flag usually reads 1 during a mission. bit 1 thf temperature high flag a logic 1 in the temperature high flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or higher than the value in the high temperature threshold register. thf is cleared by writing this bit to a logic 0.
ds1921l-f5x 12 of 38 bit 2 tlf temperature low flag a logic 1 in the temperature low flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or lower than the value in the low temperature threshold register. tlf is cleared by writing this bit to a logic 0. bit 3 0 (no function, reads always 0) bit 4 sip sample in progress if this bit reads 1 the ds1921 is currently performing a self-initiated temperature conversion as part of a mission in progress. the sip bit will change from 0 to 1 approximately 250 ms before the actual temperature conversion begins allowing the circuitry of the chip to wake-up. a temperature conversion including a ?wake-up phase? takes maximum 750 ms. during this time read accesses to the memory pages 17 and higher are permissible but may reveal invalid data. bit 5 mip mission in progress if this bit reads 1 the ds1921 has been set up for a mission and this mission is still in progress. a mission is started if the em bit of the control register (address 20eh) is 0 and a non-0 value is written to the sample rate register, address 20dh. the mip bit returns from a logic 1 to a logic 0 when a mission is ended. a mission will end with the first write attempt (copy scratchpad command) to any register in the address range of 200h to 213h. the first write access will only end the mission and not alter any data, even if the aa-bit in the e/s register reads 1 (see copy scratchpad command). an alternative method to end a mission is directly writing to the status register, address 214, and setting the mip bit to 0. this write access will alter the bit already at the first attempt. the mip bit can only be written to a 0. all other status bits are read-only. bit 6 memclr memory cleared if this bit reads 1 all the memory pages 17 and higher (alarm time stamps/durations, temperature histogram, temperature log), as well as the mission time stamp, mission samples counter, mission start delay and sample rate have been cleared to 0 from executing a clear memory function command. the memclr bit will return to 0 as soon as a new mission is started by writing a non-0 value to the sample rate register provided that the em bit is also 0. the memory has to be cleared in order for a mission to start . bit 7 tcb temperature core busy if this bit reads 0 the ds1921 is currently performing a temperature conversion, either self-initiated because of a mission being in progress or initiated by a command when a mission is not in progress. the sip bit will change from 1 to 0 approximately 250 ms before the actual temperature conversion begins allowing the circuitry of the chip to wake-up. a temperature conversion including a ?wake-up phase? takes maximum 750 ms. during this time read accesses to the memory pages 17 and higher are permissible but may reveal invalid data.
ds1921l-f5x 13 of 38 missioning the typical task of the ds1921 is recording the temperature of a temperature-sensitive object that is traveling from one place to another. usually space limitations and economic reasons do not allow such objects being monitored by sensors directly connected to a computer. since it is small enough to be mounted on almost any object the ds1921 can travel directly with the object and monitor its temperature. setting up the ds1921 for such a journey or mission is called missioning. before it is able to record valid data, the ds1921 needs to have its real-time clock set to valid time and date. this reference time may be utc (also called gmt, greenwich mean time) or any other time standard the sender and receiver of the object have agreed on. the clock must be running ( eosc = 0). setting a real-time clock alarm is optional. the memory assigned to storing alarm time stamps and durations, temperature histogram, temperature log as well as the mission time stamp, mission samples counter, mission start delay and sample rate must be cleared using the memory clear command. to enable the device for a mission, the em flag must be set to 0. these are general settings that have to be made regardless of the type of object to be monitored and the duration of the mission. next the low temperature and high temperature thresholds to specify the temperature tolerance band must be written. how to convert a temperature value into the binary code to be written to the threshold registers is described under ?temperature conversion? earlier in this document. the state of the search condition bits in the control register does not affect the mission. if multiple devices are connected to form a microlan bus, the setting of the search condition will enable devices to participate in the conditional search if certain events such as timer or temperature alarm have occurred. details on the search conditions are found in the section ?rom function commands? later in this document and in the control register description. the setting of the ro bit (rollover enable) and sample rate depend on the duration of the mission and the monitoring requirements. if the most recent temperature history is important, the rollover should be enabled (ro = 1). otherwise one should estimate the duration of the mission in minutes and divide the number by 2048 to calculate the value of the sample rate (number of minutes between temperature conversions). if the estimated duration of a mission is 10 days (= 14400 minutes), for example, then the 2048-byte capacity of the temperature logging memory would be sufficient to store a new value every 7 minutes. since large objects do not change their temperature very quickly when left to their environment, one could even chose a sample rate of 10 minutes without the risk of losing valuable information, reserving memory space for unexpected delays. if a mission is fairly long and the temperature logging memory of the ds1921 is not large enough to store all temperature readings, one can use several ds1921 and set the mission start delay to values that make the second device start recording as soon as the memory of the first device is full, and so on for the third and fourth device, etc. the ro bit needs to be set to 0 to disable rollover that would otherwise overwrite the recorded temperature log. the mission start delay is stored in minutes as unsigned 16-bit integer number at addresses 212h and 213h. the maximum delay is 65535 minutes, equivalent to 45 days, 12 hours and 15 minutes. the delay determines how many minutes will have to expire after the beginning of a mission until the first temperature measurement of the mission is done. after the ro bit and the mission start delay are set, the sample rate is the last element of data that is written to the sample rate register. the sample rate may be any value from 1 to 255, coded as an unsigned 8-bit binary number. as soon as the sample rate is written, the ds1921 will copy the current
ds1921l-f5x 14 of 38 time and date into the mission time stamp register 2 , and set the mip flag and clear the memclr flag. after as many minutes as specified by the mission start delay are over, the device will do the first temperature conversion of the mission. this will increment both the mission samples counter and device samples counter. all subsequent temperature measurements will be made as many minutes apart from each other as specified by the value in the sample rate register. one may read the memory of the ds1921 to watch the mission as it progresses at any time. after the mission is started, one should read the complete register page and store the contents of the temperature alarm registers up to the device samples counter in encrypted form as data file in the 4096-bit sram section of the device. this general purpose memory operates independently of the memory used for recording during a mission. however, one must not try writing any of the writable registers of the register page since this will end the mission. address registers and transfer status because of the serial data transfer, the ds1921 employs three address registers, called ta1, ta2 and e/s (figure 6). registers ta1 and ta2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a read command. register e/s acts like a byte counter and transfer status register. it is used to verify data integrity with write commands. therefore, the master only has read access to this register. the lower 5 bits of the e/s register indicate the address of the last byte that has been written to the scratchpad. this address is called ending offset. bit 5 of the e/s register, called pf or ?partial byte flag,? is set if the number of data bits sent by the master is not an integer multiple of 8. bit 6 is always a 0. note that the lowest 5 bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. this address is called byte offset. if the target address for a write command is 13ch, for example, then the scratchpad will store incoming data beginning at the byte offset 1ch and will be full after only 4 bytes. the corresponding ending offset in this example is 1fh. for best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1fh. however, it is possible to write 1 or several contiguous bytes somewhere within a page. the ending offset together with the partial and overflow flag is mainly a means to support the master checking the data integrity after a write command. the highest valued bit of the e/s register, called aa or authorization accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. writing with verification to write data to the ds1921, the scratchpad has to be used as intermediate storage. first the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. in the next step, the master sends the read scratchpad command to read the scratchpad and to verify data integrity. as preamble to the scratchpad data, the ds1921 sends the requested target address ta1 and ta2 and the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag indicates that the write command was not recognized by the ibutton. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue verifying every data bit. after the master has verified the data, it has to send the copy scratchpad command. this 2 note that currently the cent bit of the rtc registers is not copied to the mission time stamp. the future versions of thermochron may implement the corresponding cent bit in the mission time stamp registers and the rtc cent bit value would be copied into it. please see note 11 for an example of how dallas semiconductor?s ibutton viewer implements the mission time stamp century bit calculation that would work with both the current and future versions of thermochrons.
ds1921l-f5x 15 of 38 command must be followed exactly by the data of the three address registers ta1, ta2 and e/s as the master has read them verifying the scratchpad. as soon as the ds1921 has received these bytes, it will copy the data to the requested location beginning at the target address. memory function commands the ?memory function flow chart? (figure 7) describes the protocols necessary for accessing the memory. an example follows the flowchart. the communication between master and ds1921 takes place either at regular speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode the ds1921 assumes regular speed. write scratchpad command [0fh] after issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. the data will be written to the scratchpad starting at the byte offset (t4:t0). the ending offset (e4:e0) will be the byte offset at which the master stops writing data. only full data bytes are accepted. if the last data byte is incomplete, its content will be ignored and the partial byte flag pf will be set. when executing the write scratchpad command the crc generator inside the ds1921 (see figure 12) calculates a crc of the entire data stream, starting at the command code and ending at the last data byte sent by the master. this crc is generated using the crc16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses ta1 and ta2 as supplied by the master and all the data bytes. the master may end the write scratchpad command at any time. however, if the ending offset is 11111b, the master may send 16 read time slots and will receive the crc generated by the ds1921. the range 200h to 213h of the register page is write-protected during a mission. see the status register description for details. read scratchpad command [aah] this command is used to verify scratchpad data and target address. after issuing the read scratchpad command, the master begins reading. the first 2 bytes will be the target address. the next byte will be the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t4:t0). regardless of the actual ending offset the master may read data until the end of the scratchpad after which it will receive a crc16 of the command code, target addresses ta1 and ta2, the e/s byte, and the scratchpad data starting at the target address. after the crc is read, the bus master will receive logical 1s from the ds1921 until a reset pulse is issued. copy scratchpad [55h] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which can be obtained by reading the scratchpad for verification. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa (authorization accepted) flag will be set and the copy will begin. a pattern of alternating 1s and 0s will be transmitted after the data has been copied until a reset pulse is issued by the master. any attempt to reset the part will be ignored while the copy is in progress. copy typically takes 2 s per byte. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. anywhere from 1 to 32 bytes may be copied to memory with this command. the aa flag will be cleared only by executing a write scratchpad command.
ds1921l-f5x 16 of 38 read memory [f0h] the read memory command may be used to read the entire memory. after issuing the command, the master must provide the 2-byte target address. after the 2 bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. it is important to realize that the target address registers will contain the address provided. the ending offset/data status byte is unaffected. the hardware of the ds1921 provides a means to accomplish error-free writing to the memory section. to safeguard reading data in the 1-wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16-bit crc with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see the book of ds19xx ibutton standards, chapter 7 or application note 114 for the recommended file structure.) read memory with crc [a5h] the read memory with crc command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device during a mission. following the last data byte of the memory page addressed the ds1921 transmits a 16-bit crc generated by the device. after having sent the command code of the read memory with crc command, the bus master sends a 2-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with the subsequent read data time slots the master receives data from the ds1921 starting at the initial address and continuing until the end of a 32-byte page is reached. at that point the bus master will send 16 additional read data time slots and receive the 16-bit crc. with subsequent read data time slots the master will receive data starting at the beginning of the next page followed again by the crc for that page. this sequence will continue until the final page is read by the bus master. with the initial pass through the read memory with crc flow chart the 16-bit crc value is the result of shifting the command byte into the cleared crc generator followed by the 2 address bytes and the contents of the data memory. subsequent passes through the read memory with crc flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the contents of the data memory page. after the 16-bit crc of the last page is read, the bus master will receive logical 1s from the ds1921 until a reset pulse is issued. the read memory with crc command sequence can be ended at any point by issuing a reset pulse. clear memory [3ch] the clear memory command is used to clear the memory address range from 220h and higher as well as the sample rate, mission start delay, mission time stamp, and mission samples counter in the register page. the memory must be cleared for the device to be set up for another mission. for the clear memory command to function the mclre bit in control register must be set to 1. the clear memory command must be issued with the very next access to the device?s memory functions (?timed access?). issuing any other valid memory function command will reset the mclre bit. the clear memory command takes approximately 500 s to complete and cannot be interrupted. however, it is possible to issue a reset/presence sequence, execute any rom command and access the 4096 bits of user-ram or read the real-time clock or status register while the clear memory command is in progress. as the clear memory command is completed the memclr bit in the status register will read 1 and the mclre bit will be 0.
ds1921l-f5x 17 of 38 convert temperature [44h] the convert temperature command can be issued if a mission is not in progress to measure the current temperature of the device. the result of the temperature conversion will be found at memory address 211h in the register page. this command takes approximately 750 ms to complete and cannot be interrupted. memory access to any location of the device is possible while the temperature conversion takes place. memory function flow chart figure 7 master tx memory function command y to figure 7 second part 1) n 0fh write ? y from rom functions flow chart (figure 9) ds1921 sets scratchpad offset = (t4:t0) and clears (pf, aa) ds1921 sets (e4:e0) =scratchpad offset bus master tx ta1 (t7:t0) 1) bus master tx ta2 (t15:t8) 1) master tx data byte to scratchpad offset 1) to rom function flow chart (figure 9) 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds1921 is to be reset from overdrive speed to regular speed scratchpad n bus master rx "1"s 2) 1) y bus master tx reset ? scratch- pad offset = 11111b ? bus master tx reset ? ds1921 increments scratchpad offset n bus master rx crc16 of command, address, data bus master tx reset ? 2) n y y y n partial byte written ? n 2) 1) pf = 1 y scratchpad aah read ? bus master rx ta1 (t7:t0) bus master rx ta2 (t15:t8) master rx ending offset with data status (e/s) ds1921 sets scratchpad offset=(t4:t0) 1) 1) 1) master rx data byte from scratchpad offset 1) bus master tx reset ? n n scratch- pad offset = 11111b ? y y 2) 1) ds1921 increments scratchpad offset bus master rx "1"s figure 7 second part ds1921 sets mclre = 0 ds1921 sets mclre = 0 bus master rx crc16 of command, ta1, ta2, e/s byte, and data starting at the target address 1) bus master tx reset ? from 2) y n
ds1921l-f5x 18 of 38 memory function flow chart figure 7 (cont?d) bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) n y from figure 7 first part to figure 7 third part 1) 1) bus master tx e/s byte 1) scratchpad 55h copy ? ds1921 copies scratchpad data to memory 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds1921 is to be reset from overdrive speed to regular speed bus master tx reset ? bus master tx reset ? copying finished ? n y ds1921 tx "1" 1) ds1921 tx "0" 1) bus master rx "1"s 1) aa = 1 y n from figure 7 third part to figure 7 first part f0h read memory ? n y y bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) ds1921 sets memory address = (t15:t0) 1) 1) n y n master rx data byte from memory address 1) 2) bus master tx reset ? ? end of memory ds1921 address counter increments bus master rx "1"s 1) y n 2) bus master tx reset ? bus master rx "1"s 1) y n y n authorization code match ? 2) 2) ds1921 sets mclre = 0 ds1921 sets mclre = 0
ds1921l-f5x 19 of 38 memory function flow chart figure 7 (cont?d) read memory a5h with crc ? bus master rx crc16 of command, address, data (1st pass); crc16 of data (subsequent passes) n from figure 7 second part 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds1921 is to be reset from overdrive speed to regular speed 1) 1) legend: decision made by the master by ds1921 decision made end of memory ? bus master tx reset ? n y y n 2) crc correct ? bus master tx reset n y 2) bus master tx ta1 (t7:t0) ds1921 sets memory address = (t15:t0) y ds1921 increments address counter 1) 1) y n bus master tx reset ? 2) end of page ? n y bus master tx ta2 (t15:t8) bus master rx data from memory 1) bus master rx 1's to figure 7 second part ds1921 sets mclre = 0 to figure 7 fourth part from figure 7 fourth part
ds1921l-f5x 20 of 38 memory function flow chart figure 7 (cont?d) from figure 7 third part 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds1921 is to be reset from overdrive speed to regular speed to figure 7 third part clear memory 3ch ? n y y n mclre = 1 ? bus master tx reset ? y n 2) ds1921 sets mclre = 0 ds1921 clears alarm time stamps and durations ds1921 clears histogram memory ds1921 clears temperature log memory ds1921 clears mission time stamp mission samples counter mission start delay sample rate convert temp. 44h ? bus master tx reset ? y n 2) n y bus master tx reset ? y n 2) ds1921 performs a temperature conversion ds1921 sets mclre = 0 ds1921 copies the temperature value to address 211h ds1921 sets sip = 1 ds1921 sets sip = 0 ds1921 sets memclr = 1 mip = 1 ? y n
ds1921l-f5x 21 of 38 1-wire bus system the 1-wire bus is a system which has a single bus master and one or more slaves. in all instances the ds1921 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx ibutton standards. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or three-state outputs. the 1-wire port of the ds1921 is open-drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. at regular speed the 1-wire bus has a maximum data rate of 16.3 kbits per second. the speed can be boosted to 142 kbits per second by activating the overdrive mode. the 1-wire bus requires a pullup resistor of approximately 5 k ? . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 s (overdrive speed) or more than 120 s (regular speed), one or more devices on the bus may be reset. hardware configuration figure 8 rx tx open drain port pin data rx tx ? 100 mosfet 5 a typ. ds1921 1-wire port rx = receive tx = transmit bus master vpup 5 k ? typ. transaction sequence the protocol for accessing the ds1921 via the 1-wire port is as follows: initialization rom function command memory function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds1921 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section.
ds1921l-f5x 22 of 38 rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 9). read rom [33h] this command allows the bus master to read the ds1921's 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single ds1921 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48-bit serial number will result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds1921 on a multidrop bus. only the ds1921 that exactly matches the 64-bit rom sequence will respond to the following memory function command. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, three-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a search rom, including an actual example. conditional search [ech] the conditional search rom command operates similarly to the search rom command except that only devices fulfilling the specified condition will participate in the search. the condition is specified by the bit functions tas, ths and tls in the control register, address 20eh. the conditional search rom provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a temperature leaving the tolerance band. after each pass of the conditional search that successfully determined the 64-bit rom for a specific device on the multidrop bus, that particular device can be individually accessed as if a match rom had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse.
ds1921l-f5x 23 of 38 for the conditional search, one can select any combination of the three search conditions by writing the associated bit to a logical 1. these bits correspond directly to the flags in the status register of the device. if the flag in the status register reads 1 and the corresponding bit in the control register is a logical 1, too, the device will respond to the conditional search command. if more than one bit search condition is selected, the first event occurring will make the device respond to the conditional search command. overdrive skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit rom code. unlike the normal skip rom command, the overdrive skip rom sets the ds1921 in the overdrive mode (od = 1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed (od = 0). when issued on a multidrop bus this command will set all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will speed up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-and result). overdrive match rom [69h] the overdrive match rom command followed by a 64-bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds1921 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds1921 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive skip or match command will remain in overdrive mode. all overdrive-capable slaves will return to regular speed at the next reset pulse of minimum 480 s duration. the overdrive match rom command can be used with a single or multiple devices on the bus.
ds1921l-f5x 24 of 38 rom functions flow chart figure 9 y y y ds1921 tx bit 0 ds1921 tx bit 0 master tx bit 0 ds1921 tx family code 1 byte master tx bit 0 nn ds1921 tx bit 1 ds1921 tx bit 1 master tx bit 1 ds1921 tx serial number 6 bytes master tx bit 1 y nn y y y 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) f0h search rom command ? n n n n to figure 9 second part master tx rom function command ds1921 tx presence pulse master tx reset pulse from figure 9 second part short reset pulse ? n y od = 0 1) 2) from memory functions flow chart (figure 7) 33h read rom command ? match rom 55h command ? bit 0 match ? bit 0 match ? bit 1 match ? bit 1 match ? ds1921 tx bit 63 ds1921 tx bit 63 master tx bit 63 ds1921 tx crc byte master tx bit 63 nn y y to figure 9 second part second part from figure 9 1) to be transmitted or received at overdrive speed if od = 1 2) the presence pulse will be short if od = 1 1) 1) 1) 1) 1) bit 63 match ? bit 63 match ? to memory functions flow chart (figure 7) y ds1921 tx bit 0 ds1921 tx bit 0 master tx bit 0 1) 1) 1) ds1921 tx bit 1 ds1921 tx bit 1 master tx bit 1 1) 1) 1) ech cond. search rom cmd. ? n n y ds1921 tx bit 63 ds1921 tx bit 63 master tx bit 63 1) 1) 1) y bit 0 match ? n n bit 63 match ? y bit 1 match ? n cond. met ? n y
ds1921l-f5x 25 of 38 rom functions flow chart figure 9 (cont?d) to figure 9 to figure 9 first part first part from figure 9 3) always to be transmitted at overdrive speed first part od = 1 first part from figure 9 y overdrive 3ch ? skip n y y y od = 1 y n overdrive 69h match ? n bit 63 match ? master tx bit 63 3) n bit 1 match ? master tx bit 1 3) n bit 0 match ? master tx bit 0 3) master tx reset n y pulse ? y n cch skip rom command ?
ds1921l-f5x 26 of 38 mission example: prepare and start a new mission assumption: the previous mission has come to an end. to end an ongoing mission one may, for example, perform a sequence as in step 1 or write the mip bit in the status register to 0. the preparation of the ds1921 for a mission including the start of the mission requires up to four steps: step 1: set the real-time clock (if it needs to be adjusted) step 2: clear the data of the previous mission step 3: set the search condition and mission start delay step 4: set the temperature alarms and write the sample rate to start the mission step 1 let the actual time be 15:30:00 hours on wednesday, the 7 th of april in 1999. this results in the following data to be written to the real-time clock registers: address: 200h 201h 202h 203h 204h 205h 206h data: 00h 30h 15h 03h 07h 04h 99 with only a single ds1921 connected to the bus master, the communication of step 1 looks like this: master mode data (lsb first) comments tx reset reset pulse (480-960 s) rx presence presence pulse tx cch issue ?skip rom? command tx 0fh issue ?write scratchpad? command tx 00h ta1, beginning offset=00h tx 02h ta2, address=0200h tx <7 data bytes> write 7 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx aah issue ?read scratchpad? command rx 00h read ta1, beginning offset=00h rx 02h read ta2, address=0200h rx 06h read e/s, ending offset=6h, flags=0h rx <7 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 55h issue ?copy scratchpad? command tx 00h tx 02h tx 06h ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse
ds1921l-f5x 27 of 38 step 2 set the mclre bit to 1, enable the real-time clock and then execute the clear memory command. this results in the following data to be written to the status register: address: 20eh data: 40h with only a single ds1921 connected to the bus master, the communication of step 2 looks like this: master mode data (lsb first) comments tx reset reset pulse (480-960 s) rx presence presence pulse tx cch issue ?skip rom? command tx 0fh issue ?write scratchpad? command tx 0eh ta1, beginning offset=0eh tx 02h ta2, address=020eh tx 40h write status byte to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue "skip rom" command tx aah issue ?read scratchpad? command rx 0eh read ta1, beginning offset=0eh rx 02h read ta2, address=020eh rx 0eh read e/s, ending offset = 0eh, flags = 0h rx 40h read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 55h issue ?copy scratchpad? command tx 0eh tx 02h tx 0eh ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 3ch issue ?clear memory? command tx reset reset pulse rx presence presence pulse
ds1921l-f5x 28 of 38 step 3 in this example the rollover is disabled and the search condition is set for a high temperature only. the mission is to start with a delay of 90 (5ah) minutes. this results in the following data to be written to the special function registers: address: 20eh 20fh 210h 211h 212h 213h data: 02h 00* 00* 00* 5ah 00 * writing through address locations 20fh to 211h is faster than accessing the mission start delay register in a separate cycle. the write attempt has no effect on the contents of these registers. with only a single ds1921 connected to the bus master, the communication of step 3 looks like this: master mode data (lsb first) comments tx reset reset pulse (480-960 s) rx presence presence pulse tx cch issue ?skip rom? command tx 0fh issue ?write scratchpad? command tx 0eh ta1, beginning offset=0eh tx 02h ta2, address=020eh tx <6 data bytes> write 6 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx aah issue ?read scratchpad? command rx 0eh read ta1, beginning offset=0eh rx 02h read ta2, address=020eh rx 13h read e/s, ending offset=13h, flags=0h rx <6 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 55h issue ?copy scratchpad? command tx 0eh tx 02h tx 13h ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse
ds1921l-f5x 29 of 38 step 4 in this example the temperature alarms are set to -5 c for the low temperature threshold and 0 c for the high temperature threshold. the sample rate is once every 10 minutes, allowing the mission to last up to 14 days. this results in the following data to be written to the special function registers: address: 20bh 20ch 20dh data: 46h 50h 0ah with only a single ds1921 connected to the bus master, the communication of step 4 looks like this: master mode data (lsb first) comments tx reset reset pulse (480-960 s) rx presence presence pulse tx cch issue ?skip rom? command tx 0fh issue ?write scratchpad? command tx 0bh ta1, beginning offset=0bh tx 02h ta2, address=020bh tx <3 data bytes> write 3 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx aah issue ?read scratchpad? command rx 0bh read ta1, beginning offset=0bh rx 02h read ta2, address=020bh rx 0dh read e/s, ending offset=0dh, flags=0h rx <3 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 55h issue ?copy scratchpad? command tx 0bh tx 02h tx 0dh ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse if step 4 was successful, the mission time stamp register will contain the date and time of the real-time clock, the mip bit in the status register will be 1 and the memclr bit will be 0.
ds1921l-f5x 30 of 38 1-wire signaling the ds1921 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. all these signals except presence pulse are initiated by the bus master. the ds1921 can communicate at two different speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the ds1921 will communicate at regular speed. while in overdrive mode the fast timing applies to all waveforms. the initialization sequence required to begin any communication with the ds1921 is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds1921 is ready to send or receive data, given the correct rom command and memory function command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s at regular speed, 48 s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds1921 waits (t pdh , 15-60 s at regular speed, 2-6 s at overdrive speed) and then transmits the presence pulse (t pdl , 60-240 s at regular speed, 8-24 s at overdrive speed). a reset pulse of 480 s or longer will exit the overdrive mode, returning the device to regular speed. if the ds1921 is in overdrive mode and the reset pulse is no longer than 80 s, the device will remain in overdrive mode. read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds1921 to the master by triggering a delay circuit in the ds1921. during write time slots, the delay circuit determines when the ds1921 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the ds1921 will hold the data line low overriding the 1 generated by the master. if the data bit is a 1, the device will leave the read data time slot unchanged. initialization procedure ?reset and presence pulses? figure 10 resistor master ds1921 master rx "presence pulse" regular speed overdrive speed 480 s t rstl < * 480 s t rsth < ** 15 s t pdh < 60 s 60 t pdl < 240 s 48 s t rstl < 80 s 48 s t rsth < ** 2 s t pdh < 6 s 8 t pdl < 24 s master tx "reset pulse" v pullup v pullup min v ih min v il max 0v t rsth t rstl t pdh t pdl t r * in order not to mask interrupt signaling by other devices on the 1-wire bus and to prevent a power-on reset of the parasite powered circuit which sets the hide flag, t rstl + t r should always be less than 960 s. ** includes recovery time
ds1921l-f5x 31 of 38 read/write time diagram figure 11 write-one time slot 15s (od: 2s) 60s (od: 6s) ds1921 sampling window v pullup v pullup min v ih min v il max 0v t slot t rec t low1 regular speed overdrive speed 60 s t slot < 120 s 1 s t low1 < 15 s 6 s t slot < 16 s 1 s t low1 < 2 s 1 s t rec < 1 s t rec < resistor master write-zero time slot 15s resistor master (od: 2s) ds1921 60s t low0 sampling window (od: 6s) regular speed overdrive speed 60 s t low0 < t slot < 120 s 1 s t rec < 6 s t low0 < t slot < 16 s 1 s t rec < v pullup v pullup min v ih min v il max 0v t slot t rec
ds1921l-f5x 32 of 38 read-data time slot resistor master ds1921 master sampling window regular speed overdrive speed 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s 6 s t slot < 16 s 1 s t lowr < 2 s 0 t release < 4 s 1 s t rec < t rdv = 2 s t su < 1 s v pullup v pullup min v ih min v il max 0v t slot t rec t lowr t su t rdv t release
ds1921l-f5x 33 of 38 crc generation with the ds1921 there are two different types of crcs (cyclic redundancy checks). one crc is an 8-bit type and is stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bit rom and compare it to the value stored within the ds1921 to determine if the rom data has been received error-free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (non-inverted) form when reading the rom of the ds1921. it is computed at the factory and lasered into the rom. the other crc is a 16-bit type, generated according to the standardized crc16-polynomial function x 16 + x 15 + x 2 + 1. this crc is used for error detection when reading data memory using the read memory with crc command and for fast verification of a data transfer when writing to or reading from the scratchpad. it is the same type of crc as is used with nv ram-based ibuttons for error detection within the ibutton extended file structure. in contrast to the 8-bit crc, the 16-bit crc is always returned or sent in the complemented (inverted) form. a crc-generator inside the ds1921 chip (figure 12) will calculate a new 16-bit crc as shown in the command flow chart of figure 7. the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the crc error. with the initial pass through the read memory with crc flow chart, the 16-bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the 2 address bytes and the data bytes. subsequent passes through the read memory with crc flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the data bytes . with the write scratchpad command the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2 and all the data bytes. the ds1921 will transmit this crc only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. the data may start at any location within the scratchpad. with the read scratchpad command the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, the e/s byte, and the scratchpad data starting at the target address. the ds1921 will transmit this crc only if the reading continues through the end of the scratchpad, regardless of the actual ending offset. for more details on generating crc values, including example implementations in both hardware and software, see the ?book of ds19xx ibutton standards.?
ds1921l-f5x 34 of 38 crc-16 hardware description and polynomial figure 12 9th stage 10th stage 11th stage 12th stage 13th stage 14th stage 15th stage 16th stage 1st stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage 2nd stage x 7 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 input data crc output polynomial = x 16 x 15 x 2 + + + 1
ds1921l-f5x 35 of 38 physical specification size see mechanical drawing weight 3.3 grams humidity 90% rh at 50 c altitude 10,000 feet expected service life 10 years at 25 c safety meets ul#913 (4 th edit.); intrinsically safe apparatus, approval under entity concept for use in class i, division 1, group a, b, c and d locations (application pending) absolute maximum ratings* voltage on data to ground -0.5v to +6.0v operating and storage temperature -40 c to +85 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. this devices must not be exposed to temperatures over 70 c for extended time periods. dc electrical characteristics (vpup=2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 8 logic 0 v il -0.3 +0.8 v 1, 9 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 a3 battery life time (samples) n s 2500000 ----- 10 capacitance (ta = 25c) parameter symbol min typ max units notes i/o (1-wire) c in/out 100 800 pf 6 ac electrical characteristics regular speed (vpup=2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write-1 low time t low1 115 s write-0 low time t low0 60 120 s read low time t lowr 115 s read data valid t rdv exactly 15 s release time t release 015 45 s read data setup t su 1 s5 recovery time t rec 1 s reset time high t rsth 480 s4 reset time low t rstl 480 s7 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
ds1921l-f5x 36 of 38 ac electrical characteristics overdrive speed (vpup=2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 616 s write-1 low time t low1 12 s write-0 low time t low0 616 s read low time t lowr 12 s read data valid t rdv exactly 2 s release time t release 0 1.5 4 s read data setup t su 1 s5 recovery time t rec 1 s reset time high t rsth 48 s4 reset time low t rstl 48 80 s presence detect high t pdhigh 26 s presence detect low t pdlow 824 s rom encoding vs range of accurate operations the most significant 12 bits of the 48-bit serial number are being used in the ds1921l-f5x thermochron product series to identify both the lower limit and the range of accurate operations, as elaborated below. software developers may use this coding mechanism to automatically determine the validity of sampled temperature values based on the content of this 12-bit field. part number range of accurate operations s/n 48 bits encodeing family code ds1921l-f51 -10 c to +85c 34cxxxxxxxxx 21 ds1921l-f52 -20 c to +85c 254xxxxxxxxx 21 DS1921L-F53 -30 c to +85c 15cxxxxxxxxx 21 ds1921l-f50 -40 c to +85c 064xxxxxxxxx 21 the custom rom coding mechanism reflects both the lower limit and the operating range of the thermochron ibutton by combining coded representations of these two parameters. each parameter is first represented by a 5-bit binary code according to the following equations: starting temperature mapping code: c start = (t l +40)/5 where t l is the lower temperature limit of the specified accurate operation range. width of accurate operation range mapping code: c range = (t u -t l )/5 where t l and t u are respectively the lower and upper temperature limits of the specified accurate operation range. for example, if a part?s accurate operation range is ?30 c to +85 c. the custom code 15ch is determined as follows: 1) starting temperature -30 maps to a 5-bit binary code: c start =(-30+40)/5=2d=00010b 2) operation range width 85-(-30) = 115 maps to a 5-bit binary code: c range =115/5=23d= 10111b 3) pad two 00 onto these two codes to make a 12-bit binary code: 00010 10111 00 4) in hex form the above 12-bit code becomes: 15c
ds1921l-f5x 37 of 38 notes: 1. all voltages are referenced to ground. 2. v pup = external pull-up voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 6. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? = resistor is used to pull up the data line to v pup , 5 s after power has been applied the parasite capacitance will not affect normal communications. 7. the reset low time (t rstl ) should be restricted to a maximum of 960 s to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses. 8. v ih is a function of the external pull-up resistor and v pup . 9. under certain low-voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 10. the number of temperature conversions (= samples) possible with the built-in energy source depends on the operating and storage temperature of the device. when not in use for a mission, the device should be stored at a temperature not exceeding 25 c. 11. the 'cent' bit in the 'real time clock registers' describes what century it is. the convention that the data sheet and our demo software uses is 19xx = 0 and 20xx = 1. there is no corresponding 'cent' bit in the 'mission time stamp' as might be expected. to compensate for this, the following logic has been implemented in the ibutton viewer and other examples: if 'cent' in 'mission time stamp' is 1 then century is 20 else if there is a mission ongoing then check century of mission start by calculating the century of ('real time clock' - 'sample rate' * 'mission samples counter') else if 'mission time stamp'(years) <= 70 then century is 20 else century is 19 note: the first condition (cent = 1 in the mission time stamp) will never be true for the current version of the ds1921. however, at some point in the future, there may be other versions of the ds1921 or similar products offered that copy the cent bit from the rtc down to the mission time stamp along with the rest of the rtc information. by implementing the logic outlined above, if that change does occur in the future there will be no need to update any code written up to that point.
ds1921l-f5x 38 of 38 revision history ? 6/7/00 1. fixed a labeling error (t rdv was incorrectly labeled being 45 s) in figure 11. 2. fixed other formatting (subscripting etc.) errors in figure 11. 3. fixed formatting problems in figure 10.

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