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1999 microchip technology inc. ds21160e-page 1 features ? single supply with operation down to 2.5v ? completely implements ddc1 ? /ddc2 ? interface for monitor identification, including recovery to ddc1 ? pin and function compatible with 24lc21 ? low power cmos technology - 1 ma typical active current -10 m a standby current typical at 5.5v ? 2-wire serial interface bus, i 2 c ? compatible ? 100 khz (2.5v) and 400 khz (5v) compatibility ? self-timed write cycle (including auto-erase) ? page-write buffer for up to eight bytes ? 1,000,000 erase/write cycles guaranteed ? data retention > 200 years ? esd protection > 4000v ? 8-pin pdip and soic package ? available for extended temperature ranges description the microchip technology inc. 24lc21a is a 128 x 8- bit dual-mode electrically erasable prom. this device is designed for use in applications requiring storage and serial transmission of configuration and control information. two modes of operation have been imple- mented: transmit-only mode and bi-directional mode. upon power-up, the device will be in the transmit-only mode, sending a serial bit stream of the memory array from 00h to 7fh, clocked by the vclk pin. a valid high to low transition on the scl pin will cause the device to enter the transition mode, and look for a valid control byte on the i 2 c bus. if it detects a valid control byte from the master, it will switch into bi-directional mode, with byte selectable read/write capability of the memory array using scl. if no control byte is received, the device will revert to the transmit-only mode after it receives 128 consecutive vclk pulses while the scl pin is idle. the 24lc21a is available in a standard 8-pin pdip and soic package in both commercial and industrial temperature ranges. - commercial (c): 0c to +70c - industrial (i): -40c to +85c package types block diagram pdip soic 24lc21a nc nc nc v ss 1 2 3 4 8 7 6 5 v cc vclk scl sda 24lc21a nc nc nc v ss 1 2 3 4 8 7 6 5 v cc vclk scl sda i/o control logic hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic sda scl v cc v ss vclk 24lc21a 1k 2.5v dual mode i 2 c ? serial eeprom ddc is a trademark of the video electronics standards association. i 2 c is a trademark of philips corporation.
24lc21a ds21160e-page 2 1999 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ........................................................................7.0v all inputs and outputs w.r.t. v ss .....-0.6v to v cc +1.0v storage temperature ..........................-65 c to +150 c ambient temp. with power applied......-65 c to +125 c soldering temperature of leads (10 seconds) .. +300 c esd protection on all pins ..................................... 3 4 kv * notice: stresses above those listed under maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function v ss ground sda serial address/data i/o scl serial clock (bi-directional mode) vclk serial clock (transmit-only mode) v cc +2.5v to 5.5v power supply nc no connection table 1-2: dc characteristics v cc = +2.5v to 5.5v commercial (c): tamb = 0 c to +70 c industrial (i): tamb =-40 c to +85 c parameter symbol min max units conditions scl and sda pins: high level input voltage low level input voltage v ih v il 0.7 v cc 0.3 v cc v v input levels on vclk pin: high level input voltage low level input voltage v ih v il 2.0 0.2 v cc v v v cc 3 2.7v (note) v cc < 2.7v (note) hysteresis of schmitt trigger inputs v hys .05 v cc v(note) low level output voltage v ol 1 0.4vi ol = 3 ma, v cc = 2.5v (note) low level output voltage v ol 2 0.6vi ol = 6 ma, v cc = 2.5v input leakage current i li -10 10 m av in = 0.1v to v cc output leakage current i lo -10 10 m av out = 0.1v to v cc pin capacitance (all inputs/outputs) cin, cout 10 pf v cc = 5.0v (note) ta m b = 2 5 c, f clk = 1 mhz operating current i cc write i cc read 3 1 ma ma v cc = 5.5v v cc = 5.5v, scl = 400 khz standby current i ccs 30 100 m a m a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc v clk = v ss note: this parameter is periodically sampled and not 100% tested.
1999 microchip technology inc. ds21160e-page 3 24lc21a table 1-3: ac characteristics parameter symbol vcc= 2.5-5.5v standard mode vcc= 4.5 - 5.5v fast mode units remarks min max min max clock frequency f clk 100400khz clock high time t high 4000 600 ns clock low time t low 4700 1300 ns sda and scl rise time t r 1000 300 ns (note 1) sda and scl fall time t f 300 300 ns (note 1) start condition hold time t hd : sta 4000 600 ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 600 ns only relevant for repeated start condition data input hold time t hd : dat 0 0 ns (note 2) data input setup time t su : dat 250 100 ns stop condition setup time t su : sto 4000 600 ns output valid from clock t aa 3500 900 ns (note 2) bus free time t buf 4700 1300 ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of 250 20 + 0.1 c b 250 ns (note 1), c b 100 pf input filter spike suppres- sion (sda and scl pins) t sp 50 50 ns (note 3) write cycle time t wr 10 10 ms byte or page mode transmit-only mode parameters output valid from vclk t vaa 2000 1000 ns vclk high time t vhigh 4000 600 ns vclk low time t vlow 4700 1300 ns vclk setup time t vhst 00ns vclk hold time t spvl 4000 600 ns mode transition time t vhz 1000 500 ns transmit-only power up time t vpu 00ns input filter spike suppres- sion (vclk pin) t spv 100 100 ns endurance 1m 1m cycles 25c, vcc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide noise and spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on our website.
24lc21a ds21160e-page 4 1999 microchip technology inc. 2.0 functional description the 24lc21a is designed to comply to the ddc stan- dard proposed by vesa (figure 3-3) with the exception that it is not access.bus capable. it operates in two modes, the transmit-only mode and the bi-directional mode. there is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (sda). the device enters the transmit-only mode upon power-up. in this mode, the device transmits data bits on the sda pin in response to a clock signal on the vclk pin. the device will remain in this mode until a valid high to low transi- tion is placed on the scl input. when a valid transition on scl is recognized, the device will switch into the bi- directional mode and look for its control byte to be sent by the master. if it detects its control byte, it will stay in the bi-directional mode. otherwise, it will revert to the transmit-only mode after it sees 128 vclk pulses. 2.1 transmit-only mode the device will power up in the transmit-only mode at address 00h. this mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. this device requires that it be initialized prior to valid data being sent in the transmit-only mode (section 2.2). in this mode, data is transmitted on the sda pin in 8-bit bytes, with each byte followed by a ninth, null bit (figure 2-1). the clock source for the transmit-only mode is provided on the vclk pin, and a data bit is output on the rising edge on this pin. the eight bits in each byte are transmitted most significant bit first. each byte within the memory array will be output in sequence. after address 7fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. the bi-directional mode clock (scl) pin must be held high for the device to remain in the transmit-only mode. 2.2 initialization procedure after v cc has stabilized, the device will be in the transmit-only mode. nine clock cycles on the vclk pin must be given to the device for it to perform internal sychronization. during this period, the sda pin will be in a high impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit in address 00h. (figure 2-2). figure 2-1: transmit-only mode figure 2-2: device initialization scl sda vclk tvaa tvaa bit 1 (lsb) null bit bit 1 (msb) bit 7 tvlow tvhigh tvaa tvaa bit 8 bit 7 high impedance for 9 clock cycles tvpu 12 891011 scl sda vclk vcc
1999 microchip technology inc. ds21160e-page 5 24lc21a 3.0 bi-directional mode before the 24lc21a can be switched into the bi-direc- tional mode (figure 3-1), it must enter the transition mode, which is done by applying a valid high to low transition on the bi-directional mode clock (scl). as soon it enters the transition mode, it looks for a control byte 1010 000x on the i 2 c ? bus, and starts to count pulses on vclk. any high to low transition on the scl line will reset the count. if it sees a pulse count of 128 on vclk while the scl line is idle, it will revert back to the transmit-only mode, and transmit its contents starting with the most significant bit in address 00h. however, if it detects the control byte on the i 2 c ? bus, (figure 3-2) it will switch to the in the bi-directional mode. once the device has made the transition to the bi-directional mode, the only way to switch the device back to the transmit-only mode is to remove power from the device. the mode transition process is shown in detail in figure 3-3. once the device has switched into the bi-directional mode, the vclk input is disregarded, with the excep- tion that a logic high level is required to enable write capability. this mode supports a two-wire bi-directional data transmission protocol (i 2 c ? ). in this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. the bus must be con- trolled by a master device that generates the bi-direc- tional mode clock (scl), controls access to the bus and generates the start and stop conditions, while the 24lc21a acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. in the bi- directional mode, the 24lc21a only responds to commands for device 1010 000x. figure 3-1: mode transition with recovery to transmit-only mode figure 3-2: successful mode transition to bi-directional mode tvhz scl sda vclk tr a n s m i t only mode bi-directional recovery to transmit-only mode bit8 (msb of data in 00h) vclk count = 1 2 3 4 127 128 transition mode with possibility to return to transmit-only mode bi-directional permanently scl sda vclk count = 1 2 n 0 vclk transmit only mode mode s1 0 1 0 0 000 ack n < 128
24lc21a ds21160e-page 6 1999 microchip technology inc. figure 3-3: display operation per ddc standard proposed by vesa communication is idle is vsync present? no send edid continuously using vsync as clock high to low transition on scl? no ye s ye s stop sending edid. switch to ddc2 mode. display has transition state ? optional set vsync counter = 0 change on vclk lines? scl, sda or no ye s high - low transition on scl ? reset vsync counter = 0 no ye s valid received? ddc2 address no no vclk cycle? ye s increment vclk counter ye s switch back to ddc1 mode. ddc2 communication idle. display waiting for address byte. ddc2b address received? ye s receive ddc2b command respond to ddc2b command is display access.bus tm ye s valid access.bus address? no ye s see access.bus specification to determine correct procedure. ye s no ye s no no no the 24lc21a was designed to display power-on or ddc circuit powered from +5 volts or start timer reset counter or timer (if appropriate) counter=128 or timer expired? high to low transition on scl? no ye s comply to the portion of flowchart inside dash box note 1: the base flowchart is copyright 1993, 1994, 1995 video electronic standard association (vesa) from vesas display data channel (ddc) standard proposal ver. 2p rev. 0, used by permission of vesa. 2: the dash box and text the 24lc21a and... inside dash box. are added by microchip technology, inc. 3: vsync signal is normally used to derive a signal for vclk pin on the 24lc21a. capable?
1999 microchip technology inc. ds21160e-page 7 24lc21a 3.1 bi-directional mode bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-4). 3.1.1 bus not busy (a) both data and clock lines remain high. 3.1.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.1.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur it will replace data in a first in first out fashion. 3.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. note: once switched into bi-directional mode, the 24lc21a will remain in that mode until power is removed. removing power is the only way to reset the 24lc21a into the transmit-only mode. note: the 24lc21a does not generate any acknowledge bits if an internal programming cycle is in progress. figure 3-4: data transfer sequence on the serial bus (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl sda
24lc21a ds21160e-page 8 1999 microchip technology inc. figure 3-5: bus timing start/stop figure 3-6: bus timing data scl sda start stop v hys t su : sto t hd : sta t su : sta scl sda in sda out t su : sta t sp t aa t f t low t high t hd : sta t hd : dat t su : dat t su : sto t buf t aa t r 3.1.6 slave address after generating a start condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24lc21a. the eighth bit of slave address determines whether the master device wants to read or write to the 24lc21a (figure 3-7). the 24lc21a monitors the bus for its corresponding slave address continuously. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 3-7: control byte allocation operation slave address r/w read 1010000 1 write 1010000 0 r/w a 1010000 read/write start slave address
1999 microchip technology inc. ds21160e-page 9 24lc21a 4.0 write operation 4.1 byte write following the start signal from the master, the slave address (four bits), three zero bits (000) and the r/w bit which is a logic low are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lc21a. after receiv- ing another acknowledge signal from the 24lc21a the master device will transmit the data word to be written into the addressed memory location. the 24lc21a acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24lc21a will not generate acknowledge signals (figure 4-1). it is required that vclk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the vclk is ignored during the self-timed program operation. changing vclk from high to low during the self-timed program operation will not halt programming of the device. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lc21a in the same way as in a byte write. but instead of generating a stop condition the master transmits up to eight data bytes to the 24lc21a which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains constant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (figure 4-3). it is required that vclk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the vclk is ignored during the self-timed program operation. changing vclk from high to low during the self-timed program operation will not halt programming of the device. note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary.
24lc21a ds21160e-page 10 1999 microchip technology inc. figure 4-1: byte write figure 4-2: vclk write enable timing figure 4-3: page write bus activity master sda line bus activity control byte word address data s t o p s t a r t a c k sp a c k a c k vclk scl sda in vclk t hd : sta t hd : sto t vhst t spvl sda line control byte word address s t o p s t a r t a c k a c k a c k a c k a c k data n + 1 data n + 7 data (n) p s vclk bus activity master bus activity
1999 microchip technology inc. ds21160e-page 11 24lc21a 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the flow diagram. figure 5-1: acknowledge polling flow did device acknowledge (ack = 0)? send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 next operation no ye s 6.0 write protection when using the 24lc21a in the bi-directional mode, the vclk pin can be used as a write protect control pin. setting vclk high allows normal write operations, while setting vclk low prevents writing to any location in the array. connecting the vclk pin to v ss would allow the 24lc21a to operate as a serial rom, although this configuration would prevent using the device in the transmit-only mode.
24lc21a ds21160e-page 12 1999 microchip technology inc. 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. 7.1 current address read the 24lc21a contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24lc21a issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc21a discontinues transmission (figure 7-1). figure 7-1: current address read control a c k sp byte data n bus activity sda line bus activity a c k n o master 101 0000 1 s t o p s t a r t 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lc21a as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lc21a will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc21a discontinues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24lc21a transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lc21a to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads the 24lc21a contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection the 24lc21a employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the sda, scl and vclk inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 7-2: random read figure 7-3: sequential read bus activity master sda line bus activity control byte word address data n a c k s t a r t n o s t a r control byte a c k a c k ss t p s t o p 10100000 0 0 0 0 01 1 1 a c k a c k p bus activity master sda line bus activity control byte data n data n+1 data n+2 data n+x a c k a c k a c k n o a c k s t o p
1999 microchip technology inc. ds21160e-page 13 24lc21a 8.0 pin descriptions 8.1 sda this pin is used to transfer addresses and data into and out of the device, when the device is in the bi-direc- tional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the sda pin. this pin is an open drain terminal, therefore the sda bus requires a pullup resistor to v cc (typical 10 k w for 100 khz, 2 k w for 400 khz). for normal data transfer in the bi-directional mode, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.2 scl this pin is the clock input for the bi-directional mode, and is used to synchronize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit-only mode to the bi-direc- tional mode. it must remain high for the chip to continue operation in the transmit-only mode. 8.3 vclk this pin is the clock input for the transmit-only mode (ddc1). in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in the bi-directional mode, a high logic level is required on this pin to enable write capability.
24lc21a ds21160e-page 14 1999 microchip technology inc. notes:
24lc21a 24lc21a product identification system to order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0 c to +70c range: i =-40c to +85c device: 24lc21a dual mode serial eeprom 24lc21at dual mode serial eeprom (tape and reel) 24lc21a /p 1999 microchip technology inc. ds21160e-page 15
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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