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page 1-51 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 features ? single 5-v operation ? low power ? pci compatible dual uart ? pin-to-pin compatible to nm9735 ? 16 byte transmit-receive fifo (uart) ? selectable receive trigger levels ? programmable baud rate generator ? modem control signals ? 5, 6, 7, 8 bit characters selection ? even, odd, no parity, or force parity generations ? status report capability ? compatible with 16c550 ? multi-mode compatible controller (spp, ps2, epp, ecp) ? fast data rates up to 1.5 mbytes/s (parallel port) ? fast data rates up to 1 mbytes/s (serial ports) ? on chip oscillator ? re-map function for legacy ports ? 16 byte fifo (parallel) ? microsoft compatible ? software programmable mode selects ? 128-pin vqfp package applications ? printer server ? portable backup units ? printer interface ? embedded applications ? high speed modems ? monitoring equipment ? add on i/o cards ? serial networking general description the NM9835 is a pci based dual-channel high perfor- mance uart with enhanced bi-directional parallel con- troller. the NM9835 offers 16 byte transmit and receive fifo for each uart channel and 16 byte fifo for printer channel. the NM9835 perform serial-to-parallel conversions on data received from a peripheral device, and parallel-to-serial conversion on data received from its cpu. in addition NM9835 fully supports the existing centronics printer interface as well as ps/2, epp, and ecp modes. the NM9835 is ideally suited for pc applications, such as high speed com ports and parallel port. the NM9835 is available in 128-pin qfp package, it is fabricated in an advanced in submicron cmos process to achieve low drain power and high speed requirements. ordering information commercial grade NM9835cv 128-vqfp 0 c to +70 c industrial grade NM9835ev 128-vqfp -40 c to +85 c
page 1-52 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 128-pin vqfp package NM9835cv n.c. vcc txa ndtra nrtsa gnd rxa ndsra nctsa ncda nria vcc ee-cs ee-clk ee-do ee-di gnd ninta nreset clk ee-en n.c. gnd ad31 ad30 ad29 vcc ad28 ad27 ad26 ad25 ad24 gnd nc/be3 idsel vcc ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 vcc gnd gnd nc/be2 nframe nirdy ntrdy ndevsel nstop nlock nperr nserr par nc/be1 gnd ad15 ad14 ad13 ad12 ad11 n.c. n.c. xtal1 xtal2 gnd aclk 12xclk bclk 6xclk 3xclk vcc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd gnd nc/be0 ad8 ad9 ad10 vcc n.c. n.c. n.c. gnd pd7 pd6 pd5 pd4 gnd pd3 pd2 pd1 pd0 vcc gnd pe nack nbusy slct nfault vcc nstrobe nautofdx ninit nslctin gnd txb ndtrb nrtsb rxb ndsrb nctsb ncdb nrib n.c. n.c. vcc n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
page 1-53 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pin name 128 type description clk 122 i 33 mhz pci system clock input. nreset 121 i pci system reset (avtice low). resets all internal register, sequencers, and signals to a consistent state. during reset condition ad31-0, nser are three- stated. ad31-29 126-128 i/o multiplexed pci address / data bus. a bus transaction consists of an address phase followed by one or more data phase. during the address phase ad31- 0 contain a physical address. write data is stable and valid when nirdy and ntrdy are asserted (active). ad28-24 2-6 i/o see ad31-29 description. ad23-16 11-18 i/o see ad31-29 description. ad15-11 34-38 i/o see ad31-29 description. ad10-8 40-42 i/o see ad31-29 description. ad7-0 46-53 i/o see ad31-29 description. nframe 23 i frame is driven by the current master to indicate the beginning and duration of an access. nframe is asserted to indicate a bus transaction is beginning. while nframe is active, data transfer continues. nirdy 24 i initiator ready. during a write, nirdy asserted indicates that the initiator is driving valid data onto the data bus. during a read, nirdy asserted indicates that the initiator is ready to accept data from the NM9835. ntrdy 25 o target ready (three-state). it is asserted when NM9835 is ready to complete the current data phase. nstop 27 o NM9835 asserts nstop to indicate that it wishes the initiator to stop the transaction in process on the current data phase. nlock 28 i lock indicates an atomic operation that my require multiple transactions to complete. idsel 9 i initialization device select. it is used as a chip select during configuration read and writes transactions. ndevsel 26 o device select (three-state). NM9835 asserts ndevsel when the NM9835 has decoded its address. nperr 29 o parity error (three-state). is used to report parity errors during all pci trans-
page 1-54 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pin name 128 type description actions except a special cycle. the minimum duration of nperr is one clock cycle. nserr 30 o system error (open drain). this pin goes low when address parity errors are detected. par 31 i/o even parity. parity is even parity across ad31-0 and nc/be3-0. par is stable and valid one clock after the address phase. for data phase par is stable and valid one clock after either nirdy is asserted on a write transaction or ntrdy is asserted on a read transaction. nc/be3 8 i bus command and byte enable. during the address phase of a transaction, nc/be3-0 defines the bus command. during data phase nc/be3-0 are used as byte enables.nc/be3 applies to byte ?3?. nc/be2 22 i bus command and byte enable. during the address phase of a transaction, nc/be3-0 defines the bus command. during data phase nc/be3-0 are used as byte enables. nc/be2 applies to byte ?2?. nc/be1 32 i bus command and byte enable. during the address phase of a transaction, nc/be3-0 defines the bus command. during data phase nc/be3-0 are used as byte enables. nc/be1 applies to byte ?1?. nc/be0 43 i bus command and byte enable. during the address phase of a transaction, nc/be3-0 defines the bus command. during data phase nc/be3-0 are used as byte enables. nc/be0 applies to byte ?0?. ninta 120 o pci active low interrupt output (open-drain). this signal goes low (active) when an interrupt condition occurs. ee-cs 115 o external ee-prom chip select (active high). after power on reset, NM9835 reads the ee-prom and loads the read-only configuration registers sequen- tially from the first 64 bytes in the ee-prom. ee-clk 116 o external ee-prom clock. ee-di 118 i external ee-prom data input. ee-do 117 o external ee-prom data output. ee-en 123 i enable/disable external eeprom (active high, internal pull-up). external eeprom can be disabled when this pin is tied to gnd or pulled low. when external eeprom is disabled, the default values for NM9835 will be loaded into pci configuration register. xtal1 62 i crystal oscillator input or external clock input pin (22.1184 mhz). this signal
page 1-55 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pin name 128 type description input is used in conjunction with xtal2 to form a feedback circuit for the internal timing. two external capacitors (10pf) connected from each side of the xtal1 and xtal2 to gnd is required to form a crystal oscillator circuit. xtal2 61 o crystal oscillator output. see xtal1 description. 12xclk 58 o external clock or crystal oscillator clock divide by 12 output (1.8432 mhz standard pc uart clock for 115.2k data rate). 6xclk 56 o external clock or crystal oscillator clock divide by 6 output (3.6864 mhz pc uart clock for 230.4k data rate). 3xclk 55 o external clock or crystal oscillator clock divide by 3 output (7.3728 mhz uart clock for 460.8k data rate). aclk 59 i uart-a clock input. aclk should be connected to external clock source or one of the 12xclk, 6xclk, 3xclk output pins of the NM9835. bclk 57 i uart-b clock input. bclk should be connected to external clock source or one of the 12xclk, 6xclk, 3xclk output pins of the NM9835. txa 105 o uart-a serial data output. nrtsa 107 o active low, uart-a request-to-send signal. it is set to high (in active) after a hardware reset or during internal loop-back mode. when low, this indicates that modem or data set is ready to establish a communication link. nrtsa has no effect on the transmitter or receiver. ndtra 106 o active low, uart-a data-terminal-ready signal. it is set to high (in active) after a hardware reset or during internal loop-back mode. when low, this output indicates to the modem or data set that the uart-a is ready to estab- lish a communication link. ndtra has no effect on the transmitter or re- ceiver. rxa 109 i uart-a, serial data input. nctsa 111 i active low, uart-a clear-to-send signal. when low this indicates that mo- dem or data set is ready to exchange data. nctsa has no effect on the transmitter. ndsra 110 i active low, uart-a data-set-ready signal. ncda 112 i active low, uart-a carrier-detect signal. when low this indicates that mo- dem or data set has detected the data carrier. ncda has no effect on the transmitter.
page 1-56 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pin name 128 type description nria 113 i active low, uart-a ring-detect signal. txb 76 o uart-b serial data output. nrtsb 74 o active low, uart-b request-to-send signal. it is set to high (in active) after a hardware reset or during internal loop-back mode. when low, this indicates that modem or data set is ready to establish a communication link. nrtsb has no effect on the transmitter or receiver. ndtrb 75 o active low, uart-b data-terminal-ready signal. it is set to high (in-active) after a hardware reset or during internal loop-back mode. when low, this output indicates to the modem or data set that the uart-b is ready to estab- lish a communication link. ndtrb has no effect on the transmitter or re- ceiver. rxb 73 i uart-b, serial data input. nctsb 71 i active low, uart-b clear-to-send signal. when low this indicates that mo- dem or data set is ready to exchange data. nctsb has no effect on the transmitter. ndsrb 72 i active low, uart-b data-set-ready signal. ncdb 70 i active low, uart-b carrier-detect signal. when low this indicates that mo- dem or data set has detected the data carrier. ncdb has no effect on the transmitter. nrib 69 i active low, uart-b ring-detect signal. slct 84 i peripheral/printer selected (internal pull-up). this pin is set to high by periph- eral/printer when it is selected. pe 87 i paper empty (internal pull-up). this pin is set to high by peripheral/printer when printer paper is empty. nbusy 85 i peripheral/printer busy (internal pull-up). this pin is set to high by peripheral/ printer, when printer or peripheral is not ready to accept data. nack 86 i peripheral/printer data acknowledge (internal pull-up). this pin is set to low by peripheral/printer to indicate a successful data transfer has taken place. during spp mode when interrupt is enabled, ninta pin follows the nack input pin state. nfault 83 i peripheral/printer data error (internal pull-up). this pin is set to low by periph- eral/printer during error condition.
page 1-57 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pin name 128 type description nstrobe 81 o peripheral/printer data strobe (open drain, active low). on the rising edge of the nstrobe, data is latched into printer port. nautofdx 80 o peripheral/printer auto feed (open-drain, active low). continuous autofed pa- per is selected when this pin is set to low. ninit 79 o initialize the peripheral/printer (open drain, active low). when set to low, pe- ripheral/printer starts it?s initialization routine. nslctin 78 o peripheral/printer select (open-drain, active low). selects the peripheral/printer when it is set to low. pd7-pd4 98-95 i/o peripheral/printer data ports. pd3-pd0 93-90 i/o peripheral/printer data ports. gnd 7,20,21, pwr power and signal ground. 33,44,45, 60,77,88, 94,99,108 119,125 vcc 1,10,19, pwr 5-v supply. 39,54,66, 82,89,104, 114
page 1-58 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 pci bus operation: the execution of pci bus transaction takes place in broadly five stages, address phase, transaction claim- ing, data phase(s), final data transfer and transaction completion. address phase: every pci transaction starts off with an address phase, one pci clock period in duration. during address phase the initiator (also known as current bus master) identi- fies the target device (via the address) and type of trans- action. (via the command).the initiator drives the 32 bit address on to 32 bit address/data bus and 4bit com- mand on to 4bit command / byte enable bus. the ini- tiator also asserts the nframe signal during the same clock cycle to indicate the presence of valid address and transaction type on those buses. the initiator sup- plies start address (and the target, NM9835, generates the subsequent sequential addresses for burst trans- fers) and command type for one pci clock cycle. the address/data bus becomes data bus and command/ byte enable bus becomes byte enable bus for the re- mainder of the clock cycles of that transaction. the tar- get (NM9835) latches the address and command type on the next rising edge of pci clock (and so do all the devices on that pci bus). the target (NM9835) decodes the address and determines whether it is being ad- dressed, and decodes the command to determine the type of transaction. claiming the transaction: when NM9835 determines that it is the target of a trans- action, it claims the transaction by asserting ndevsel. data phase(s): the data phase of a transaction is the period during which a data object is transferred between the initiator and the target (NM9835). the number of data bytes to be transferred during a data phase is determined by the number of command/byte enable signals that are asserted by the initiator during the data phase. each data phase is at least one pci clock period in duration. both initiator and target must indicate that they are ready to complete a data phase. if not, the data phase is ex- tended by a wait state of one clock period in duration. the initiator and the target indicate this by asserting nirdy and ntrdy respectively and the data transfer is completed at the rising edge of the next pci clock. transaction duration: the initiator, as stated earlier, gives only start address during address phase but does not tell the number of data transfers in a burst transfer transaction. however the initiator indicates the completion of data transfer of a transaction by asserting nirdy and de-asserting nframe during the last data transfer phase. the trans- action however, does not complete until the target has also asserted the ntrdy signal and the last data trans- fer takes place. at this point the ntrdy and ndevsel are de-asserted by the target. transaction completion: when all of nirdy, ntrdy, ndevsel, and nframe are in inactive state (high state), the bus is in idle state. the bus is ready to be claimed by another bus master. internal address select configuration i/o address function xx00-xx07 uart-a xx00-xx07 uart-b xx00-xx07 standard printer xx00 printer configuration register a xx01 printer configuration register b xx02 printer ecr register
page 1-59 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 NM9835 configuration space register map ad 31-23 ad 22-16 ad 15-8 ad 7-0 addr device id (9835) vendor id (9710) 00h status command 04h class code (070002) revision id (01) 08h bist header type latency timer cache size (08) 0ch i/o (e1)base address 10h i/o (e2)base address 14h i/o (e3)base address 18h i/o (e4)base address 1ch reserved 20h reserved 24h reserved 28h subsystem id subsystem vendor id 2ch reserved 30h reserved 34h reserved 38h max latency (00) min grant (00) interrupt pin (01) interrupt line 3ch
page 1-60 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 uart registers table ex a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ex 0 0 0 rhr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ex 0 0 0 thr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ex 0 0 1 ier 0 0 power sleep modem receive transmit receive down mode status line holding holding interrupt status register register interrupt ex 0 1 0 fcr rcvr rcvr 0 0 dma xmit rcvr fifo trigger trigger mode fifo fifo enable (msb) (lsb) select reset reset ex 0 1 0 iir 0/ 0/ 0 0 int int int int fifo fifo priority priority priority status enabled enabled bit-2 bit-1 bit-0 ex 0 1 1 lcr divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 ex 1 0 0 mcr 0 0 flow loop int (nop1) nrts ndtr control back enable (nop2) ex 1 0 1 lsr 0/ trans. trans. break framing parity overrun receive fifo empty holding interrupt error error error data error empty ready ex 1 1 0 msr ncd nri ndsr ncts delta delta delta delta ncd nri ndsr ncts ex 1 1 1 spr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ex 0 0 0 dll bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ex 0 0 1 dlm bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 dll and dlm are accessible only when lcr bit-7=1. e1: internal uart-a chip select e2: internal uart-b chip select
page 1-61 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 printer registers table ex a2 a1 a0 register d7 d6 d5 d4 d3 d2 d1 d0 e3 0 0 0 dpr pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 e3 0 0 1 dsr nbusy nack pe slct fault int ?0? epp state timeout e3 0 1 0 dcr ?0? ?0? dir inta nslctin init nautofd nstrobe e3 0 1 1 epp add-7 add-6 add-5 add-4 add-3 add-2 add-1 add-0 address e3 1 0 0 epp dat-7 dat-6 dat-5 dat-4 dat-3 dat-2 dat-1 dat-0 data e3 1 0 1 epp dat-15 dat-14 dat-13 dat-12 dat-11 dat-10 dat-9 dat-8 data e3 1 1 0 epp dat-23 dat-22 dat-21 dat-20 dat-19 dat-18 dat-17 dat-16 data e3 1 1 1 epp dat-31 dat-30 dat-29 dat-28 dat-27 dat-26 dat-25 dat-24 data e4 0 0 0 c-fifo cdat-7 cdat-6 cdat-5 cdat-4 cdat-3 cdat-2 cdat-1 cdat-0 e4 0 0 0 conf-a ?1? ?0? ?0? ?1? ?0? ?1? ?0? ?0? e4 0 0 1 conf-b ?0? int ?0? ?0? ?0? ?0? ?0? ?0? pin e4 0 1 0 ecr mode errintren service fifo fifo select enable ?0? int full empty e3: internal standard printer chip select e4: internal printer configuration register chip select
page 1-62 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 uart registers description transmitter holding register (thr) the transmitter section of the NM9835 consists of a transmitter holding register (thr) and a transmitter shift register (tsr). the thr is actually a 16-byte fifo. transmitter section control is a function of the NM9835 line control register. the NM9835 thr receives data off the internal data bus and when the shift register is idle, moves it into the tsr. the tsr serializes the data and outputs it at tx. in the 16c450 mode, if the thr is empty and the transmitter holding register empty (thre) interrupt is enabled (ier-1=1), an interrupt is generated. this interrupt is cleared when a character is loaded into the register. in the fifo mode, the interrupts are gen- erated based on the control setup in the fifo control register. receive holding register (rhr) the receiver section of the NM9835 consists of a re- ceiver shift register (rsr) and a receiver holding reg- ister (rhr). the rhr is actually a 16-byte fifo. tim- ing to receive holding register is supplied by the 16x- receiver clock. receiver section control is a function of the NM9835 line control register. the NM9835 rhr receives serial data from rx. the rsr then concatenates the data and moves it into the rhr fifo. in the 16c450 mode, when a character is placed in the receiver holding register and the received data available interrupt is enabled (ier-0=1), an inter- rupt is generated. this interrupt is cleared when the data is read out of the receiver holding register. in the fifo mode, the interrupts are generated based on the con- trol setup in the fifo control register. interrupt enable register (ier) the interrupt enables register enables each of the five types of interrupts and int pin response to an interrupt generation. the interrupt enable register can also be used to disable the interrupt system by setting bits 0-3 to logic 0. the contents of this register are described below. ier bit-0: 0 = disable the received data available interrupt. 1 = enables the received data available interrupt. ier bit-1: 0 = disable the transmitter holding register empty inter- rupt. 1 = enable the transmitter holding register empty inter- rupt. ier bit-2: 0 = disables the receiver line status interrupt. 1 = enables the receiver line status interrupt. ier bit-3: 0 = disables the modem status interrupt. 1 = enables the modem status interrupt. ier bit 4: 0 = standard 16c450/550 mode. sleep mode is dis- abled. 1 = enables sleep mode. the NM9835 is always awake when there is a byte in the transmitter, activity on the rx, or either delta cts, delta dsr, delta cd, delta ri is/are set to logic ?1?, or when the device is in the loop- back mode. ier bit 5: 0 = standard 16c450/550 mode. power down mode is disabled. 1 = enables the power down mode. power down mode functions similar to sleep mode, except oscillator sec- tion. ier bits 6-7: these bits are not used (always set to 0). interrupt identification register (iir) the NM9835 has an on chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors. iir bit-0: 0 = an interrupt is pending. used either in a hardware prioritized or polled interrupt system. 1 = no interrupt is pending.
page 1-63 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 iir bits 1-2: the NM9835 provides four prioritized levels of interrupts: priority 1 - receiver line status (highest priority) priority 2 - receiver data ready priority 2 - receiver character time-out priority 3 - transmitter holding register empty priority 4 - modem status (lowest priority) when an interrupt is generated, the interrupt identifica- tion register indicates that an interrupt is pending and encodes the type of interrupt in its three least signifi- cant bits (bits 0, 1, and 2). interrupt priority decode bit-3 bit-2 bit-1 bit-0 interrupt source 0110 receive data error 0100 receive data ready 1100 receive time-out 0010 transmit holding empty 0000 modem status change the bits are used to identify the highest priority inter- rupt pending. iir bit-0 will clear to ?1? when no interrupt is pending. to clear the interrupts following reads from registers are required. receive data error: reading lsr register will clear this interrupt. user should save lsr value after reading the register to maintain the error condition. receive data ready: reading rhr register till fifo becomes empty. receive timeout: reading entire characters from rhr. transmit holding empty: writing a character into thr register or reading iir reg- ister (if source of interrupt). modem status change: reading msr register will clear this interrupt. iir bit-3: 0 = in the 16c450 mode. in fifo mode, this bit is set along with bit-2 to indicate that a time-out interrupt is pending. iir bit 4: this bit is not used (always reset at 0). iir bit 5: 0 = 16c450/550 mode, 16 byte fifo mode. 1 = enhance fifo mode. 64 byte fifo mode enabled. iir bits 6-7: 0 = in the 16c450 mode. 1 = when fcr-0 is equal to 1. fifo control register (fcr) the fifo control register (fcr) is a write only register. the (fcr) enables and clears the fifo sets receive fifo trigger level, and selects the type of dma signal- ing. fcr bit-0: 0 = 16c450 mode, disables the transmitter and receiver fifo. 1 = enables the transmitter and receiver fifo. this bit must be set to 1 when other (fcr) bits are written to or they are not programmed. changing this bit clears the fifo. fcr bit-1: 0 = normal operation 1 = clears all bytes in the receiver fifo and resets its counter logic to 0. the shift register is not cleared. the one that is written to this bit position is self-clearing. fcr bit-2: 0 = normal operation 1 = clears all bytes in the transmit fifo and resets its counter logic to 0. the shift register is not cleared. the one that is written to this bit position is self-clearing. fcr bit-3: 0 = mode [0]: supports single transfer dma (16c450 mode) in which a transfer is made between cpu bus cycle.
page 1-64 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 1 = mode [1]: supports multi transfer dma in which multiple transfers are made continuously until the receiver fifo has been emptied. fcr bit 5-4: this bit is not used. fcr bits 6-7: these bits are used to set the trigger level for receive fifo interrupt. receive trigger levels (bytes) bit-7 bit-6 rx fifo trigger level 00 1 01 4 10 8 11 14 line control register (lcr) the system programmer controls the format of the asyn- chronous data communication exchange through the line control register. in addition, the programmer is able to retrieve, inspect, and modify the contents of the line control register; this eliminates the need for separate storage of the line characteristics in system memory. lcr bits 0-1: these two bits specify the number of bits in each trans- mitted or received serial character. word length bit-1 bit-0 word length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits lcr bit-2: this bit specifies, 1, 1-1/2, or 2 stop bits in each trans- mitted character. when bit-2 is reset to 0, one stop bit is generated in the data. when bit-2 is set to 1, the num- ber of stop bits generated is dependent on the word length selected with bits 0 and 1. the receiver clocks only the first stop bit regardless of the number of stop bits selected. the number of stop bits generated in re- lation to word length and bit-2. stop bits bit-2 word length stop bit(s) 0x 1 1 5 bits 1-1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 lcr bit-3: 0 = parity is disabled. no parity is generated or checked. 1 = parity bit is generated in transmitted data between the last data word bit and the first stop bit. in received data, parity is checked. lcr bit-4: 0 = odd parity select bit. when parity is enabled by bit- 3, a 1 in bit-4 produces odd parity (an odd number of 1?s in the data and parity bits. 1 = even parity select bit. when parity is enabled by bit- 3, a 1 in bit-4 produces even parity (an even number of 1?s in the data and parity bits). lcr bit-5: 0 = stick parity is disabled. 1 = stick parity bit. when bits 3-5 are set to 1 the parity bit is transmitted and checked as a 0. when bits-3 and 5 are 1?s and bit-4 is a 0, the parity bit is transmitted and checked as 1.
page 1-65 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 parity selection bit-5 bit-4 bit-3 parity type x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ?1? 1 1 1 forced parity ?0? lcr bit-6: 0 = normal operation. break condition is disabled and has no effect on the transmitter logic. 1 = force a break condition. a condition where tx is forced to the space (low) state. lcr bit-7: 0 = normal operation. 1 = divisor latch enable. must be set to 1 to access the divisor latches of the baud generator during a read or write. bit-7 must be reset to 0 during a read or write to the receiver holding, the transmitter holding register, or the interrupt enable register. modem control register (mcr) the modem control register is an 8-bit register that con- trols an interface with a modem, data set, or peripheral device that is emulating a modem. mcr bit-0: 0 = sets the ndtr output pin to high. 1 = sets the ndtr output pin to low. mcr bit-1: 0 = sets the nrts output pin to high. 1 = sets the nrts output pin to low. mcr bit-2: 0 = sets the nop1 to high during loop-back mode. 1 = sets the nop1 to low during loop-back mode. mcr bit-3: 0 = disables uart interrupt. sets the nop2 to high during loop-back mode. 1 = enables uart interrupt. this bit is gated with ier bits 0-3. sets the nop2 to low during loop-back mode. mcr bit-4: 0 = normal operation. 1 = internal loop back mode. provides a local loop-back feature for diagnostic testing of the NM9835. when loop is set to 1, the following occurs: the transmitter tx pin is set to high. the receiver rx pin is disconnected. the output of the transmitter shift register is looped back into the receiver shift register input. the four modem inputs (ncts, ndsr ncd and nri) pins are disconnected. the four modem outputs (ndtr, nrts, nop1, and nop2) pins are internally connected to the four modem inputs. the four modem outputs are forced to the high levels. in the diagnostic mode, data that is transmitted is im- mediately received. this allows the processor to verify transmit and receive data paths to the NM9835. the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational, but the modem control interrupt sources are now the lower four bits of the modem control register instead of the four modem control inputs. all interrupts are still con- trolled by the interrupt enable register. mcr bit-5: 0 = 16c450/550 mode. hardware flow control is dis- abled. 1 = enable hardware flow control (nrts/ncts). mcr bit-5 mcr bit-1 flow control 1 1 auto rts/cts 1 0 auto cts only 0 x disabled nrts becomes active (low) when the receiver is empty or the threshold has not been reached. when receiver fifo level reaches a trigger level of 1, 4, 8, and 14, nrts is de-asserted (high). nrts is automatically re- asserted once the receiver fifo is empty by reading receive holding register. the transmitter circuitry checks ncts before sending the next data byte. when ncts is active (low), the trans- mitter sends the next byte. to stop the transmitter from
page 1-66 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 sending the next byte, ncts must be released before the middle of the last stop bit that is currently being sent. mcr bits 6-7: these bits are not used. line status register (lsr) the line status register provides information to the cpu concerning the status of data transfers. the line status register is intended for read operations only; writing to this register is not recommended. bits 1-4 are the error conditions that produce a receiver line status interrupt. lsr bit-0: 0 = no data in receive holding or fifo. 1 = data ready indicator for the receiver. this bit is set to 1 whenever a complete incoming character has been received and transferred into the receiver holding reg- ister or the fifo. it is reset to 0 by reading all of the data in the receiver holding register or the fifo. lsr bit-1: 0 = normal operation. no overrun error. 1 = it indicates that before the character in the receiver holding register was read, it was over written by the next character transferred into the register. oe is reset every time the cpu reads the contents of the line sta- tus register. if the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error occurs only after the fifo is full and the next character has been completely received in the shift register. an over- run error is indicated to the cpu as soon as it happens. the character in the shift register is overwritten, but it is not transferred to the fifo. lsr bit-2: 0 = normal operation (no parity error). 1 = it indicates that the parity of the received data char- acter does not match the parity selected in the line con- trol register. pe is reset every time the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo to which it applies. this error is revealed to the cpu when its associated character is at the top of the fifo. lsr bit-3: 0 = normal operation (no framing error). 1 = it indicates that the received character did not have a valid stop bit. fe is reset every time the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo to which it applies. this error is revealed to the cpu when its associated character is at the top of the fifo. the NM9835 tries to re-synchronize after a framing error. to accomplish this, it is assumed that the framing error is due to the next start bit. lsr bit-4: 0 = normal operation. 1 = it indicates that the received data input was held in the logic low state for longer than a full word transmis- sion time. a full word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. bi is reset every time the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo to which it applies. this error is revealed to the cpu when its associated character is at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. lsr bit-5: 0 = at least one byte is written to the transmit fifo or transmit holding register. 1 = transmitter holding register is empty, indicating that the NM9835 is ready to accept a new character. if the thre interrupt is enabled when thre is set to 1, an interrupt is generated. thre is set to 1 when the con- tents of the transmitter holding register are transferred to the transmitter shift register. lsr bit-6: 0 = when either the transmitter holding register or the transmitter shift register contains a data character. 1 = transmitter holding register and the transmitter shift register are both empty. lsr bit-7: 0 = in the 16c450, this bit is always reset to 0. 1 = in the fifo mode, at least one parity, framing, or break error in the fifo. it is cleared when the micro- processor reads the lsr and there are no subsequent errors in the fifo.
page 1-67 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 modem status register (msr) the modem status register is an 8-bit register that pro- vides information about the current state of the control lines from the modem, data set, or peripheral device to the cpu. additionally, four bits of this register provide change information, when input from the modem changes state, the appropriate bit is set to 1. all four bits are reset to 0 when the cpu reads the modem sta- tus register. msr bit-0: 0 = no change to ncts input. 1 = indicates that the ncts input has changed state since the last time it was read by the cpu. when inter- rupt is enabled, a modem status interrupt is generated. msr bit-1: 0 = no change to ndsr input. 1 = indicates that the ndsr input has changed state since the last time it was read by the cpu. when inter- rupt is enabled, a modem status interrupt is generated. msr bit-2: 0 = no change to nri input. 1 = indicates that the nri input has changed from a low to a high level. when nri is set to 1 and the modem status interrupt is enabled, a modem status interrupt is generated. msr bit-3: 0 = no change to ncd input. 1 = indicates that the ncd input has changed state since the last time it was read by the cpu. when interrupt is enabled, a modem status interrupt is generated. msr bit-4: complement of the clear to send (ncts) input. when the NM9835 is in the diagnostic test mode, this bit is equal to nrts. msr bit-5: complement of the data set ready (ndsr) input. when the NM9835 is in the diagnostic test mode, this bit is equal to ndtr. msr bit-6: complement of the ring indicator (nri) input. when the NM9835 is in the diagnostic test mode, this bit is equal to nop1. msr bit-7: complement of the data carrier detects (ncd) input. when the NM9835 is in the diagnostic test mode, this bit is equal to nop2. scratch pad register (spr) the scratch pad register is an 8-bit register that is in- tended for programmer use as a scratch pad in the sense that it temporarily holds the programmer data without affecting any other NM9835 operation. programmable baud-rate generator the NM9835 contains a programmable baud genera- tor that takes a clock input of 1.8432 mhz and divides it by a divisor in the range between 1 and (2 16 -1) the out- put frequency of the baud generator is 16 times the baud rate. two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization of the NM9835 in order to ensure desired operation of the baud genera- tor. when either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. baud rate generator programming table for 1.8432 mhz clock (12xclk). baud out dlm dll (hex) (hex) 115.2k 00 01 57.6k 00 02 38.4k 00 03 19.2 00 06 9600 00 0c 2400 00 30 1200 00 60 600 00 c0 300 01 80 150 03 00 50 09 00 fifo interrupt mode operation when the receiver fifo and receiver interrupts are enabled (fcr-0=1, ier-0=1, ier-2=1), a receiver in- terrupt occurs as follows:
page 1-68 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 the received data available interrupt issued to the mi- croprocessor when the fifo has reached its pro- grammed trigger level. it is cleared when the fifo drops below its programmed trigger level. the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt, it is cleared when the fifo drops below the trigger level. the receiver line status interrupt has higher priority than the received data available interrupt. the data ready bit (lsr-0) is set when a character is transferred from the shift register to the receiver fifo. it is reset when the fifo is empty. when the receiver fifo and receiver interrupts are enabled, fifo time-out interrupt occurs when the fol- lowing conditions exist: at least one character is in the fifo. the most recent serial character was received more than four continu- ous character times ago (if two stop bits are pro- grammed, the second one is included in this time de- lay). the most recent microprocessor read of the fifo occurred more than five continuous character times ago. when a time-out interrupt has occurred, it is cleared and the timer is reset when the microprocessor reads one character from the receiver fifo. when a time-out interrupt has not occurred, the time- out timer is reset after a new character is received or after the microprocessor reads the receiver fifo. when the transmitter fifo and thre interrupt are en- abled (fcr-0=1, ier-1=1), transmit interrupts occur as follows: the occurrence of transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter fifo at the same time since the last time the transmitter fifo was empty. it is cleared as soon as the transmitter holding register is written to (1 to 64 characters may be written to transmit fifo while servicing this interrupt) or the iir is read. the first trans- mitter interrupt after changing fcr is immediate if it is enabled. the transmitter empty indicator is delayed one charac- ter time when there has not been at least two bytes in the transmitter fifo at the same time since the last time that temt=1. temt is set after the stop bit has been completely shifted out. the transmitter fifo empty indicator works the normal way in this mode and is not delayed. character time- out and receiver fifo trigger-level interrupts have the same priority as the current received data available interrupt. parallel port register description data register data register is cleared at initialization by reset. dur- ing a write operation, the data register latches the con- tents of the data bus with the rising edge of the niow input. the contents of this register are buffered and output onto the pd7-pd0 ports. during a read opera- tion pd7-pd0 ports are buffered and output to the host cpu on the falling edge of the nior input. device status register the contents of this register are latched for the duration of an nior cycle. the bits of the status port are de- fined as follows. dsr bit-0: 0 = normal. 1 = 10 s timeout (epp mode only). cleared by writing 1 into dsr register or consecutive reads (after the first read) always returns ?0?. dsr bit-1: not used, set to ?0?. dsr bit-2: 0 = nack input pin is at low state (int follows the nack pin), when spp mode is selected. normal (no interrupt) when ps/2 mode is selected. 1 = normal (no interrupt). in standard mode operation, int is active (interrupt is generated on the rising edge of the nack). it is cleared when dsr is read. dsr bit-3: 0 = printer reports error condition. 1 = normal operation. dsr bit-4: 0 = printer is off line.
page 1-69 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 1 = printer is on line. dsr bit-5: 0 = normal operation 1 = paper end/empty is detected dsr bit-6: 0 = state of the nack pin (ack = low). 1 = state of the nack pin (ack = high). dsr bit-7: 0 = nbusy pin is high, printer is not ready to take data. 1 = nbusy pin is low, printer is read to take data. device control register dcr bit-0 0 = sets the nstrobe pin to high. 1 = sets the nstrobe pin to low. pd7-pd0 data are latched into printer dcr bit-1: 0 = sets the nautofd pin to high. printer generates auto line feed after each line is printed. 1 = sets the nautofd pin to low. no auto feed func- tion. dcr bit-2: 0 = sets the init pin to high. 1 = sets the init pin to low. peripheral/printer starts it?s initialization routine. dcr bit-3: 0 = sets the nslctin pin to high. selects the printer. 1 = sets the nslctin pin to low. printer is not selected. dcr bit-4: 0 = disables printer interrupt function. nack pin has no effect on the int pin. 1 = enables printer interrupt function. the int follows the nack input pin during standard mode, latches high on the rising edge of the nack, when ps/2 mode is selected. dcr bit-5: 0 = pd7-pd0 pins are out put mode. 1 = pd7-pd0 pins are input mode. dcr bits 7-6: not used, set to ?0?. config: -a register configuration a register (read only). reading this reg- ister returns 10010100. writing to this register has no effect and the data is ignored. config: -b register configuration b register. this register allows software to control the selecting of interrupts. a read-write imple- mentation implies a ?software-configurable? device. reading this register, returns the configured interrupt, and interrupt pin state. if a value is not set to 000 (the jumper-default) then it is assumed that the value in the register is correct and software will use the default in- terrupt. config-b bit-7: not used, set to ?0?. config-b bit-6: 0 = configured printer interrupt pin is low. 1 = configured printer interrupt pin is high. config-b bit 7-0: interrupt pin select register. extended control register (ecr) this register controls the mode selection and dma op- eration. bit-7 bit-6 bit-5 operating mode 0 0 0 spp 0 0 1 ps/2 0 1 0 ppf (fifo mode) 0 1 1 ecp 1 0 0 epp 1 0 1 not used 1 1 0 fifo test 1 1 1 config a/b enable
page 1-70 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 mode changes. after hardware reset, ps/2 mode is selected as default mode. it is required to select mode 000 or 001 between any other mode configuration. mode ?000? spp/centronics/compatible mode forward direction only. the direction bit is forced to ?0? and pd7-pd0 are set to output direction. the NM9835 is under software controlled. this mode defines the pro- tocol used by most pc?s to transfer data to a printer. it is commonly called the ?centronics? mode and is the method utilized with the standard parallel port. data is placed on the pd7-pd0 port?s, the printer status is checked via dsr register. if no error condition is flagged and printer is not busy, software toggles the nstrobe pin to latch the pd7-pd0 data into printer. this operat- ing cycle continues when printer/peripheral issues data acknowledge signal (pules the ack and nbusy pin). nibble mode the nibble mode is the most common way to get re- verse channel data from a printer or peripheral. this mode is usually combined with the centronics mode or a proprietary forward channel mode to create a bi-di- rectional channel. in this mode printer status bits are used as nibble bits. bits order for nibble mode. pins data bits nbusy bit-7 pe bit-6 slct bit-5 nfault bit-4 nbusy bit-3 pe bit-2 slct bit-1 nfault bit-0 mode ?001? ps/2, byte mode the byte mode protocol is used to transfer bi-directional data via pd7-pd0 ports without fifo utilization. the direction of the port is controlled with dir bit in dcr register. ps/2-byte use spp protocol for data transfer. dcr bit-5: 0 = pd7-pd0 pins are out put mode. 1 = pd7-pd0 pins are input mode. mode ?010? fifo output mode in this mode, bytes written to the fifo are transmitted automatically using the spp/centronics standard pro- tocol. mode ?011? extended capability port ?ecp? mode the ecp provides an advanced mode for communica- tion with printer or peripherals. like epp protocol, ecp provides 16 byte fifo for a high performance bi-direc- tional communication path between the host adapter and the peripheral. the ecp protocol provides the fol- lowing cycle types in both the forward and reverse di- rection. ? data cycle ? command cycles ? run-length counts (rle) ? channel address the rle feature enables real time data compression that can achieve compression ratios up to 64:1. this is particularly useful for printers and peripherals that are transferring large raster images that have large strings of identical data. in order for the rle mode to be en- abled, both the host and peripheral must support it. channel addressing is intended to address multiple logi- cal devices within single physical device like modem/ fax/printer in one physical package. mode ?100? enhanced parallel port ?epp? mode in epp mode, nslctin (address strobe) and nautofd (data strobe) are automatically generated while nstrobe indicates a write or read cycle. additional i/ o addresses are defined for data and address access and when these locations are used, handshaking is performed automatically by NM9835.
page 1-71 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 mode ?110? fifo test mode in this mode, the fifo can be written and read in any direction, but no data will be transmitted on the pd7- pd0 ports. whoever, data in the fifo may be displayed on the pd7-pd0 ports. ecr bit-4: error interrupt enable. 0 = enable nfault interrupt. nfault pin is used as source of interrupt. 1 = disable nfault interrupt (nack is used as source of interrupt). ecr bit-3: 0 = normal operating mode. ecr bit-2: 1 = disables service interrupt. 0 = enables one of the following 3 cases of interrupts. one of the 3 service interrupts has occurred, service interrupt bit will be set to a ?1? by hardware. writing this bit to a ?1? will not cause an interrupt. port direction (dcr bit-5 = 0), this bit will be set to ?1? whenever there are write interrupt threshold (4 charac- ters) or more bytes free in the fifo. the NM9835 gen- erates interrupt when this condition is occurred and service interrupt is cleared to ?0?. port direction (dcr bit-5 = 1), this bit will be set to ?1? whenever there are read interrupt threshold (12 char- acters) or more bytes to be read from the fifo. the NM9835 generates interrupt when this condition is oc- curred and service interrupt is cleared to ?0?. ecr bit-1: 0 = one or more empty location in fifo is available. 1 = fifo full. ecr bit-0: 0 = one or more data in fifo. 1 = fifo empty. master rest conditions register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rhr 00000000 thr xxxxxxxx ier 00000000 fcr 00000000 iir 00000001 lcr 00000000 mcr 00000000 lsr 01100000 msr xxxx0 0 0 0 spr 00000000 dpr xxxxxxxx dsr 01111000 dcr 00000000 epp 00000000 c-fifo 00000000 conf-a 10010100 conf-b 0 x 000000 ecr 00000001
page 1-72 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 absolute maximum ratings supply range 7 volts voltage at any pin gnd ? 0.3 to vcc +0.3 operating temperature -45 c to 90 c storage temperature -65 c to 150 c package dissipation 500 mw esd 2000 volts latch up 220 ma dc electrical specification t = 0 c to 70 c (-40 c to +85 c for industrial ?e? grade parts), vcc = 5v 10% unless otherwise specified. symbol parameter 5-v unit condition min max vil input low voltage -0.3 0.8 v vih input high voltage 2.0 v vt- schmitt trigger negative 1.10 v going threshold voltage vt+ schmitt trigger positive 1.87 v going threshold voltage vol output low voltage 0.4 v iol=4 ma voh output high voltage 3.5 c ioh=4 ma iil input low current 1 a iih input high current 1 a ioz three state leakage current 10 a cin input capacitance 3 5 pf cout output capacitance 3 5 pf icc operating current 60 ma no load revision notes date 1.0 - 7/00
page 1-73 netmos technology NM9835 pci + dual uart and 1284 printer port rev. 1.0 notes:

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