1 file number 4598.2 hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds 25a, 1200v, npt series n-channel igbt with anti-parallel hyperfast diode the hgtg5n120cnd, hgtp5n120cnd and hgt1s5n120cnds are n on- p unch t hrough (npt) igbt designs. they are new members of the mos gated high voltage switching igbt family. igbts combine the best features of mosfets and bipolar transistors. this device has the high input impedance of a mosfet and the low on-state conduction loss of a bipolar transistor. the igbt used is developmental type ta49309. the diode used in anti-parallel is developmental type ta49058. the igbt is ideal for many high voltage switching applications operating at moderate frequencies where low conduction losses are essential, such as ac and dc motor controls, power supplies and drivers for solenoids, relays and contactors. formerly developmental type ta49307. symbol features 25a, 1200v, t c = 25 o c 1200v switching soa capability typical fall time. . . . . . . . . . . . . . . . 350ns at t j = 150 o c short circuit rating low conduction loss temperature compensating saber model thermal impedance spice model www.intersil.com related literature - tb334 ?uidelines for soldering surface mount components to pc boards packaging jedec to-220ab alternate version jedec to-263ab jedec style to-247 ordering information part number package brand hgtg5n120cnd to-247 5n120cnd hgtp5n120cnd to-220ab 5n120cnd hgt1s5n120cnds to-263ab 5n120cnd note: when ordering, use the entire part number. add the suf? 9a to obtain the to-263ab variant in tape and reel, i.e., HGT1S5N120CNDS9A. c e g g c e collector (flange) g collector e (flange) collector (flange) c e g intersil corporation igbt product is covered by one or more of the following u.s. patents 4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,587,713 4,598,461 4,605,948 4,620,211 4,631,564 4,639,754 4,639,762 4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690 4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606 4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951 4,969,027 data sheet january 2000 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 2000 saber is a trademark of analogy, inc.
2 absolute maximum ratings t c = 25 o c, unless otherwise speci?d hgtg5n120cnd hgtp5n120cnd hgt1s5n120cnds units collector to emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bv ces 1200 v collector current continuous at t c = 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i c25 25 a at t c = 110 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i c110 12 a collector current pulsed (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i cm 40 a gate to emitter voltage continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ges 20 v gate to emitter voltage pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gem 30 v switching safe operating area at t j = 150 o c, figure 2 . . . . . . . . . . . . . . . . . . . . . . . . ssoa 30a at 1200v power dissipation total at t c = 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 167 w power dissipation derating t c > 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33 w/ o c operating and storage junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum lead temperature for soldering leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l 300 o c package body for 10s, see tech brief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 260 o c short circuit withstand time (note 2) at v ge = 15v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t sc 8 s short circuit withstand time (note 2) at v ge = 12v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t sc 15 s caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. pulse width limited by maximum junction temperature. 2. v ce(pk) = 840v, t j = 125 o c, r g = 25 ?. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units collector to emitter breakdown voltage bv ces i c = 250 a, v ge = 0v 1200 - - v collector to emitter leakage current i ces v ce = bv ces t c = 25 o c - - 250 a t c = 125 o c - 100 - a t c = 150 o c--2ma collector to emitter saturation voltage v ce(sat) i c = 5.5a, v ge = 15v t c = 25 o c - 2.1 2.4 v t c = 150 o c - 2.9 3.5 v gate to emitter threshold voltage v ge(th) i c = 45 a, v ce = v ge 6.0 7.0 - v gate to emitter leakage current i ges v ge = 20v - - 250 na switching soa ssoa t j = 150 o c, r g = 25 ?, v ge = 15v, l = 200 h, v ce(pk) = 1200v 25 - - a gate to emitter plateau voltage v gep i c = 5.5a, v ce = 0.5 bv ces - 10.6 - v on-state gate charge q g(on) i c = 5.5a, v ce = 0.5 bv ces v ge = 15v - 45 55 nc v ge = 20v - 60 75 nc current turn-on delay time t d(on)i igbt and diode at t j = 25 o c i ce = 5.5a v ce = 0.8 bv ces v ge = 15v r g = 25 ? l = 5mh test circuit (figure 20) -2230ns current rise time t ri -1216ns current turn-off delay time t d(off)i - 180 250 ns current fall time t fi - 280 350 ns turn-on energy e on - 400 500 j turn-off energy (note 3) e off - 640 700 j hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds
3 current turn-on delay time t d(on)i igbt and diode at t j = 150 o c i ce = 5.5a v ce = 0.8 bv ces v ge = 15v r g = 25 ? l = 5mh test circuit (figure 20) -2025ns current rise time t ri -1216ns current turn-off delay time t d(off)i - 225 300 ns current fall time t fi - 350 400 ns turn-on energy e on - 1 1.2 mj turn-off energy (note 3) e off - 1 1.1 mj diode forward voltage v ec i ec = 5.5a - 2.4 3.3 v diode reverse recovery time t rr i ec = 5.5a, di ec /dt = 200a/ s - 48 60 ns i ec = 1a, di ec /dt = 200a/ s - 30 40 ns thermal resistance junction to case r jc igbt - - 0.75 o c/w diode - - 1.9 o c/w note: 3. turn-off energy loss (e off ) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (i ce = 0a). all devices were tested per jedec standard no. 24-1 method for measurement of power device turn-off switching loss. this test method produces the true total turn-off energy loss. electrical speci?ations t c = 25 o c, unless otherwise speci?d (continued) parameter symbol test conditions min typ max units typical performance curves unless otherwise speci?d figure 1. dc collector current vs case temperature figure 2. minimum switching safe operating area t c , case temperature ( o c) i ce , dc collector current (a) 50 5 0 20 10 15 v ge = 15v 25 75 100 125 150 25 v ce , collector to emitter voltage (v) 1400 15 0 i ce , collector to emitter current (a) 5 10 600 800 400 200 1000 1200 0 20 25 t j = 150 o c, r g = 25 ? , v ge = 15v, l = 200 h 30 35 hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds
4 figure 3. operating frequency vs collector to emitter current figure 4. short circuit withstand time figure 5. collector to emitter on-state voltage figure 6. collector to emitter on-state voltage figure 7. turn-on energy loss vs collector to emitter current figure 8. turn-off energy loss vs collector to emitter current typical performance curves unless otherwise speci?d (continued) f max , operating frequency (khz) 1 i ce , collector to emitter current (a) 10 50 200 2 f max1 = 0.05 / (t d(off)i + t d(on)i ) r jc = 0.75 o c/w, see notes p c = conduction dissipation (duty factor = 50%) f max2 = (p d - p c ) / (e on + e off ) t j = 150 o c, r g = 25 ? , l = 5mh, v ce = 960v t c v ge 110 o c 12v 15v 15v 75 o c 110 o c 75 o c 12v t c = 75 o c, v ge = 5v 35 10 ideal diode 100 20 v ge , gate to emitter voltage (v) i sc , peak short circuit current (a) t sc , short circuit withstand time ( s) 10 11 12 13 14 15 10 15 20 25 30 30 40 50 60 t sc 35 70 20 v ce = 840v, r g = 25 ? , t j = 125 o c i sc 01 4 v ce , collector to emitter voltage (v) i ce , collector to emitter current (a) 0 5 10 15 6810 30 25 20 35 23 5 7 9 250 s pulse test duty cycle < 0.5%, v ge = 12v t c = -55 o c t c = 25 o c t c = 150 o c i ce , collector to emitter current (a) v ce , collector to emitter voltage (v) 20 30 60 024 0 6810 10 40 50 70 80 duty cycle < 0.5%, v ge = 15v 250 s pulse test t c = -55 o c t c = 150 o c t c = 25 o c e on , turn-on energy loss (mj) 2500 1500 i ce , collector to emitter current (a) 2000 1000 500 5 37 6 4 2 3000 89 10 0 t j = 25 o c, v ge = 15v, v ge = 12v t j = 150 o c, v ge = 15v, v ge = 12v r g = 25 ? , l = 5mh, v ce = 960v i ce , collector to emitter current (a) e off , turn-off energy loss ( j) 0 4 2 135 250 750 500 1000 1250 1500 9 68 710 r g = 25 ? , l = 5mh, v ce = 960v t j = 150 o c, v ge = 12v or 15v t j = 25 o c, v ge = 12v or 15v 1750 hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds
5 figure 9. turn-on delay time vs collector to emitter current figure 10. turn-on rise time vs collector to emitter current figure 11. turn-off delay time vs collector to emitter current figure 12. fall time vs collector to emitter current figure 13. transfer characteristic figure 14. gate charge waveforms typical performance curves unless otherwise speci?d (continued) i ce , collector to emitter current (a) t di , turn-on delay time (ns) 3 246 15 20 25 30 35 5 40 79 810 t j = 25 o c, t j = 150 o c, v ge = 12v t j = 25 o c, t j = 150 o c, v ge = 15v r g = 25 ? , l = 5mh, v ce = 960v i ce , collector to emitter current (a) t ri , rise time (ns) 3 0 10 30 25 15 7 2 20 6 5 410 9 8 35 40 t j = 25 o c, t j = 150 o c, v ge = 12v t j = 25 o c, t j = 150 o c, v ge = 15v r g = 25 ? , l = 5mh, v ce = 960v 23 6 1 300 5 4 100 200 i ce , collector to emitter current (a) t d(off)i , turn-off delay time (ns) 9 8 7 600 400 500 10 0 t j = 150 o c, v ge = 12v, v ge = 15v t j = 25 o c, v ge = 12v, v ge = 15v r g = 25 ? , l = 5mh, v ce = 960v i ce , collector to emitter current (a) t fi , fall time (ns) 23 5 1 300 400 4 100 200 500 600 8 7 610 9 700 800 t j = 150 o c, v ge = 12v and 15v t j = 25 o c, v ge = 12v and 15v 900 r g = 25 ? , l = 5mh, v ce = 960v i ce , collector to emitter current (a) 0 10 12 6789 11 v ge , gate to emitter voltage (v) 10 20 30 13 14 40 250 s pulse test duty cycle < 0.5%, v ce = 20v 50 60 70 80 15 t c = -55 o c t c = 25 o c t c = 150 o c 16 90 100 v ge , gate to emitter voltage (v) q g , gate charge (nc) 8 4 20 2 6 0 050 10 30 60 40 14 10 12 16 i g(ref) = 1ma, r l = 120 ? , t c = 25 o c v ce = 800v v ce = 1200v v ce = 400v hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds
6 figure 15. capacitance vs collector to emitter voltage figure 16. collector to emitter on-state voltage figure 17. normalized transient thermal response, junction to case figure 18. diode forward current vs forward voltage drop figure 19. recovery times vs forward current typical performance curves unless otherwise speci?d (continued) c res v ce , collector to emitter voltage (v) 0 5 10 15 20 25 0 0.5 c, capacitance (nf) c ies 1.0 1.5 2.0 c oes frequency = 1mhz i ce , collector to emitter current (a) 0 1 2 3 2.5 0 0.5 1.0 2.0 v ce , collector to emitter voltage (v) 1.5 4 5 6 3.0 250 s pulse test duty cycle < 0.5%, t c = 110 o c v ge = 10v 7 3.5 v ge = 15v t 1 , rectangular pulse duration (s) z jc , normalized thermal response 10 -2 10 -1 10 0 10 -5 10 -3 10 -2 10 -1 10 0 10 -4 0.20 t 1 t 2 p d duty factor, d = t 1 / t 2 peak t j = (p d x z jc x r jc ) + t c single pulse 0.10 0.50 0.05 0.02 0.01 v ec , forward voltage (v) 01234 6 1 i ec , forward current (a) 10 100 578 25 o c 150 o c -55 o c i ec , forward current (a) 12345 0 10 t r , recovery times (ns) 20 30 40 7 6 50 60 t rr t a t b t c = 25 o c, di ec /dt = 200a/ s hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds
7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com handling precautions for igbts insulated gate bipolar transistors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. when handling these devices, care should be exercised to assure that the static charge built in the handler s body capacitance is not discharged through the device. with proper handling and application procedures, however, igbts are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. igbts can be handled safely if the following basic precautions are taken: 1. prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as ?ccosorbd ld26?or equivalent. 2. when devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. tips of soldering irons should be grounded. 4. devices should never be inserted into or removed from circuits with power on. 5. gate voltage rating - never exceed the gate-voltage rating of v gem . exceeding the rated v ge can result in permanent damage to the oxide layer in the gate region. 6. gate termination - the gates of these devices are essentially capacitors. circuits that leave the gate open- circuited or floating should be avoided. these conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. gate protection - these devices do not have an internal monolithic zener diode from gate to emitter. if gate protection is required an external zener is recommended. operating frequency information operating frequency information for a typical device (figure 3) is presented as a guide for estimating device performance for a specific application. other typical frequency vs collector current (i ce ) plots are possible using the information shown for a typical unit in figures 5, 6, 7, 8, 9 and 11. the operating frequency plot (figure 3) of a typical device shows f max1 or f max2 ; whichever is smaller at each point. the information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. f max1 is defined by f max1 = 0.05/(t d(off)i + t d(on)i ). deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. other definitions are possible. t d(off)i and t d(on)i are defined in figure 21. device turn-off delay can establish an additional frequency limiting condition for an application other than t jm . t d(off)i is important when controlling output ripple under a lightly loaded condition. f max2 is defined by f max2 = (p d - p c )/(e off + e on ). the allowable dissipation (p d ) is defined by p d = (t jm - t c )/r jc . the sum of device switching and conduction losses must not exceed p d . a 50% duty factor was used (figure 3) and the conduction losses (p c ) are approximated by p c =(v ce xi ce )/2. e on and e off are defined in the switching waveforms shown in figure 21. e on is the integral of the instantaneous power loss (i ce xv ce ) during turn-on and e off is the integral of the instantaneous power loss (i ce x v ce ) during turn-off. all tail losses are included in the calculation for e off ; i.e., the collector current equals zero (i ce = 0). test circuit and waveforms figure 20. inductive switching test circuit figure 21. switching test waveforms v dd = 960v r g = 25 ? l = 5mh + - hgtp5n120cnd t fi t d(off)i t ri t d(on)i 10% 90% 10% 90% v ce i ce v ge e off e on hgtg5n120cnd, hgtp5n120cnd, hgt1s5n120cnds eccosorbd is a trademark of emerson and cumming, inc.
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