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1997 data sheet mos integrated circuit m pd780306y,780308y 8-bit single-chip microcontroller description m pd780306y and 780308y are products in the m pd780308y subseries within the 78k/0 series, which incorporates lcd controller/driver, 8-bit resolution a/d converter, timer, serial interface, interrupt functions and many other peripheral hardwares. a one-time prom product capable of operating in the same power supply voltage range as of the mask rom product, eprom product, m pd78p0308y, and other development tools are available. for the details of functional description, refer to the following users manual. m pd780308, 780308y subseries users manual : u11377e 78k/0 series users manual (instruction) : u12326e features ? large on-chip rom & ram ? minimum instruction execution time can be varied from high speed (0.4 m s) to ultra-low speed (122 m s) ? i/o ports: 57 (including segment signal output dual-function pins) ? lcd controller/driver supply voltage : v dd = 2.0 to 5.5 v (operable in any mode) ? 8-bit resolution a /d converter : 8 channels ? serial interface : 3 channels ? timer: 5 channels ? supply voltage : v dd = 2.0 to 5.5 v application field celullar phones, compact disk players, cameras, meters, etc. item program memory data memory product name (rom) high-speed ram expansion ram lcd display ram m pd780306y 48k bytes 1024 bytes 1024 bytes 40 4 bits m pd780308y 60k bytes document no. u12251ej2v1ds00 (2nd edition) date published november 2000 n cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd780306y, 780308y 2 data sheet u12251ej2v1ds ordering information part number package m pd780306ygc- -8eu 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd780306ygf- -3ba 100-pin plastic qfp (14 20 mm) m pd780308ygc- -8eu 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd780308ygf- -3ba 100-pin plastic qfp (14 20 mm) remark indicates rom code suffix.
m pd780306y, 780308y 3 data sheet u12251ej2v1ds 78k/0 series development the following shows the products organized according to usage. the names in the parallelograms are subseries names. note under planning 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 uart and d/a converter enhanced to the pd78014 and i/o enhanced pd78054 pd78054y pd78058f pd78058fy pd780065 pd780034 pd780988 pd780034y m m m m m m m m 64-pin ram capacity of the pd780024 increased. a/d converter of the pd780024 enhanced m m m m on-chip inverter control circuit and uart. emi-noise reduced. pd78044h pd780232 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd780948 80-pin 78k/0 series for panel control. on-chip fip and c/d. display output total: 53 an n-ch open drain i/o added to the pd78044f. display output total: 34 lcd drive the sio of the pd78064 enhanced, and rom, ram capacity increased. emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported on-chip d-can controller m m m m m m m m m m m m pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m 42/44-pin 64-pin 64-pin serial i/o of the pd78018f added and emi-noise reduced. m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 enhanced and emi-noise reduced. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer added to the pd78054 and external interface enhanced rom-less version of the pd78078 pd78070a pd78070ay m pd78078 pd78078y pd780018ay m m m m m 100-pin serial i/o of the pd78078y enhanced and the function limited. m m 100-pin control pd78075b m emi-noise reduced version of the pd78078 m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h enhanced. display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f enhanced. display output total: 53 m m pd780208 m pd78098b iebus tm controller added to the pd78054. emi-noise reduced. m 80-pin pd780024 pd780024y m m 80-pin 80-pin pd780973 pd780955 m m ultra low-power consumption. on-chip uart 100-pin pd780958 m for industrial meter control on-chip automobile meter controller/driver meter control pd78044f 80-pin basic subseries for driving fip. display output total: 34 m m 80-pin pd780701y on-chip d-can/iebus controller m 80-pin pd780833y on-chip controller compliant with j1850 (class 2) m
m pd780306y, 780308y 4 data sheet u12251ej2v1ds the following lists the main functional differences between y subseries products. remark the functions other than the serial interface are the same as those of subseries products without the suffix y. subseries name function rom capacity serial interface i/o v dd min value control m pd78078y m pd78070ay m pd780018ay m pd780058by m pd78058fy m pd78054y m pd780034y m pd780024y m pd78018fy m pd780308y m pd78064y lcd drive 48 k to 60 k C 48 k to 60 k 24 k to 60 k 48 k to 60 k 16 k to 60 k 8 k to 32 k 8 k to 60 k 48 k to 60 k 16 k to 32 k 3-wire/2-wire/i 2 c : 1 ch with automatic transmit/receive function, 3-wire : 1 ch 3-wire/uart : 1 ch with automatic transmit/receive function, 3-wire : 1 ch time division 3-wire : 1 ch i 2 c bus (multi master supported) : 1 ch 3-wire/2-wire/i 2 c : 1 ch with automatic transmit/receive function, 3-wire : 1 ch 3-wire/time division uart : 1 ch 3-wire/2-wire/i 2 c : 1ch with automatic transmit/receive function, 3-wire : 1 ch 3-wire/uart : 1 ch uart : 1 ch 3-wire : 1 ch i 2 c bus (multi master supported) : 1 ch 3-wire/2-wire/i 2 c : 1 ch with automatic transmit/receive function, 3-wire : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire/time division uart : 1 ch 3-wire : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch 88 61 88 68 69 51 53 57 1.8 v 2.7 v 1.8 v 2.7 v 2.0 v 1.8 v 2.0 v
m pd780306y, 780308y 5 data sheet u12251ej2v1ds overview of function product name m pd780306y m pd780308y item 48k bytes 60k bytes 1024 bytes 1024 bytes 40 4 bits 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at 5.0 mhz operation) 122 m s (at 32.768 khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 57 ? cmos input : 0 2 ? cmos i/o : 55 ? 8-bit resolution 8 channels ? segment signal output : maximum 40 ? common signal output : maximum 4 ? bias : 1/2 or 1/3 switchable ? 3-wire serial i/o/i 2 c bus/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o/uart mode selectable : 1 channel ? 3-wire serial i/o mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output capability : 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock: 5.0 mhz operation) 32.768 khz (at subsystem clock: 32.768 khz operation) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 5.0 mhz operation) internal: 13, external: 6 internal: 1 1 internal: 1, external: 1 v dd = 2.0 to 5.5 v ? 100-pin plastic lqfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm) rom high-speed ram expansion ram lcd display ram internal memory when main system clock selected when subsystem clock selected instruction set i/o ports (including segment signal output pins) a/d converter lcd controller/driver serial interface timer vectored interrupt sources maskable non-maskable software package general registers minimum instruction execution time timer output clock output test input supply voltage buzzer output
m pd780306y, 780308y 6 data sheet u12251ej2v1ds contents 1. pin configuration (top view) .......................................................................................................... 7 2. block diagram ............................................................................................................................... ..... 10 3. pin functions ............................................................................................................................... ........ 11 3.1 port pins ............................................................................................................................... .......................... 11 3.2 other pins ............................................................................................................................... ....................... 13 3.3 pin i/o circuits and recommended connection of unused pins ............................................ 14 4. memory space ............................................................................................................................... ....... 18 5. peripheral hardware function feature .............................................................................. 19 5.1 port ............................................................................................................................... .................................... 19 5.2 clock generator ............................................................................................................................... ........ 20 5.3 timer/event counter ............................................................................................................................... .. 20 5.4 clock output control circuit ............................................................................................................ 23 5.5 buzzer output control circuit .......................................................................................................... 23 5.6 a/d converter ............................................................................................................................... ............... 24 5.7 serial interface ............................................................................................................................... .......... 25 5.8 lcd controller/driver ............................................................................................................................ 27 6. interrupt functions and test functions .............................................................................. 28 6.1 interrupt functions ............................................................................................................................... .. 28 6.2 test functions ............................................................................................................................... .............. 32 7. standby function .............................................................................................................................. 3 3 8. reset function ............................................................................................................................... ..... 33 9. instruction set ............................................................................................................................... .... 34 10. electrical specifications ............................................................................................................. 37 11. characteristic curve (reference value) ............................................................................. 58 12. package drawings ............................................................................................................................ 60 13. recommended soldering conditions ....................................................................................... 62 appendix a. development tools ......................................................................................................... 63 appendix b. related documents ........................................................................................................ 66
m pd780306y, 780308y 7 data sheet u12251ej2v1ds 1. pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd780306ygc- -8eu, 780308ygc- -8eu cautions 1. connect directly the ic (internally connected) pin to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to v dd0 and v dd1 , and connecting v dd0 and v dd1 to ground lines separately. p11/ani1 p10/ani0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 av ss p117 p116 p115 p114/rxd p113/txd p112/sck3 p111/so3 p110/si3 p05/intp5 p04/intp4 p03/intp3 p02/intp2 86 85 84 83 82 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd1 1 p12/ani2 p13/ani3 2 3 p14/ani4 4 p15/ani5 5 p16/ani6 6 p17/ani7 7 v dd0 8 av ref 9 p100 10 p101 11 v ss1 12 p102 13 p103 14 p30/to0 15 p31/to1 16 p32/to2 17 p33/ti1 18 19 20 p34/ti2 p35/pcl 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 s13 44 43 42 41 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss0 v lc2 v lc1 v lc0 bias com3 p36/buz 21 p37 22 com0 23 24 25 com1 com2 50 s18 49 48 47 46 s17 s16 s15 s14 p27/sck0/scl 72 73 74 75 70 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 p70/si2/r x d p26/so0/sb1/sda1 p25/si0/sb0/sda0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 55 54 53 52 51 s23 s22 s21 s20 s19 80 79 78 77 76 x1 x2 ic p72/sck2/asck p71/so2/t x d 81
m pd780306y, 780308y 8 data sheet u12251ej2v1ds ? 100-pin plastic qfp (14 20 mm) m pd780306ygf- -3ba, 780308ygf- -3ba cautions 1. connect directly the ic (internally connected) pin to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to v dd0 and v dd1 , and connecting v dd0 and v dd1 to ground lines separately. p26/so0/sb1/sda1 p25/si0/sb0/sda0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 86 85 84 83 82 p95/s26 p96/s25 p97/s24 s23 s22 s21 1 p27/sck0/scl p70/si2/r x d 2 3 p71/so2/t x d 4 p72/sck2/asck 5 ic 6 x2 7 x1 8 v dd1 9 xt1/p07 10 xt2 11 reset 12 p00/intp0/ti00 13 p01/intp1/ti01 14 p02/intp2 15 p03/intp3 16 p04/intp4 17 p05/intp5 18 19 p110/si3 20 p111/so3 p112/sck3 21 p113/txd 22 p114/rxd 23 24 25 p115 p116 81 26 p117 av ss 27 p10/ani0 28 p11/ani1 29 30 p12/ani2 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 50 49 48 47 46 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 v ss1 p101 p100 av ref v dd0 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 77 78 79 80 75 76 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss0 v lc2 v lc1 v lc0 bias com3 com2 com1 com0
m pd780306y, 780308y 9 data sheet u12251ej2v1ds ani0 to ani7 : analog input asck : asynchronous serial clock av ref : analog reference voltage av ss : analog ground bias : lcd power supply bias control buz : buzzer clock com0 to com3 : common output ic : internally connected intp0 to intp5 : interrupt from peripherals p00 to p05, p07 : port0 p10 to p17 : port1 p25 to p27 : port2 p30 to p37 : port3 p70 to p72 : port7 p80 to p87 : port8 p90 to p97 : port9 p100 to p103 : port10 p110 to p117 : port11 pcl : programmable clock reset : reset rxd : receive data s0 to s39 : segment output sb0, sb1 : serial bus sck0, sck2, sck3 : serial clock scl : serial clock sda0, sda1 : serial data si0, si2, si3 : serial input so0, so2, so3 : serial output ti00, ti01, ti1, ti2 : timer input to0 to to2 : timer output txd : transmit data v dd0 , v dd1 : power supply v lc0 to v lc2 : lcd power supply v ss0 , v ss1 : ground x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock)
m pd780306y, 780308y 10 data sheet u12251ej2v1ds 2. block diagram remark the internal rom capacity varies depending on the product. to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer watch timer sda0/si0/sb0/p25 serial interface 0 sda1/so0/sb1/p26 scl/sck0/p27 si3/p110 serial interface 3 so3/p111 sck3/p112 a/d converter av ss av ref ani0/p10- ani7/p17 interrupt control intp0/p00- intp5/p05 buzzer output buz/p36 clock output control pcl/p35 p00 port 0 p01-p05 p07 port 1 p10-p17 port 11 p110-p117 port 2 p25-p27 port 3 p30-p37 port 7 p70-p72 port 8 p80-p87 port 9 p90-p97 port 10 p100-p103 lcd controller/ driver s0-s23 bias f lcd reset x1 x2 xt1/p07 xt2 78k/0 cpu core rom ram system control v dd0 , v dd1 v ss0 , v ss1 ic s24/p97- s31/p90 s32/p97- s39/p80 com0-com3 v lc0 -v lc2 so2/txd/p71 serial interface 2 rxd/p114 sck2/asck/p72 si2/rxd/p70 txd/p113
m pd780306y, 780308y 11 data sheet u12251ej2v1ds 3. pin functions 3.1 port pins (1/2) dual- function pin pin name i/o input only port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. note2 input to0 to1 to2 ti1 ti2 pcl buz si2/rxd so2/txd sck2/ asck p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. p00 p01 p02 p03 p04 p05 p07 note1 p10 to p17 input input only input intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 xt1 ani0 to ani7 input p70 p71 p72 input input input input input port 3 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/ output input/ output port 2 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/ output input/ output input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. port 0 7-bit i/o port. input/ output notes 1. when using the p07/xt1 pins as an input port, set (1) bit 6 (frc) of the processor clock control register (pcc) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, port 1 is set to input mode. however, internal pull-up resistor is not automatically used. so0/sb1/ sda1 si0/sb0/ sda0 sck0/scl function on reset
m pd780306y, 780308y 12 data sheet u12251ej2v1ds 3.1 port pins (2/2) dual- function pin pin name i/o port 8 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd display control register (lcdc). port 9 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd display control register (lcdc). p80 to p87 input/ output input s39 to s32 s31 to s24 input input/ output p90 to p97 input/ output p100 to p103 input input function on reset port 10 4-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. led direct drive capability. p110 p111 p112 p113 p114 p115 to p117 port 11 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. falling edge detection capability. input/ output si3 so3 sck3 txd rxd
m pd780306y, 780308y 13 data sheet u12251ej2v1ds 3.2 other pins (1/2) intp0 intp1 intp2 intp3 intp4 intp5 si0 si2 si3 so0 so2 so3 sb0 sb1 sda0 sda1 sck0 sck2 sck3 scl rxd txd asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz s0 to s23 s24 to s31 s32 to s39 com0 to com3 v lc0 to v lc2 bias dual- function pin pin name i/o function on reset input output output output output input serial interface serial clock input/output. serial interface serial data input/output. input output input input/ output input/ output output serial interface serial data output. input serial interface serial data input. input external interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. input input input input input input input input input input input output input p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0/sda0 p70/rxd p110 p26/sb1/sda1 p71/txd p111 p25/si0/sda0 p26/so0/sda1 p25/si0/sb0 p26/so0/sb1 p27 p72/asck p112 p27/sck0 p70/si2, p114 p71/so2, p113 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p97 to p90 p87 to p80 output output asynchronous serial interface serial data input. asynchronous serial interface serial data output. asynchronous serial interface serial clock input. external count clock input to 16-bit timer (tm0). capture trigger signal input to capture register (cr00). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer output (shared with 14-bit pwm output). 8-bit timer output. clock output (for main system clock, subsystem clock trimming). buzzer output. lcd controller/driver segment signal output. lcd controller/driver common signal output. lcd drive voltage. split resistors can be incorporated by mask option. lcd drive power supply.
m pd780306y, 780308y 14 data sheet u12251ej2v1ds 3.2 other pins (2/2) a/d converter analog input. reference voltage input of a/d converter and d/a converter (shared with analog power supply). ground potential of a/d converter and d/a converter. set the same potential as v ss0 . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply for port block. ground potential for port block. positive power supply (except port block). ground potential (except port and analog block). internally connected. connect directly to v ss0 or v ss1 pin. pin name i/o ani0 to ani7 av ref av ss reset x1 x2 xt1 xt2 v dd0 v ss0 v dd1 v ss1 ic function on reset dual- function pin p10 to p17 p07 input input input input input input input 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1 . table 3-1. input/output circuit type of each pin (1/2) p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 p10/ani0 to p17/ani7 p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 connect to v ss0 . connect to v dd0 . input input/output input input/output 2 8-c 16 11-b 10-b 5-h 8-c pin name i/o recommended connection when not used input/output circuit type independently connect to v ss0 through resistor. independently connect to v dd0 or v ss0 through resistor.
m pd780306y, 780308y 15 data sheet u12251ej2v1ds i/o recommended connection when not used pin name input/output circuit type 5-h 8-c 5-h 8-c 17-c 5-h 8-c 17-b 18-a 2 16 table 3-1. input/output circuit type of each pin (2/2) p35/pcl p36/buz p37 p70/si2/rxd p71/so2/txd p72/sck2/asck p80/s39 to p87/s32 p90/s31 to p97/s24 p100 to p103 p110/si3 p111/so3 p112/sck3 p113/txd p114/rxd p115 to p117 s0 to s23 com0 to c0m3 v lc0 to v lc2 bias reset xt2 av ref av ss ic independently connect to v dd0 through resistor. input/output output input leave unconnected. leave unconnected. connect to v ss0 . connect to v ss0 . connect directly to v ss0 or v ss1 . independently connect to v dd0 or v ss0 through resistor.
m pd780306y, 780308y 16 data sheet u12251ej2v1ds in type 2 type 5-h type 8-c type 11-b type 16 type 10-b schmitt-triggered input with hysteresis characteristic figure 3-1. pin input/output circuits (1/2) pull-up enable data output disable p-ch in/out v dd0 v dd0 p-ch n-ch v ss0 pull-up enable data output disable p-ch in/out v dd0 v dd0 p-ch n-ch open-drain v ss0 feedback cut-off p-ch xt1 xt2 pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch v ss0 pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch n-ch v ref + p-ch (threshold voltage) comparator v ss0 av ss
m pd780306y, 780308y 17 data sheet u12251ej2v1ds p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 com data n-ch p-ch out v ss1 figure 3-1. pin input/output circuits (2/2) type 17-b type 18-a type 17-c out p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data v ss1 pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data v ss0 v ss1
m pd780306y, 780308y 18 data sheet u12251ej2v1ds m pd780306y bfffh m pd780308y efffh 4. memory space the memory map of m pd780306y and 780308y is shown in figure 4-1. figure 4-1. memory map note the capacity of internal rom differs according to product. (refer to the following table.) last address of internal rom nnnnh product name ffffh ff00h feffh fedfh fa80h fa7fh fa58h fa57h nnnnh+1 nnnnh 0000h nnnnh 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h use prohibited internal expansion ram 1024 8 bits program area callf entry area program area callt table area vector table area general registers 32 8 bits internal high-speed ram 1024 8 bits lcd display ram 40 4 bits program memory space data memory space special function register (sfr) 256 8 bits 1000h internal rom note fee0h f800h f7ffh use prohibited f400h f3ffh use prohibited fb00h faffh
m pd780306y, 780308y 19 data sheet u12251ej2v1ds 5. peripheral hardware function feature 5.1 port there are two kinds of i/o port. ? cmos input (p00, p07) : 2 ? cmos input/output (p01 to p05, port 1 to 3, 7 to 11) : 55 total : 57 table 5-1. functions of ports function name pin name dedicated input port input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifialbe bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. direct led drive capability. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. test flag (krif) is set to 1 by falling edge detection. port 0 port 1 port 2 port 3 port 7 port 8 port 9 port 10 port 11 p00, p07 p01 to p05 p10 to p17 p25 to p27 p30 to p37 p70 to p72 p80 to p87 p90 to p97 p100 to p103 p110 to p117
20 m pd780306y, 780308y data sheet u12251ej2v1ds x1 x2 xt1/p07 xt2 f xt f xx 2 f xx 2 2 f xx 2 3 f xx 2 4 f xt 2 f x 2 stop f x cpu clock (f cpu ) subsystem clock oscillator main system clock oscillator scaler selec- tor prescaler prescaler standby control circuit selec- tor watch timer clock output function clock to peripheral hardware to intp0 sampling clock f xx 1/2 interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels C C timer output 1 output 2 outputs C C pwm output 1 output C C C pulse width measurement 2 inputs C C C square wave output 1 output 2 outputs C C one-shot pulse output 1 output C C C interrupt request 2211 test input C C 1 input C 5.2 clock generator there are two kinds of clocks, main system clock and subsystem clock. the minimum instruction execution time can also be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (main system clock: in 5.0 mhz operation) ? 122 m s (subsystem clock: in 32.768 khz operation) figure 5-1. clock generator block diagram 5.3 timer/event counter five timer/event counter channels are incorporated. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. timer/event counter types and functions 16-bit timer/ event counter 8-bit timer/ event counter watch timer watchdog timer type function
m pd780306y, 780308y 21 data sheet u12251ej2v1ds figure 5-2. 16-bit timer/event counter block diagram inttm1 to2/p32 inttm2 to1/p31 f xx /2-f xx /2 9 fx x /2 11 ti1/p33 ti2/p34 f xx /2-f xx /2 9 fx x /2 11 internal bus 8-bit compare register (cr10) match match selec- tor 8-bit timer register 1 (tm1) clear selec- tor selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) clear selec- tor output control circuit output control circuit internal bus selec- tor figure 5-3. 8-bit timer/event counter block diagram ti01/p01/intp1 watch timer output ti00/p00/intp0 2f xx f xx f xx /2 f xx /2 2 intp0 inttm01 intp1 inttm00 to0/p30 internal bus selec- tor 16-bit capture/compare register (cr00) match match pwm pulse output control circuit output control circuit edge detector 16-bit timer register (tm0) clear 16-bit capture/compare register (cr01) internal bus selec- tor selector
22 m pd780306y, 780308y data sheet u12251ej2v1ds figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 f xx 2 11 f xx 2 5 f xx 2 4 f xx 2 3 reset intwdt non-maskable interrupt request intwdt maskable interrupt request prescaler selector 8-bit counter control circuit f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f xx /2 7 f xt f w f w 2 14 f w 2 13 intwt inttm3 selec- tor prescaler 5-bit counter selector selector selector to 16-bit timer/event counter to lcd controller/driver
m pd780306y, 780308y 23 data sheet u12251ej2v1ds 5.4 clock output control circuit clocks of the following frequency can be output as clock outputs. ? 19.5 khz/39.1khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (main system clock: in 5.0 mhz operation) ? 32.768 khz (subsystem clock: in 32.768 khz operation) figure 5-6. clock output control circuit block diagram 5.5 buzzer output control circuit clocks of the following frequency can be output as buzzer outputs. ? 1.2 khz/2.4 khz/4.9 khz/9.8 khz (main system clock : in 5.0 mhz operation) figure 5-7. buzzer output control circuit block diagram pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt selector synchronization circuit f xx /2 f xx output control circuit buz/p36 selector f xx /2 9 f xx /2 10 f xx /2 11 output control circuit
24 m pd780306y, 780308y data sheet u12251ej2v1ds ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 av ref av ss intad intp3 selec- tor sample & hold circuit intp3/p03 voltage comparator series resistor string tap selec- tor successive approximation register (sar) control circuit edge detector a/d conversion result register (adcr) internal bus 5.6 a/d converter eight 8-bit resolution a/d converter channels are incorporated. the following two types of start-up method are available. ? hardware start ? software start figure 5-8. a/d converter block diagram
m pd780306y, 780308y 25 data sheet u12251ej2v1ds figure 5-9. serial interface channel 0 block diagram 5.7 serial interface three clocked serial interface channels are incorporated. ? serial interface channel 0 ? serial interface channel 2 ? serial interface channel 3 table 5-3. serial interface channel block diagram function serial interface channel 0 serial interface channel 2 serial interface channel 3 3-wire serial i/o mode (msb/lsb-first switchable) (msb/lsb-first switchable) (msb/lsb-first switchable) i 2 c (inter ic) bus mode (msb-first) 2-wire serial i/o mode (msb-first) asynchronous serial interface (with dedicated baud rate (uart) mode generator, data i/o pin switch function) si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intcsi0 to2 f xx /2-f xx /2 8 internal bus selector selector serial i/o shift register 0 (sio0) output latch busy/acknowledge output circuit stop condition/ start condition/ acknowledge detector serial clock counter interrupt request signal generator serial clock control circuit selector
26 m pd780306y, 780308y data sheet u12251ej2v1ds figure 5-11. serial interface channel 3 block diagram si3/p110 so3/p111 sck3/p112 intcsi3 f xx /2-f xx /2 8 internal bus serial i/o shift register 3 (sio3) serial clock counter interrupt request signal generator serial clock control circuit selector figure 5-10. serial interface channel 2 block diagram r x d/si2/p70 t x d/so2/p71 asck/sck2/p72 intser intsr/intcsi2 f xx -f xx /2 10 intst receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) direction control circuit transmit shift register (txs/sio2) transmit control circuit receive control circuit sck output control circuit baud rate generator internal bus selector selector r x d/p114 t x d/p113
m pd780306y, 780308y 27 data sheet u12251ej2v1ds 5.8 lcd controller/driver an lcd controller/driver with the following functions is incorporated. ? selection of 5 types of display mode ? 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (p80/s39 to p87/s32, p90/s31 to p97/s24) table 5-4. display mode types and maximum number of display pixels bias method time multiplexing common signal used maximum number of display pixels static com0 (com1 to com3) 40 (40 segments 1 common) 1/2 2 com0, com1 80 (40 segments 2 commons) 3 com0 to com2 120 (40 segments 3 commons) 1/3 3 com0 to com2 4 com0 to com3 160 (40 segments 4 commons) figure 5-12. lcd controller/driver block diagram v lc2 v lc1 v lc0 bias com3 com2 com1 com0 s39/p80 s0 s23 s24/p97 lcdcl f w 2 9 f w 2 8 f w 2 7 f w 2 6 internal bus display data memory segment data selector port output data segment driver prescaler selector timing controller lcd drive voltage generator common driver lcd drive mode switch circuit
28 m pd780306y, 780308y data sheet u12251ej2v1ds 6. interrupt functions and test functions 6.1 interrupt functions there are twenty-one of interrupt sources of three different kinds, as shown below. ? non-maskable : 1 ? maskable : 19 ? software : 1
m pd780306y, 780308y 29 data sheet u12251ej2v1ds table 6-1. interrupt source list interrupt source name interrupt type default priority note1 internal/ external vector table address basic con- figuration type note2 watchdog timer overflow (with watchdog timer mode 1 selected) watchdog timer overflow (with interval timer mode selected) pin input edge detection serial interface channel 0 transfer termination serial interface channel 2 uart reception error generation serial interface channel 2 uart reception termination serial interface channel 2 3-wire transfer termination serial interface channel 2 uart transmission termination reference time interval signal from watch timer 16-bit timer register and capture/compare register (cr00) match signal generation 16-bit timer register and capture/compare register (cr01) match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation a/d converter conversion termination serial interface channel 3 transfer termination brk instruction execution intwdt intwdt intp0 intp1 intp2 intp3 intp4 intp5 intcsi0 intser intsr intcsi2 intst inttm3 inttm00 inttm01 inttm1 inttm2 intad intcsi3 brk trigger (a) (b) internal 0004h 0006h 0008h 000ah 000ch 000eh 0010h 0014h 0018h 001ah 001ch 001eh 0020h 0022h 0024h 0026h 0028h 002ah 003eh (c) (d) external 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 maskable non- maskable (e) software internal (b) notes 1. default priority is a priority order when more than one maskable interrupt source is generated simultaneously. 0 is the highest and 17 the lowest. 2. basic configuration types (a) to (e) correspond to those shown on the next page.
30 m pd780306y, 780308y data sheet u12251ej2v1ds interrupt request standby release signal internal bus vector table address generator priority control circuit figure 6-1. basic configuration of interrupt functions (1/2) (a) internal non-maskable interrupt (b) intrnal maskable interrupt mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0) sampling clock select register (scs) if ie pr isp external interrupt mode register (intm0) sampling clock edge detector interrupt request internal bus mk priority control circuit vector table address generator standby release signal
m pd780306y, 780308y 31 data sheet u12251ej2v1ds figure 6-1. basic configuration of interrupt functions (2/2) (d) external maskable interrupt (except intp0) if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit (e) software interrupt internal bus interrupt request vector table address generator priority control circuit if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority hung-up flag
32 m pd780306y, 780308y data sheet u12251ej2v1ds 6.2 test functions there are two test functions as shown in table 6-2. table 6-2. test input source list figure 6-2. basic configuration of test function if : test input flag mk : test mask flag test input source name trigger internal/external intwt watch timer overflow internal intpt11 port 11 falling edge detection external mk if internal bus standby release signal test input signal
m pd780306y, 780308y 33 data sheet u12251ej2v1ds 7. standby function the standby function is a function to reduce the current consumption and there are the following two kinds of standby functions. ? halt mode : halts cpu operating clock and can reduce average current consumption by the intermittent operation along with the normal operation. ? stop mode : halts main system clock oscillation. halts all operations with the main system clock and sets ultra- low current consumption state with subsystem clock only. figure 7-1. standby function note halting the main system clock enables the current consumption to be reduced. when the cpu is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (mcc) of the processor clock control register (pcc). the stop instruction is not available. caution when the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time by a program. 8. reset function there are the following two kinds of resetting methods. ? external reset by reset pin. ? internal reset by watchdog timer hung-up time detection. css=1 css=0 main system clock operation interrupt request stop mode main system clock oscillation halted stop instruction () interrupt request halt instruction halt mode clock supply to cpu halted, oscillation maintained () subsystem clock operation note halt instruction interrupt request halt mode note clock supply to cpu halted, oscillation maintained ()
34 m pd780306y, 780308y data sheet u12251ej2v1ds 9. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subs, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz #byte a r note sfr saddr !addr16 psw [de] [hl] $addr16 1 none 2nd operand 1st operand add addc sub subc and or xor cmp mov mov mov add addc sub subc and or xor cmp mov mov add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp [hl+byte] [hl+b] [hl+c] ror rol rorc rolc inc dec inc dec push pop ror4 rol4 mulu divuw dbnz dbnz a r b, c sfr saddr !addr16 psw [de] [hl] [hl+byte] [hl+b] [hl+c] x c note except r = a
m pd780306y, 780308y 35 data sheet u12251ej2v1ds (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note sfrp saddrp !addr16 sp none ax rp sfrp saddrp !addr16 sp addw subw cmpw movw movw movw movw movw note movw movw movw movw movw movw movw movw incw, decw push, pop movw xchw note only when rp = bc, de, hl (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bits [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 mov1 mov1 mov1 mov1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr mov1 and1 or1 xor1
36 m pd780306y, 780308y data sheet u12251ej2v1ds (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dnzb callt callf call br br basic instruction compound instruction br, bc, bnc, bz, bnz 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop bt, bf, btclr dbnz
37 m pd780306y, 780308y data sheet u12251ej2v1ds 10. electrical specifications absolute maximum ratings (t a = 25 c) v dd av ref av ss v i v o v an i oh i ol parameter symbol test conditions rating unit v v v v v v v ma ma ma ma ma ma ma ma ma ma c c supply voltage input voltage output voltage analog input voltage output current, high p10-p17 analog input pin 1 pin total for p01-p05, p10-p17, p25-p27, p70-p72, p110-p117 total for p30-p37, p80-p87, p90-p97, p100-p117 C0.3 to +7.0 C0.3 to v dd + 0.3 C0.3 to +0.3 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 av ss C 0.3 to av ref + 0.3 C10 C15 C15 30 15 note 60 40 note 140 100 note 50 20 note C40 to +85 C65 to +150 peak value r.m.s. value peak value r.m.s. value peak value r.m.s. value peak value r.m.s. value 1 pin total for p01-p05, p10-p17, p110-p117 total for p30-p37, p100-p103 total for p25-p27, p70-p72, p80-p87, p90-p97 operating ambient temperature storage temperature t a t stg note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution the product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. that is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. the absolute maximum rating values must therefore be observed in using the product. remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. capacitance (t a = 25 c, v dd = v ss = 0 v) ? output current, low input capacitance output capacitance i/o capacitance pf pf pf parameter symbol test conditions min. typ. max. unit 15 15 15 c in c out c io f = 1 mhz unmeasured pins returned to 0 v.
38 m pd780306y, 780308y data sheet u12251ej2v1ds x1 x2 ic c1 c2 r1 x1 x2 ic c1 c2 r1 main system clock oscillation circuit characteristics (t a = ?0 to +85 c, v dd = 2.0 note 4 to 5.5 v) unit mhz ms mhz ms mhz ns max. 5 4 5 10 30 5.0 500 recommended circuit parameter oscillator frequency (f x ) note 1 oscillation stabilization time note 2 oscillator frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) min. 1 1 1.0 85 resonator ceramic resonator crystal resonator external clock notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. 3. after v dd reaches the minimum oscillator voltage range. 4. actually, oscillation start voltage or over, and v dd = 2.0 or over (for an external clock, v dd = 2.0 or over is ok). cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. if the main system clock oscillation circuit is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. typ. m pd74hcu04 test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = oscillator voltage range v dd = 4.5 to 5.5 v note 3 note 3 x1 x2
39 m pd780306y, 780308y data sheet u12251ej2v1ds r2 xt2 xt1 ic c4 c3 xt1 xt2 subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.0 note 4 to 5.5 v) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd has reached the minimum oscillation voltage range. 3. after v dd reaches the minimum oscillator voltage range. 4. actually, oscillation start voltage or over, and v dd = 2.0 or over (for an external clock, v dd = 2.0 or over is ok). cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillation circuit is designed as a low amplification circuit to provide low consumption current, causing misoperation to noise more frequently than the main system clock oscillation circuit. special care should therefore be taken to wiring method when the subsystem clock is used. v dd = 4.5 to 5.5 v note 3 note 3 crystal resonator external clock oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth /t xtl ) 35 2 10 100 15 32.768 1.2 32 32 5 khz s khz m s resonator recommended circuit parameter test conditions min. typ. max. unit v dd = oscillator voltage range
40 m pd780306y, 780308y data sheet u12251ej2v1ds main system clock: ceramic resonator (t a = C40 to +85 c) manufacturer product name frequency recommended circuit constant oscillator voltage range (mhz) c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) matsushita efoec2004a5 2.00 built-in built-in 4.7 2.0 5.5 electronics efoec3584a4 3.58 built-in built-in 0 2.0 5.5 components efoec419a4 4.19 built-in built-in 0 2.0 5.5 co., ltd. efoec4914a4 4.91 built-in built-in 0 2.0 5.5 efoec5004a4 5.00 built-in built-in 0 2.0 5.5 tdk corp. ccr1000k2 1.00 150 150 0 2.0 5.5 ccr3.58mc3 3.58 built-in built-in 0 2.0 5.5 ccr4.19mc3 4.19 built-in built-in 0 2.0 5.5 ccr4.91mc3 4.91 built-in built-in 0 2.0 5.5 ccr5.0mc3 5.00 built-in built-in 0 2.0 5.5 murata mfg. csb1000j 1.00 100 100 2.2 2.0 5.5 co., ltd. csa2.00mg040 2.00 100 100 0 2.0 5.5 cst2.00mg040 2.00 built-in built-in 0 2.0 5.5 csa3.58mg 3.58 30 30 0 2.0 5.5 cst3.58mgw 3.58 built-in built-in 0 2.0 5.5 csa4.19mg 4.19 30 30 0 2.0 5.5 cst4.19mgw 4.19 built-in built-in 0 2.0 5.5 csa4.91mg 4.91 30 30 0 2.0 5.5 cst4.91mgw 4.91 built-in built-in 0 2.0 5.5 csa5.00mg 5.00 30 30 0 2.0 5.5 cst5.00mgw 5.00 built-in built-in 0 2.0 5.5 caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used. recommended oscillation circuit constant
41 m pd780306y, 780308y data sheet u12251ej2v1ds dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 5.5 v) 0.7 v dd v dd v 0.8 v dd v dd v 0.8 v dd v dd v 0.85 v dd v dd v v dd C0.5 v dd v v dd C0.2 v dd v 0.8 v dd v dd v 0.9 v dd v dd v 0.9 v dd v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.2 v dd v 0 0.15 v dd v 0 0.4 v 0 0.2 v 0 0.2 v dd v 0 0.1 v dd v 0 0.1 v dd v v dd C1.0 v dd v v dd C0.5 v dd v 0.6 2.0 v 0.4 v 0.2 v dd v 0.5 v parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v 4.5 v dd 5.5 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v 4.5 v dd 5.5 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note input voltage, low v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v il4 v oh v ol1 v ol2 v ol3 output voltage, high output voltage, low note when used as p07, the inverse phase of p07 should be input to xt2 using an inverter. remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 v dd = 4.5 to 5.5 v i oh = C1 ma i oh = C100 m a p100-p103 p01-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p110-p117 sb0, sb1, sck0 i ol = 400 m a input voltage, high v dd = 4.5 to 5.5 v, i ol = 15 ma v dd = 4.5 to 5.5 v, i ol = 1.6 ma v dd = 4.5 to 5.5 v, open-drain, pulled up (r = 1 k w )
42 m pd780306y, 780308y data sheet u12251ej2v1ds parameter symbol test conditions min. typ. max. unit p00-p05, p10-p17, p25-p27, i lih1 p30-p37, p70-p72, p80-p87, v in = v dd p90-p97, p100-p103, 3 m a p110-p117 i lih2 x1, x2, xt1/p07, xt2 20 m a p00-p05, p10-p17, p25-p27, i lil1 p30-p37, p70-p72, p80-p87, v in = 0 v p90-p97, p100-p103, C3 m a p110-p117 i lih2 x1, x2, xt1/p07, xt2 C20 m a i loh v out = v dd 3 m a i lol v out = 0 v C3 m a rv in = 0 v 15 45 90 k w v dd = 5.0 v 10 % note 5 412ma v dd = 3.0 v 10 % note 6 0.6 1.8 ma i dd1 v dd = 2.2 v 10 % note 6 0.35 1.05 ma v dd = 5.0 v 10 % note 5 6.5 19.5 ma v dd = 3.0 v 10 % note 6 0.8 2.4 ma v dd = 5.0 v 10 % 1.4 4.2 ma v dd = 3.0 v 10 % 500 1500 m a i dd2 v dd = 2.2 v 10 % 280 840 m a v dd = 5.0 v 10 % 1.6 4.8 ma v dd = 3.0 v 10 % 650 1950 m a v dd = 5.0 v 10 % 60 120 m a i dd3 v dd = 3.0 v 10 % 32 64 m a v dd = 2.2 v 10 % 24 48 m a v dd = 5.0 v 10 % 25 55 m a i dd4 v dd = 3.0 v 10 % 5 15 m a v dd = 2.2 v 10 % 2.5 12.5 m a v dd = 5.0 v 10 % 1 30 m a i dd5 v dd = 3.0 v 10 % 0.5 10 m a v dd = 2.2 v 10 % 0.3 10 m a v dd = 5.0 v 10 % 0.1 30 m a i dd6 v dd = 3.0 v 10 % 0.05 10 m a v dd = 2.2 v 10 % 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 5.5 v) notes 1. current flowing v dd pin. not including a/d converter, ports, on-chip pull-up resistors or lcd dividing resistors. 2. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 3. main system clock f xx = f x operation (when osms is set to 01h) 4. when the main system clock is stopped. 5. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when pcc is set to 04h) remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. supply current note 1 p01-p05, p10-p17, p25- p27, p30-p37, p70-p72, p80-p87, p90-p97, p100- p103, p110-p117 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 halt mode 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 operating mode 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 operating mode 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 halt mode 32.768 khz, crystal oscillation operating mode note 4 32.768 khz, crystal oscillation halt mode note 4 xt1 = v dd stop mode when feedback resistor is connected xt1 = v dd stop mode when feedback resistor is disconnected input leakage current, high input leakage current, low output leakage current, high output leakage current, low software pull-up resistor
43 m pd780306y, 780308y data sheet u12251ej2v1ds parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.5 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) lcd controller/driver characteristics (at normal operation) (1) static display mode (t a = C10 to +85 c, v dd = 2.0 to 5.5 v) v lcd0 = v lcd note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). (2) 1/3 bias method (t a = C10 to +85 c, v dd = 2.5 to 5.5 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) (3) 1/2 bias method (t a = C10 to +85 c, v dd = 2.7 to 5.5 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 v lcd0 = v lcd v lcd1 = v lcd 1/2 v lcd2 = v lcd1
44 m pd780306y, 780308y data sheet u12251ej2v1ds parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) lcd controller/driver characteristics (at low-voltage operation) parameteter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) (1) static display mode (t a = C10 to +85 c, 2.0 v v dd < 3.4 v) v lcd0 = v lcd note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). (2) 1/3 bias method (t a = C10 to +85 c, 2.0 v v dd < 3.4 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage v odc i o = 5 m a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 m a0 0.2 v deviation note (segment) (3) 1/2 bias method (t a = C10 to +85 c, 2.0 v v dd < 3.4 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 v lcd0 = v lcd v lcd1 = v lcd 1/2 v lcd2 = v lcd1
45 m pd780306y, 780308y data sheet u12251ej2v1ds parameter symbol test conditions min. typ. max. unit t cy operating on main system clock v dd = 2.7 to 5.5 v 0.8 64 m s (f xx = 2.5 mhz) note 1 2.0 64 m s operating on main system clock 3.5 v dd 5.5 v 0.4 32 m s (f xx = 5.0 mhz) note 2 2.7 v dd < 3.5 v 0.8 32 m s operating on subsystem clock 40 note 3 122 125 m s f ti00 f ti00 = t tih00 + t til00 0 1/t ti00 mhz t tih00 , 3.5 v v dd 5.5 v 2/f sam +0.1 note 4 m s t til00 2.7 v v dd < 3.5 v 2/f sam +0.2 note 4 m s 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 m s f ti01 v dd = 2.7 to 5.5 v 0 100 khz 0 50 khz t tih01 ,v dd = 2.7 to 5.5 v 10 m s t til01 20 m s f ti1 v dd = 4.5 to 5.5 v 0 4 mhz 0 275 khz t tih, v dd = 4.5 to 5.5 v 100 ns t til 1.8 m s t inth , intp0 3.5 v v dd 5.5 v 2/f sam +0.1 note 4 m s t inth , 2.7 v v dd < 3.5 v 2/f sam +0.2 note 4 m s t inth , 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 m s t intl intp1-intp5, p110-p117 v dd = 2.7 to 5.5 v 10 m s 20 m s t rst v dd = 2.7 to 5.5 v 10 m s 20 m s ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.0 to 5.5 v) notes 1. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 2. main system clock f xx = f x operation (when osms is set to 01h) 3. this is the value when the external clock is used. the value is 114 m s (min.) when the crystal resonator is used. 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n+1 , f xx /32, f xx /64 and f xx /128 (when n = 0 to 4). ti00 input high/ low-level width ti01 input high/ low-level width ti1, ti2 input high/low-level width interrupt request input high/low- level width ti01 input frequency ti00 input frequency cycle time (min. instruction execution time) ti1, ti2 input frequency reset low level width
46 m pd780306y, 780308y data sheet u12251ej2v1ds t cy vs v dd (at main system clock f xx = f x /2 operation) t cy vs v dd (at main system clock f xx = f x operation) 60 10 2.0 1.0 1 023456 0.8 0.4 60 10 2.0 1.0 1 023456 0.8 0.4 supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range 32 3.5 2.7
47 m pd780306y, 780308y data sheet u12251ej2v1ds (2) serial interface (t a = C40 to +85 c, v dd = 2.0 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy1 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2C50 ns t kl1 t kcy1 /2C100 ns 4.5 v v dd 5.5 v 100 ns t sik1 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck0, so0 output line. sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 t kh2 , t kl2 note c is the load capacitance of so0 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy2 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik2 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns 1000 ns t r2 , t f2 sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 sck0 rise, fall time (ii) 3-wire serial i/o mode (sck0...external clock input)
48 m pd780306y, 780308y data sheet u12251ej2v1ds (iii) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1600 ns 3200 ns v dd = 2.7 to 5.5 v t kcy3 /2C160 ns t kcy3 /2C190 ns v dd = 4.5 to 5.5 v t kcy3 /2C50 ns t kcy3 /2C100 ns 4.5 v v dd 5.5 v 300 ns 2.7 v v dd < 4.5 v 350 ns 400 ns 600 ns 300 ns r = 1 k w , c = 100 pf note note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. t kcy3 t ksi3 t kso3 t sik3 t kh3 t kl3 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 (iv) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1600 ns 3200 ns v dd = 2.7 to 5.5 v 650 ns 1300 ns v dd = 2.7 to 5.5 v 800 ns 1600 ns 100 ns t kcy4 /2 ns r = 1 k w ,v dd = 4.5 to 5.5 v 0 300 ns c = 100 pf note 0 500 ns 1000 ns t kcy4 t kh4 t kl4 t sik4 t ksi4 t kso4 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sck0 rise, fall time t r4 , t f4
49 m pd780306y, 780308y data sheet u12251ej2v1ds (v) i 2 c bus mode (scl...internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v 10 m s 20 m s v dd = 2.7 to 5.5 v t kcy5 C160 ns t kcy5 C190 ns v dd = 4.5 to 5.5 v t kcy5 C50 ns t kcy5 C100 ns v dd = 2.7 to 5.5 v 200 ns 300 ns 0ns v dd = 4.5 to 5.5 v 0 300 ns 0 500 ns 200 ns 400 ns 500 ns note r and c are the load resistance and load capacitance of scl, sda0, and sda1 output line. (vi) i 2 c bus mode (scl...external clock output) r = 1 k w , c = 100 pf note parameter symbol test conditions min. typ. max. unit 1000 ns 400 ns 200 ns 0ns v dd = 4.5 to 5.5 v 0 300 ns 0 500 ns 200 ns 400 ns 500 ns 1000 ns scl cycle time scl high/low-level width sda0, sda1 setup time (to scl - ) sda0, sda1 hold time (to scl ) sda0, sda1 output delay time (from scl ) sda0, sda1 from scl - or sda0, sda1 - from scl - scl from sda0, sda1 sda0, sda1 high-level width scl rise, fall time t kcy6 t kh5 , t kl6 t sik6 t ksi6 t kso6 t ksb t sbk t sbh r = 1 k w , c = 100 pf note note r and c are the load resistance and load capacitance of scl, sda0, and sda1 output line. t r6 , t f6 sda0, sda1 high-level width scl cycle time scl high-level width scl low-level width sda0, sda1 setup time (to scl - ) t kcy5 t kh5 t kl5 t sik5 sda0, sda1 hold time (to scl ) t ksi5 sda0, sda1 output delay time (from scl ) t kso5 sda0, sda1 from scl - or sda0, sda1 - from scl - t ksb scl from sda0, sda1 t sbk t sbh
50 m pd780306y, 780308y data sheet u12251ej2v1ds (b) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy7 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2C50 ns t kl7 t kcy7 /2C100 ns 4.5 v v dd 5.5 v 100 ns t sik7 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi7 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck2, so2 output line. sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 note c is the load capacitance of so2 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy8 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik8 100 ns t ksi8 400 ns t kso8 c = 100 pf note 300 ns 1000 ns t r8 , t f8 sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 sck2 rise, fall time t kh8 , t kl8 (ii) 3-wire serial i/o mode (sck2...external clock input)
51 m pd780306y, 780308y data sheet u12251ej2v1ds parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy9 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns 4.5 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 78125 bps transfer rate 2.7 v v dd < 4.5 v 39063 bps 19531 bps (iii) uart mode (dedicated baud rate generator output) (iv) uart mode (external clock input) t kh9 , t kl9 t r9 , t f9 asck cycle time asck high/low-level width transfer rate asck rise, fall time
52 m pd780306y, 780308y data sheet u12251ej2v1ds (c) serial interface channel 3 (i) 3-wire serial i/o mode (sck3... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy10 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh10 ,v dd = 4.5 to 5.5 v t kcy10 /2C50 ns t kl10 t kcy10 /2C100 ns 4.5 v v dd 5.5 v 100 ns t sik10 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi10 400 ns t kso10 c = 100 pf note 300 ns note c is the load capacitance of sck3, so3 output line. sck3 cycle time sck3 high/low-level width si3 setup time (to sck3 - ) si3 hold time (from sck3 - ) so3 output delay time from sck3 note c is the load capacitance of so3 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy11 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik11 100 ns t ksi11 400 ns t kso11 c = 100 pf note 300 ns 1000 ns t r11 , t f11 sck3 cycle time sck3 high/low-level width si3 setup time (to sck3 - ) si3 hold time (from sck3 - ) so3 output delay time from sck3 sck3 rise, fall time (ii) 3-wire serial i/o mode (sck3...external clock input) t kh11 , t kl11
53 m pd780306y, 780308y data sheet u12251ej2v1ds t til1 t tih1 1/f ti1 ti1, ti2 ti00, ti01 t til00 , t til01 t tih00 , t tih01 1/f ti00, 01 t xl t xh 1/f x v ih3 (min.) v il3 (max.) t xtl t xth 1/f xt v ih4 (min.) v il4 (max.) x1 input xt1 input 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ac timing test point (excluding x1, xt1 input) clock timing ti timing
54 m pd780306y, 780308y data sheet u12251ej2v1ds t kcym t klm t khm sck0, sck2, sck3 si0, si2, si3 so0, so2, so3 t sikm t ksim t ksom input data output data t rn t fn m = 1, 2, 7, 8, 10, 11 n = 2, 8, 11 serial transfer timing 3-wire serial i/o mode: 2-wire serial i/o mode: i 2 c bus mode: t kl5, 6 t sbh t sbk t kh5, 6 t kso5, 6 t ksi5, 6 t sbk t sik5, 6 t ksb t ksb t f6 t r6 t kcy5, 6 scl sda0, sda1 t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t r4 t f4
55 m pd780306y, 780308y data sheet u12251ej2v1ds asck t kcy9 t kl9 t kh9 t r9 t f9 uart mode: a/d converter (t a = ?0 to +85 c, av dd = v dd = 2.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 888bit 2.7 v av ref 5.5 0.6 % 2.0 v av ref < 2.7 v 1.4 % t conv 19.1 200 m s t samp 12/f xx m s v ian av ss av ref v av ref 2.0 av dd v r ref when not operating a/d conversion 4 14 k w ai ref when operating a/d conversion note 2 2.5 5.0 ma when not operating a/d conversion note 3 0.5 1.5 ma resolution overall error note 1 conversion time sampling time analog input voltage reference voltage av ref -av ss resistance av ref current notes 1. quantization error ( 1/2 lsb) is not included. this is expressed in proportion to the full-scale value. 2. indicates current flowing to av ref pin when the cs bit of the a/d converter mode register (adm) is 1. 3. indicates current flowing to av ref pin when the cs bit of the adm is 0.
56 m pd780306y, 780308y data sheet u12251ej2v1ds t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.6 5.5 v data retention power supply v dddr = 1.6 v current i dddr subsystem clock stop and 0.1 10 m a feed-back resistor disconnected release signal set time t srel 0 m s oscillation stabilization wait t wait release by reset 2 17 /f x ms time release by interrupt note ms note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal)
57 m pd780306y, 780308y data sheet u12251ej2v1ds t rsl reset t intl t inth intp0?ntp5 interrupt request input timing reset input timing
58 m pd780306y, 780308y data sheet u12251ej2v1ds 10.0 pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = 04h pcc = 03h pcc = 02h pcc = 01h (t a = 25 ?) i dd vs v dd (f x = f xx = 5.0 mhz) 5.0 1.0 0.5 0.1 supply current i dd (ma) supply voltage v dd (v) 02345678 0.05 0.01 0.005 0.001 pcc = 00h 11. characteristics curve (reference value)
59 m pd780306y, 780308y data sheet u12251ej2v1ds 10.0 pcc = 30h halt (x1 oscillation, xt1 oscillation) halt (x1 stopped, xt1 oscillation) pcc = 04h pcc = 03h pcc = 02h pcc = 01h (t a = 25 ?) 5.0 1.0 0.5 0.1 supply current i dd (ma) supply voltage v dd (v) i dd vs v dd (f x = 5.0 mhz, f xx = 2.5 mhz) 02345678 0.05 0.01 0.005 0.001 pcc = 00h pcc = b0h
60 m pd780306y, 780308y data sheet u12251ej2v1ds 12. package drawings 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00?.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50?.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 16.00?.20 0.630?.008 g 1.00 0.039 h 0.22 0.009?.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00?.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40?.05 0.055?.002 r3 3 +7 ? +7 ? d 16.00?.20 0.630?.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10?.05 0.004?.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b remark dimensions and materials of es products are the same as those of the mass production product.
61 m pd780306y, 780308y data sheet u12251ej2v1ds remark dimensions and materials of es products are the same as those of the mass production product. 100pin plastic qfp (14x20) item millimeters inches note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p100gf-65-3ba1-3 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.6?.4 0.693?.016 f 0.8 0.031 g 0.6 0.024 h 0.30?.10 0.012 i 0.15 0.006 j 0.65 (t.p.) 0.026 (t.p.) k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 n 0.10 0.004 q 0.1?.1 0.004?.004 s 3.0 max. 0.119 max. detail of lead end r q j k m l n p g f h i m p 2.7?.1 0.106 +0.005 ?.004 80 81 50 100 1 31 30 51 b a cd s a 23.6?.4 0.929?.016 m 0.15 0.006 +0.10 ?.05 r5 ? 5 ? +0.004 ?.005 +0.009 ?.008 +0.004 ?.003
62 m pd780306y, 780308y data sheet u12251ej2v1ds 13. recommended soldering conditions the m pd780306y and 780308y should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 13-1. surface mounting type soldering conditions (1) m pd780306ygf- -3ba: 100-pin plastic qfp (14 20 mm) m pd780308ygf- -3ba: 100-pin plastic qfp (14 20 mm) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-3 number of times: three times max. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-00-3 number of times: three times max. wave soldering solder bath temperature: 260 c max., duration: 10 sec. max., number of times: ws60-00-1 once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., duration: 3 sec. max. (per device side) (2) m pd780306ygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd780308ygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14 mm) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-2 number of times: twice max. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-00-2 number of times: twice max. partial heating pin temperature: 300 c max., duration: 3 sec. max. (per device side) caution use of more than one soldering method should be avoided (except in the case of partial heating).
63 m pd780306y, 780308y data sheet u12251ej2v1ds appendix a. development tools the following development tools are available for system development using m pd780306y/780308y. also refer to (5) notes on using development tools . (1) language processing software ra78k/0 78k/0 series common assembler package cc78k/0 78k/0 series common c compiler package df780308 device file common to m pd780308 subseries (part number : m s df78064) cc78k/0-l 78k/0 series common c compiler library source file (2) prom writing tools pg-1500 prom programmer pa-78p0308gc pa-78p0308gf programmer adapters connected to pg-1500 pa-78p0308kl-t pg-1500 controller pg-1500 control program (3) debugging tools ? when in-circuit emulator ie-78k0-ns is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-70000-98-if-c interface adapter used when pc-9800 series (except notebook type) is used as host machine ie-70000-cd-if pc card and interface cable used when notebook type pc-9800 series is used as host machine ie-70000-pc-if-c interface adapter used when ibm pc/at tm compatible machine is used as host machine ie-780308-ns-em1 emulation board to emulate m pd780308 subseries np-100gc emulation probe for 100-pin plastic lqfp (gc-3eu type) np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect np-100gc and a target system board made to be mounted on 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 78k/0 series common system simulator df780308 m pd780308 subseries device file (part number: m s df78064)
64 m pd780306y, 780308y data sheet u12251ej2v1ds ? when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-b interface adapter used when pc-9800 series (except notebook type) is used as host machine ie-70000-98-if-c ie-70000-pc-if-b interface adapter used when ibm pc/at compatible machine is used as host machine ie-70000-pc-if-c ie-78000-r-sv3 interface adapter and cable used when ews is used as host machine ie-780308-ns-em1 emulation board to emulate m pd780308 subseries ie-780308-r-em ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780308-ns-em1 on ie-78001-r-a np-100gc emulation probe for 100-pin plastic lqfp (gc-3eu type) np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect np-100gc and a target system board made to be mounted on 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (gf-3ba type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780308 device file for m pd780308 subseries (part number: m s df78064) (4) real-time os rx78k/0 78k/0 series real-time os mx78k0 78k/0 series os
65 m pd780306y, 780308y data sheet u12251ej2v1ds (5) notes on using development tools ? the package name of df780308 is the df78064. ? use id78k0-ns, id78k0, and sm78k0 in combination with df780308. ? use cc78k/0 and rx78k/0 in combination with ra78k/0 and df780308. ? np-100gc and np-100gf are products of naito densei machida mfg. co., ltd. (tel (044) 822-3813). consult your nec distributor when purchasing these products. ? tgc-100sdw is a product of tokyo eletech corp. reference: daimaru kogyo ltd. electronics dept. (tel: tokyo 03-3820-7112) electronics 2nd dept. (tel: osaka 06-244-6672) ? for development tools made by third parties, refer to single-chip microcontroller development tool selection guide (u11069e) . ? the host machine corresponding to each software package is as follows: host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible machines sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news (risc) tm [news-os tm ] ra78k/0 note cc78k/0 note pg-1500 controller note id78k0-ns id78k0 sm78k0 rx78k/0 note mx78k0 note note this software is based on dos.
66 m pd780306y, 780308y data sheet u12251ej2v1ds appendix b. related documents device related documents document name document no. m pd780308, 780308y subseries users manual u11377e m pd780306, 780308 data sheet u11105e m pd780306y, 780308y data sheet this document m pd78p0308 data sheet u11776e m pd78p0308y data sheet u11832e 78k/0 series users manual (instruction) u12326e 78k/0 series application note basic (iii) u10182e document name document no. ra78k0 assembler package operation u11802e assembly language u11801e structured assembly language u11789e cc78k0 c compiler operation u11517e language u11518e pg-1500 prom programmer u11940e ie-78k0-ns in-circuit emulator u13731e ie-78k0-r-ex1 in-circuit emulator planned ie-780308-ns-em1 emulation board u13304e ie-780308-r-em emulation board u11362e ep-78064 emulation probe eeu-1469 caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. development tool related documents (users manual) (1/2)
67 m pd780306y, 780308y data sheet u12251ej2v1ds document name document no. sm78k0s, sm78k0 system sumilator ver. 2.10 or lator windows based operation u14611e sm78k series system simulator ver. 2.10 or lator external part user open planned interface specifications id78k0-ns integrated debugger ver. 2.00 or lator windows based operation u14379e id78k0-ns, id78k0s-ns integrated debugger ver. 2.20 or lator windows based operation u14910e id78k0 integrated debugger windows based reference u11539e guide u11649e embedded software related documents (users manual) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on semiconductor devices c11531e nec semiconductor device reliability and quality control c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. other related documents development tool related documents (users manual) (2/2)
68 m pd780306y, 780308y data sheet u12251ej2v1ds [memo]
69 m pd780306y, 780308y data sheet u12251ej2v1ds [memo]
70 m pd780306y, 780308y data sheet u12251ej2v1ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
71 m pd780306y, 780308y data sheet u12251ej2v1ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd780306y, 780308y some of related document may be preliminary, but is not marked as such. fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos and solaris are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of december, 1998. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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