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sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 1 revision 1.94 sn8p1700 series user?s manual general release specification sn8p1702 sn8p1704 sn8p1706 sn8p1707 sn8p1708 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improv e reliability, function or desig n. sonix does not assume any liability arising out of the application or use of any product or circuit described herei n; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and reas onable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 2 revision 1.94 amendment history version date description ver 1.90 sep. 2002 v1.90 first issue ver 1.93 feb. 2003 1. extend chip operating temperature from ?0 c ~ +70 c? to ?-20 c ~ +70 c?. 2. change the description of a dd m,a instruction from ?m m+a? to ?m a+m? 3. add adc grade table. 4. remove ?support hardware multiplier (mul)? in sn8p1702 features section. 5. change ?four internal interrupts? to ?three internal interrupts? in sn8p1704 features section. 6. change ?acc can?t be access by ?b0mov? in struction? to ?acc can?t be access by ?b0mov? instruction during the instant addressing mode?. 7. correct the description of stknh. 8. change ?special register is located at 08h~ ffh? to ?special register is located at 80h~ffh?. 9. correct the bit definit ion of inten register. 10. correct the description of ?tc0 clock frequency output? section. 11. correct the description of ?tc1 clock frequency output? section. 12. sckmd = 1 means sio is in slave mode. sckmd = 0 means sio is in master mode. 13. remove ?sio clock and spi clock are compatible?. 14. modify adb?s output data table. 15. correct an error of template code: ?b0bclr fwdrst? ?b0bset fwdrst?. 16. add a notice about oscm register access cycle. 17. sn8p1702/sn8a1702a don?t provide ?m ul, push, pop? instruction. 18. add a notice about oscm register access cycle. ver 1.94 sep. 2003 1. correct eoc description. 2. correct watchdog timer overflow time. 3. correct pop operand. 4. correct adcks table. 5. add new section about checksum calculate must avoid 04h~07h. 6. reserved last 16 word rom addresses 7. add siom table and sio rate note 8. remove register bit description 9. modify tc0m description 10. modify tc1m description 11. modify pwm description 12. modify adc frequency description 13. change code option table to chapter 2 14. add adc current consumption
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 3 revision 1.94 15. add lvd detect voltage 16. remove approval sheet. 17. remove pcb layout notice section. 18. add mask/otp relative table. 19. modify the description of intrq register. 20. modify the calculation fo rmula of sior and sio clock.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 4 revision 1.94 table of contents amendment history .............................................................................................................. 2 1 1 1 product o verview ................................................................................................... 11 general des cription ......................................................................................................... 11 features selection table ....................................................................................... 11 mask/otp r elative t able ................................................................................................. 11 adc grade table ............................................................................................................. 11 sn8p1702 f eature s.............................................................................................................. .12 sn8p1704 f eature s.............................................................................................................. .13 sn8p1707/sn8p1708 feature s ............................................................................................ 15 system block diagra m ...................................................................................................... 16 pin assign ment ................................................................................................................. .... 17 pin descri ptions ............................................................................................................... ... 22 pin circuit di agrams .......................................................................................................... 2 2 2 2 2 code option table ................................................................................................... 23 3 3 3 address space s ........................................................................................................ 24 program memory (rom)..................................................................................................... 24 overvi ew ....................................................................................................................... ...... 24 user reset vector address ( 0000h) .......................................................................... 26 interrupt vector a ddress (0008h ) ............................................................................ 26 checksum cal culation .................................................................................................. 28 general purpose progr am memory area.............................................................. 29 lookup table descript ion............................................................................................ 29 jump table d escript ion................................................................................................. 31 data memory (ram) .............................................................................................................. 33 overvi ew ....................................................................................................................... ...... 33
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 5 revision 1.94 ram bank sel ection ........................................................................................................ 35 working re gisters ............................................................................................................. 3 6 h, l re giste rs ................................................................................................................. ... 36 y, z re giste rs ................................................................................................................. ... 37 x regis ters .................................................................................................................... .... 38 r regis ters .................................................................................................................... .... 38 program flag ................................................................................................................... .... 39 carry flag ..................................................................................................................... .... 39 decimal carry flag ......................................................................................................... 39 zero flag ...................................................................................................................... ...... 39 accumul ator .................................................................................................................... .... 40 stack oper ations............................................................................................................... .41 overvi ew ....................................................................................................................... ...... 41 stack regis ters............................................................................................................... 4 2 stack operation exampl e............................................................................................. 43 program co unter ............................................................................................................... 4 4 one address skipping .................................................................................................... 45 multi-address jumping .................................................................................................. 46 4 4 4 addressing mode...................................................................................................... 47 overvi ew....................................................................................................................... .......... 47 immediate addr essing mo de ........................................................................................ 47 directly addr essing mo de .......................................................................................... 47 indirectly addr essing mo de....................................................................................... 47 to access data in ram ban k 0....................................................................................... 48 to access data in ram ban k 1....................................................................................... 48 5 5 5 system regis ter ....................................................................................................... 49 overvi ew....................................................................................................................... .......... 49 system register arrang ement (ban k 0) ..................................................................... 49 bytes of system registe r.............................................................................................. 49 bits of system register ................................................................................................. 51
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 6 revision 1.94 6 6 6 power on reset ........................................................................................................ 55 overvi ew....................................................................................................................... .......... 55 external reset descript ion........................................................................................... 56 low voltage detector (lvd) des cription .................................................................. 57 7 7 7 oscillato rs................................................................................................................ 58 overvi ew....................................................................................................................... .......... 58 clock block diagra m ..................................................................................................... 58 oscm register descript ion ......................................................................................... 59 external high-speed oscilla tor............................................................................... 60 oscillator mode code op tion .................................................................................... 60 oscillator devide by 2 code op tion......................................................................... 60 oscillator safe gua rd code op tion ....................................................................... 60 system oscillato r circui ts ........................................................................................ 61 external rc oscillator frequency meas urement .................................................................... 62 internal low-speed oscillato r .................................................................................... 63 system mode d escript ion ................................................................................................ 64 overvi ew ....................................................................................................................... ...... 64 normal mode .................................................................................................................... .64 slow mode ...................................................................................................................... .... 64 power down mode........................................................................................................... 64 system mode contro l ....................................................................................................... 65 sn8p1700 system mode block diag ram ..................................................................... 65 system mode switchi ng ................................................................................................ 66 wakeup time.................................................................................................................... ....... 67 overvi ew ....................................................................................................................... ...... 67 hardware w akeup ........................................................................................................... 67 8 8 8 timers co unters ....................................................................................................... 68 watchdog time r (wdt ) ....................................................................................................... 68 basic timer 0 (t0) ............................................................................................................. ..... 69
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 7 revision 1.94 overvi ew ....................................................................................................................... ...... 69 t0m register d escript ion ............................................................................................ 69 t0c counting register .................................................................................................. 70 t0 basic timer oper ation seq uence ......................................................................... 71 timer counter 0 (tc0 ) ......................................................................................................... 7 2 overvi ew ....................................................................................................................... ...... 72 tc0m mode registe r........................................................................................................ 73 tc0c counting registe r................................................................................................ 74 tc0r auto-loa d registe r .............................................................................................. 75 tc0 timer counter o peration seq uence ................................................................ 76 tc0 clock frequency output (b uzzer) .................................................................... 78 tc0out freque ncy tabl e .................................................................................................. 79 timer counter 1 (tc1 ) ......................................................................................................... 8 1 overvi ew ....................................................................................................................... ...... 81 tc1m mode registe r........................................................................................................ 82 tc1c counting registe r................................................................................................ 83 tc1r auto-loa d registe r .............................................................................................. 84 tc1 timer counter o peration seq uence ................................................................ 85 tc1 clock frequency output (b uzzer) .................................................................... 87 pwm function d escript ion .............................................................................................. 88 overvi ew ....................................................................................................................... ...... 88 pwm program d escript ion........................................................................................... 89 9 9 9 interrup t..................................................................................................................... 9 0 overvi ew....................................................................................................................... .......... 90 inten interrupt en able regis ter ................................................................................. 91 intrq interrupt requ est regis ter.............................................................................. 91 interrupt operation descri ption ................................................................................ 92 gie global inte rrupt oper ation ............................................................................... 92 int0 (p0.0) inte rrupt oper ation .................................................................................. 93 int1 (p0.1) inte rrupt oper ation .................................................................................. 93 int2 (p0.2) inte rrupt oper ation .................................................................................. 94 t0 interrupt operation................................................................................................. 95 tc0 interrupt operat ion .............................................................................................. 96 tc1 interrupt operat ion .............................................................................................. 97 sio interrupt operat ion............................................................................................... 98 multi-interrupt operat ion .......................................................................................... 99
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 8 revision 1.94 1 1 1 0 0 0 serial input/output t ransceiver (sio) ................................................ 101 overvi ew....................................................................................................................... ........ 101 siom mode re gister .......................................................................................................... 102 siob data buffe r............................................................................................................... .103 sior register d escription ............................................................................................ 103 sio master operatin g descript ion ............................................................................ 104 rising edge transmitte r/receiver mode.............................................................. 104 falling edge transmitte r/receiver mode ........................................................... 105 rising edge rece iver mo de ........................................................................................ 106 falling edge rece iver mo de ..................................................................................... 107 sio slave operating descript ion................................................................................ 108 rising edge transmitte r/receiver mode.............................................................. 109 falling edge transmitte r/receiver mode ........................................................... 110 rising edge rece iver mo de ........................................................................................ 111 falling edge rece iver mo de ..................................................................................... 112 sio interrupt operation descript ion....................................................................... 113 1 1 1 1 1 1 i/o port ............................................................................................................. 114 overvi ew....................................................................................................................... ........ 114 i/o port function table .................................................................................................. 115 pull-up r esister s.............................................................................................................. 116 i/o port data register .................................................................................................... 119 1 1 1 2 2 2 8-channel analog to digital converte r........................................... 121 overvi ew....................................................................................................................... ........ 121 adm regis ter................................................................................................................... .... 122 adr regis ters.................................................................................................................. ... 122 adb regis ters .................................................................................................................. ... 122 adc converting time ........................................................................................................ 124 adc ci rcuit.................................................................................................................... ....... 125
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 9 revision 1.94 1 1 1 3 3 3 7-bit digital to anal og converte r ...................................................... 126 overvi ew....................................................................................................................... ........ 126 dam regis ter................................................................................................................... .... 126 d/a converter operation .............................................................................................. 127 1 1 1 4 4 4 coding i ssue .................................................................................................. 128 template code.................................................................................................................. .. 128 chip declaration in assembl er.................................................................................... 133 program check list ......................................................................................................... 133 1 1 1 5 5 5 instruction set table ............................................................................... 134 1 1 1 6 6 6 electrical charact eristic ..................................................................... 135 absolute maximu m rating .............................................................................................. 135 standard electrical characteris tic ....................................................................... 135 sn8p1700 series (otp) ....................................................................................................... 135 1 1 1 7 7 7 package inform ation ................................................................................ 136 p-dip18 pin .................................................................................................................... ......... 136 sop18 pin ...................................................................................................................... ......... 137 ssop20 pin ..................................................................................................................... ........ 138 s-dip28 pin .................................................................................................................... ......... 139 sop28 pin ...................................................................................................................... ......... 140 qfp 44 pin..................................................................................................................... .......... 141 ssop 48 pin .................................................................................................................... ........ 142
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 10 revision 1.94 p-dip 48 pin ................................................................................................................... ......... 143 p-dip 40 pin ................................................................................................................... ......... 144
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 11 revision 1.94 1 1 1 product overview general description the sn8p1700 is a series of 8-bit micro-contro ller including sn8p1702, sn8p1704, sn8p1706, sn8p1707 and sn8p1708. this series is utilized with cmos technology fabrication and featured with low power consumption and high performance by its unique electronic structure. these chips are designed with the excellent ic structure including the large program memory otp rom, the massive data memory ram, one 8-bit basic timer (t0), two 8-bit timer counters (tc0, tc1), a watchdog timer, up to seven interrupt sources (t0, tc0, tc1, sio, int0, int1, int2), a 7-bit dac conv erter, an 8-channel adc converter with 8-bit/12-bit resolution, two channel pwm output (pwm0, pwm1), tw0 channel buzzer output (bz0, bz1) and 8-level stack buffers. besides, the user can choos e desired oscillator configurations for t he controller. there are four oscillator configurations to select for generat ing system clock, including high/low speed crystal, ceramic resonator or cost-saving rc. sn8p1700 series also includes an internal rc oscillator for slow mode controlled by programming. features selection table timer pwm wakeup chip rom ram stack t0 tc0 tc1 i/o adc dac buzzer sio pin no. package sn8p1702 1k*16 64 - v - 12 4ch - 1 - 3 dip18/sop18 sn8p1704 2k*16 128 - v v 18 5ch 1ch 2 1 8 skdip28/sop28 sn8p1706 v v v 30 8ch 1ch 2 1 9 dip40 sn8p1707 v v v 33 8ch 1ch 2 1 9 qfp44 sn8p1708 4k*16 256 8 v v v 33 8ch 1ch 2 1 9 dip48/ssop48 table 1-1. selection table of sn8p1700 mask/otp relative table mask version package form otp chip for verification assembler declaration sn8a1702a dip18/sop18/sso p20 sn8p1702 chip sn8p1702 sn8a1704a skdip28/sop28 sn8p1704 chip sn8p1704 sn8a1706a dip40 sn8p1706 chip sn8p1706 sn8a1707a qfp44 sn8p1707 chip sn8p1707 sn8a1708a dip48/ssop48 sn8p1708 chip sn8p1708 note: recommend sn8p1702a to replace sn8p1702 in new design. refer sn8p1702a datasheet for details. table 1-2. mask/otp relative table adc grade table chip parameter min max units remark resolution 12 bits no mission code 8 12 bits sn8p170x differential nonlinearity (dnl) 16 lsb 170x: 1702~1708 resolution 12 bits no mission code 10 12 bits sn8p170x-12 differential nonlinearity (dnl) 4 lsb 170x: 1702~1708 table 1-3. adc grade table
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 12 revision 1.94 sn8p1702 features ? memory configuration ? two interrupt sources otp rom size: 1k * 16 bits. one internal interrupts: tc0. ram size: 64 * 8 bits. one external interrupts: int0. ? i/o pin configuration (total 12 pins) ? an 4-channel adc with 8-bit/12-bit resolution input only: p0 bi-directional: p1, p4, p5 ? one channel pwm output. (pwm0) wakeup: p0, p1 ? one channel buzzer output. (bz0) pull-up resisters: p0, p1, p4, p5 external interrupt: p0 ? dual clock system offers three operating modes p4 pins shared with adc inputs. external high clock: rc type up to 10 mhz external high clock: crystal type up to 16 mhz ? one 8-bit timer counters. (tc0). internal low clock: rc type 16khz(3v), 32khz(5v) ? on chip watchdog timer. normal mode: both high and low clock active ? eight levels stack buffer. slow mode: low clock only sleep mode: both high and low clock stop ? 59 powerful instructions four clocks per instruction cycle all of instructions are one word length. ? package (chip form support) most of instructions are one cycle only. pdip 18 pins all rom area lookup table function (movc) sop 18 pins / ssop20 (mask type only) notice: 1. declare ?chip sn8p1702? in assembler. 2. use @set_pur macro to control pull-up resist er. refer i/o chapter for detailed information 3. call @set_pur macro at least one time to avoid sleep mode fail.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 13 revision 1.94 sn8p1704 features ? memory configuration ? six interrupt sources otp rom size: 2k * 16 bits. three internal interrupts: tc0, tc1, sio. ram size: 128 * 8 bits. three external interr upts: int0, int1, int2. ? i/o pin configuration (total 18 pins) ? a 5-channel adc with 8-bit/12-bit resolution. input only: p0 bi-directional: p1, p4, p5 ? one channel dac with 7-bit resolution. wakeup: p0, p1 pull-up resisters: p0, p1, p4, p5 ? sio function. external interrupt: p0 ? two channel pwm output. (pwm0, pwm1) p4 pins shared with adc inputs. ? two channel buzzer output. (bz0, bz1) ? two 8-bit timer counters. (tc0, tc1). ? dual clock system offers three operating modes ? on chip watchdog timer. external high clock: rc type up to 10 mhz ? eight levels stack buffer. external high clock: crystal type up to 16 mhz internal low clock: rc type 16khz(3v), 32khz(5v) ? 60 powerful instructions normal mode: both high and low clock active four clocks per instruction cy cle slow mode: low clock only all of instructions are one word length. sleep mode: both high and low clock stop most of instructions are one cycle only. all rom area lookup table function (movc) ? package (chip form support) support hardware multiplier (mul). sop 28 pins skdip 28 pins notice: 1. declare ?chip sn8p1704? in assembler. 2. use @set_pur macro to control pull-up resist er. refer i/o chapter for detailed information 3. call @set_pur macro at least one time to avoid sleep mode fail.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 14 revision 1.94 sn8p1706 features ? memory configuration ? seven interrupt sources otp rom size: 4k * 16 bits. four internal interrupts: t0, tc0, tc1, sio. ram size: 256 * 8 bits (bank 0 and bank 1). three external interr upts: int0, int1, int2. ? i/o pin configuration (total 30 pins) ? an 8-channel adc with 8-bit/12-bit resolution. input only: p0 bi-directional: p1, p2, p4, p5 ? one channel dac 7bit resolution. wakeup: p0, p1 pull-up resisters: p0, p1, p2, p4, p5 external interrupt: p0 ? sio function. p4 pins shared with adc inputs. ? two channel pwm output. (pwm0, pwm1) ? two channel buzzer output. (bz0, bz1) ? an 8-bit basic timer. (t0). ? two 8-bit timer counters. (tc0, tc1). ? dual clock system offers three operating modes ? on chip watchdog timer. external high clock: rc type up to 10 mhz ? eight levels stack buffer. external high clock: crystal type up to 16 mhz internal low clock: rc type 16khz(3v), 32khz(5v) ? 60 powerful instructions normal mode: both high and low clock active four clocks per instruction cy cle slow mode: low clock only all of instructions are one word length. sleep mode: both high and low clock stop most of instructions are one cycle only. all rom area lookup table function (movc) support hardware multiplier (mul). ? package (chip form support) p-dip 40 pins notice: 1. declare ?chip sn8p1706? in assembler. 2. use @set_pur macro to control pull-up resist er. refer i/o chapter for detailed information
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 15 revision 1.94 sn8p1707/sn8p1708 features ? memory configuration ? seven interrupt sources otp rom size: 4k * 16 bits. four internal interrupts: t0, tc0, tc1, sio. ram size: 256 * 8 bits (bank 0 and bank 1). three external interr upts: int0, int1, int2. ? i/o pin configuration (total 33 pins) ? an 8-channel adc with 8-bit/12-bit resolution. input only: p0 bi-directional: p1, p2, p4, p5 ? one channel dac with 7-bit resolution. wakeup: p0, p1 pull-up resisters: p0, p1, p2, p4, p5 external interrupt: p0 ? sio function. p4 pins shared with adc inputs. ? two channel pwm output. (pwm0, pwm1) ? two channel buzzer output. (bz0, bz1) ? an 8-bit basic timer. (t0). ? two 8-bit timer counters. (tc0, tc1). ? dual clock system offers three operating modes ? on chip watchdog timer. external high clock: rc type up to 10 mhz ? eight levels stack buffer. external high clock: crystal type up to 16 mhz internal low clock: rc type 16khz(3v), 32khz(5v) ? 60 powerful instructions normal mode: both high and low clock active four clocks per instruction cy cle slow mode: low clock only all of instructions are one word length. sleep mode: both high and low clock stop most of instructions are one cycle only. all rom area lookup table function (movc) support hardware multiplier (mul). ? package (chip form support) qpf 44 pins (sn8p1707) ssop 48 pins (sn8p1708) pdip 48 pins (sn8p1708) notice: 1. declare ?chip sn8p1707? for sn8p1707 in assembler. 2. declare ?chip sn8p1708? for sn8p1708 in assembler. 3. use @set_pur macro to control pull-up resist er. refer i/o chapter for detailed information
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 16 revision 1.94 system block diagram figure 1-1.simplified system block diagram pc ir otp rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 port 4 port 5 flags dac adc dao ain0~ain7 sio tx/rx internal clk pwm1 pwm0 pwm0/buzzer0 pwm1/buzzer1 low volt detector watch-dog timer pc ir otp rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 port 4 port 5 flags dac adc dao ain0~ain7 sio tx/rx internal clk pwm1 pwm0 pwm0/buzzer0 pwm1/buzzer1 low volt detector watch-dog timer
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 17 revision 1.94 pin assignment format description sn8p17xxy y = q > qfp p > pdip k > skdip s > sop x> ssop otp type: sn8p1702 (sop 18pin) sn8p1702 (pdip 18pin) p0.0/int0 1 u 18 vdd/vpp rst 2 17 xin p1.1 3 16 xout p1.0 4 15 p5.0 vss 5 14 p5.1 p4.3/ain3 6 13 p5.2 p4.2/ain2 7 12 p5.3 p4.1/ain1 8 11 p5.4/bz0/pwm0 p4.0/ain0 9 10 vdd sn8p1702p sn8p1702s mask type: sn8a1702a (sop 18pin) sn8a1702a (pdip 18pin) sn8a1702a (ssop 20pin) p0.0/int0 1 u 18 vdd rst 2 17 xin p1.1 3 16 xout p1.0 4 15 p5.0 vss 5 14 p5.1 p4.3/ain3 6 13 p5.2 p4.2/ain2 7 12 p5.3 p4.1/ain1 8 11 p5.4/bz0/pwm0 p4.0/ain0 9 10 vdd sn8a1702ap sn8a1702as vss 1 u 20 p1.0 vss 2 19 p1.1 p4.3/ain3 3 18 rst p4.2/ain2 4 17 p0.0/int0 p4.1/ain1 5 16 vdd p4.0/ain0 6 15 xin avrefh 7 14 xout vdd 8 13 p5.0 p5.3 9 12 p5.1 p5.2 10 11 p5.4/bz0/pwm0 sn8a1702ax only mask type support ssop20 package
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 18 revision 1.94 otp type: sn8p1704 (sop 28pin) sn8p1704 (skdip 28pin) p1.4 1 u 28 rst p1.3 2 27 p0.2/int2 vdd 3 26 p0.1/int1 p1.2 4 25 p0.0/int0 p1.1 5 24 vdd/vpp p1.0 6 23 xin vss 7 22 xout p4.4/ain4 8 21 vss p4.3/ain3 9 20 p5.0/sck p4.2/ain2 10 19 p5.1/si p4.1/ain1 11 18 p5.2/so p4.0/ain0 12 17 p5.3/bz1/pwm1 avrefh 13 16 p5.4/bz0/pwm0 vdd 14 15 dao sn8p1704k sn8p1704s mask type: sn8a1704a (sop 28pin) sn8a1704a (skdip 28pin) p1.4 1 u 28 rst p1.3 2 27 p0.2/int2 vdd 3 26 p0.1/int1 p1.2 4 25 p0.0/int0 p1.1 5 24 vdd p1.0 6 23 xin vss 7 22 xout p4.4/ain4 8 21 vss p4.3/ain3 9 20 p5.0/sck p4.2/ain2 10 19 p5.1/si p4.1/ain1 11 18 p5.2/so p4.0/ain0 12 17 p5.3/bz1/pwm1 avrefh 13 16 p5.4/bz0/pwm0 vdd 14 15 dao sn8a1704ak sn8a1704as
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 19 revision 1.94 otp type: sn8p1706 (p-dip 40pin) p1.5 1 u 40 rst p1.4 2 39 p0.2/int2 p1.3 3 38 p0.1/int1 vdd 4 37 p0.0/int0 p1.2 5 36 vdd/vpp p1.1 6 35 xin p1.0 7 34 xout p2.0 8 33 vss p2.1 9 32 p2.4 p2.2 10 31 p5.0/sck p2.3 11 30 p5.1/si vss 12 29 p5.2/so p4.7/ain7 13 28 p5.3/bz1/pwm1 p4.6/ain6 14 27 p5.4/bz0/pwm0 p4.5/ain5 15 26 p5.5 p4.4/ain4 16 25 p5.6 p4.3/ain3 17 24 p5.7 p4.2/ain2 18 23 dao p4.1/ain1 19 22 vdd p4.0/ain0 20 21 avrefh sn8p1706p mask type: sn8a1706a (p-dip 40pin) p1.5 1 u 40 rst p1.4 2 39 p0.2/int2 p1.3 3 38 p0.1/int1 vdd 4 37 p0.0/int0 p1.2 5 36 nc p1.1 6 35 xin p1.0 7 34 xout p2.0 8 33 vss p2.1 9 32 p2.4 p2.2 10 31 p5.0/sck p2.3 11 30 p5.1/si avrefl 12 29 p5.2/so p4.7/ain7 13 28 p5.3/bz1/pwm1 p4.6/ain6 14 27 p5.4/bz0/pwm0 p4.5/ain5 15 26 p5.5 p4.4/ain4 16 25 p5.6 p4.3/ain3 17 24 p5.7 p4.2/ain2 18 23 dao p4.1/ain1 19 22 vdd p4.0/ain0 20 21 avrefh sn8a1706ap for otp type (sn8p1706) compatible issue, please connect avrefl pin of mask type (sn8a1706a) to the analog ground of pcb. the voltage level of avrefl pin is the valid lowest adc input voltage. by the way, the avrefh is the valid highest adc input voltage.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 20 revision 1.94 otp type: sn8p1707 (qfp 44pin) xin xout vss p2.7 p2.6 p2.5 p2.4 p5.0/sck p5.1/si p5.2/so p5.3/bz1/pwm1 44 43 42 41 40 39 38 37 36 35 34 vpp/vdd 1 o 33 p5.4/bz0/pwm0 p0.0/int0 2 32 p5.5 p0.1/int1 3 31 p5.6 p0.2/int2 4 30 p5.7 rst 5 29 dao p1.5 6 SN8P1707Q 28 vdd p1.4 7 27 avrefh p1.3 8 26 p4.0/ain0 vdd 9 25 p4.1/ain1 p1.2 10 24 p4.2/ain2 p1.1 11 23 p4.3/ain3 12 13 14 15 16 17 18 19 20 21 22 p1.0 p2.0 p2.1 p2.2 p2.3 vss avss p4.7/ain7 p4.6/ain6 p4.5/ain5 p4.4/ain4 mask type: sn8a1707a (qfp 44pin) xin xout vss p2.7 p2.6 p2.5 p2.4 p5.0/sck p5.1/si p5.2/so p5.3/bz1/pwm1 44 43 42 41 40 39 38 37 36 35 34 nc 1 o 33 p5.4/bz0/pwm0 p0.0/int0 2 32 p5.5 p0.1/int1 3 31 p5.6 p0.2/int2 4 30 p5.7 rst 5 29 dao p1.5 6 sn8a1707aq 28 vdd p1.4 7 27 avrefh p1.3 8 26 p4.0/ain0 vdd 9 25 p4.1/ain1 p1.2 10 24 p4.2/ain2 p1.1 11 23 p4.3/ain3 12 13 14 15 16 17 18 19 20 21 22 p1.0 p2.0 p2.1 p2.2 p2.3 vss avrefl p4.7/ain7 p4.6/ain6 p4.5/ain5 p4.4/ain4 for otp type (sn8p1707) compatible issue, please connect avrefl pin of mask type (sn8a1707a) to the analog ground of pcb. the voltage level of avrefl pin is the valid lowest adc input voltage. by the way, the avrefh is the valid highest adc input voltage.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 21 revision 1.94 otp type: sn8p1708 (ssop 48pin) sn8p1708 (p-dip 48pin) p2.5 1 u 48 p2.4 p2.6 2 47 p5.0/sck p2.7 3 46 p5.1/si vss 4 45 p5.2/so vss 5 44 p5.3/bz1/pwm1 xout 6 43 vss xin 7 42 p5.4/bz0/pwm0 vpp/vdd 8 41 p5.5 p0.0/int0 9 40 p5.6 p0.1/int1 10 39 p5.7 p0.2/int2 11 38 dao rst 12 37 vdd p1.5 13 36 avdd p1.4 14 35 avrefh p1.3 15 34 p4.0/ain0 vdd 16 33 p4.1/ain1 vss 17 32 p4.2/ain2 p1.2 18 31 p4.3/ain3 p1.1 19 30 p4.4/ain4 p1.0 20 29 p4.5/ain5 p2.0 21 28 p4.6/ain6 p2.1 22 27 p4.7/ain7 p2.2 23 26 avss p2.3 24 25 vss sn8p1708p sn8p1708x mask type: sn8a1708a (ssop 48pin) sn8a1708a (p-dip 48pin) p2.5 1 u 48 p2.4 p2.6 2 47 p5.0/sck p2.7 3 46 p5.1/si vss 4 45 p5.2/so vss 5 44 p5.3/bz1/pwm1 xout 6 43 vss xin 7 42 p5.4/bz0/pwm0 nc 8 41 p5.5 p0.0/int0 9 40 p5.6 p0.1/int1 10 39 p5.7 p0.2/int2 11 38 dao rst 12 37 vdd p1.5 13 36 avdd p1.4 14 35 avrefh p1.3 15 34 p4.0/ain0 vdd 16 33 p4.1/ain1 vss 17 32 p4.2/ain2 p1.2 18 31 p4.3/ain3 p1.1 19 30 p4.4/ain4 p1.0 20 29 p4.5/ain5 p2.0 21 28 p4.6/ain6 p2.1 22 27 p4.7/ain7 p2.2 23 26 avrefl p2.3 24 25 vss sn8a1708ap sn8a1708ax for otp type (sn8p1708) compatible issue, please connect avrefl pin of mask type (sn8a1708a) to the analog ground of pcb. the voltage level of avrefl pin is the valid lowest adc input voltage. by the way, the avrefh is the valid highest adc input voltage.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 22 revision 1.94 pin descriptions pin name type description vdd, vss p power supply input pins for digital circuit. avdd, avss p power supply input pins for analog circuit. vpp/vdd p otp rom programming pin. connect to vdd in normal operation. rst i system reset input pin. schmitt trigger stru cture, active ?low?, normal stay to ?high?. xin, xout i, o external oscillator pins. rc mode from xin. p0.0 / int0 i port 0.0 and shared with int0 trigger pin (schmitt trigger) / built-in pull-up resisters. p0.1 / int1 i port 0.1 and shared with int1 trigger pin (schmitt trigger) / built-in pull-up resisters. p0.2 / int2 i port 0.2 and shared with int2 trigger pin (schmitt trigger) / built-in pull-up resisters. p1.0 ~ p1.5 i/o port 1.0~port 1.5 bi-d irection pins / built-in pull-up resisters. p2.0 ~ p2.7 i/o port 2.0~port 2.7 bi-d irection pins / built-in pull-up resisters. p4.0 ~ p4.7 i/o port 4.0~port 4.7 bi-d irection pins / built-in pull-up resisters. p5.0 / sck i/o port 5.0 bi-direction pin and sio? s clock input/output / bu ilt-in pull-up resisters. p5.1 / si i/o port 5.1 bi-direction pin and sio?s data input / built-in pull-up resisters. p5.2 / so i/o port 5.2 bi-direction pin and sio?s data output / built-in pull-up resisters. p5.3 / bz1 / pwm1 i/o port 5.3 bi-direction pin, tc1 2 signal output pin for buzzer or pwm1 output pin. built-in pull-up resisters. p5.4 / bz0 / pwm0 i/o port 5.4 bi-direction pin, tc0 2 signal output pin for buzzer or pwm0 output pin. built-in pull-up resisters. p5.5 ~ p5.7 i/o port 5.5~port 5.7 bi-d irection pins / built-in pull-up resisters. avrefh i a/d converter high analog reference voltage. ain0 ~ ain7 i analog signal i nput pins for adc converter. dao o 5-bit dac signal output pin. table 1-4. sn8p1700 pin description pin circuit diagrams figure 1-2. pin circuit diagram note: all of the latch output circuits are push-pull structures. port0 structure pur pin int. bus pur pnm pin int. bus pnm latch port1, 2, 4, 5 structure pnm port0 structure pur pin int. bus pur pnm pin int. bus pnm latch port1, 2, 4, 5 structure pnm
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 23 revision 1.94 2 2 2 code option table code option content function description rc low cost rc for external high clock oscillator 32k x?tal low frequency, power saving crystal (e.g. 32.768k) for external high clock oscillator 12m x?tal high speed crystal /resonator (e.g . 12m) for external high clock oscillator high_clk 4m x?tal standard crystal /resonator (e.g. 3.58m) for external high clock oscillator enable external high clock divided by two, fosc = high clock / 2 high_clk / 2 disable fosc = high clock enable enable oscillator safe guard function osg disable disable oscillator safe guard function enable enable watch dog function watch_dog disable disable watch dog function enable enable the low voltage detect lvd disable disable the low voltage detect enable enable rom code security function security disable disable rom code security function table 2-1. code option table of sn8p1700 notice : the osg working voltage and the frequency relation table: the min. working voltage will be affect by the osg option. it is very important to check this code option. turn on the osg will improve the emi performance. but the side effect is an increase in the working voltage. osc. freq.(mhz) osg on (volt) osg off(volt) 1 2.4 2.2 2 2.4 2.2 4 2.5 2.2 6 2.5 2.3 8 2.6 2.4 10 2.8 2.6 12 3 2.7 16 3.5 2.8 18 3.7 3 20 4.1 3.2 notice : the system working frequency is only warranty under 16mhz.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 24 revision 1.94 3 3 3 address spaces program memory (rom) overview rom maps for sn8p1700 devices provide otp memory t hat programmable by user. sn8p1702 has 1k x 16-bit program memory, sn8p1704 has 2k x 16-bit program memory and sn8p1706, sn8p1707 and sn8p1708 have 4k x 16-bit program memory. the sn8p1700 program memory is able to fetch instructions through 12-bit wide pc (program counter) and can look up rom data by using rom code registers (r, x, y, z). in standard configuration, the device?s 4,096 x 16-bit program memory has four areas: 1-word reset vector addresses 1-word interrupt vector addresses 5-words reserved area 4k words (sn8p1706, sn8p1707, sn8p1708) 2k words (sn8p1704) 1k words (sn8p1702) all of the program memory is parti tioned into three coding areas. the 1 st area is located from 00h to 03h(the reset vector area), the 2 nd area is a reserved area 04h ~07h, the 3 rd area is for the interrupt vector and the user code area from 0008h to 0ffeh. the address 08h is the interrupt enter address point. rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 03feh general purpose area end of user program 03ffh reserved figure 3-1. rom address structure (sn8p1702)
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 25 revision 1.94 rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 07feh general purpose area end of user program 07ffh reserved figure 3-2. rom address structure (sn8p1704) rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 0ffeh general purpose area end of user program 0fffh reserved figure 3-3. rom address struct ure (sn8p1706/sn8p1707/sn8p1708)
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 26 revision 1.94 user reset vector address (0000h) a 1-word vector address area is used to execute system re set. after power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. the following example shows the way to define t he reset vector in the program memory. example: after power on reset, external reset active or reset by watchdog timer overflow. chip sn8p1708 org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 10h start: ; 0010h, the head of user program. . ; user program . . . endp ; end of program interrupt vector address (0008h) a 1-word vector address area is used to execute interrupt request. if any interrupt servic e is executed, the program counter (pc) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. users have to define the interrupt vector. the following exam ple shows the way to define the interrupt vector in the program memory. example 1: this demo program includes interrupt ser vice routine and the user program is behind the interrupt service routine. chip sn8p1708 org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 8 ; interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push 80h ~ 87h system registers . . . pop ; pop 80h ~ 87h system registers b0xch a, accbuf reti ; end of interrupt service routine start: ; the head of user program. . ; user program . . . jmp start ; end of user program endp ; end of program
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 27 revision 1.94 example 2: the demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. chip sn8p1708 org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 08 jmp my_irq ; 0008h, jump to interrupt service routine address org 10h start: ; 0010h, the head of user program. . ; user program . . . jmp start ; end of user program my_irq: ;the head of interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push 80h ~ 87h system registers . . . pop ; pop 80h ~ 87h system registers b0xch a, accbuf reti ; end of interrupt service routine endp ; end of program remark: it is easy to get the rules of sonix program from demo programs given above. these points are as following. 1. the address 0000h is a ?jmp? instruction to make the program go to general-purpose rom area. the 0004h~0007h are reserved. users have to skip 0004h~0007h addresses. it is very important and necessary. 2. the interrupt service starts from 0008h. users can put the whole interrupt service routine from 0008h (example1) or to put a ?jmp? instruction in 0008h then place the interrupt service routine in other general-purpose rom area (example2) to get more modularized coding style.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 28 revision 1.94 checksum calculation the rom addresses 0004h~0007h and last address are re served area. user should avoid these addresses (0004h~0007h and last address) when calculate the checksum value. example: the demo program shows how to avoid 0004h~0007h when calculated checksum from 00h to the end of user?s code mov a,#end_user_code$l b0mov end_addr1,a ;save low end address to end_addr1 mov a,#end_user_code$ m b0mov end_addr2,a ;save middle end address to end_addr2 clr y ;set y to ooh clr z ;set z to 00h @@: call yz_check ;call function of check yz value movc ; b0bset fc ;clear c glag add data1,a ;add a to data1 mov a,r adc data2,a ;add r to data2 jmp end_check ;check if the yz address = the end of code aaa: incms z ;z=z+1 jmp @b ;if z!= 00h calculate to next address jmp y_add_1 ;if z=00h increase y end_check: mov a,end_addr1 cmprs a,z ;check if z = low end address jmp aaa ;if not jump to checksum calculate mov a,end_addr2 cmprs a,y ;if yes, check if y = middle end address jmp aaa ;if not jump to checksum calculate jmp checksum_end ;if yes checksum calculated is done. yz_check: ;check if yz=0004h mov a,#04h cmprs a,z ;check if z=04h ret ;if not return to checksum calculate mov a,#00h cmprs a,y ;if yes, check if y=00h ret ;if not return to checksum calculate incms z ;if yes, increase 4 to z incms z incms z incms z ret ;set yz=0008h then return y_add_1: incms y ;increase y nop jmp @b ;jump to checksum calculate checksum_end: ???. ???. end_user_code: ;label of program end
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 29 revision 1.94 general purpose program memory area the 4089 1 -word at rom locations 0010h~0ffeh are used as general-purpose memory. the area is stored instruction?s op-code and look-up table data. the sn8p1700 includes jump table function by using program counter (pc) and look-up table function by usi ng rom code registers (r, x, y, z). the boundary of program memory is separated by the high-by te program counter (pch) every 100h. in jump table function and look-up table function, the program count er can?t leap over the boundary by program counter automatically. users need to modify the pch value to ?pch+1? as the pcl overflow (from 0ffh to 000h). notice: 1:the sn8p1702?s rom size is about 1k words and the sn8p1704?s rom size is about 2k words. lookup table description in the rom?s data lookup function, the x register is pointed to the highest 8-bi t, y register to the middle 8-bit and z register to the lowest 8-bit data of rom address. after mo vc instruction is executed, the low-byte data of rom then will be stored in acc and high-byte data stored in r register. example: to look up the rom data located ?table1?. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; ; increment the index address for next address incms z ; z+1 jmp @f ; not overflow incms y ; z overflow (ffh 00), y=y+1 nop ; not overflow ; @@: movc ; to lookup data, r = 51h, acc = 05h. . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ? causion: the y register can't increase automatically if z register cross boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z register overflow, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatically. note: because the program counter (pc) is only 12-bit, the x register is useless in the application. users can omit ?b0mov x, #table1$h?. sonix ice support more larger program memory addressing capability. so make sure x register is ?0? to avoid unpredicted error in loop-up table operation. example: inc_yz macro inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 30 revision 1.94 the other coding style of loop-up table is to add y or z index register by accumulator. be careful if carry happen. refer following example for detailed information: example: increase y and z register by b0add/add instruction b0mov y, #table1$m ; to set lookup table?s middle address. b0mov z, #table1$l ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 . . . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ?
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 31 revision 1.94 jump table description the jump table operation is one of multi-address jumping function. add low-byte pr ogram counter (pcl) and acc value to get one new pcl. the new program counter (pc) point s to a series jump instructions as a listing table. the way is easy to make a multi-stage program. when carry flag occurs after executing of ?add pcl, a?, it will not affect pch regi ster. users have to check if the jump table leaps over the rom page boundary or the listing file gener ated by sonix assembly software. if the jump table leaps over the rom page boundary (e.g. from xxffh to xx00h), move the jump table to the top of next program memory page (xx00h). here one page mean 256 words. example : if pc = 0323h (pch = 03h pcl = 23h) org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. when execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error because pch doesn't increase one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the program counter (pc) will point to a wrong address 0x0000 and crash system operation. it is important to check whether the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put the jump table at the start of rom boundary (e.g. 0100h). example: if ?jump table? crosses over rom boundary will cause errors. rom address . . . . . . 0x00fd b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 jump table cross boundary here 0x0101 jmp a3point ; acc = 3 . . . . sonix provides a macro for safe jump table function. this macro will check the rom boundary and move the jump table to the right position automatically . the side effect of this macro is maybe wasting some rom size. notice the maximum jmp table number for this macro is limited under 254. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 32 revision 1.94 example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is from 00fdh to 0101h, the ?@jmp_ a? macro will make the jump table to start from 0100h.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 33 revision 1.94 data memory (ram) overview the sn8p1700 has internally built-in the data memory up to 256 bytes for storing the general-purpose data. for sn8p1702 48 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area for sn8p1704 128 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area for sn8p1706/sn8p1707/sn8p1708 128 * 8-bit general purpose area in bank 0 128 * 8-bit general purpose area in bank 1 128 * 8-bit system special register area the memory is separated into bank 0 and bank 1. the user can program ram bank selection bits of rbank register to access all data in any of the two ram banks. the bank 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. the bank 1, using the first 128-byte location assigned as general-purpose area, and others useless. ram location 000h 000h~03fh of bank 0 = to store general- ? purpose data (64 bytes). ? ? ? ? 03fh general purpose area 080h 080h~0ffh of bank 0 = to store system ? registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area figure 3-4. ram location of sn8p1702
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 34 revision 1.94 ram location 000h 000h~03fh of bank 0 = to store general- ? purpose data (128 bytes). ? ? ? ? 07fh general purpose area 080h 080h~0ffh of bank 0 = to store system ? registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area figure 3-5. ram location of sn8p1704 ram location 000h 000h~07fh of bank 0 = to store general- ? purpose data (128 bytes). ? ? ? ? 07fh general purpose area 080h 080h~0ffh of bank 0 = to store system ? registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area 100h bank 1 = to store general-purpose data. ? ? ? ? 17eh general purpose area bank 1 17fh end of bank 1 area bank 1 has 128 bytes ram. figure 3-6 ram location of sn8p1706/sn8p1707/sn8p1708 note: the undefined locations of system register ar ea are logic ?high? after executing read instruction ?mov a, m?.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 35 revision 1.94 ram bank selection the rbank is a 1-bit register located at 87h in ram bank 0. the user can access ram dat a by using this register pointing to working ram bank for acc to read/write ram data. rbank initial value = xxxx xxx0 087h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbank 0 0 0 0 0 0 0 rbnks0 - - - - - - - r/w rbnksn: ram bank selecting control bit. 0 = bank 0, 1 = bank 1. example: ram bank selecting. ; bank 0 clr rbank ; b0bclr frbnks0 . ; bank 1 mov a, #1 ; b0bset frbnks0 b0mov rbank, a . note: ?b0mov? instruction can access the ram of bank 0 in other bank situation directly. example: access ram bank 0 in ram bank 1. ; bank 1 b0bset rbnks0 ; get into ram bank 1 b0mov a, buf0 ; read buf0 data. buf0 is in ram bank0. mov buf1, a ; write buf0 data to buf1. buf1 is in ram bank1. . . . mov a, buf1 ; read buf1(bank1) data and store in acc. b0mov buf0, a ; write acc data to buf0(bank0). under bank 1 situation, using ?b0mov? instruction is an easy way to access ram bank 0 data. user can make a habit to read/write system register (0087h~ 00ffh). then user can access system registers without switching ram bank. example: to access the system regi sters in bank 1 situation. ; bank 1 b0bset rbnks0 ; switch the ram bank into bank 1 . . mov a, #0ffh ; set all pins of p1 to be logic high. b0mov p1, a ; operate the bank 0 specia l register by the b0mov instruction . ; while the ram system in the bank1. b0mov a, p0 ; read p0 data in the b ank 0 and store into buf1 in the bank 1. mov buf1, a ;
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 36 revision 1.94 working registers the locations 80h to 85h of ram bank 0 in data memory stores the specially defined registers su ch as register h, l, r, x, y, z, respectively shown in the following table. thes e registers can use as the general purpose of working buffer and be used to access rom?s and ram?s data. for instance, a ll of the rom?s table can be looked-up with r, x, y and z registers. the data of ram memory can be indi rectly accessed with h, l, y and z registers. 80h 81h 82h 83h 84h 85h ram l h r z y x r/w r/w r/w r/w r/w r/w h, l registers the h and l are 8-bit register with two major functions. one is to use the registers as working register. the other is to use the registers as data pointer to access ram?s data. the @hl that is dat a point_0 index buffer located at address e6h in ram bank_0. it employs h and l registers to addressi ng ram location in order to read/write data through acc. the lower 4-bit of h register is pointed to ram bank number and l register is pointed to ram address number, respectively. the higher 4-bit data of h register is truncated in ram indirectly access mode. h initial value = 0000 0000 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w r/w r/w r/w r/w r/w r/w r/w l initial value = 0000 0000 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w r/w r/w r/w r/w r/w r/w r/w example: if want to read a data from ram address 20h of bank_0, it can use indirectly addressing mode to access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc example: clear general-purpose data memo ry area of bank 0 using @hl register. clr h ; h = 0, bank 0 mov a, #07fh b0mov l, a ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l ? 1, if l = 0, finish the routine jmp clr_hl_buf ; not zero clr @hl end_clr: ; end of clear general purpose data memory area of bank 0 . . . .
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 37 revision 1.94 y, z registers the y and z registers are the 8-bit buffers. there are three ma jor functions of these regist ers. first, y and z registers can be used as working registers. second, these two regist ers can be used as data pointers for @yz register. third, the registers can be address rom location in order to look-up rom data. y initial value = 0000 0000 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w r/w r/w r/w r/w r/w r/w r/w z initial value = 0000 0000 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w r/w r/w r/w r/w r/w r/w r/w the @yz that is data point_1 index bu ffer located at address e7h in ram bank 0. it employs y and z registers to addressing ram location in order to read/write data through a cc. the lower 4-bit of y register is pointed to ram bank number and z register is pointed to ram address number, respectively. the higher 4-bit data of y register is truncated in ram indirectly access mode. example: if want to read a data from ram address 25h of bank 1, it can use indirectly addressing mode to access data as following. b0mov y, #01h ; to set ram bank 1 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: clear general-purpose data memo ry area of bank 1 using @yz register. mov a, #1 b0mov y, a ; y = 1, bank 1 mov a, #07fh b0mov z, a ; y = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; y ? 1, if y= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 . note: please consult the ?look-up table description? about y, z register look-up table application.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 38 revision 1.94 x registers there are two major functions of the x register. first, x register can be used as working registers. second, the x registers must be clear in order to look-up the ro m data. the sn8p1700?s program counter only has 12-bit. in look-up table function, the users can omit x register. x initial value = 0000 0000 085h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w r/w r/w r/w r/w r/w r/w r/w note: please consult the ?look-up table description? about x register look-up table application. r registers there are two major functions of the r register. first, r register can be used as worki ng registers. second, the r registers can be store high-byte data of look-up rom data. after movc instruct ion executed, the high-byte data of a rom address will be stored in r register and the low-byte data stored in acc. r initial value = 0000 0000 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r/w r/w r/w r/w r/w r/w r/w note: please consult the ?look-up table description? about r register look-up table application.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 39 revision 1.94 program flag the pflag includes carry flag (c), decimal carry flag (dc) and zero flag (z). if the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to pflag register. pflag initial value = xxxx x000 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag - - - - - c dc z - - - - - r/w r/w r/w carry flag c = 1: if executed arithmetic addition wi th occurring carry signal or executed ar ithmetic subtracti on without borrowing signal or executed rotation instruct ion with shifting out logic ?1?. c = 0: if executed arithmetic addition wi thout occurring carry signal or executed arithmetic s ubtraction with borrowing signal or executed rotation instruct ion with shifting out logic ?0?. decimal carry flag dc = 1: if executed arithmetic addition wi th occurring carry signal from low nibbl e or executed arithmetic subtraction without borrow signal from high nibble. dc = 0: if executed arithmetic addition wit hout occurring carry signal from low nibbl e or executed arithmetic subtraction with borrow signal from high nibble. zero flag z = 1: after operation, the content of acc is zero. z = 0: after operation, the c ontent of acc is not zero.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 40 revision 1.94 accumulator the acc is an 8-bits data register responsible for tr ansferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be a ccess by ?b0mov? instruction during the instant addressing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a . . ; write a immediate data into acc mov a, #0fh . . ; write acc data from buf data memory mov a, buf . . the push and pop instructions don?t store acc value as any interrupt service execut ed. acc must be exchanged to another data memory defined by users. thus, once interrupt occurs, these data must be stored in the data memory based on the user?s program as follows. example: acc and working registers protection. accbuf equ 00h ; accbuf is acc data buffer in bank 0. int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push. . ; push instruction . . . . pop ; pop instruction b0xch a, accbuf ; re-load acc reti ; exit interrupt service vector notice: to save and re-load acc data must be used ?b0xch? instruction, or the plage value maybe modified by acc.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 41 revision 1.94 stack operations overview the stack buffer of sn8p1700 has 8-level high area and each leve l is 12-bits length. this buffer is designed to save and restore program counter?s (pc) data when interrupt serv ice is executed. the stkp register is a pointer designed to point active level in order to save or restore data fr om stack buffer for kernel circuit. the stknh and stknl are the 12-bit stack buffers to store program counter (pc) data. figure 3-7 stack-save and stack-restore operation stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 call / interrupt ret / reti stkp pch pcl stkp stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 stkp - 1 stkp - 1 stkp + 1 call / interrupt ret / reti stkp stkp pch pcl pch pch pcl pcl stkp stkp
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 42 revision 1.94 stack registers the stack pointer (stkp) is a 4-bit register to store t he address used to access the stack buffer, 12-bits data memory (stknh and stknl) set aside for tem porary storage of stack addresses. the two stack operations are writing to the top of the stack (stack-save) and r eading (stack-restore) from the top of stack. stack-save operation decrement s the stkp and the stack-resotre operat ion increments one time. that makes the stkp always points to the top address of stack buffer and writes the last progr am counter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction executed or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. stkp (stack pointer) initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w stkpbn: stack pointer. (n = 0 ~ 3) gie: global interrupt control bit. 0 = disable, 1 = enabl e. more detail information is in interrupt chapter. example: stack pointer (stkp) reset routine. mov a, #00001111b b0mov stkp, a stkn (stack buffer) initial value = xxxx xxxx xxxx xxxx, stkn = stknh + stknl (n = 7 ~ 0) 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - snpc11 snpc10 snpc9 snpc8 - - - - r/w r/w r/w r/w 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 r/w r/w r/w r/w r/w r/w r/w r/w stknh: store pch data as interrupt or call executing. the n expressed 0 ~7. stknl: store pcl data as interrupt or call executing. the n expressed 0 ~7.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 43 revision 1.94 stack operation example the two kinds of stack-save operations to reference the stack pointer (stkp) and write the program counter contents (pc) into the stack buffer are call instruction and interr upt service. under each condition, the stkp is decremented and points to the next available stack lo cation. the stack buffer stores the pr ogram counter about the op-code address. the stack-save operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 1 stk0h stk0l - 1 1 1 1 0 stk1h stk1l - 2 1 1 0 1 stk2h stk2l - 3 1 1 0 0 stk3h stk3l - 4 1 0 1 1 stk4h stk4l - 5 1 0 1 0 stk5h stk5l - 6 1 0 0 1 stk6h stk6l - 7 1 0 0 0 stk7h stk7l - >8 - - - - - - stack overflow table 3-1. stkp, stknh and stknl relative of stack-save operation there is a stack-restore operation corresponding each push oper ation to restore the program counter (pc). the reti instruction is for interrupt service rout ine. the ret instruction is for call in struction. when a st ack-restore operation occurs, the stkp is incremented and points to the next free sta ck location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack-restore operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 7 1 0 0 0 stk7h stk7l - 6 1 0 0 1 stk6h stk6l - 5 1 0 1 0 stk5h stk5l - 4 1 0 1 1 stk4h stk4l - 3 1 1 0 0 stk3h stk3l - 2 1 1 0 1 stk2h stk2l - 1 1 1 1 0 stk1h stk1l - 0 1 1 1 1 stk0h stk0l - table 3-2. stkp, stknh and stknl re lative of stack-restore operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 44 revision 1.94 program counter the program counter (pc) is a 12-bit bi nary counter separated into the high-byte 4 bits and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by executing call or jmp inst ruction. when jmp or call instruction is executed, t he destination address will be inserted to bit 0 ~ bit 11. pc initial value = xxxx 0000 0000 0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl pch initial value = xxxx 0000 0cfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pch - - - - pc11 pc10 pc9 pc8 - - - - r/w r/w r/w r/w pcl initial value = 0000 0000 0ceh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcl pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w r/w r/w r/w r/w r/w r/w r/w
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 45 revision 1.94 one address skipping there are 9 instructions (cmprs, i ncs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is matched, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is matched, the pc will add 2 steps to skip next instruction. b0bts1 fc ; skip next instruction, if carry_flag = 1 jmp c0step ; else jump to c0step. . c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; skip next instruction, if zero flag = 0. jmp c1step ; else jump to c1step. . c1step: nop if the acc is equal to the immediate data or memory , the pc will add 2 steps to skip next instruction. cmprs a, #12h ; skip next instruction, if acc = 12h. jmp c0step ; else jump to c0step. . c0step: nop if the result after increasing or decreasing by 1 is 0xff or 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 46 revision 1.94 multi-address jumping users can jump round multi-address by either jmp instruct ion or add m, a instruction (m = pcl) to activate multi-address jumping function. if carry signal occurs after ex ecution of add pcl, a, the carry signal will not affect pch register. example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h . . . . ; pc = 0328h . . mov a, #00h b0mov pcl, a ; jump to address 0300h example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point . . ;
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 47 revision 1.94 4 4 4 addressing mode overview the sn8p1700 provides three addressing modes to access ra m data, including immediate addressing mode, directly addressing mode and indirectly address mode. the main purpos e of the three different modes is described in the following: immediate addressing mode the immediate addressing mode uses an immediate data to set up the location (mov a, #i, b0mov m,#i) in acc or specific ram. immediate addressing mode mov a, #12h ; to set an immediate data 12h into acc directly addressing mode the directly addressing mode uses address number to a ccess memory location (mov a,12h, mov 12h,a). directly addressing mode b0mov a, 12h ; to get a content of location 12h of bank 0 and save in acc indirectly addressing mode the indirectly addressing mode is to set up an address in dat a pointer registers (y/z) and uses mov instruction to read/write data between acc and @yz regi ster (mov a,@yz, mov @yz,a). example: indirectly addressing mode with @yz register clr y ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. mov a, #01h b0mov y, a ; to set y = 1 for accessing ram bank 1. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. mov a, #0fh b0mov y, a ; to set y = 15 for accessing ram bank 15. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location 012h ; into acc.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 48 revision 1.94 to access data in ram bank 0 in the ram bank 0, this area memory can be read/written by these three access methods. example 1: to use ram bank0 dedicate in struction (such as b0xxx instruction). b0mov a, 12h ; to move content fr om location 12h of ram bank 0 to acc example 2: to use directly addr essing mode (through rbank register). b0mov rbank, #00h ; to set ram bank = 0 mov a, 12h ; to move content from location 12h of ram bank 0 to acc example 3: to use indirectly addressing mode with @yz register. clr y ; to clear y register for accessing ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. to access data in ram bank 1 in the ram bank 1, this area memory can be read/written by these two access methods. example 1: to use directly addr essing mode (through rbank register). b0mov rbank, #01h ; to set ram bank = 1 mov a, 12h ; to move content from location 12h of ram bank 0 to acc example 2: to use indirectly addressing mode with @yz register. mov a, #01h b0mov y, a ; to set y = 1 for accessing ram bank 1. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 49 revision 1.94 5 5 5 system register overview the system special register is located at 80h~ffh. the main purpose of system registers is to control the peripheral hardware of the chip. using system registers can control i/o ports, sio, adc, pwm, timers and counters by programming. the memory map provides an easy and quick re ference source for writing application program. to accessing these system regist ers is controlled by the select memory bank (rbank = 0) or the bank 0 read/write instruction (b0mov, b0bset, b0bclr?). system register arrangement (bank 0) bytes of system register sn8p1702 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag - - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - - - b - adm adb adr - - - - - - - - - - - - c p1w p1m - - p4m p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 - - p4 p5 - - - - tc0m tc0c - - - stkp e - - - - - - - @yz - - - - - - - - f stk7 stk7 stk6 stk6 stk5 stk5 stk4 stk4 stk3 stk3 st k2 stk2 stk1 stk1 stk0 stk0 table 5-1. system regist er arrangement of sn8p1702 sn8p1704 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag - - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - - - b dam adm adb adr siom sior siob - - - - - - - - - c p1w p1m - - p4m p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 - - p4 p5 - - - - tc0m tc0c tc1m tc1c tc1r stkp e - - - - - - - @yz - - - - - - - - f stk7 stk7 stk6 stk6 stk5 stk5 stk4 stk4 stk3 stk3 st k2 stk2 stk1 stk1 stk0 stk0 table 5-2. system regist er arrangement of sn8p1704
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 50 revision 1.94 sn8p1706/sn8p1707/sn8p1708 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y x pflag rbank - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - - - b dam adm adb adr siom sior siob - - - - - - - - - c p1w p1m p2m - p4m p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 p2 - p4 p5 - - t0m t0c tc0m tc0c tc1m tc1c tc1r stkp e - - - - - - @hl @yz - - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h table 5-3. system register a rrangement of sn8p1706/sn8p1707/sn8p1708 description l, h = working & @hl addressing register. r = working register and rom lookup data buffer. x = working and rom address register. y, z = working, @yz and rom addressing register. pflag = rom page and special flag register. rbank = ram bank select register. dam = dac?s mode register. adm = adc?s mode register. adb = adc?s data buffer. adr = adc?s resolution selects register. siom = sio mode control register. sior = sio?s clock reload buffer. siob = sio?s data buffer. p1w = port 1 wakeup register. pnm = port n input/output mode register. pn = port n data buffer. intrq = interrupts? request register. inten = interrupts? enable register. oscm = oscillator mode register. pch, pcl = program counter. t0m = timer 0 mode register. tc0m = timer/counter 0 mode register. t0c = timer 0 counting register. tc0c = timer/counter 0 counting register. tc1m = timer/counter 1 mode register. tc0r = timer/counter 0 auto-reload data buffer. tc1c = timer/counter 1 counting register. tc1r = timer/counter 1 auto-reload data buffer. stkp = stack pointer buffer. stk0~stk7 = stack 0 ~ stack 7 buffer. @hl = ram hl indirect addressing index pointer. @yz = ram yz indirect addressing index pointer. note: a). all of register names had been declared in sonix 8-bit mcu assembler. b). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. c). it will get logic ?h? data, when use instruction to check empty location. d). the low nibble of adr register is read only. e). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? in structions only support ?r/w? registers.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 51 revision 1.94 bits of system register sn8p1702 system register table address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h - - - - - c dc z r/w pflag 0b1h adenb ads eoc gchs - 0 chs1 chs0 r/w adm mode register 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb data buffer 0b3h - adcks adlen 0 adb3 adb2 adb1 adb0 r/w adr register 0c0h 0 0 0 0 0 0 p11w p10w w p1w wakeup register 0c1h 0 0 0 0 0 0 p11m p10m r/w p1m i/o direction 0c4h 0 0 0 0 p43m p42m p41m p40m r/w p4m i/o direction 0c5h 0 0 0 p54m p53m p52m p51m p50m r/w p5m i/o direction 0c8h 0 0 tc0irq 0 0 0 0 p00irq r/w intrq 0c9h 0 0 tc0ien 0 0 0 0 p00ien r/w inten 0cah 0 wdrst wdrate 0 cpum0 clkmd stphx 0 r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - - pc10 pc9 pc8 r/w pch 0d0h - - - - - - - p00 r p0 data buffer 0d1h - - - - - - p11 p10 r/w p1 data buffer 0d4h - - - - p43 p42 p41 p40 r/w p4 data buffer 0d5h - - - p54 p53 p52 p51 p50 r/w p5 data buffer 0dah tc0enb tc0rate2 tc0r ate1 tc0rate0 0 aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - - - s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - - s6pc10 s6pc9 s6pc8 r/w stk6h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - - s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - - s0pc10 s0pc9 s0pc8 r/w stk0h table 5-4. bit system register table of sn8p1702 note: a). to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register name had been declared in sonix 8-bit mcu assembler. c). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructions only support ?r/w? registers.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 52 revision 1.94 sn8p1704 system register table address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h - - - - - c dc z r/w pflag 0b0h daenb dab6 dab5 dab4 dab3 d ab2 dab1 dab0 r/w dam data register 0b1h adenb ads eoc gchs - chs2 chs1 chs0 r/w adm mode register 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb data buffer 0b3h - adcks adlen 0 adb3 adb2 adb1 adb0 r/w adr register 0b4h senb start srate1 srate0 0 sckmd sedge txrx r/w siom mode register 0b5h sior7 sior6 sior5 sior4 sior 3 sior2 sior1 sior0 w sior reload buffer 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob data buffer 0c0h 0 0 0 p14w p13w p12w p11w p10w w p1w wakeup register 0c2h 0 0 0 0 0 0 0 0 r/w p2m i/o direction 0c1h 0 0 0 p14m p13m p12m p11m p10m r/w p1m i/o direction 0c4h 0 0 0 p44m p43m p42m p41m p40m r/w p4m i/o direction 0c5h 0 0 0 p54m p53m p52m p51m p50m r/w p5m i/o direction 0c8h 0 tc1irq tc0irq 0 sioir q p02irq p01irq p00irq r/w intrq 0c9h 0 tc1ien tc0ien 0 sioien p02ien p01ien p00ien r/w inten 0cah 0 wdrst wdrate 0 cpum0 clkmd stphx 0 r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - p02 p01 p00 r p0 data buffer 0d1h - - - p14 p13 p12 p11 p10 r/w p1 data buffer 0d4h - - - p44 p43 p42 p41 p40 r/w p4 data buffer 0d5h - - - p54 p53 p52 p51 p50 r/w p5 data buffer 0dah tc0enb tc0rate2 tc0r ate1 tc0rate0 0 aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rat e1 tc1rate0 0 aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - - s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h table 5-5. bit system register table of sn8p1704 note: a). to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register name had been declared in sonix 8-bit mcu assembler. c). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? in structions only support ?r/w? registers. e). for detail description please refer file of ?system register quick reference table?
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 53 revision 1.94 sn8p1706 system register table address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h - - - - - c dc z r/w pflag 087h - - - - - - - rbnks0 r/w rbank 0b0h daenb dab6 dab5 dab4 dab3 d ab2 dab1 dab0 r/w dam data register 0b1h adenb ads eoc gchs - chs2 chs1 chs0 r/w adm mode register 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb data buffer 0b3h - adcks adlen 0 adb3 adb2 adb1 adb0 r/w adr register 0b4h senb start srate1 srate0 0 sckmd sedge txrx r/w siom mode register 0b5h sior7 sior6 sior5 sior4 sior3 s ior2 sior1 sior0 w sior reload buffer 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob data buffer 0c0h 0 0 p15w p14w p13w p12w p11w p10w w p1w wakeup register 0c1h 0 0 p15m p14m p13m p12m p11m p10m r/w p1m i/o direction 0c2h 0 0 0 p24m p23m p22m p21m p20m r/w p2m i/o direction 0c4h p47m p46m p45m p44m p43m p 42m p41m p40m r/w p4m i/o direction 0c5h p57m p56m p55m p54m p53m p 52m p51m p50m r/w p5m i/o direction 0c8h 0 tc1irq tc0irq t0irq s ioirq p02irq p01irq p00irq r/w intrq 0c9h 0 tc1ien tc0ien t0ien sioien p02ien p01ien p00ien r/w inten 0cah 0 wdrst wdrate 0 cpum0 clkmd stphx 0 r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - p02 p01 p00 r p0 data buffer 0d1h - - p15 p14 p13 p12 p11 p10 r/w p1 data buffer 0d2h - - - p24 p23 p22 p21 p20 r/w p2 data buffer 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 data buffer 0d5h p57 p56 p55 p54 p53 p52 p51 p50 r/w p5 data buffer 0d8h t0enb t0rate2 t0rate1 t0rate0 0 0 0 0 r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0r ate1 tc0rate0 0 aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rat e1 tc1rate0 0 aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl index pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - - s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h table 5-6. bit system register table of sn8p1706 note: a). to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register name had been declared in sonix 8-bit mcu assembler. c). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? in structions only support ?r/w? registers. e). for detail description please refer file of ?system register quick reference table?
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 54 revision 1.94 sn8p1707/ sn8p1708 system register table address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h - - - - - c dc z r/w pflag 087h - - - - - - - rbnks0 r/w rbank 0b0h daenb dab6 dab5 dab4 dab3 d ab2 dab1 dab0 r/w dam data register 0b1h adenb ads eoc gchs - chs2 chs1 chs0 r/w adm mode register 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb data buffer 0b3h - adcks adlen 0 adb3 adb2 adb1 adb0 r/w adr register 0b4h senb start srate1 srate0 0 sckmd sedge txrx r/w siom mode register 0b5h sior7 sior6 sior5 sior4 sior3 s ior2 sior1 sior0 w sior reload buffer 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob data buffer 0c0h 0 0 p15w p14w p13w p12w p11w p10w w p1w wakeup register 0c1h 0 0 p15m p14m p13m p12m p11m p10m r/w p1m i/o direction 0c2h p27m p26m p25m p24m p23m p 22m p21m p20m r/w p2m i/o direction 0c4h p47m p46m p45m p44m p43m p 42m p41m p40m r/w p4m i/o direction 0c5h p57m p56m p55m p54m p53m p 52m p51m p50m r/w p5m i/o direction 0c8h 0 tc1irq tc0irq t0irq s ioirq p02irq p01irq p00irq r/w intrq 0c9h 0 tc1ien tc0ien t0ien sioien p02ien p01ien p00ien r/w inten 0cah 0 wdrst wdrate 0 cpum0 clkmd stphx 0 r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - p02 p01 p00 r p0 data buffer 0d1h - - p15 p14 p13 p12 p11 p10 r/w p1 data buffer 0d2h p27 p26 p25 p24 p23 p22 p21 p20 r/w p2 data buffer 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 data buffer 0d5h p57 p56 p55 p54 p53 p52 p51 p50 r/w p5 data buffer 0d8h t0enb t0rate2 t0rate1 t0rate0 0 0 0 0 r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0r ate1 tc0rate0 0 aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rat e1 tc1rate0 0 aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl index pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - - s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h table 5-7. bit system regist er table of sn8p1707/ sn8p1708 note: a). to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register name had been declared in sonix 8-bit mcu assembler. c). one-bit name had been declared in sonix 8-bit mcu assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? in structions only support ?r/w? registers. e). for detail description please refer file of ?system register quick reference table?
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 55 revision 1.94 6 6 6 power on reset overview sn8p1700 provides two system resets. one is external rese t and the other is low voltage detector (lvd). the external reset is a simple rc circuit connecting to the reset pin. the low voltage detector (lvd) is built in internal circuit. when one of the reset devices occurs, the system will reset and the system registers become initial value. the timing diagram is as following. vdd external reset internal reset signal end of lvd reset lvd end of external reset lvd detect level external reset detect level figure 6-1 power on reset timing diagram notice : the working current of the lvd is about 100ua.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 56 revision 1.94 external reset description the external reset is a low level active device. the rese t pin receives the low voltage and resets the system. when the voltage detects high level, it stops rese tting the system. users can use an exter nal reset circuit to control system operation. it is necessary that the vdd must be stable. external reset vdd internal reset signal external reset detect level end of external reset system reset figure 6-2 external reset timing diagram users must to be sure the vdd stable earlie r than external reset (figure 5-2) or t he external reset will fail. the external reset circuit is a simple rc circuit as following. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf figure 6-3. external reset circuit
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 57 revision 1.94 in worse-power condition as brown out reset. the reset pi n may keep high level but the vdd is low voltage. that makes the system reset fail and chip error. to connect a di ode from reset pin to vdd is a good solution. the circuit can force the capacitor to rel ease electric charge and drop the voltage, and solve the error. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf diode figure 6-4. external reset circuit with diode low voltage detector (lvd) description the lvd is a low voltage detector. it detects vdd level and reset the system as t he vdd lower than the desired voltage. the detect level is 2.4v. if the vdd lower than 2.4v, the system resets. the lvd f unction is controlled by code option. users can turn on it for special application like wors e power condition. lvd work with external reset function. they are or active. system reset lvd detect level end of lvd reset vdd lvd figure 6-5. lvd timing diagram the lvd can protect system to work well under brownout reset. but it is a high consumptive circuit. in 3v condition, the lvd consumes about 100ua. it is a very la rge consumption for battery system. so the lvd supports ac system well. notice: lvd is selected by code option.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 58 revision 1.94 7 7 7 oscillators overview the sn8p1700 highly performs the dual clock micro-cont roller system. the dual clocks are high-speed clock and low-speed clock. the high-speed clock frequency is supplied through the external oscillator circuit. the low-speed clock frequency is supplied through on-chip rc oscillator circuit. the external high-speed clock and the internal low-speed clo ck can be system clock (fosc) . and the system clock is divided by 4 to be the instruction cycle (fcpu). fcpu = fosc / 4 the system clock is required by the following peripheral modules: basic timer (t0) timer counter 0 (tc0) timer counter 1 (tc1) watchdog timer serial i/o interface (sio) ad converter pwm output (pwm0, pwm1) buzzer output (tc0out, tc1out) clock block diagram fl cpum0 lxosc. fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 2 osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) fl cpum0 lxosc. fl cpum0 lxosc. fcpu fosc/4 cpum0 fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 4 divided by 4 clkmd divided by 2 divided by 2 osg osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) figure 7-1. clock block diagram hxosc: external high-speed clock. lxosc: internal low-speed clock. osg: oscillator safe guard.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 59 revision 1.94 oscm register description the oscm register is a oscillator control register. it can control oscillator select, system mode, watchdog timer clock source and rate. oscm initial value = 000x 000x 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm 0 wdrst wdrate 0 cpum0 clkmd stphx 0 - r/w r/w - r/w r/w r/w - stphx: eternal high-speed oscillator control bit. 0 = free run, 1 = stop. this bit just only controls external high-speed oscillator. if stphx=1, the internal low-speed rc oscillator is still running. clkmd: system high/low speed mode select bi t. 0 = normal (dual) mode, 1 = slow mode. cpum0: cpu operating mode control bit. 0 = normal, 1 = sleep (power down) mode to turn off both high/low clock. notice: the bit 7 of oscm register must be ?0?, or the system will be error.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 60 revision 1.94 external high-speed oscillator sn8p1700 can be operated in four different oscillator modes. there are external rc oscillator modes, high crystal/resonator mode (12m code opt ion), standard crystal/resonator mode (4m code option) and low crystal mode (32k code option). for different application, the users c an select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset. example: stop external high-speed oscillator. b0bset fstphx ; to stop external high-speed oscillator only. b0bset fcpum0 ; to stop external hi gh-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). oscillator mode code option sn8p1700 has four oscillator modes for different applicat ions. these modes are 4m, 12m, 32k and rc. the main purpose is to support different oscilla tor types and frequencies. high-speed crystal needs more current but the low one doesn?t. for crystals, there are three steps to select. if the oscillator is rc type, to select ?rc? and the system will divide the frequency by 2 automatically. user can select o scillator mode from code option table before compiling. the table is as follow. code option oscillator mode remark 00 rc mode output the fcpu square wave from xout pin. 01 32k 32768hz 10 12m 12mhz ~ 16mhz 11 4m 3.58mhz oscillator devide by 2 code option sn8p1700 has an external clock divide by 2 function. it is a code option called ?high_clk / 2?. if ?high_clk / 2? is enabled, the external clock frequency is divi ded by 8 for the fcpu. fcpu is equal to fo sc/8. if ?high_clk / 2? is disabled, the external clock frequency is divided by 4 for the fcpu. the fcpu is equal to fosc/4. note: in rc mode, ?high_clk / 2? is always enabled. oscillator safe guard code option sn8p1700 builds in an oscillator safe guard (osg) to make oscillator more stable. it is a low-pass filter circuit and stops high frequency noise into system from external oscillato r circuit. this function makes system to work better under ac noisy conditions.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 61 revision 1.94 system oscillator circuits mcu xin vdd xout vss crystal 20pf 20pf figure 7-2. crystal/ceramic oscillator mcu xin vdd vss xout c r figure 7-3. rc oscillator xin vdd mcu vss xout external clock input figure 7-4. external clock input note1: the vdd and vss of external oscillator circuit must be from the micro-controller. don?t connect them from the neighbor power terminal. note2: the external clock input mode can select rc type oscillator or crystal type oscillator of the code option and input the external clock into xin pin. note3: in rc type oscillator code option situation, the external clock?s frequency is divided by 2. note4: the power and ground of external oscillator circ uit must be connected from the micro-controller?s vdd and vss. it is necessary to step up the performance of the whole system.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 62 revision 1.94 external rc oscillator frequency measurement there are two ways to get the fosc frequency of external rc oscillator. one measures the xout output waveform. under external rc oscillator mode, the xout outputs t he square waveform whose frequency is fcpu. the other measures the external rc frequency by in struction cycle (fcpu). the external rc frequency is the fcpu multiplied by 4. we can get the fosc frequency of external rc from the fcpu frequency. the sub-routi ne to get fcpu frequency of external oscillator is as the following. example: fcpu instruction cy cle of external oscillator b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p1.0 ; output fcpu toggle signal in low-speed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 63 revision 1.94 internal low-speed oscillator the internal low-speed oscillator is built in the micro-cont roller. the low-speed clock?s source is a rc type oscillator circuit. the low-speed clock can supplies clock for system clock, timer counter, watchdog timer, sio clock source and so on. example: stop internal low-speed oscillator. b0bset fcpum0 ; to stop external hi gh-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). note: the internal low-speed clock can?t be turned o ff individually. it is controlled by cpum0 bit of oscm register. the low-speed oscillator uses rc type oscillator circuit. t he frequency is affected by the voltage and temperature of the system. in common condition, the frequency of the rc oscillator is about 16khz at 3v and 32khz at 5v. the relative between the rc frequency and voltage is as following. internal rc vs. vdd 7.329 8.663 11.998 15.333 18.668 22.003 25.338 28.673 32.008 35.343 38.678 0 5 10 15 20 25 30 35 40 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 vdd (volts) fintrc (khz) figure 7-5. internal rc vs. vdd diagram example: to measure the internal rc frequency is by in struction cycle (fcpu). the internal rc frequency is the fcpu multiplied by 4. so we can get the fosc frequency of internal rc from the fcpu frequency. b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. b0bset fclkmd ; switch the system cl ock to internal low-speed clock mode. @@: b0bset p1.0 ; output fcpu toggle signal in low-speed clock mode. b0bclr p1.0 ; measure t he fcpu frequency by oscilloscope. jmp @b
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 64 revision 1.94 system mode description overview the chip is featured with low power consumption by switching around three different modes as following. high-speed mode low-speed mode power-down mode (sleep mode) in actual application, the user can adjust the chip?s controller to work in these three modes by using oscm register. at the high-speed mode, the instruction cy cle (fcpu) is fosc/4. at the low- speed mode and 3v, the fcpu is 16khz/4. normal mode in normal mode, the system clock source is external high-speed clock. after power on, the system works under normal mode. the instruction cycle is fosc/4. when the external high-speed oscillator is 3.58mhz, the instruction cycle is 3.58mhz/4 = 895khz. all software and hardware are executed and working. in normal mode, system can get into power down mode and slow mode. slow mode in slow mode, the system clock source is internal low-speed rc clock. to set cl kmd = 1, the system switch to slow mode. in slow mode, the system works as normal mode but the slower clock. t he system in slow mode can get into normal mode and power down mode. to set stphx = 1 to stop the external high-speed oscillator, and then the system consumes less power. power down mode the power down mode is also called sleep mode. the chip stops working as sleeping status. the power consumption is very less almost to zero. the power down mode is usually applied to low power consuming system as battery power productions. to set cupm0 = 1, the system gets into power down mode. the external high-speed and low-speed oscillators are turned off. the system c an be waked up by p0, p1 trigger signal.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 65 revision 1.94 system mode control sn8p1700 system mode block diagram normal mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum0 = 01 clkmd = 0 clkmd = 1 normal mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum0 = 01 clkmd = 0 clkmd = 1 figure 7-6. sn8p1700 system mode block diagram operating mode description mode normal slow power down (sleep) remark hx osc. running by stphx stop lx osc. running running stop cpu instruction execut ing executing stop t0 timer *active *active inactive tc0 timer *active *active inactive tc1 timer *active *active inactive * active by programm. watchdog timer active active inactive internal interrupt all active all active all inactive external interrupt all active all active all inactive wakeup source - - p0, p1, reset table 7-1. operating mode description
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 66 revision 1.94 system mode switching switch normal/slow mode to power down (sleep) mode. cpum0 = 1 b0bset fcpum0 ; set the system into power down mode. during the sleep, only the wakeup pin and reset c an wakeup the system back to the normal mode. switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high-speed oscillator for power saving. switch slow mode to normal mode if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. b0mov z, #27 ; if vdd = 5v, internal rc=32khz (typical) will delay @@: decms z ; 0.125ms x 81 = 10.125m s for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 67 revision 1.94 wakeup time overview the external high-speed oscillator needs a delay time from stopping to operating. the del ay is very necessary and makes the oscillator to work stably. some conditions duri ng system operating, the exter nal high-speed oscillator often runs and stops. under these condition, the delay time for ex ternal high-speed oscillator restart is called wakeup time. there are two conditions need wakeup time. one is power dow n mode to normal mode. the other one is slow mode to normal mode. for the first case, sn8p1700 provides 2048 oscilla tor clocks to be the wakeup time. but in the last case, users need to make the wakeup time by themselves. hardware wakeup when the system is in power down mode (sleep mode), t he external high-speed oscillator stops. for wakeup into normal, sn8p1700 provides 2048 external high-speed oscilla tor clocks to be the wakeup time for warming up the oscillator circuit. after the wakeup time, the system goes in to the normal mode. the value of the wakeup time is as following. the wakeup time = 1/fosc * 2048 (sec) example: in power down mode (sleep mode), the system is waked up by p0 or p1 trigger signal. after the wakeup time, the system goes into normal mode. the wakeup time of p0, p1 wakeup function is as following. the wakeup time = 1/fosc * 2048 = 0.57 ms (fosc = 3.58mhz) the wakeup time = 1/fosc * 2048 = 62.5 ms (fosc=32768hz) under power down mode (sleep mode), ther e are only i/o ports with wakeup function making the system to return normal mode. the port 0 and port 1 have wakeup function. port 0?s wakeup function always enables. the port 1 controls by the p1w register. p1w initial value = xx00 0000 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w 0 0 p15w p14w p13w p12w p11w p10w - - w w w w w w p10w~p15w: port 1 wakeup function control bits. 0 = none wakeup function, 1 = enable each pin of port 1 wakeup function. note: for sn8p1702 the p1w register only obtains p 10w and p11w. for sn8p1704 the p1w register only obtain p10w~p14w.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 68 revision 1.94 8 8 8 timers counters watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program get into the unknown status by noise interferenc e, wdt?s overflow signal will reset this chip and restart operation. the instruction that clear the watch-dog timer (b0bset fw drst) should be executed at proper points in a program within a given period. if an instruct ion that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. in order to generate different output timings, the user can control watchdog timer by modifying wdrate control bits of oscm register. the watchdog timer will be disabled at green and power down modes. oscm initial value = 0000 000x 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm 0 wdrst wdrate - cpum0 clkmd stphx - - r/w r/w - r/w r/w r/w - notice: the bit 7 must be ?0?, or the system will be error. wdrate: watchdog timer rate select bit. 0 =14 th , 1 = 8 th . wdrst : watch dog timer reset bit. 0 = non reset, 1 = clear the watchdog timer?s counter. watchdog timer overflow time wdrate external high-speed oscillator 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 / ( fcpu 2 14 16 ) = 32 s, fosc=32768hz 1 / ( fcpu 2 8 16 ) = 4.5 ms, fosc=3.58mhz 1 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz figure 8-1. watchdog timer overflow time table note: the watch dog timer can be enabled or disabled by the code option. example: an operation of watch-dog timer is as followi ng. to clear the watchdog timer?s counter in the top of the main routine of the program. main: b0bset fwdrst ; clear the watchdog timer?s counter. . . call sub1 call sub2 . . . . . . jmp main
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 69 revision 1.94 basic timer 0 (t0) overview the basic timer (t0) is an 8-bit binary up counter. it uses t0m register to se lect t0c?s input clock for counting a precision time. if the t0 timer has occur an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 basic timer is as following. 8-bit programmable timer: generates interrupts at specific time intervals based on the selected clock frequency. figure 8-2. basic timer t0 block diagram t0m register description the t0m is the basic timer mode register which is a 8-bi t read/write register and only us ed the high nibble. by loading different value into the t0m register, users can modify t he basic timer clock dynamically as program executing. eight rates for t0 timer can be selected by t0rate0 ~ t0 rate2 bits. the range is from fcpu/2 to fcpu/256. the t0m initial value is zero and the rate is fcpu/256. the bit7 of t0m called t0enb is the control bit to start t0 timer. the combination of these bits is to determine the t0 timer clock frequency and the intervals. t0m initial value = 0000 xxxx 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 0 0 0 0 r/w r/w r/w r/w - - - - t0enb: t0 timer control bit. 0 = disable, 1 = enable. t0rate2~t0rate0: the t0 timer?s cl ock source select bits. 000 = fcpu/256, 001 = fcpu/128, ? , 110 = fcpu/4, 111 = fcpu/2. t0enb t0c 8-bit binary counter t0 time out pre_load internal data bus 2 (8-t0rate) f cpu t0enb t0c 8-bit binary counter t0 time out pre_load internal data bus 2 (8-t0rate) f cpu
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 70 revision 1.94 t0c counting register t0c is an 8-bit counter register for the basic timer (t0). t0 c must be reset whenever the t0enb is set ?1? to start the basic timer. t0c is incremented by one with every clock pulse which frequency is determined by t0rate0 ~ t0rate2. when t0c has incremented to ?0ffh?, it will be cleared to ?00h? in next clock and an overflow generated. under t0 interrupt service request (t0ien) enable condition, the t0 interrupt request flag will be set ?1? and the system executes the interrupt service routine. the t0c has no auto reload function. afte r t0c overflow, the t0c is continuing counting. users need to reset t0c value to get a accurate time. t0c initial value = xxxx xxxx 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w r/w r/w r/w r/w r/w r/w r/w high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms figure 8-3. the timing table of basic timer t0. the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example : to set 10ms interval time for t0 interrupt at 3.58mhz high-speed mode. t0c value (74h) = 256 - (10ms * fcpu/64) t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 71 revision 1.94 t0 basic timer operation sequence the t0 basic timer?s sequence of operation can be following. set the t0c initial value to setup the interval time. set the t0enb to be ?1? to enable t0 basic timer. t0c is incremented by one with each clock pulse which frequency is corresponding to t0m selection. t0c overflow when t0c from ffh to 00h. when t0c overflow occur, the t0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the t0c value and resume the t0 timer operation. example: setup the t0m and t0c. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to set t0 interval = 10 ms) b0bset ft0ien ; to enable t0 interrupt service b0bclr ft0irq ; to cl ear t0 interrupt request b0bset ft0enb ; to enable t0 timer example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a,#74h ; reload t0c b0mov t0c,a . . ; t0 interrupt service routine . . jmp exit_int ; end of t0 interrupt se rvice routine and exit interrupt vector . . . . exit_int: pop ; pop b0xch a, accbuf ;restore acc value reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 72 revision 1.94 timer counter 0 (tc0) overview the timer counter 0 (tc0) is used to generate an interrupt request when a specified time interval has elapsed. tc0 has a auto re-loadable counter that consis ts of two parts: an 8-bit reload regist er (tc0r) into which you write the counter reference value, and an 8-bit counter register (tc0 c) whose value is automatic ally incremented by counter logic. figure 8-4. timer count tc0 block diagram the main purposes of the tc0 ti mer counter is as following. 8-bit programmable timer: generates interrupts at specific time intervals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequenc ies to the bz0 pin (p5.4). pwm function: pwm output can be generated by the pwm1out bit and output to pwm0out pin (p5.4). p5.4 tc0r reload data buffer tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload ? 2 tc0out internal p5.4 i/o circuit cpum0 s r compare pwm0out pwm buzzer 2 (8-tc0rate) f cpu p5.4 tc0r reload data buffer tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload ? 2 tc0out internal p5.4 i/o circuit cpum0 s r compare pwm0out pwm buzzer 2 (8-tc0rate) f cpu
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 73 revision 1.94 tc0m mode register the tc0m is the timer counter mode register, which is an 8- bit read/write register. by loading different value into the tc0m register, users can modify the timer counter clock frequency dynamically when program executing. eight rates for tc0 timer can be selected by tc0rate0 ~ tc0rate2 bits. the range is from fcpu/2 to fcpu/256. the tc0m initial value is zero and the rate is fcpu/256. the bit7 of tc0m called tc0enb is the c ontrol bit to start tc0 timer. the combination of these bits is to determi ne the tc0 timer clock frequency and the intervals. tc0m initial value = 0000 0000 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0r ate0 0 aload0 tc0out pwm0out r/w r/w r/w r/ w - r/w r/w r/w tc0enb: tc0 counter/bz0/pwm0out enable bit. 0 = disable, 1 = enable. tc0rate2~tc0rate0: tc0 internal clock select bi ts. 000 = fcpu/256, 001 = fcpu/128, ? , 110 = fcpu/4, 111 = fcpu/2. aload0: tc0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. tc0out: tc0 time-out toggle signal output control bit. 0 = to disable tc0 signal output and to enable p5.4?s i/o function, 1 = to enable tc0?s signal output and to disable p5 .4?s i/o function. (auto-disable the pwm0out function.) pwm0out: tc0?s pwm output control bit. 0 = to dis able the pwm output, 1 = to enable the pwm output (the tc0out control bit must = 0 ) note: bit3 must set to 0.. note: the ice s8kc do not support the pwm0out and tc0out function. the pwm0out and tc0out must use the s8kd ice (or later) to verify the function.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 74 revision 1.94 tc0c counting register tc0c is an 8-bit counter register for the timer counter (tc0 ). tc0c must be reset whenever the tc0enb is set ?1? to start the timer counter. tc0c is incremented by one wi th a clock pulse which the frequency is determined by tc0rate0 ~ tc0rate2. when tc0c has incremented to ?0ffh ?, it is will be cleared to ?00h? in next clock and an overflow is generated. under tc0 interrupt service reques t (tc0ien) enable condition, the tc0 interrupt request flag will be set ?1? and the system executes the interrupt service routine. tc0c initial value = xxxx xxxx 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w r/w r/w r/w r/w r/w r/w r/w high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms table 8-1. the timing table of timer count tc0 the equation of tc0c initial value is as following. tc0c initial value = 256 - (tc0 interrupt interval time * input clock) example: to set 10ms interval time for tc0 interrupt at 3.58mhz high-speed mode. tc0c value (74h) = 256 - (10ms * fcpu/64) tc0c initial value = 256 - (tc0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 75 revision 1.94 tc0r auto-load register tc0r is an 8-bit register for the tc0 auto-reload functi on. tc0r?s value applies to tc0out and pwm0out functions.. under tc0out application, users must enable and set the tc0r register. the main purpose of tc0r is as following. store the auto-reload value and set into tc0c when the tc0c overflow. (aload0 = 1). store the duty value of pwm0out function. tc0r initial value = xxxx xxxx 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w w w w w w w w the equation of tc0r initial value is like tc0c as following. tc0r initial value = 256 - (tc0 interrupt interval time * input clock) note: the tc0r is write-only register can?t be process by incms, decms instructions.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 76 revision 1.94 tc0 timer counter operation sequence the tc0 timer counter?s sequence of operation can be following. set the tc0c initial value to setup the interval time. set the tc0enb to be ?1? to enable tc0 timer counter. tc0c is incremented by one with each clock pulse which frequency is corresponding to t0m selection. tc0c overflow when tc 0c from ffh to 00h. when tc0c overflow occur, the tc0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc0c value and resume the tc0 timer operation. example: setup the tc0m and tc0c without auto-reload function. b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ;(to set tc0 interval = 10 ms) b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer example: setup the tc0m and tc0c with auto-reload function. b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ; (to set tc0 interval = 10 ms) b0mov tc0r,a ; to set tc0r auto-reload register b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer b0bset aload0 ; to enable tc0 auto-reload function.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 77 revision 1.94 example: tc0 interrupt service routine without auto-reload function. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a,#74h ; reload tc0c b0mov tc0c,a . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc0 interrupt service routine with auto-reload. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 78 revision 1.94 tc0 clock frequency output (buzzer) tc0 timer counter provides a frequency out put function. by setting the tc0 clo ck frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-dis able. the tc0 output signal di vides by 2. the tc0 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-5. the tc0out pulse frequency example: setup tc0out output from tc0 to tc0out (p5.4). the external high-speed clock is 4mhz. the tc0out frequency is 1khz. because the tc0out signal is divided by 2, set the tc0 clock to 2khz. the tc0 clock source is from external oscillator clock. t0c rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and disable p5.4 i/o function b0bset faload0 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 79 revision 1.94 tc0out frequency table fosc = 4mhz, tc0 rate = fcpu/8 tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.2441 56 0.3125 112 0.4340 168 0.7102 224 1.9531 1 0.2451 57 0.3141 113 0.4371 169 0.7184 225 2.0161 2 0.2461 58 0.3157 114 0.4401 170 0.7267 226 2.0833 3 0.2470 59 0.3173 115 0.4433 171 0.7353 227 2.1552 4 0.2480 60 0.3189 116 0.4464 172 0.7440 228 2.2321 5 0.2490 61 0.3205 117 0.4496 173 0.7530 229 2.3148 6 0.2500 62 0.3222 118 0.4529 174 0.7622 230 2.4038 7 0.2510 63 0.3238 119 0.4562 175 0.7716 231 2.5000 8 0.2520 64 0.3255 120 0.4596 176 0.7813 232 2.6042 9 0.2530 65 0.3272 121 0.4630 177 0.7911 233 2.7174 10 0.2541 66 0.3289 122 0.4664 178 0.8013 234 2.8409 11 0.2551 67 0.3307 123 0.4699 179 0.8117 235 2.9762 12 0.2561 68 0.3324 124 0.4735 180 0.8224 236 3.1250 13 0.2572 69 0.3342 125 0.4771 181 0.8333 237 3.2895 14 0.2583 70 0.3360 126 0.4808 182 0.8446 238 3.4722 15 0.2593 71 0.3378 127 0.4845 183 0.8562 239 3.6765 16 0.2604 72 0.3397 128 0.4883 184 0.8681 240 3.9063 17 0.2615 73 0.3415 129 0.4921 185 0.8803 241 4.1667 18 0.2626 74 0.3434 130 0.4960 186 0.8929 242 4.4643 19 0.2637 75 0.3453 131 0.5000 187 0.9058 243 4.8077 20 0.2648 76 0.3472 132 0.5040 188 0.9191 244 5.2083 21 0.2660 77 0.3492 133 0.5081 189 0.9328 245 5.6818 22 0.2671 78 0.3511 134 0.5123 190 0.9470 246 6.2500 23 0.2682 79 0.3531 135 0.5165 191 0.9615 247 6.9444 24 0.2694 80 0.3551 136 0.5208 192 0.9766 248 7.8125 25 0.2706 81 0.3571 137 0.5252 193 0.9921 249 8.9286 26 0.2717 82 0.3592 138 0.5297 194 1.0081 250 10.4167 27 0.2729 83 0.3613 139 0.5342 195 1.0246 251 12.5000 28 0.2741 84 0.3634 140 0.5388 196 1.0417 252 15.6250 29 0.2753 85 0.3655 141 0.5435 197 1.0593 253 20.8333 30 0.2765 86 0.3676 142 0.5482 198 1.0776 254 31.2500 31 0.2778 87 0.3698 143 0.5531 199 1.0965 255 62.5000 32 0.2790 88 0.3720 144 0.5580 200 1.1161 33 0.2803 89 0.3743 145 0.5631 201 1.1364 34 0.2815 90 0.3765 146 0.5682 202 1.1574 35 0.2828 91 0.3788 147 0.5734 203 1.1792 36 0.2841 92 0.3811 148 0.5787 204 1.2019 37 0.2854 93 0.3834 149 0.5841 205 1.2255 38 0.2867 94 0.3858 150 0.5896 206 1.2500 39 0.2880 95 0.3882 151 0.5952 207 1.2755 40 0.2894 96 0.3906 152 0.6010 208 1.3021 41 0.2907 97 0.3931 153 0.6068 209 1.3298 42 0.2921 98 0.3956 154 0.6127 210 1.3587 43 0.2934 99 0.3981 155 0.6188 211 1.3889 44 0.2948 100 0.4006 156 0.6250 212 1.4205 45 0.2962 101 0.4032 157 0.6313 213 1.4535 46 0.2976 102 0.4058 158 0.6378 214 1.4881 47 0.2990 103 0.4085 159 0.6443 215 1.5244 48 0.3005 104 0.4112 160 0.6510 216 1.5625 49 0.3019 105 0.4139 161 0.6579 217 1.6026 50 0.3034 106 0.4167 162 0.6649 218 1.6447 51 0.3049 107 0.4195 163 0.6720 219 1.6892 52 0.3064 108 0.4223 164 0.6793 220 1.7361 53 0.3079 109 0.4252 165 0.6868 221 1.7857 54 0.3094 110 0.4281 166 0.6944 222 1.8382 55 0.3109 111 0.4310 167 0.7022 223 1.8939 table 8-2. tc0out frequency table for fosc = 4mhz, tc0 rate = fcpu/8
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 80 revision 1.94 fosc = 16mhz, tc0 rate = fcpu/8 tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.9766 56 1.2500 112 1.7361 168 2.8409 224 7.8125 1 0.9804 57 1.2563 113 1.7483 169 2.8736 225 8.0645 2 0.9843 58 1.2626 114 1.7606 170 2.9070 226 8.3333 3 0.9881 59 1.2690 115 1.7730 171 2.9412 227 8.6207 4 0.9921 60 1.2755 116 1.7857 172 2.9762 228 8.9286 5 0.9960 61 1.2821 117 1.7986 173 3.0120 229 9.2593 6 1.0000 62 1.2887 118 1.8116 174 3.0488 230 9.6154 7 1.0040 63 1.2953 119 1.8248 175 3.0864 231 10.0000 8 1.0081 64 1.3021 120 1.8382 176 3.1250 232 10.4167 9 1.0121 65 1.3089 121 1.8519 177 3.1646 233 10.8696 10 1.0163 66 1.3158 122 1.8657 178 3.2051 234 11.3636 11 1.0204 67 1.3228 123 1.8797 179 3.2468 235 11.9048 12 1.0246 68 1.3298 124 1.8939 180 3.2895 236 12.5000 13 1.0288 69 1.3369 125 1.9084 181 3.3333 237 13.1579 14 1.0331 70 1.3441 126 1.9231 182 3.3784 238 13.8889 15 1.0373 71 1.3514 127 1.9380 183 3.4247 239 14.7059 16 1.0417 72 1.3587 128 1.9531 184 3.4722 240 15.6250 17 1.0460 73 1.3661 129 1.9685 185 3.5211 241 16.6667 18 1.0504 74 1.3736 130 1.9841 186 3.5714 242 17.8571 19 1.0549 75 1.3812 131 2.0000 187 3.6232 243 19.2308 20 1.0593 76 1.3889 132 2.0161 188 3.6765 244 20.8333 21 1.0638 77 1.3966 133 2.0325 189 3.7313 245 22.7273 22 1.0684 78 1.4045 134 2.0492 190 3.7879 246 25.0000 23 1.0730 79 1.4124 135 2.0661 191 3.8462 247 27.7778 24 1.0776 80 1.4205 136 2.0833 192 3.9063 248 31.2500 25 1.0823 81 1.4286 137 2.1008 193 3.9683 249 35.7143 26 1.0870 82 1.4368 138 2.1186 194 4.0323 250 41.6667 27 1.0917 83 1.4451 139 2.1368 195 4.0984 251 50.0000 28 1.0965 84 1.4535 140 2.1552 196 4.1667 252 62.5000 29 1.1013 85 1.4620 141 2.1739 197 4.2373 253 83.3333 30 1.1062 86 1.4706 142 2.1930 198 4.3103 254 125.0000 31 1.1111 87 1.4793 143 2.2124 199 4.3860 255 250.0000 32 1.1161 88 1.4881 144 2.2321 200 4.4643 33 1.1211 89 1.4970 145 2.2523 201 4.5455 34 1.1261 90 1.5060 146 2.2727 202 4.6296 35 1.1312 91 1.5152 147 2.2936 203 4.7170 36 1.1364 92 1.5244 148 2.3148 204 4.8077 37 1.1416 93 1.5337 149 2.3364 205 4.9020 38 1.1468 94 1.5432 150 2.3585 206 5.0000 39 1.1521 95 1.5528 151 2.3810 207 5.1020 40 1.1574 96 1.5625 152 2.4038 208 5.2083 41 1.1628 97 1.5723 153 2.4272 209 5.3191 42 1.1682 98 1.5823 154 2.4510 210 5.4348 43 1.1737 99 1.5924 155 2.4752 211 5.5556 44 1.1792 100 1.6026 156 2.5000 212 5.6818 45 1.1848 101 1.6129 157 2.5253 213 5.8140 46 1.1905 102 1.6234 158 2.5510 214 5.9524 47 1.1962 103 1.6340 159 2.5773 215 6.0976 48 1.2019 104 1.6447 160 2.6042 216 6.2500 49 1.2077 105 1.6556 161 2.6316 217 6.4103 50 1.2136 106 1.6667 162 2.6596 218 6.5789 51 1.2195 107 1.6779 163 2.6882 219 6.7568 52 1.2255 108 1.6892 164 2.7174 220 6.9444 53 1.2315 109 1.7007 165 2.7473 221 7.1429 54 1.2376 110 1.7123 166 2.7778 222 7.3529 55 1.2438 111 1.7241 167 2.8090 223 7.5758 table 8-3. tc0out frequency table for fosc = 16mhz, tc0 rate = fcpu/8
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 81 revision 1.94 timer counter 1 (tc1) overview the timer counter 1 (tc1) is used to generate an interrupt request when a specified time interval has elapsed. tc1 has a auto re-loadable counter that consis ts of two parts: an 8-bit reload regist er (tc1r) into which you write the counter reference value, and an 8-bit counter register (tc1 c) whose value is automatic ally incremented by counter logic. figure 8-6. timer count tc1 block diagram the main purposes of the tc1 timer is as following. 8-bit programmable timer: generates interrupts at specific time intervals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequencies to the bz1 pin (p5.3). pwm function: pwm output can be generated by the pwm1out bit and output to pwm1out pin (p5.3). cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 82 revision 1.94 tc1m mode register the tc1m is an 8-bit read/write timer mode register. by l oading different value into the tc1m register, users can modify the timer clock frequency dynam ically as program executing. eight rates for tc1 timer can be selected by tc1rate0 ~ tc1rate2 bits. the range is from fcpu/2 to fcpu/256. the tc1m initial value is zero and the rate is fcpu/256. the bit7 of tc1m called tc1enb is the c ontrol bit to start tc1 timer. the combination of these bits is to determi ne the tc1 timer clock frequency and the intervals. tc1m initial value = 0000 0000 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1r ate0 0 aload1 tc1out pwm1out r/w r/w r/w r/ w - r/w r/w r/w tc1enb: tc1 counter/bz1/pwm1out enable bit. 0 = disable, 1 = enable. tc1rate2~tc1rate0: tc1 internal clock select bi ts. 000 = fcpu/256, 001 = fcpu/128, ? , 110 = fcpu/4, 111 = fcpu/2. aload1: tc1 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. tc1out: tc1 time-out toggle signal output control bit. 0 = to disable tc1 signal output and to enable p5.3?s i/o function, 1 = to enable tc1?s signal output and to disable p5 .3?s i/o function. (auto-disable the pwm1out function.) pwm1out: tc1?s pwm output control bit. 0 = to dis able the pwm output, 1 = to enable the pwm output (the tc1out control bit must = 0 ) note: bit3 must set to 0.. note: the s8kc ice do not support the pwm1out and tc1out function. the pwm1out and tc1out must use the s8kd ice (or later) to verify the function.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 83 revision 1.94 tc1c counting register tc1c is an 8-bit counter register for the timer counter (tc1 ). tc1c must be reset whenever the tc1enb is set ?1? to start the timer. tc0c is incremented by one with a cl ock pulse which the frequency is determined by tc0rate0 ~ tc0rate2. when tc0c has incremented to ?0ffh?, it is will be cleared to ?00h? in next clock and an overflow is generated. under tc1 interrupt service request (tc1ien) enable condition, the tc1 interrupt request flag will be set ?1? and the system executes the interrupt service routine. tc1c initial value = xxxx xxxx 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w r/w r/w r/w r/w r/w r/w r/w the interval time of tc1 basic timer table. high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1cloc k max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms table 8-4. the timing table of timer count tc1 the equation of tc1c initial value is as following. tc1c initial value = 256 - (tc1 interrupt interval time * input clock) example: to set 10ms interval time for tc1 interrupt at 3.58mhz high-speed mode. tc1c value (74h) = 256 - (10ms * fcpu/64) tc1c initial value = 256 - (tc1 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 84 revision 1.94 tc1r auto-load register tc1r is an 8-bit register for the tc1 auto-reload functi on. tc1r?s value applies to tc1out and pwm1out functions. under tc1out application, users must enable and set the tc1r register. the main purpose of tc1r is as following. store the auto-reload value and set into tc1c when the tc1c overflow. (aload1 = 1). store the duty value of pwm1out function. tc1r initial value = xxxx xxxx 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w w w w w w w w the equation of tc1r initial value is like tc1c as following. tc1r initial value = 256 - (tc1 interrupt interval time * input clock) note: the tc1r is write-only register can?t be process by incms, decms instructions.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 85 revision 1.94 tc1 timer counter operation sequence the tc1 timer?s sequence of operation can be following. set the tc1c initial value to setup the interval time. set the tc1enb to be ?1? to enable tc1 timer counter. tc1c is incremented by one with each clock pulse which frequency is corresponding to tc1m selection. tc1c overflow if tc 1c from ffh to 00h. when tc1c overflow occur, the tc1irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc1c value and resume the tc1 timer operation. example: setup the tc1m and tc1c without auto-reload function. b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ;(to set tc1 interval = 10 ms) b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer example: setup the tc1m and tc1c with auto-reload function. b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ; (to set tc1 interval = 10 ms) b0mov tc1r,a ; to set tc1r auto-reload register b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer b0bset aload1 ; to enable tc1 auto-reload function.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 86 revision 1.94 example: tc1 interrupt service routine without auto-reload function. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a,#74h ; reload tc1c b0mov tc1c,a . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc1 interrupt service routine with auto-reload. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 87 revision 1.94 tc1 clock frequency output (buzzer) tc1 timer counter provides a frequency out put function. by setting the tc1 clo ck frequency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-dis able. the tc1 output signal di vides by 2. the tc1 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-7. the tc1out pulse frequency example: setup tc1out output from tc1 to tc1out (p5.3). the external high-speed clock is 4mhz. the tc1out frequency is 1khz. because the tc1out signal is divided by 2, set the tc1 clock to 2khz. the tc1 clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 131. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and disable p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer note: the tc1out frequency table is as tc0out frequency table. please consult tc0out frequency table. (table 7-2~7-5)
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 88 revision 1.94 pwm function description overview pwm function is generated by tc0/tc1 timer counter and output the pwm signal to pwm0out pin (p5.4)/ pwm1out pin (p5.3). the 8-bit counter counts modulus 256, fr om 0-255, inclusive. the value of the 8-bit counter is compared to the contents of the referenc e register (tc0r/tc1r). when the refe rence register value (tc0r/tc1r) is equal to the counter value (tc0c/tc1c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pwm0/pwm1 output is tc0r/256 and tc1r/256. all pwm outputs remain inactive during the first 256 input clock signals. then, when the counter value (tc0c/tc1c) changes from ffh back to 00h, the pwm output is forced to high level. the pulse width ratio (duty cycle) is defined by the contents of the reference register (tc0r/tc1r) and is programmed in in crements of 1:256. the 8-bit pwm data register tc0r/tc1r is write only register. pwm output can be held at low level by continuously loading t he reference register with 00h. under pwm operating, to change the pwm?s duty cycle is to modify the tc0r/tc1r. reference register value (tc0r/tc1r) duty 0000 0000 0/256 0000 0001 1/256 0000 0010 2/256 . . . . 1000 0000 128/256 1000 0001 129/256 . . . . 1111 1110 254/256 1111 1111 255/256 table 8-5. the pwm duty cycle table figure 8-8 the output of pwm with different tc0r/tc1r. tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... ..... 01 128 ..... 254 255 ..... .....
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 89 revision 1.94 pwm program description example: setup pwm0 output from tc0 to pwm0out (p5.4). the external high-speed oscillator clock is 4mhz. the duty of pwm is 30/256. the pwm freque ncy is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fc pu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 30. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#0x00 ;first time initial tc0 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0r,a b0bclr ftc0out ; disable tc0out function. b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer note1: the tc0r and tc1r are write-only regi sters. don?t process them using incms, decms instructions. note2: set tc0c at initial is to make first duty-cycl e correct. after tc0 is enabled, don?t modify tc0r value to avoid duty cycle error of pwm output. example: modify tc0r/tc1r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by b0mov a, buf0 ; programming. b0mov tc0r, a note3: that is better to set the tc0c and tc0r value together when pwm0 duty modified. it protects the pwm0 signal no glitch as pwm0 duty changing. that is better to set the tc1c and tc1r value together when pwm1 duty modified. it protects the pw m1 signal no glitch as pwm1 duty changing. note4: the tc0out function must be set ?0? when pwm0 output enable. the tc1out function must be set ?0? when pwm1 output enable. note5: the pwm can work with interrupt request.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 90 revision 1.94 9 9 9 interrupt overview the sn8p1700 provides 7 1 interrupt sources, including four internal interrupts (t0, tc0, tc1 & sio) and three external interrupts (int0 ~ int2). these external interr upts can wakeup the chip from power down mode to high-speed normal mode. the external clock input pins of int0/int1/in t2 are shared with p0.0/p0.1/p0.2 pins. once interrupt service is executed, the gie bit in stkp register will cl ear to ?0? for stopping other interrupt request. when interrupt service exits, the gie bit will set to ?1? to accept the next interrupts? request. all of the interrupt request signals are stored in intrq register. the user c an program the chip to check intrq?s content for setting executive priority. global interrupt request signal interrupt vector address (0008h) intrq 7-bit latchs t0irq tc0irq tc1irq sioirq interrupt enable gating t0 time out tc0 time out tc1 time out inten interrupt enable register sio time out the interrupt trigger edge : int0 ~ int2 = falling edge p00irq int0 trigger p01irq int1 trigger p02irq int2 trigger figure 9-1. the 7 interrupts of sn8p1700 note: 1.for sn8p1702 only obtain one internal interrupt p00 and one external interrupt tc0. note: 2.the gie bit must enable and all interrupt operations work.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 91 revision 1.94 inten interrupt enable register inten is the interrupt request control register including f our internal interrupts, three external interrupts and sio interrupt enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the program jump to org 8 to execute in terrupt service routines. the program exits the interrupt service routine when the returning interrupt serv ice routine instruction (reti) is executed. inten initial value = x000 0000 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten 0 tc1ien tc0ien t0ien sioi en p02ien p01ien p00ien - r/w r/w r/w r/w r/w r/w r/w p00ien : external p0.0 interrupt control bit. 0 = disable, 1 = enable. p01ien : external p0.1 interrupt control bit. 0 = disable, 1 = enable. p02ien : external p0.2 interrupt control bit. 0 = disable, 1 = enable. sioien : sio interrupt control bit. 0 = disable, 1 = enable. t0ien : t0 timer interrupt control bit. 0 = disable, 1 = enable. tc0ien : timer interrupt control bit. 0 = disable, 1 = enable. tc1ien : timer interrupt control bit. 0 = disable, 1 = enable. intrq interrupt request register intrq is the interrupt request flag regi ster. the register includes all interr upt request indication flags. each one of these interrupt request occurs, the bit of the intrq regist er would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. intrq initial value = x000 0000 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq 0 tc1irq tc0irq t0irq sioi rq p02irq p01irq p00irq - r/w r/w r/w r/w r/w r/w r/w p00irq : external p0.0 interrupt request bit. 0 = non-request, 1 = request. p01irq : external p0.1 interrupt request bit. 0 = non-request, 1 = request. p02irq : external p0.2 interrupt request bit. 0 = non-request, 1 = request. sioirq : sio interrupt reques t bit. 0 = non-request, 1 = request. t0irq : t0 timer interrupt request control bit. 0 = non request, 1 = request. tc0irq : tc0 timer interrupt request controls bit. 0 = non request, 1 = request. tc1irq : tc1 timer interrupt request controls bit. 0 = non request, 1 = request. when interrupt occurs, the related request bit of intrq regi ster will be set to ?1? no matter the related enable bit of inten register is enabled or disabled. if the related bit of inte n = 1 and the related bit of intrq is also set to be ?1?. as the result, the system will execute the interrupt vector (org 8). if the re lated bit of inten = 0, moreover, the system won?t execute interrupt vector even when the related bit of intrq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 92 revision 1.94 interrupt operation description sn8p1700 provides 7 interrupts. the operation of the 7 interrupts is as following. gie global interrupt operation gie is the global interrupt control bit. all interrupts start wo rk after the gie = 1. it is necessary for interrupt service request. one of the interrupt requests occurs, and the program counter (pc) points to the interrupt vector (org 8) and the stack add 1 level. stkp initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w gie: global interrupt control bit. 0 = disable, 1 = enable. example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable and all interrupt operations work.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 93 revision 1.94 int0 (p0.0) interrupt operation the int0 is triggered by falling edge. when the int0 trigger occurs, the p00irq will be set to ?1? however the p00ien is enable or disable. if the p00ien = 1, the trigger event will make the p00irq to be ?1? and the system enter interrupt vector. if the p00ien = 0, the trigger ev ent will make the p00irq to be ?1? but t he system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: int0 interrupt request setup. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq . . ; int0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector note: the push and pop instruction only save l,h, r,z,y,x,pflag and rbank registers but a register. user must save register a by b0xch in struction when push command is used. int1 (p0.1) interrupt operation the int1 is triggered by falling edge. when the int1 trigger occurs, the p01irq will be set to ?1? however the p01ien is enable or disable. if the p01ien = 1, the trigger event will make the p01irq to be ?1? and the system enter interrupt vector. if the p01ien = 0, the trigger ev ent will make the p01irq to be ?1? but t he system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: int1 interrupt request setup. b0bset fp01ien ; enable int1 interrupt service b0bclr fp01irq ; clear int1 interrupt request flag b0bset fgie ; enable gie
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 94 revision 1.94 example: int1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push b0bts1 fp01irq ; check p01irq jmp exit_int ; p01irq = 0, exit interrupt vector b0bclr fp01irq ; reset p01irq . . ; int1 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector int2 (p0.2) interrupt operation the int2 is triggered by falling edge. when the int2 trigger occurs, the p02irq will be set to ?1? however the p02ien is enable or disable. if the p02ien = 1, the trigger event will make the p02irq to be ?1? and the system enter interrupt vector. if the p02ien = 0, the trigger ev ent will make the p02irq to be ?1? but t he system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: int2 interrupt request setup. b0bset fp02ien ; enable int2 interrupt service b0bclr fp02irq ; clear int2 interrupt request flag b0bset fgie ; enable gie example: int2 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push b0bts1 fp02irq ; check p02irq jmp exit_int ; p02irq = 0, exit interrupt vector b0bclr fp02irq ; reset p02irq . . ; int2 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 95 revision 1.94 t0 interrupt operation when the t0c counter occurs overflow, the t0irq will be se t to ?1? however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be ?1? and the system enter interrupt vector. if the t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interr upt vector. users need to care for the operation under multi-interrupt situation. example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. . . ; t0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 96 revision 1.94 tc0 interrupt operation when the tc0c counter occurs overflow, the tc0irq will be se t to ?1? however the tc0ien is enable or disable. if the tc0ien = 1, the trigger event will make the tc0irq to be ?1 ? and the system enter interrupt vector. if the tc0ien = 0, the trigger event will make the tc0irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. . . ; tc0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 97 revision 1.94 tc1 interrupt operation when the tc1c counter occurs overflow, the tc1irq will be se t to ?1? however the tc1ien is enable or disable. if the tc1ien = 1, the trigger event will make the tc1irq to be ?1 ? and the system enter interrupt vector. if the tc1ien = 0, the trigger event will make the tc1irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ft c1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. . . ; tc1 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 98 revision 1.94 sio interrupt operation when the sio finished transmitting, the sioirq will be set to ?1? however the sioien is enable or disable. if the sioien = 1, the trigger event will make the sioirq to be ?1? and the system enter interrupt vector. if the sioien = 0, the trigger event will make the sioirq to be ?1? but the system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: sio interrupt request setup. b0bset fsioien ; enable sio interrupt service b0bclr fsioirq ; clear sio interrupt request flag b0bset fgie ; enable gie example: sio interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push b0bts1 fsioirq ; check sioirq jmp exit_int ; sioirq = 0, exit interrupt vector b0bclr fsioirq ; reset sioirq . . ; sio interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 99 revision 1.94 multi-interrupt operation in most conditions, the software designer uses more t han one interrupt request. proce ssing multi-interrupt request needs to set the priority of these interr upt requests. the irq flags of the 7 interr upt are controlled by the interrupt event occurring. but the irq flag set doesn?t mean the system to ex ecute the interrupt vector. the irq flags can be triggered by the events without interr upt enable. just only any the event occurs and the irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger. falling edge. p01irq p0.1 trigger. falling edge. p02irq p0.2 trigger. falling edge. t0irq t0c overflow. tc0irq tc0c overflow. tc1irq tc1c overflow. sioirq end of sio transmitter operating. there are two things need to do for multi-interrupt. one is to make a good priority for these interrupt requests. two is using ien and irq flags to decide executing interrupt service routine or not. users have to check interrupt control bit and interrupt request flag in interrupt vector. there is a simple routine as following.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 100 revision 1.94 example: how does users check the interrupt request in multi-interrupt situation? org 8 ; interrupt vector b0xch a, accbuf ; b0xch doesn t change c, z flag push ; push intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intp01chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 ; jump to int0 interrupt service routine intp01chk: ; check int1 interrupt request b0bts1 fp01ien ; check p01ien jmp intp02chk ; jump check to next interrupt b0bts0 fp01irq ; check p01irq jmp intp01 ; jump to int1 interrupt service routine intp02chk: ; check int2 interrupt request b0bts1 fp02ien ; check p02ien jmp intt0chk ; jump check to next interrupt b0bts0 fp02irq ; check p02irq jmp intp02 ; jump to int2 interrupt service routine intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1hk: ; check tc1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp intsiochk ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp inttc1 ; jump to tc1 interrupt service routine intsiochk: ; check sio interrupt request b0bts1 fsioien ; check sioien jmp int_exit ; jump to exit of irq b0bts0 fsioirq ; check sioirq jmp intsio ; jump to sio interrupt service routine int_exit: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 101 revision 1.94 1 1 1 0 0 0 serial input/output transceiver (sio) overview the sn8p1700provides an 8-bit sio interface circuit with clo ck rate selection. the siom register can control sio operating function, such as: transmit/receive, clock rate, tr ansfer edge and starting this circuit. this sio circuit will tx or rx 8-bit data automatically by setting senb and start bits in siom register. the siob is an 8-bit buffer, which is designed to store transfer data. sioc and sior are designed to generate sio?s clock source with auto-reload function. the 3-bit i/o counter can monitor the operation of sio and announce an interrupt request after transmitting/receiving 8 bits data. after transferring 8-bit data, this circuit will be disabled automatically and re -transfer data by programming siom register. siob 8-bit buffer senb, txrx so/p5.2 pin siom register sck/p5.0 pin senb si/p5.1 pin sio time out 3-bit i/o counter sckmd senb senb auto_reload sioc 8-bit binary counter sior register senb srate sckmd sedge data bus reset sck sources cpum1,0 cpum1,0 cpum1,0 siob 8-bit buffer senb, txrx so/p5.2 pin siom register sck/p5.0 pin senb si/p5.1 pin sio time out 3-bit i/o counter sckmd senb senb auto_reload sioc 8-bit binary counter sior register senb srate sckmd sedge data bus reset sck sources cpum1,0 cpum1,0 cpum1,0 figure 10-1. sio interface circuit diagram
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 102 revision 1.94 figure 9-2 shows a typical transfer between two microcontrolle rs. process 1 sends sck for initial the data transfer. both processors must work in the same clock edge direct ion, then both controllers woul d send and receive data at the same time. figure 10-2. sio data transfer diagram siom mode register siom initial value = 0000 x000 0b4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siom senb start srate1 srate0 0 sckmd sedge txrx r/w r/w r/w r/ w - r/w r/w r/w senb: sio function control bit. 0 = disable (p5.0~p5.2 is general purpose port), 1 = enable (p5.0~p5.2 is sio pins). start: sio progress control bit. 0 = end of transfer, 1 = progressing. srate1, 0: sio?s transfer rate select bit. 00 = fcpu, 01 = fcpu/32, 10 = fcpu/16, 11 = fcpu/8. (note: these 2-bits are workless when sckmd=1) sckmd: sio?s clock mode select bit. 0 = internal, 1 = external mode. sedge: sio?s transfer clock edge select bit. 0 = falling edge, 1 = raising edge. txrx: sio?s transfer direction select bit. 0 = re ceiver only , 1 = transmitter/receiver full duplex. note 1: if sckmd=1 for external clock, the sio is in slave mode. if sckmd=0 for internal clock, the sio is in master mode. note 2: don?t set senb and start bits in th e same time. that makes the sio function error. msb lsb msb lsb process 1 process 2 sck sck sio clock sdo sdo sdi sdi siob 8 bit buffer siob 8 bit buffer siom register siom register msb lsb msb lsb process 1 process 2 sck sck sio clock sdo sdo sdi sdi siob 8 bit buffer siob 8 bit buffer siom register siom register
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 103 revision 1.94 because sio function is shared with port5 for p5.0 as sck, p5.1 as si and p5.2 as so the following table shown the port5[2:0] i/o m ode behavior and setting when sio function enable and disable senb=1 (sio function enable) (sckmd=1) sio source = external clock p5.0 will change to input mode automatically, no matter what p5m setting p5.0/sck (sckmd=0) sio source = internal clock p5.0 will change to output mode automatically, no matter what p5m setting p5.1/si p5.1 must be set as input mode in p5m ,or the sio function will be abnormal (txrx=1) sio = transmitter/receiver p5.2 will change to output mode automatically, no matter what p5m setting p5.2/so (txrx=0) sio = receiver only p5.2 will change to input mode automatically, no matter what p5m setting senb=0 (sio function disable) p5.0/p5.1/p5.2 port5[2:0] i/o mode are fully controlled by p5m when sio function disable siob data buffer siob initial value = 0000 0000 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siob x x x x x x x x r/w r/w r/w r/w r/w r/w r/w r/w siob is the sio data buffer register. it stor es serial i/o transmit and receive data. sior register description sior initial value = 0000 0000 0b5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sior x x x x x x x x w w w w w w w w the sior is designed for the sio counter to reload the c ounted value when end of counting. it is like a post-scaler of sio clock source and let sio has more flexible to setti ng sck range. users can set the sior value to setup sio transfer time. to setup sior value equation to desire transfer time is as following. sck frequency = sio rate / (256 - sior) sior = 256 - ( 1 / ( sck frequency ) * sio rate / 2 ) example: setup the sio clock to be 5khz. fosc = 3.58mhz. sio?s rate = fcpu = fosc/4. sior = 256 ? (1/(5khz) * 3.58mhz/4) = 256 ? 89 = 167
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 104 revision 1.94 sio master operating description under master-transmitter situation, the sck has two directions as following. sck sck figure 10-3. the two sck directions of sio master operation rising edge transmitter/receiver mode example: master tx/rx rising edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000011b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a so di4 do2 di3 di7 do6 di0 do1 do4 do5 di5 si tx/rx data di2 lsb msb do0 do7 sck do3 di6 di1 figure 10-4. the rising edge timing diagram of master transfer and receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 105 revision 1.94 falling edge transmitter/receiver mode example: master tx/rx falling edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000001b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a do2 sck do1 tx/rx data do0 di7 di6 di5 di4 si di3 do7 di2 do6 so di1 do5 di0 msb do4 lsb do3 figure 10-5. the falling edge timing diagram of master transfer and receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 106 revision 1.94 rising edge receiver mode example: master rx rising edge mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000010b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di0 di7 di6 so di5 normal i/o application di4 sck rx data di3 lsb di2 di1 msb si figure 10-6. the rising edge timing di agram of master receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 107 revision 1.94 falling edge receiver mode example: master rx falling edge mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000000b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a so si di0 rx data lsb normal i/o application di7 di6 di5 di4 msb di3 di2 di1 sck figure 10-7. the falling edge timing diagram of master receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 108 revision 1.94 sio slave operating description under slave-receiver situation, t he sck has four phases as following. sck4 sck3 sck2 sck1 figure 10-8. the four phases sck clock of sio slave operation.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 109 revision 1.94 rising edge transmitter/receiver mode example: slave tx/rx rising edge mov a,txdata ; load transfer data into siob register. b0mov siob,a mov a,# 10000111b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di0 do6 do1 di5 di4 do7 si di1 do2 di7 di2 sck1 msb do0 di6 so lsb do4 tx/rx data di3 do3 do5 di7 do0 do4 msb do5 di4 di5 do2 so di6 do3 tx/rx data lsb di2 sck2 do6 di1 di3 di0 do1 si do7 figure 10-9. the rising edge timing diagram of slave transfer and receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 110 revision 1.94 falling edge transmitter/receiver mode example: slave tx/rx falling edge mov a,txdata ; load transfer data into siob register. b0mov siob,a mov a,# 10000101b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start transfer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a do7 do6 do5 msb so do4 lsb do1 do3 do2 sck3 do0 di7 di6 di5 di4 di3 di2 di1 si di0 tx/rx data si do2 lsb do1 do0 di7 so di6 di5 msb di4 di3 sck4 do7 tx/rx data do6 di2 do5 di1 di0 do4 do3 figure 10-10. the falling edge timing diagram of slave transfer and receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 111 revision 1.94 rising edge receiver mode example: slave rx rising edge mov a,# 10000110b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a lsb di6 msb rx data sck3 so si di5 di0 di4 normal i/o application di2 di3 di1 di7 normal i/o application lsb msb so rx data sck4 di3 di2 di7 di6 si di5 di0 di4 di1 figure 10-11. the rising edge timing di agram of slave receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 112 revision 1.94 falling edge receiver mode example: slave rx falling edge mov a,# 10000100b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di5 di4 rx data di3 di7 di2 di1 normal i/o application di0 si lsb sck1 so msb di6 di1 si di0 rx data sck2 so msb di7 lsb di6 normal i/o application di5 di4 di3 di2 figure 10-12. the falling edge timing di agram of slave receiving operation
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 113 revision 1.94 sio interrupt operation description the sio provides an interrupt function. users can process sio data after the sio interrupt request occurring. there is a example for the application as following. example: sio interrupt demo routine. main: mov a,# 10000100b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start transfer sio data. . . . . jmp main org 8 ; interrupt vector b0xch a, accbuf push b0bts1 fsioirq jmp int_exit b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a b0bclr fsioirq ; clear sio interrupt request flag. int_exit: pop b0xch a, accbuf
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 114 revision 1.94 1 1 1 1 1 1 i/o port overview the sn8p1700 provides up to 5 ports for users? application, consisting of one input only port (p0), four i/o ports (p1, p2, p4, p5). the direction of i/o port is selected by pn m register and a macro @set_pur is defined for user setting pull-up register. after the system resets, all ports work as input function without pull-up resistors. figure 11-1. the i/o port block diagram note : all of the latch output circuits are push-pull structures. port0 structure pur pin int. bus pur pnm pin int. bus pnm latch port1, 2, 4, 5 structure pnm port0 structure pur pin int. bus pur pnm pin int. bus pnm latch port1, 2, 4, 5 structure pnm
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 115 revision 1.94 i/o port function table port/pin i/o function description remark general-purpose input function external interrupt (int0~int2) p0.0~p0.2 i wakeup for power down mode general-purpose input/output function p1.0~p1.5 i/o wakeup for power down mode p2.0~p2.7 i/o general-purpose input/output function general-purpose input/output function p4.0~p4.7 i/o adc analog signal input general-purpose input/output function p5.0 i/o sio clock pin. i/o general-purpose input/output function p5.1 i sio data input pin. p5m.1 must be set ?0? i/o general-purpose input/output function p5.2 o sio data output pin. p5m.1 must be set ?1? p5.3~p5.7 i/o general-purpose input/output function table 11-1. i/o function table
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 116 revision 1.94 pull-up resisters sn8p1700 series chips built-in pull-up resisters in port 0, port 1, port4 and port 5. for mask type compatible issues, sonix 8-bit mcu assembler provide a @set_pur macro to control pull-up resisters. @set_pur macro only allows enable or disable pull-up resisters as a whole port. sn8p1702 / sn8p1704: @set_pur val i/o port port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 val bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 disable pull-up 0 0 0 0 enable pull-up fixed ?0? fixed ?0? 1 1 fixed ?0? fixed ?0? 1 1 sn8p1706 / sn8p1707 / sn8p1708: @set_pur val i/o port port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 val bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 disable pull-up 0 0 0 0 0 enable pull-up fixed ?0? fixed ?0? 1 1 fixed ?0? 1 1 1 example 1: enable port 0 and port 1 pull-up resisters and disable others chip sn8p1708 org 0x10 main: . . @set_pur 0x03 ; enable port 0 and port 1 pull-up resisters example 2: enable all pull-up resisters chip sn8p1708 org 0x10 main: . . @set_pur 0x37 ; enable port 0, port 1, port 4 and port 5 pull-up resisters note: a. enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup in sleep mode. b. sn8p1704 and sn8p1702 must call @set_pur at least one time to avoid sleep mode fail.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 117 revision 1.94 i/o port mode the port direction is programmed by pnm register. port 0 is always input mode. port 1,2,4 and 5 can select input or output direction. p1m initial value = xx00 0000 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m 0 0 p15m p14m p13m p12m p11m p10m - - r/w r/w r/w r/w r/w r/w p10m~p15m: p1.0~p1.5 i/o direction contro l bit. 0 = input mode, 1 = output mode. p2m initial value = 0000 0000 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m p27m p26m p25m p24m p23m p22m p21m p20m r/w r/w r/w r/w r/w r/w r/w r/w p20m~p27m: p2.0~p2.7 i/o direction contro l bit. 0 = input mode, 1 = output mode. p4m initial value = 0000 0000 0c4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4m p47m p46m p45m p44m p43m p42m p41m p40m r/w r/w r/w r/w r/w r/w r/w r/w p40m~p47m: p4.0~p4.7 i/o direction contro l bit. 0 = input mode, 1 = output mode. p5m initial value = 0000 0000 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m p57m p56m p55m p54m p53m p52m p51m p50m r/w r/w r/w r/w r/w r/w r/w r/w p50m~p57m: p5.0~p5.7 i/o direction contro l bit. 0 = input mode, 1 = output mode. the each bit of pnm is set to ?0?, the i/o pin is input mode. the each bit of pnm is set to ?1?, the i/o pin is output mode. input mode is with pull-up resistor controlled by setti ng @set_up macro. the output mode disables the pull-up resistors no matter pull-up resistors is set or not. the pnm registers are read/write bi-direction regi sters. users can program them by bit control instructions (b0bset, b0bclr).
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 118 revision 1.94 example: i/o mode selecting. clr p1m ; set all ports to be input mode. clr p2m clr p4m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p1m, a b0mov p2m, a b0mov p4m, a b0mov p5m, a b0bclr p1m.5 ; set p1.5 to be input mode. b0bset p1m.5 ; set p1.5 to be output mode.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 119 revision 1.94 i/o port data register p0 initial value = xxxx x000 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - p02 p01 p00 - - - - - r r r p1 initial value = xx00 0000 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - p15 p14 p13 p12 p11 p10 - - r/w r/w r/w r/w r/w r/w p2 initial value = 0000 0000 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 r/w r/w r/w r/w r/w r/w r/w r/w p4 initial value = 0000 0000 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 p47 p46 p45 p44 p43 p42 p41 p40 r/w r/w r/w r/w r/w r/w r/w r/w p5 initial value = 0000 0000 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 p57 p56 p55 p54 p53 p52 p51 p50 r/w r/w r/w r/w r/w r/w r/w r/w example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p2 ; read data from port 2 b0mov a, p4 ; read data from port 4 b0mov a, p5 ; read data from port 5 example: write data to output port. mov a, #55h ; write data 55h to port 1, port2, port 4, port 5 b0mov p1, a b0mov p2, a b0mov p4, a b0mov p5, a
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 120 revision 1.94 example: write one bit data to output port. b0bset p1.3 ; set p1.3 and p4.0 to be ?1?. b0bset p4.0 b0bclr p2.3 ; set p2.3 and p5.5 to be ?0?. b0bclr p5.5 example: port bit test. b0bts1 p0.0 ; bit test 1 for p0.0 . b0bts0 p1.5 ; bit test 0 for p1.5
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 121 revision 1.94 1 1 1 2 2 2 8-channel analog to digital converter overview this analog to digital converter of sn8p1700 has 8-input sources with up to 4096-step resolution to transfer analog signal into 12-bits digital data. the sequence of adc operation is to select input source (ain0 ~ ain7) at first, then set gchs and ads bit to ?1? to start conversion. when the conver sion is complete, the adc circuit will set eoc bit to ?1? and final value output in adb register. this adc circuit can select between 8-bit and 12-bit resolution operation by programming adlen bit in adr register. a/d converter (adc) data bus 8/12 ain0/p4.0 ain5/p4.5 ain2/p4.2 ain3/p4.3 ain4/p4.4 ain1/p4.1 ain6/p4.6 ain7/p4.7 a/d converter (adc) data bus 8/12 data bus 8/12 ain0/p4.0 ain0/p4.0 ain5/p4.5 ain5/p4.5 ain2/p4.2 ain2/p4.2 ain3/p4.3 ain3/p4.3 ain4/p4.4 ain4/p4.4 ain1/p4.1 ain1/p4.1 ain6/p4.6 ain6/p4.6 ain7/p4.7 ain7/p4.7 figure 12-1. ad converter function diagram note: for 8-bit resolution the conversion time is 12 steps. for 12-bit resolution the conversion time is 16 steps. note: the analog input level must be between the avrefh and avss. note: the avrefh level must be between the avdd and avss.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 122 revision 1.94 adm register adm initial value = 0000 x000 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs - chs2 chs1 chs0 r/w r/w r/w r/ w - r/w r/w r/w chs2, 1, 0: adc input channels select bit. 000 = ai n0, 001 = ain1, 010 = ain2, 011 = ain3, .. , 111 = ain7. gchs: global channel select bit. 0 = to disable ain channel, 1 = to enable ain channel. eoc: adc status bit. 0 = progressing, 1 = end of converting and reset adenb bit. ads: adc start bit. 0 = stop, 1 = starting. adenb: adc control bit. 0 = disable, 1 = enable. adr registers adr initial value = x00x 0000 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks adlen 0 adb3 adb2 adb1 adb0 - r/w r/w - r r r r adbn: adc data buffer. adb11~adb4 bits for 8- bit adc. adb11~adb0 bits for 12-bit adc. adlen: adc?s resolution select bits. 0 = 8-bit, 1 = 12-bit. adcks: adc?s clock source select bit. adcks adc clock source note 0 fcpu/4 both validate in normal mode and slow mode 1 fhosc only validate in normal mode adb registers adb initial value = xxxx xxxx 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r r r r r r r r adb is adc data buffer to store ad converter result. the ad b is only 8-bit register including bit 4~bit11 adc data. to combine adb register and the low-nibble of adr will get full 12-bit adc data buffer. the adc buffer is a read-only register. in 8-bit adc mode, the adc dat a is stored in adb register. in 12-bi t adc mode, the adc data is stored in adb and adr registers.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 123 revision 1.94 the ain?s input voltage v.s. adb?s output data ain n adb1 1 adb10 adb9 adb8 adb7 adb6 ad b5 adb4 adb3 ad b2 adb1 adb0 0/4096*avrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/4096*avrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/4096*avrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/4096*avrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more than 8-bit resolution but less than 12-bit adc converter. to process the adb and adr data can make the job well. first, the ad resolution must be set 12-bit mode and then to execute adc converter routine. then delete the lsb of adc data and get the new resolution result. the table is as following. adb adr adc resolution adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8-bit o o o o o o o o x x x x 9-bit o o o o o o o o o x x x 10-bit o o o o o o o o o o x x 11-bit o o o o o o o o o o o x 12-bit o o o o o o o o o o o o o = selected, x = delete
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 124 revision 1.94 adc converting time 12-bit adc conversion time = 1/(adc clock /4)*16 sec 8-bit adc conversion time = 1/(adc clock /4)*12 sec high clock (fosc) is @3.58mhz adlen adcks0 adc clock adc conversion time 0 fcpu/4 1/((3.58mhz/4)/4/4)*12 = 214.5 us 0 (8-bit) 1 fhosc 1/(3.58mhz/4)*12 = 13.4 us 0 fcpu/4 1/((3.58mhz/4)/4/4)*16 = 286 us 1 (12-bit) 1 fhosc 1/(3.58mhz/4)*16 = 17.9 us example : to set ain0 ~ ain1 fo r adc input and executing 12-bit adc adc0: mov a, #60h b0mov adr, a ; to set 12-bit adc and adc clock = fosc. mov a,#90h b0mov adm,a ; to enable adc and set ain0 input b0bset fads ; to start conversion wadc0: b0bts1 feoc ; to skip, if end of converting =1 jmp wadc0 ; else, jump to wadc0 b0mov a,adb ; to get ain0 input data adc1: mov a,#91h ; b0mov adm,a ; to enable adc and set ain1 input b0bset fads ; to start conversion . . . qexadc: b0bclr fgchs ; to release ainx input channel
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 125 revision 1.94 adc circuit avrefh is connected to vdd. avrefh is connected to external ad reference voltage. figure 12-2. the ainx and avrefh circuit of ad converter note: the capacitor between ain and gnd is a bypass cap acitor. it is helpful to stable the analog signal. users can omit it. vdd avref ain0/p40 analog signal input 0.1uf mcu vdd avref ain0/p40 analog signal input 0.1uf mcu vdd avref ain0/p40 analog signal input 0.1uf mcu reference voltage input 47uf vdd avref ain0/p40 analog signal input 0.1uf mcu reference voltage input 47uf
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 126 revision 1.94 1 1 1 3 3 3 7-bit digital to analog converter overview the d/a converter uses 7-bit structure to synthesize 128 steps' analog signal with current source output. after daenb bit is set to ?1?, dac circuit will turn to be enabled and the da m register, from bit0 to bit6, will send digital signal to ladder resistors in order to generate analog signal on dao pin. ladder resistors dam register dao output ladder resistors dam register dao output figure 13-1. the da converter block diagram in order to get a proper linear output, a loading resistor r l is usually added between dao and ground. the example shows the result of vdd = 5v, r l =150ohm and vdd = 3v, r l =150ohm. figure 13-2 dao circuit with r l figure 13-3. dac output voltage in vdd=5v and 3v the d/a converter is not designed for a precise dc voltage output and is suitable for a simple audio application e.g. tone or melody generation. dam register dam initial value = 0000 0000 0b0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dam daenb dab6 dab5 dab4 dab3 dab2 dab1 dab0 r/w r/w r/w r/w r/w r/w r/w r/w daenb: digital to analog converter control bit. 0 = disable, 1 = enable. dabn: digital input data. vdd=3v vdd=5v
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 127 revision 1.94 d/a converter operation when the daenb = 0, the dao pin is out put floating status. after setting daen b to ?1?, the dao output value is controlled by dab bits. example: output 1/2 vdd from dao pin. mov a, #00111111b b0mov dam, a ; set dab to a half of the full scale. b0bset fdaenb ; enable d/a function. the dab?s data v.s. dao?s output voltage as following: dab6 dab5 dab4 dab3 dab2 dab1 dab0 dao 0 0 0 0 0 0 0 vss 0 0 0 0 0 0 1 idac 0 0 0 0 0 1 0 2 * idac 0 0 0 0 0 1 1 3 * idac . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 0 126 * idac 1 1 1 1 1 1 1 127 * idac table 13-1. dab and dao relative table note: idac = i fso / (2 7 -1) (i fso : full-scale output current)
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 128 revision 1.94 1 1 1 4 4 4 coding issue template code ;******************************************************************************* ; filename : template.asm ; author : sonix ; purpose : template code for sn8x17xx ; revision : 09/01/2002 v1.0 first issue ;******************************************************************************* ;* (c) copyright 2002, sonix technology co., ltd. ;******************************************************************************* chip sn8p1708 ; select the chip ;------------------------------------------------------------------------------- ; include files ;------------------------------------------------------------------------------- .nolist ; do not list the macro file includestd macro1.h includestd macro2.h includestd macro3.h .list ; enable the listing function ;------------------------------------------------------------------------------- ; constants definition ;------------------------------------------------------------------------------- ; one equ 1 ;------------------------------------------------------------------------------- ; variables definition ;------------------------------------------------------------------------------- .data org 0h ;bank 0 data section start from ram address 0x000 wk00b0 ds 1 ;temporary buffer for main loop iwk00b0 ds 1 ;temporary buffer for isr accbuf ds 1 ;accumulater buffer pflagbuf ds 1 ;pflag buffer org 100h ;bank 1 data section start from ram address 0x100 bufb1 ds 20 ;temporary buffer in bank 1 ;------------------------------------------------------------------------------- ; bit flag definition ;------------------------------------------------------------------------------- wk00b0_0 equ wk00b0.0 ;bit 0 of wk00b0 iwk00b0_1 equ iwk00b0.1 ;bit 1 of iwk00 ;-------------------------------------------------------------------------------
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 129 revision 1.94 ; code section ;------------------------------------------------------------------------------- .code org 0 ;code section start jmp reset ;reset vector ;address 4 to 7 are reserved org 8 jmp isr ;interrupt vector org 10h ;------------------------------------------------------------------------------- ; program reset section ;------------------------------------------------------------------------------- reset: mov a,#07fh ;initial stack pointer and b0mov stkp,a ;disable global interrupt b0mov pflag,#00h ;pflag = x,x,x,x,x,c,dc,z b0mov rbank,#00h ;set initial ram bank in bank 0 mov a,#40h ;clear watchdog timer and initial system mode b0mov oscm,a call clrram ;clear ram call sysinit ;system initial b0bset fgie ;enable global interrupt ;------------------------------------------------------------------------------- ; main routine ;------------------------------------------------------------------------------- main: b0bset fwdrst ;clear watchdog timer call mnapp jmp main ;------------------------------------------------------------------------------- ; main application ;------------------------------------------------------------------------------- mnapp: ; put your main program here ret ;----------------------------------- ; jump table routine ;----------------------------------- org 0x0100 ;the jump table should start from the head ;of boundary. b0mov a,wk00 and a,#3 add pcl,a jmp jmpsub0 jmp jmpsub1 jmp jmpsub2 ;-----------------------------------
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 130 revision 1.94 jmpsub0: ; subroutine 1 jmp jmpexit jmpsub1: ; subroutine 2 jmp jmpexit jmpsub2: ; subroutine 3 jmp jmpexit jmpexit: ret ;return main ;------------------------------------------------------------------------------- ; isr (interrupt service routine) ; arguments : ; returns : ; reg change: ;------------------------------------------------------------------------------- isr: ;----------------------------------- ; save acc and system registers ;----------------------------------- b0xch a,accbuf ;b0xch instruction do not change c,z flag push ;remark this line in sn8p1702 registers ;save 80h ~ 87h system ;following two lines for sn8x1702 only ;b0mov a,pflag ;b0mov pflagbuf,a ;----------------------------------- ; check which interrupt happen ;----------------------------------- intp00chk: b0bts1 fp00ien jmp inttc0chk ;modify this line for another interrupt b0bts0 fp00irq jmp p00isr ;if necessary, insert another interrupt checking here inttc0chk: b0bts1 ftc0ien jmp isrexit ;suppose tc0 is the last interrupt which you b0bts0 ftc0irq ;want to check jmp tc0isr
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 131 revision 1.94 ;----------------------------------- ; exit interrupt service routine ;----------------------------------- isrexit: ; following two lines for sn8x1702 only ;b0mov a,pflag ;b0mov pflagbuf,a pop ;remark this line in sn8p1702 ;restore 80h ~ 87h system registers b0xch a,accbuf ;b0xch instruction do not change c,z flag reti ;exit the interrupt routine ;------------------------------------------------------------------------------- ; int0 interrupt service routine ;------------------------------------------------------------------------------- p00isr: b0bclr fp00irq ;process p0.0 external interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; tc0 interrupt service routine ;------------------------------------------------------------------------------- tc0isr: b0bclr ftc0irq ;process tc0 timer interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; sysinit ; initialize i/o, timer, interrupt, etc. ;------------------------------------------------------------------------------- sysinit: ret
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 132 revision 1.94 ;------------------------------------------------------------------------------- ; clrram ; use index @yz to clear ram (00h~7fh) ;------------------------------------------------------------------------------- clrram: ; ram bank 0 clr y ;select bank 0 b0mov z,#0x7f ;set @yz address from 7fh clrram10: clr @yz ;clear @yz content decms z ;z = z ? 1 , skip next if z=0 jmp clrram10 clr @yz ;clear address 0x00 ; ram bank 1 mov a,#1 b0mov y,a ;select bank 1 b0mov z,#0x7f ;set @yz address from 17fh clrram20: clr @yz ;clear @yz content decms z ;z = z ? 1 , skip next if z=0 jmp clrram20 clr @yz ;clear address 0x100 ret ;------------------------------------------------------------------------------- endp
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 133 revision 1.94 chip declaration in assembler assembler otp device part number mask device part number chip sn8p1702 sn8p1702 sn8a1702a chip sn8p1704 sn8p1704 sn8a1704a chip sn8p1706 sn8p1706 sn8a1706a chip sn8p1707 sn8p1707 sn8a1707a chip sn8p1708 sn8p1708 sn8a1708a program check list item description pull-up resister use @set_pur macro to enable or disable on-chip pull-up resisters. refer i/o port chapter for detailed information. undefined bits all bits those are marked as ?0? (undefined bits ) in system registers should be set ?0? to avoid unpredicted system errors. adc set adc input pin i/o direction as input mode and disable pull-up resister of adc input pin sio master mode set sck (p5.0) and so (p5.2) pin as output mode. set si (p5.1) pin as input mode. sio slave mode set so (p5.2) pin as output mode. set sck (p5.0) and si (p5.1) pin as input mode. pwm0 set pwm0 (p5.4) pin as output mode. pwm1 set pwm1 (p5.3) pin as output mode. interrupt do not enable interrupt before initializing ram. non-used i/o non-used i/o ports should be pull- up or pull-down in input mode, or be set as low in output mode to save current consumption. sleep mode enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup. stack buffer be careful of function call and interrupt serv ice routine operation. don?t let stack buffer overflow or underflow. system initial 1. write 0x7f into stkp register to init ial stack pointer and disable global interrupt 2. clear all ram. 3. initialize all system r egister even unused registers. noisy immunity 1. enable osg and high_clk / 2 code option together 2. enable the watchdog option to protect system crash. 3. non-used i/o ports should be set as output low mode 4. constantly refresh import ant system registers and variabl es in ram to avoid system crash by a high electrical fast transient noise. 5. enable the lvd option to improve the pow er on reset or brown-out reset performance
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 134 revision 1.94 1 1 1 5 5 5 instruction set table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bnak 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, (m = only for working registers r, y, z , rbank & pflag) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borro w, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borro w, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 mul a,m r, a a * m, the lb of product stored in acc and hb stored in r register. zf affected by acc. - - 2 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s push to push working registers (080h~087h) into buffers - - - 1 c pop to pop working registers (080h~087h) from buffers 1 nop no operation - - - 1 @set_pur val enable or disable pull-up resisters. bit n of val: ?0? disable port n pull-up, ?1? enable port n pull-up - - - table 15-1. instruction set table of sn8p1700 note 1: any instruction that read/write from 0scm, will add an extra cycle.) note 2: sn8p1702/sn8a1702 don?t provide ?mul, push, pop? instruction.
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 135 revision 1.94 1 1 1 6 6 6 electrical characteristic absolute maximum rating (all of the voltages referenced to vss) supply voltage (vdd)????????????????????????????????????? - 0.3v ~ 6.0v input in voltage (vin)????????????????????????????????..vss - 0.2v ~ vdd + 0.2v operating ambient temperature (topr)????????????????????????????..-20 c ~ + 70 c storage ambient temperature (tstor)?????????????????????????????-30 c ~ + 125 c power consumption (pc)?????????????????????????????????????..500 mw standard electrical characteristic sn8p1700 series (otp) (all of voltages referenced to vss, vdd = 5.0v, fosc = 3.579545 mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit normal mode, vpp = vdd 2.2 5.0 5.5 operating voltage vdd programming mode, vpp = 12.5v 4.5 5.0 5.5 v ram data retention voltage vdr - 1.5 - v internal por vpor vdd rise rate to ens ure internal power-on reset - 0.05 - v/ms vil1 all input pins except thos e specified below vss - 0.3vdd v vil2 input with schmitt trigger buffer - port0 vss - 0.2vdd v vil3 reset pin ; xin ( in rc mode ) vss - 0.2vdd v input low voltage vil4 xin ( in x?tal mode ) vss - 0.3vdd v vih1 all input pins except thos e specified below 0.7vdd - vdd v vih2 input with schmitt trigger buffer ?port0 0.8vdd - vdd v vih3 reset pin ; xin ( in rc mode ) 0.9vdd - vdd v input high voltage vih4 xin ( in x?tal mode ) 0.7vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port pull-up resistor rup vin = vss , vdd = 5v - 100 - k ? i/o port input leakage current ilekg pull-up re sistor disable, vin = vdd - - 2 ua port1 output source current io h vop = vdd - 0.5v - 12 - ma sink current iol vop = vss + 0.5v - 15 - port2 output source current io h vop = vdd - 0.5v - 12 - ma sink current iol vop = vss + 0.5v - 15 - port4 output source current io h vop = vdd - 0.5v - 12 - ma sink current iol vop = vss + 0.5v - 15 - port5 output source current io h vop = vdd - 0.5v - 12 - ma sink current iol vop = vss + 0.5v - 15 - intn trigger pulse width tint0 int0 ~ int2 interrupt request pulse width 2/fcpu - - cycle avrefh input voltage varef vdd = 5.0v 1.2v - vdd v ain0 ~ ain7 input voltage vani vss+0.2 - avref v fosc crystal type or ceramic resonator 32768 4m 16m vdd = 3v, rc type for external mode - 6m - oscillator frequency vdd = 5v, rc type for external mode - 10m - hz vdd= 5v 4mhz - 7 15 ma vdd= 3v 4mhz - 1.5 3 ma idd1 run mode vdd= 3v 32768hz - 50 100 ua vdd= 5v 32khz int rc - 80 150 ua idd2 slow mode (stop high clock) vdd= 3v 16khz int rc - 15 30 ua vdd= 5v - 10 18 ua supply current (disable adc and lvd) idd3 sleep mode vdd= 3v - 3 6 ua lvd detect voltage vdet low voltage detect level - 2.4 - v voltage detector current ivdet lvd enable operating current - 100 180 ua vdd=5.0v - 0.6 1 ma adc current consumption i adc vdd=3.0v - 0.4 0.8 ma dac full-scale output current i fso vdd=5v, rl =150ohm - 12 - ma
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 136 revision 1.94 1 1 1 7 7 7 package information p-dip18 pin symbols min. nor. max. a - - 0.210 a1 0.015 - - a2 0.125 0.130 0.135 d 0.880 0.900 0.920 e 0.300bsc. e1 0.245 0.250 0.255 l 0.115 0.130 0.150 b 0.335 0.355 0.375 ? 0 7 15 unit : inch
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 137 revision 1.94 sop18 pin symbols min. max. a 0.093 0.104 a1 0.004 0.012 d 0.447 0.463 e 0.291 0.299 h 0.394 0.419 l 0.016 0.050 ? 0 8 unit : inch
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 138 revision 1.94 ssop20 pin dimension (mm) dimension (mil) symbols min, nom. max. min. nom. max. a 1.35 1.60 1.75 53 63 69 a1 0.10 0.15 0.25 4 6 10 a2 - - 1.50 - - 59 b 0.20 0.254 0.30 8 10 12 b1 0.20 0.254 0.28 8 11 11 c 0.18 0.203 0.25 7 8 10 c1 0.18 0.203 0.23 7 8 9 d 8.56 8.66 8.74 337 341 344 e 5.80 6.00 6.20 228 236 244 e1 3.80 3.90 4.00 150 154 157 e 0.635 bsc 25 bsc h 0.25 0.42 0.50 10 17 20 l 0.40 0.635 1.27 16 25 50 l1 1.00 1.05 1.10 39 41 43 zd 1.50 ref 58 ref y - - 0.10 - - 4 ? 0 - 8 0 - 8
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 139 revision 1.94 s-dip28 pin symbols min. nor. max. a - - 0.210 a1 0.015 - - a2 0.114 0.130 0.135 d 1.390 1.390 1.400 e 0.310bsc. e1 0.283 0.288 0.293 l 0.115 0.130 0.150 b 0.330 0.350 0.370 ? 0 7 15 unit : inch
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 140 revision 1.94 sop28 pin symbols min. max. a 0.093 0.104 a1 0.004 0.012 d 0.697 0.713 e 0.291 0.299 h 0.394 0.419 l 0.016 0.050 ? 0 8 unit : inch
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 141 revision 1.94 qfp 44 pin min nor max min nor max symbols (inch) (mm) a - - 0.106 - - 2.700 a1 0.010 0.012 0.014 0.250 0.300 0.350 a2 0.075 0.079 0.087 1.900 2.000 2.200 b 0.012 0.300 c 0.004 0.006 0.008 0.100 0.150 0.200 d 0.512 0.520 0.528 13.000 13.200 13.400 d1 0.390 0.394 0.398 9.900 10.000 10.100 e 0.512 0.520 0.528 13.000 13.200 13.400 e1 0.390 0.394 0.398 9.900 10.000 10.100 l 0.029 0.035 0.037 0.730 0.880 0.930 [e] 0.031 0.800 0 - 7 0 - 7
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 142 revision 1.94 ssop 48 pin min nor max min nor max symbols (inch) (mm) a 0.095 0.102 0.110 2.413 2.591 2.794 a1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.089 0.094 0.099 2.261 2.388 2.515 b 0.008 0.010 0.030 0.203 0.254 0.762 c - 0.008 - - 0.203 - d 0.620 0.625 0.630 15.748 15.875 16.002 e 0.291 0.295 0.299 7.391 7.493 7.595 [e] - 0.025 - - 0.635 - he 0.396 0.406 0.416 10.058 10.312 10.566 l 0.020 0.030 0.040 0.508 0.762 1.016 l1 - 0.056 - - 1.422 - y - - 0.003 - - 0.076 0 - 8 0 - 8
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 143 revision 1.94 p-dip 48 pin min nor max min nor max symbols (inch) (mm) a - - 0.220 - - 5.588 a1 0.015 - - 0.381 - - a2 0.150 0.155 0.160 3.810 3.937 4.064 d 2.400 2.450 2.550 60.960 62.230 64.770 e 0.600 15.240 e1 0.540 0.545 0.550 13.716 13.843 13.970 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.630 0.650 0.067 16.002 16.510 1.702 0 7 15 0 7 15
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 144 revision 1.94 p-dip 40 pin min nor max min nor max symbols (inch) (mm) a - - 0.220 - - 5.588 a1 0.015 - - 0.381 - - a2 0.150 0.115 0.160 3.810 2.921 4.064 d 2.055 2.060 2.070 52.197 52.324 52.578 e 0.600 15.240 e1 0.540 0.545 0.550 13.716 13.843 13.970 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.630 0.650 0.067 16.002 16.510 1.702 0 7 15 0 7 15
sn8p1700 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 145 revision 1.94 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of the application or use of any product or circ uit described herein; neither does it convey any license under its patent rights nor the rights of ot hers. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into t he body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use so nix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its o fficers , employees , subsidiaries, affiliates and distributors harmless agains t all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any cl aim of personal injury or death associ ated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th s t, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 gr anville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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