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june 2008 rev 1 1/44 44 STULPI01A stulpi01b high speed usb on-the -go ulpi transceiver features usb-if high speed certified to the universal serial bus specification rev 2.0. meets the requirements of the universal serial bus specification revision 2.0, on-the-go supplement to the usb 2.0 specification 1.0a and ulpi transceiver specification 1.1. standard ulpi (utmi+ low pin interface) 1.1 digital interface. fully compliant with ulpi 1.1 register set. external square wave clock with 1v8vio amplitude must be applied to oscillator input xi. supports 480 mbit/s high speed, 12 mbit/s full- speed and 1.5 mbit/s low speed modes of operation. supports 2.7 v uart mode. supports session request protocol (srp) and host negotiation protocol (hnp) for dual-role device features. ability to control exter nal charge pump for higher vbus currents. single supply, +3 v to +4.5 v voltage range. integrated dual voltage regulator to supply internal circuits with stable 3.3 v and 1.2 v. integrated over current detector. integrated hs termination and fs/ls/otg pull-up/pull-down resistors. integrated usb 2.0 ?short-circuit withstand? protection. power down mode with very low power consumption for battery-powered devices. ideal for system asics with built-in usb host, device or otg cores. available in tfbga36 rohs package. -40 c to 85 c operating temperature range. applications mobile phones pdas mp3 players digital still cameras set top box portable navigation devices description the stulpi01 is a high speed usb 2.0 transceiver compliant with ulpi (utmi+ low pin interface) and otg (on-the-go) specifications, providing a complete physical layer solution for any high speed usb host, device or otg dual role core. it allows usb asics to interface with the physical layer of the usb through a 12-pin interface. it contains vbus comparators, id line detector, usb differential driver and receivers and complete ulpi register map and interrupt generator. the stulpi01 transceiver is suitable for mobile applications and battery powered devices because of its low power consumption, power down operating mode and minimal die/package dimensions. tfbga36 www.st.com
contents STULPI01A - stulpi01b 2/44 contents 1 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 power-on-reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 utmi + core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 ulpi wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 external charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.7 vbus comparators and vbus over current (oc) detector . . . . . . . . . . . 19 6.8 vb_ref_fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.10 id detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.11 usb 2.0 phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.12 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.1 ulpi synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.2 6 pin fs/ls serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.3 3 pin fs/ls serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.14 car kit (uart) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.15 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.16 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.17 vio off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18 start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.1 ulpi device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STULPI01A - stul pi01b contents 3/44 6.18.2 sdr mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.3 external clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.4 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.5 interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.7 high speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 ulpi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables STULPI01A - stulpi01b 4/44 list of tables table 1. bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. high-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. vb_ref_fault configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. usb state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. ulpi register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. vendor and product id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. power control registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19. otg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20. usb interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 21. usb interrupt enab le falling register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22. usb interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 23. usb interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 24. setting rules for interrupt latch register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 25. debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 26. scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 27. carkit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 28. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 29. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STULPI01A - stulpi01b list of figures 5/44 list of figures figure 1. peripheral only. configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. high-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. vb_ref_fault pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. usb 2.0 phy block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. resetn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. high speed mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. uart mode entry (2.7 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. uart mode exit (2.7 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
application diagrams st ulpi01a - stulpi01b 6/44 1 application diagrams figure 1. peripheral only. configuration with external clock table 1. bill of materials - external components q.ty symbol value description 1c f1 0.1 - 1 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25v x5r (tmk107bj105ka) 2c f4 0.1 - 1 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25v x5r (tmk107bj105ka) 1c f2 1f - 1.5 f filtering capacitor. suggested components: murata 10 v x5r (grm188r61a105ka61) or murata 10 v y5v (grm188f51a105za01) or taiyo yuden 25v x5r (tmk107bj105ka) 1c f3 1 - 4.7 f filtering capacitor. suggested components: murata 10 v y5v (grm188f51a475ze20) or taiyo yuden 6.3 v x5r (jmk107bj475ka) 1c t 4.7 f tank capacitor 1r ref 12 k reference resistor 1% 1 e1 usbulc6-2f3 1 e2 esda14v2-2bf3 1r bus 2.2 k series over-voltage protection resistor
STULPI01A - stulpi01b bump configuration 7/44 2 bump configuration figure 2. pin connections tfbga36 (bottom view) a b c d e f 1 2 3 4 5 6 tfbga36 (through top side view) 6 5 4 3 2 1 d5 d4 clk d3 d2 d1 a d6 1v8 vio gnd 1v8 vio 1v8 vio d0 b d7 gnd resetn csn/ pwrdn rref dm c stp nxt pswn id gnd dp d 1v2v dir gnd 3v3v vb_ref _fault gnd e xo xi vbus vbat nc nc f 6 5 4 3 2 1 d5 d4 clk d3 d2 d1 a d6 1v8 vio gnd 1v8 vio 1v8 vio d0 b d7 gnd resetn csn/ pwrdn rref dm c stp nxt pswn id gnd dp d 1v2v dir gnd 3v3v vb_ref _fault gnd e xo xi vbus vbat nc nc f table 2. pinout and bump description bump symbol type description b1 d0 i/o data bit[0] (1v8vio referred). uart txd signal. a1 d1 i/o data bit[1] (1v8vio referred). uart rxd signal. a2 d2 i/o data bit[2] (1v8vio referred). uart reserved pin. a3 d3 i/o data bit[3] (1v8vio referred). uart active high interrupt indication. a4 clk o clock out (1v8vio referred). a5 d4 i/o data bit[4] (1v8vio referred). a6 d5 i/o data bit[5] (1v8vio referred). b6 d6 i/o data bit[6] (1v8vio referred). c6 d7 i/o data bit[7] (1v8vio referred). d6 stp i ulpi stop signal (1v8vio referred). d5 nxt o ulpi next signal (1v8vio referred). e5 dir o ulpi direction signal (1v8vio referred). c3 csn/pwrdn i chipselect active low, power down active high. c4 resetn i active low asynchronous reset. d1 dp i/o positive data line of the usb. 5v tolerant. c1 dm i/o negative data line of the usb. 5v tolerant. d3 id i id pin of the usb connector for initial device role selection. 5v tolerant. f4 vbus i/o v bus line of the usb interface, requires an external capacitor of 4.7f. f1 nc not connected.
bump configuration STULPI01A - stulpi01b 8/44 bump symbol type description f2 nc not connected. e2 vb_ref_fault i voltage reference for internal oc de tector input or digital input from external oc detector (v 3v3v referred). 5v tolerant. d4 pswn o external charge pump control, active low. 5v tolerant, open drain. f5 xi i external clock input (1v8vio referred). crystal terminal (on request). f6 xo o left floating or connect to gnd when external clock signal is used. crystal terminal on request. f3 vbat pwr battery power input for the ldo (3 v ? 4.5 v). bypass v bat to gnd with a 1f capacitor. e3 3v3v pwr 3.3v ldo output. bypass 3v 3v to gnd with a 1.5f capacitor. e6 1v2v pwr 1.2v ldo output. bypass 1v 2v to gnd with a 1.5f capacitor. c2 rref i/o reference resistor (12k 1%). b2/b3/b5 1v8vio pwr digital i/o supply voltage 1.8v. bypass each 1v8vio to gnd with a 100nf-1uf capacitor. balls b2-b5 can share common capacitor. c5/d2 gnd pwr ground. b4/e4/e1 gnd pwr ground. table 2. pinout and bump description (continued)
STULPI01A - stulpi 01b maximum ratings 9/44 3 maximum ratings note: absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are referenced to gnd. table 3. absolute maximum ratings symbol parameter value unit v 1v8vio digital i/o supply voltage -0.3 to +2.0 v v 1v2 digital core supply voltage (provided internally by ldo) -0.3 to +1.4 v v 3v3 analog supply voltage (provided internally by ldo) -0.3 to +4.0 v v bat battery supply voltage -0.3 to +7.0 v v dcdig dc voltage on digital pins (clk, dir, stp, nxt, d[0-7], resetn) -0.3 to +2.0 v v dcana dc voltage on analog pins (xi, xo, pswn) -0.3 to +4.0 v v dcvbus dc voltage on 5v tolerant pins (vbus,vb_ref_fault, dp, dm, id) -0.3 to +5.5 v t stg storage temperature range -40 to +125 c v esd-hbm electrostatic discharge voltage on all pins (according to jesd22- a114-b) 2.0 kv table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient (simulated value as per jedec jsd51) 113.8 c/w r thjc thermal resistance junction-case (simulated value as per jedec jsd51) 47 c/w r thjb thermal resistance junction-base (simul ated value as per jedec jsd51) 66.2 c/w table 5. recommended operating conditions symbol parameter min. typ. max. unit v bat battery supply vo ltage 3.0 3.6 4.5 v v 1v8vio digital i/o supply voltage 1.65 1.80 1.95 v t a operating temperature range -40 +85 c c t tank capacitor 1 4.7 6.5 f r ref external reference resistor 11.88 12 12.12 k xtal external square wave (01a, 01b versions) 19.2 or 26 mhz recommended rise/fall time 4 ns
electrical characteristics STULPI01A - stulpi01b 10/44 4 electrical characteristics table 6. electrical characteristics (characteristics measured over recommended oper ating conditions unless otherwise noted. all typical values are referred to t a = 25 c, v 1v8io = 1.8 v, v bat = 3.6 v, r ref = 12 k ; c t = 4.7 f) symbol parameter test conditions min. typ. max. unit power consumption i bat supply current active mode (usb bus idle) 15 ma active mode (fs transmission, 12mb/s traffic) 30 ma active mode (hs transmission) 50 ma suspend mode (not including dp pull-up current, external clock stopped) 120 a uart mode (no transmission) 15 ma power down mode 0.4 2 a vio off mode (1v8vio=0) 0.4 2 a i 1v8vio ulpi bus supply current 1v8vio power down mode 0.1 10 a active mode, 4pf load 1.8 ma logic inputs and outputs c ulpiin ulpi port i/o capacitance 2.4 3.5 pf v oh high level output voltage (ulpi bus) i oh = -2 ma v 1v8vio -0.15 v v ol low level output voltage (ulpi bus) i ol = +2 ma 0.15 v i ozh_pswn high level output leakage (pswn) v oh_pswn = 3.3v power switch disabled 1.0 a v ol_pswn low level output voltage (pswn) i ol = +2 ma power switch enabled 0.15 v v ih high level input voltage (ulpi port and resetn) 0.65xv 1v8vio v v il low level input voltage (ulpi port and resetn) 0.35xv 1v8vio v i ih high level input leakage current v ih = v 1v8vio -0.2v 1.0 a
STULPI01A - stulpi01b electrical characteristics 11/44 symbol parameter test conditions min. typ. max. unit i il low level input leakage current v il = 0.2v 1.0 a v pdh high level input voltage (csn/pwrdn pin) v bat =3.0v to 4.5v 1.4 v v pdl low level input voltage (csn/pwrdn pin) v bat =3.0v to 4.5v 0.4 v i pdh high level input leakage current (csn/pwrdn pin) v pd = 1.4v, v bat = 4.5v 1.0 a i pdl low level input leakage current (csn/pwrdn pin) v pd = 0.4v, v bat = 4.5v 1.0 a v faulth high level input voltage (vb_ref_fault pin) overcurrent_pd bit is set 0.65xv 3v3 v v faultl low level input voltage (vb_ref_fault pin) overcurrent_pd bit is set 0.15xv 3v3 v r in_vb_ref vb_ref_fault pin input resistance 112 148 168 k v xi_hyst_ext external clock input hysteresis xo = ?0? @ reset 500 mv v xih high level input voltage (xi pin) xo = ?0? @ reset 0.65xv 1v8vio v v xil low level input voltage (xi pin) xo = ?0? @ reset 0.15xv 1v8vio v vbus v bus_lkg v bus leakage voltage no load 200 mv r vbus v bus input impedance 40 100 k v bus_vld v bus valid comparator threshold 1k series resistors 4.4 4.75 v v sess_vld session valid comparator threshold for both a and b device low to high transition 0.8 1.45 2.0 v high to low transition 1.25 v v sess_end session end comparator threshold 0.2 0.8 v r vbus_pu v bus charge pull-up resistance 650 950 1150 r vbus_pd v bus discharge pull-down resistance 800 1250 1500 table 6. electrical characteristics (continued) (characteristics measured over recommended oper ating conditions unless otherwise noted. all typical values are referred to t a = 25 c, v 1v8io = 1.8 v, v bat = 3.6 v, r ref = 12 k ; c t = 4.7 f)
electrical characteristics STULPI01A - stulpi01b 12/44 symbol parameter test conditions min. typ. max. unit overcurrent detector v oc over current trip threshold vb_ref_fault ? vbus v oc = vb_ref_fault ? vbus 20 45 95 mv id i id_pu id pin pull-up current v id = 0v 70 a r id_gnd id line short resistance to detect id gnd state 1k r id_float id line short resistance to detect id float state 100 k uart mode (2.7 v 5 %) v oh_uart high level output voltage (d1,d3) i oh = -2ma v 1v8vio -0.15 v v ol_uart low level output voltage (d1,d3) i ol = +2ma 0.15 v v ih_uart_d0 high level input voltage (d0) 0.65xv 1v8vio v v il_uart_d0 low level input voltage (d0) 0.35xv 1v8vio v v oh_dfms high level output voltage (dp) i oh = -2ma 2.16 2.85 v v ol_dfms low level output voltage (dp) i ol = +2ma, pull-up=10k -0.10 0.37 v v ih_dtms high level input voltage (dm) 2.0 3.0 v v il_dtms low level input voltage (dm) -0.3 0.81 v full-speed/low-speed driver z drv output impedance (acting also as high-speed termination) 40.5 49.5 v oh_drv high level output voltage r lh = 14.25k 2.8 3.6 v v ol_drv low level output voltage r ll = 1.425k 0.0 0.3 v v crs driver crossover voltage c load =50 to 600pf (1) 1.3 1.67 2.0 v high-speed driver v hsoi hs idle level -10 10 mv v hsdpj hs data dp j state level (1) 380 440 mv v hsdk hs data dp k state level -10 10 mv table 6. electrical characteristics (continued) (characteristics measured over recommended oper ating conditions unless otherwise noted. all typical values are referred to t a = 25 c, v 1v8io = 1.8 v, v bat = 3.6 v, r ref = 12 k ; c t = 4.7 f)
STULPI01A - stulpi01b electrical characteristics 13/44 symbol parameter test conditions min. typ. max. unit v hsdnj hs data dn j state level (1) 380 440 mv v hsdnk hs data dn k state level -10 10 mv v chirpj chirp j level (differential voltage) (1) 700 1100 mv v chirpk chirp k level (differential voltage -900 -500 mv full-speed/low-speed receivers v di diff. receiver input sensitivity (v dp -v dm ) v cm = 0.8 to 2.5v 200 mv v se_th se receivers switching threshold low to high transition 0.8 1.6 2.0 v high to low transition 0.8 1.1 2.0 v r inp input resistance pu/pd resistors deactivated 300 k c in input capacitance (1) 5pf cin difference in capacitance between dp and dm input 10 % v dt_lkg data line leakage voltage r pu_ext = 300k 342 mv high-speed receiver v hssq hs squelch detector threshold 100 150 mv v hsdsc hs disconnect detection threshold 525 625 mv v hscm hs data signaling common mode volt. range (1) -50 500 mv v hsterm termination voltage in hs (1) -10 10 mv data pull-up/pull-down resistors r pu data line pull-up resistance (dp, dm) 1.425 k v ihz fs idle high level voltage 2.7 v r pd data line pull-down resistance (dp, dm) 14.25 24.8 k voltage regulator 3v3v 3.3v internal power supply voltage v bat = 3.6v, active mode 3.26 3.4 3.54 v 1v2v 1.2v internal power supply voltage v bat = 3.6v, active mode 1.187 1.25 1.31 v 1. guaranteed by design. table 6. electrical characteristics (continued) (characteristics measured over recommended oper ating conditions unless otherwise noted. all typical values are referred to t a = 25 c, v 1v8io = 1.8 v, v bat = 3.6 v, r ref = 12 k ; c t = 4.7 f)
electrical characteristics STULPI01A - stulpi01b 14/44 table 7. switching characteristics (over recommended operating conditions unless otherwise noted. all the typical values are referred to t a = 25 c, v 1v8vio = 1.8 v, v bat = 3.6 v, c t = 4.7 f) symbol parameter test conditions min. typ. max. unit reset t resetext width of reset pulse on resetn pin 10 s uart mode t rise switching time (max low to min high) c load =185pf 215 ns t fall switching time (min high to max low) c load =185pf 215 ns t pd_rx delay time (50% dm to 50% d1) c l =10pf 60 ns t pd_tx delay time (50% d0 to 50% dp) 60 ns t uarton2v7 turn-on time for txd line (2v7) uart_2v7 = 1 measured from dir assertion 22.5ms t uartoff2v7 turn-off time for txd line (2v7) uart_2v7 = 1 measured from stp assertion 1s t uarton turn-on time for txd line uart_2v7 = 0 measured from dir assertion 60 ns t uartoff turn-off time for txd line uart_2v7 = 0 measured from dir de-assertion 60 ns low-speed driver t lr data signal rise time c load = 600pf 75 100 300 ns t lf data signal fall time c load = 600pf 75 100 300 ns rfm ls rise and fall time matching -20 20 % dr ls low-speed data rate 1.49925 1.50075 mb/s t ddj1 data jitter to next transition includes freq. tolerances -25 25 ns t ddj2 data jitter for paired transitions includes freq. tolerances -14 14 ns t leopt se0 interval of eop 1250 1500 ns full-speed driver t fr data signal rise time c load = 50pf 4 20 ns t ff data signal fall time c load = 50pf 4 20 ns rfm fs rise and fall time matching -10 +10 % dr hs full-speed data rate 11.994 12.006 mb/s t dj1 data jitter to next transition in cludes freq. tolerances -3.5 3.5 ns t dj2 data jitter for paired transitions includes freq. tolerances -4 4 ns t feopt se0 interval of eop 160 175 ns clock generation constants t pll pll lock time (1) 200 s t dll dll lock time (1) 280 s
STULPI01A - stulpi01b electrical characteristics 15/44 symbol parameter test conditions min. typ. max. unit high-speed driver t hsr data rise time 500 ps t hsf data fall time 500 ps waveform requirements including jitter specified by eye pattern ( figure 3 ) dr hs high-speed data rate 479.76 480.24 mb/s ulpi interface clock (measured on clk pin) f start_u frequency (first transition) (1) 54 60 66 mhz f steady_u frequency (steady state) 59.97 60 60.03 mhz d start_u duty cycle (first transition) 40 50 60 % d steady_u duty cycle (steady state) (1) 45 50 55 % t steady_u time to reach steady state frequency and duty cycle after first transition (1) 1.4 ms t jitter_u jitter 400 ps t sclk60out clock start up time measured from assertion of stp during suspend, or after release of resetn pin 250 900 s ulpi control si gnals (sdr mode) (1) t sc_u control in setup time c load = 15pf v 1v8vio = 1.65 - 1.95v 6.0 ns t hc_u control in hold time 0.0 ns t dc_u control output delay 9.0 ns ulpi data signals (sdr mode) (1) t sd_u data in setup time c load = 15pf v 1v8vio = 1.65 - 1.95v 6.0 ns t hd_u data in hold time 3.0 ns t dd_u data output delay 9.0 ns 1. guaranteed by design. table 7. switching characteristics (continued) (over recommended operating conditions unless otherwise noted. all the typical values are referred to t a = 25 c, v 1v8vio = 1.8 v, v bat = 3.6 v, c t = 4.7 f)
electrical characteristics STULPI01A - stulpi01b 16/44 figure 3. high-speed driver eye pattern +400mv differential -400mv differential 0 v differential level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 0% 100% unit interval table 8. high-speed driver eye pattern level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 voltag e level (dp ? dm) 525mv (1) 475mv -525mv (1) -475mv 0v 0v 300mv 300mv -300mv -300mv time (% of unit interval) 5% 95% 35% 65% 35% 65% 1. this value is valid for unit interv als following a transition. for all other intervals the other value is valid.
STULPI01A - stulpi 01b timing diagram 17/44 5 timing diagram figure 4. rise and fall time figure 5. simplified block diagram ulpi wrapper oscillator & pll power on reset usb 2.0 phy utmi + interface xi xo clk dir stp nxt d0 - d7 1v8vio vbus resetn dp dm id pswn gnd dual voltage regulator vbat gnd voltage reference utmi + core otg block charge pump, vbus comparators id detector vb_ref_fault over current fault detector rref ulpi wrapper oscillator & pll power on reset usb 2.0 phy utmi + interface xi xo clk dir stp nxt d0 - d7 1v8vio vbus resetn dp dm id pswn gnd dual voltage regulator vbat gnd voltage reference utmi + core otg block charge pump, vbus comparators id detector vb_ref_fault over current fault detector rref
block description STULPI01A - stulpi01b 18/44 6 block description the stulpi01 integrates a comparator for the vbus, id line detector, differential hs data driver, differential and single-ended receivers, low dropout voltage regulators, and control logic. the stulpi01 provides a complete solution for connection of a digital usb host/device/otg controller to a usb bus. 6.1 oscillator and pll an external clock (digital square wave 1v8vio referred) driven into xi must be used (version STULPI01A or stulpi01b). the pll internally produces all frequencies needed for operation: 60 mhz clock for the utmi core and ulpi interface controller 1.5 mhz for low speed usb data 12 mhz for full speed usb data 480 mhz for high speed usb data other internal frequencies for data conversion and data recovery 6.2 voltage reference this block provides the precise reference voltage needed by internal circuit. it requires a 12 k +/- 1% resistor connected to the r ref pin. 6.3 power-on-reset (por) the power-on-reset circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. power-on-reset senses the v 3v3v and v 1v2v voltage. during power-on-reset pulse, the ulpi pins are in a high impedance state with pull- down/pull-up resistors disabled. 6.4 utmi + core this is the digital heart of the chip and performs the bit-stuffing, nrzi decoding and serial- to-parallel conversion during receive and the reverse operation during transmit for hs and fs/ls. 6.5 ulpi wrapper this implements the ulpi related protocol and conversion from utmi+ to ulpi interface. this block also implements the interrupt logic and complete ulpi register set.
STULPI01A - stulpi01 b block description 19/44 6.6 external charge pump it is possible to use an external charge pump or power switch controlled by the pswn pin (active low open drain). this functionality is controlled by drvvbus and drvvbusexternal ulpi otg control register bits. 6.7 v bus comparators and v bus over current (oc) detector these comparators monitor the v bus voltage. v bus valid status signalizes that the voltage is above the v bus_vld level (4.4 v). session valid status signalizes that the v bus voltage is above the v sess_vld level (0.8 to 2.0 v). session end detector signalizes v bus voltage is below v sess_end level. stulpi01 also implements embedded v bus over current detector which compares v bus voltage to external analog 5 v reference signal applied to vb_ref_fault pin. 6.8 vb_ref_fault pin v bus over-current conditions can be monitored by either internal or an external oc detector. the internal oc detector is enabled when over-current_pd bit in the power control register (vendor-specific area) is set to 0b and use ex ternal vbus indicator is set to 1b. in this mode, the vb_ref_fault pin functions as the input of the analog reference for internal over-current detector. if the external charge pump is already equipped with an over-current detector, its output can be also monitored through vb_ref_fault pin, but over-current_pd bit must be set to 1b. in this mode vb_ref_fault will function as st andard digital input pin with 5 v tolerance. functionality of vb_ref_fault pin can be seen in more detail (on figure 6 ). note: after reset, over-current_pd bit is 1b, internal over-current detector is disabled. figure 6. vb_ref_fault pin functionality + - ref vbref_fault internal vbus valid vbusvld [useexternalvbusindicator, indicatorpassthru] rx cmd vbus valid 2 0 1 [0,x] [1,0] [1,1] bus vb ref v bus schmit (5 v tolerant) vbus fault + - vboc en /en + - valid indicatorcomplement overcurrent_pd or neg (useexternalvbusindicator) 0 1 [0,x] [1,1] v v vbus + - vboc r in_vbref + - ref vbref_fault internal vbus valid vbusvld [useexternalvbusindicator, indicatorpassthru] rx cmd vbus valid 2 0 1 [0,x] [1,0] [1,1] bus vb ref v bus schmit (5 v tolerant) vbus fault + - vboc en /en + - valid indicatorcomplement overcurrent_pd or neg (useexternalvbusindicator) 0 1 [0,x] [1,1] v v vbus + - vboc r in_vbref
block description STULPI01A - stulpi01b 20/44 6.9 voltage regulator dual output ultra low dropout voltage regulator provides power supply for analog and digital internal circuits. an external capacitor on bo th 3v3v and 1v2v pins is needed for proper operation. 6.10 id detector this block provides sensing of status of the id line. it is capable of detecting whether the pin is floating or tied to the ground. 6.11 usb 2.0 phy the usb 2.0 phy block provides complete phys ical layer transceiver for low-speed, full- speed, and high-speed usb operating modes. analog part of this block deals with impedances adaptation, controlled voltage swing, and common mode voltage generation and sensing. digital part consists of serializer and deserializer, transforming serial bit stream to 8-bit parallel port, and finite state machine implementing the phy protocol layer, bit stuffing, unstuffing etc. table 9. vb_ref_fault configuration bit settings rx cmd vbus valid use external vbus indicator over-current_pd indicator pass-true indicator complement vbusvld 0 1 x x vboc 1 0 1 x vboc and vbusvld 1 0 0 x neg (fault) 1 1 1 0 fault 1 1 1 1 vbusvld and fault 1 1 0 1 vbus_vld and neg (fault) 1 1 0 0
STULPI01A - stulpi01 b block description 21/44 6.12 power saving features to reduce power consumption stulpi01 implements 2 low power modes of operation. 1. low power mode, which is defined in ulpi specification. 2. power-down mode to save more power in case usb function is not needed. more information on these modes can be found in following paragraph: 6.13 modes of operation 6.13.1 ulpi synchronous mode stulpi01 transceiver supports sdr mode operation (12 pin interface). the selection of sdr mode is performed during startup reset procedure. 6.13.2 6 pin fs/ls serial mode this mode is entered by writing to correspon ding bit in the interface control register. 6.13.3 3 pin fs/ls serial mode this mode is entered by writing to correspon ding bit in the interface control register. figure 7. usb 2.0 phy block diagram hs ser-des ls/fs ser-des 45 ? hs disconnect det. squelch detector ls/fs se receivers 3.3v 1.5k ? 19.25k ? 3.3v 1.5k ? 19.25k ? dp dn
block description STULPI01A - stulpi01b 22/44 6.14 car kit (uart) mode this mode is entered by writ ing to the car kit mode bit in the interface control register. stulpi01 does not implement all features of car kit mode, only the uart functionality is preserved. txd or rxd paths are activated only when co rresponding bits txd_en/rxd_en in car kit control register bits ( ta bl e 2 3 ) are set. uart_2v7 bit controls the voltage level of uart signaling. in case 2v7 volt signaling is used, after the uart mode is entered, pll is disabled and the voltage on the regulator output starts to decrease to 2.7 v. after time marked as t uarton2v7 the txd output on usb bus is enabled. when leaving car kit mode, txd is disabled immediately when stp pin is asserted. the time required to exit car kit mode is equivalent to the time needed for pll startup. when 3.3 volt uart signaling is selected, txd line is enabled immediately after entering car kit mode, and disabled after exit from this mode. note: when car kit mode is used with 2v7 signaling, pll and output clock is always stopped regardless on the setting of clocksuspendm bit. 6.15 low power mode stulpi01 enters low power mode when suspendm bit in interface control register is set to 0b. most of the references are turned off, pll and clock are turned off, but the full wake-up capability as defined in the ulpi specification is still maintained. when in low power mode, the phy drives d3-d0 with the signals listed in table below. line state is driven combinatorially from the se receivers. the int signal is asserted whenever any unmasked interrupt occurs. the phy latches interrupt events directly from analog circuitry because the clock is powered down. table 10. car kit signals mapping default car kit signals mapping (uart_dir = 0) signal ulpi lines usb lines txd data[0] (input) -> dm (output) rxd data[1] (output) <- dp (input) reserved data[2] (input) int data[3] (output) car kit signals mapping (uart_dir = 1) signal ulpi lines usb lines txd data[0] (input) -> dp (output) rxd data[1] (output) <- dm (input) reserved data[2] (input) int data[3] (output)
STULPI01A - stulpi01 b block description 23/44 low power mode is exited by asserting stp pin high. pll is started immediately, and when the clock becomes stable, it is passed on the output of clk pin. then after minimum of 5 clock cycles dir is deasserted and low power mode is exited. suspendm bit is reset to 1b. note: stp signal must be kept hi gh until the dir is deasserted, otherwise low power mode will not be exited. 6.16 power down mode power down mode is entered by asserti ng the csn/pwrdn pin high. internal voltage regulators are disabled, and the device has minimum possible power consumption. stulpi01 has no wake-up capability or usb fu nctionality during power down mode. this mode can be exited by deasserting csn/pwr dn pin. voltage regulators will be turned on and internal power-on-reset circ uit will reset the chip to initial state. ulpi interface pins are in high impedance state during power down mode. 6.17 vio off mode in case 1v8vio voltage is below the minimum value, the vio off mode is entered. the behavior of the device in vio off mode is the same as in power down mode. 6.18 start-up procedure 6.18.1 ulpi device detection link detects ulpi device presence by sampling the dir signal at the reset time ( figure 8 ). the nxt signal is '0' after reset to signalize 8-bit device to link cont roller. clk is '1' to signalize a ddr capable device. 6.18.2 sdr mode selection the stulpi01 samples the d0 line on the first rising edge of the output clock on the clk pin. when the sampled value is '0', the stulpi01 remains in sdr mode. sdr mode can be selected again only after hardware reset. during software reset mode, selection is not performed. note: important: the controller must not drive the data lines to a value other than 0x00 or 0x01 during the first rising edge of ulpi clk, otherwise the behavior of the device may be undefined. table 11. low power mode signal map to dir description linestate (0) d0 out driven combinatorially from se receivers linestate (1) d1 out driven combinatorially from se receivers reserved d2 out reserved int d3 out active high interrupt indication. asserted whenever any unmasked interrupt occurs.
block description STULPI01A - stulpi01b 24/44 6.18.3 external clock detection the square wave clock can be applied to the oscillator in put. the input s quare wave clock amplitude is referenced to the 1v8vio voltage. the xo pin can be left floating or grounded. 6.18.4 reset behavior typical startup sequence is shown in figure 9 . stulpi01 contains internal power-on-reset generator which senses the v3v3v and v1v2v voltage. assertion of resetn is not necessary fo r proper initialization. however, if required, this pin can be also used. the internal reset signal is the combination of the signal from resetn pin and the signal from the internal power-on-reset circuit. when resetn is asserted, all internal registers are reset to their default values, the output dir signal is driven to '1', and dat a lines pulled low by weak pull-downs. during reset the stp pin can be driven low, high , or can be left floating. it will be pulled up by internal pull-up and the ulpi interface enters a holding state. during the reset state the nxt signal is driven low and the clk is driven high. when the pll is stabilized, th e clock on the clk pin is enabled, and dir is deasserted. note: note: the minimum duration of the external reset signal is tresetext. (see chapter crystal or external clock detection). when internal por reset is asserted, the re set procedure is equivalent to the resetn signal, with the only exception being that the ulpi lines are in high impedance state. all pull- downs and pull-ups on the ulpi signals are also disabled. 6.18.5 interface protection the stulpi01 activates weak pull-downs on data lines and pull-up on the stp during reset and holding state. these are to provide interface protection during startup and anytime the link is not able to drive the ulpi lines properly. the holding state is entered when the controller drives the stp for more than 1 clock cycle. any command on the ulpi bus is ignored in this state. for more information, see ulpi specification 1.1, section 3.12 (safeguarding phy input signals). interface protection can be switched off at any time after startup in order to save power, by writing the interface protect disable bit in the interface control register to 1b. 6.18.6 software reset the stulpi01 supports software reset by writ ing the reset bit in the function control register to 1b. during the software reset, dir is asserted and the pull down resistors on data lines are enabled, but the ulpi registers remain unaffect ed. software reset initializes utmi core logic only. also, during software reset, external clock detection, sdr mode selection is not performed, and clock is not turned off (pll is not re-started). note: note: software reset is not required in the startup procedure for the stulpi. the chip is ready for operation after the hardware reset procedure.
STULPI01A - stulpi01 b block description 25/44 6.18.7 high speed mode entry in high speed mode, the internal 480 mhz clock is generated by the dll, which must be calibrated any time device enters high speed mode by writing '00' to the xcvrsel field in the function control register. during the dll calibration it is not possible to accept any commands, therefore to avoid any communication problems with the controller the clock on the ulpi interface is stopped. see figure 10 for more information. figure 8. start-up sequence figure 9. resetn behavior
block description STULPI01A - stulpi01b 26/44 figure 10. high speed mode entry figure 11. uart mode entry (2.7 v)
STULPI01A - stulpi01 b block description 27/44 figure 12. uart mode exit (2.7 v)
state transitions STULPI01A - stulpi01b 28/44 7 state transitions table 12. usb state transitions signaling mode register settings resistor settings xcvrselect termselect opmode dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en general settings 3-state drivers xxbxb 01b 0b0b0b0b0b0b0b xxbxb 01b 1b1b0b0b1b1b0b power-up or v bus < v th(sessend) 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b host settings host chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b host hi-speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b host full speed x1b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b host low speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host low speed suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host low speed resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b host test_j/test_k 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral hi-speed 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b peripheral full speed 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral low speed 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral low speed suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral low speed resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b peripheral test_j/test_k 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b
STULPI01A - stulpi01 b state transitions 29/44 signaling mode register settings resistor settings xcvrselect termselect opmode dppulldown dmpulldown rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en otg device, peripheral chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hi-speed 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b otg device, peripheral full speed 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device peripheral, hs/fs resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device peripheral, test_j/test_k 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b table 12. usb state transitions (continued)
ulpi registers STULPI01A - stulpi01b 30/44 8 ulpi registers table 13. ulpi register map overview field name size (bits) address (6 bits) rd wr set clr immediate register set vendor id low 8 00h - - - vendor id high 8 01h - - - product id low 8 02h - - - product id high 8 03h - - - function control 8 04-06h 04h 05h 06h interface control 8 07-09h 07h 08h 09h otg control 8 0a-0ch 0ah 0bh 0ch usb interrupt enable rising 8 0d-0fh 0dh 0eh 0fh usb interrupt enable falling 8 10-12h 10h 11h 12h usb interrupt status register 8 13h - - - usb interrupt latch register 8 14h - - - debug 8 15h - - - scratch 8 16-18h 16h 17h 18h car kit control register 8 16-1bh 19h 1ah 1bh reserved 8 1c-2eh access extended register set (see ta b l e 1 4 )8-2fh-- reserved 8 30-3ch power control 3d-3fh extended register set address (8 bits) maps to immediate register set above 8 00-3fh reserved 8 40-ffh table 14. register access legend access code expanded name meaning rd read register can be read. read-only if this is the only mode given. wr write pattern on the data bus will be written over all bits of the register. s set pattern on the data bus is or?d with and written into the register. c clear pattern on the data bus is a mask. if a bit in the mask is set, then the corresponding register bit will be set to zero (cleared).
STULPI01A - stulpi01b ulpi registers 31/44 table 15. vendor and product id register bits access address value description vendor_id_low 7:0 rd 00h 83 h lower byte of vendor id. vendor_id_high 7:0 rd 01h 04 h upper byte of vendor id. product_id_low 7:0 rd 02h 4b h lower byte of product id number. product_id_high 7:0 rd 03h 4f h upper byte of product id number. table 16. power control register (3dh-3fh read, 3dh write, 3eh set, 3fh clear) (controls various power aspects of the usb trans) field name bits access reset description reserved 0 rd/wr/s/c 0b reserved. the link must never write a 1b to this bit. over-current_pd 1 rd/wr/s/c 1b power control of the intern al over-current circuit. 0b: enables the ove r-current circuit. 1b: disables the over-current circuit. uart_dir 2 rd/wr/s/c 0b 0b: txd on dm and rxd on dp 1b: txd on dp and rxd on dm uart_2v7 3 rd/wr/s/c 1b 0b: uart signaling at 3v3 1b: uart signaling at 2v7 reserved 7:4 rd/wr/s/c 0b reserved. the link must never write a 1b to these bits.
ulpi registers STULPI01A - stulpi01b 32/44 table 17. function control register 04h-06h(read), 04h(write), 05h(set), 06h(clear) (controls utmi function setting of the usb transceiver phy) field name bits access reset description xcvrselect 1:0 rd/wr/s/c 01b selects the required transceiver speed. 00b: enable hs transceiver 01b: enable fs transceiver 10b: enable ls transceiver 11b: enable fs transceiver for ls packets (fs preamble is automatically pre-pended) important note : every time the xcvrselect is changed to ?00?, the output ulpi clock is stopped for the time needed for internal dll calibration. termselect 2 rd/wr/s/c 0b controls the internal pull-up resistors or hs terminations. control over these resistors changes depending on xcvrselect, opmode, dppulldown and dmpulldown, as shown in ta bl e 2 4 . opmode 4:3 rd/wr/s/c 00b selects the required bit encoding style during transmit. 00b: normal operation 01b: non-driving 10b: disables bit-stuff and nrzi encoding 11b: do not automatically add sync and eop when transmitting. must be used only for hs packets. reset 5 rd/wr/s/c 0b active high transceiver reset. after the link sets this bit, stulpi01 asserts dir and reset the utmi+ core. when the reset is completed, stulpi01 de-asserts dir and automatically clears this bi t. after de-asserting dir, stulpi01 re-asserts dir and sends an rx cmd update to the link. note: if reset bit is set to ?1? and suspendm bit is set to ?0? in the same register access, suspendm bit takes higher priority and chip will enter low power mode. reset bit will be cleared. suspendm 6 rd/wr/s/c 1b active low phy suspend. puts phy into low power mode. stulpi01 automatically sets this bit to ?1? when low power mode is exited. 0b: low power mode 1b: powered note: if reset bit is set to ?1? and suspendm bit is set to ?0? in the same register access, suspendm bit takes higher priority and chip will enter low power mode. reset bit will be cleared. reserved 7 rd/wr/s/c 0b reserved
STULPI01A - stulpi01b ulpi registers 33/44 table 18. interface control register 07h-09h(read), 07h(write), 08h(set), 09h(clear) (enables alternative interface and stulpi01 features.) field name bits access reset description 6-pin fslsserialmode 0 rd/wr/s/c 0b changes the ulpi interface to 6-pin serial mode. the stulpi01 automatically clears this bit when serial mode is exited. 0b: fs/ls packets are sent using parallel interface. 1b: fs/ls packets are sent 6-pin using serial interface. 3-pin fslsserialmode 1 rd/wr/s/c 0b changes the ulpi interface to 3-pin serial mode. stulpi01 automatically clears this bit when serial mode is exited. 0b: fs/ls packets are sent using parallel interface. 1b: fs/ls packets are sent using 4-pin serial interface. carkit mode 2 rd/wr/s/c 0b stulpi01 does not support all the features of car kit mode. only the uart functionality is implemented. 0b: disables serial car kit mode. 1b: enables serial car kit mode. clocksuspendm 3 rd/wr/s/c 0b active low clock suspend. valid only in serial mode and car kit mode. powers down the inter nal clock circuitry. valid only when suspendm = 1b. stulpi01 ignores clocksuspend when suspendm = 0b. by default, the clock will not be powered in serial and car kit modes. 0b: clock will not be powered in serial and car kit modes. 1b: clock will be powered in serial and car kit modes. reserved 4 rd/wr/s/c 0b stulpi01 do not implement autoresume feature, because the clock can be restarted in less than 1ms. indicator complement 5 rd/wr/s/c 0b tells to invert the externalvbusindicator signal, generating the complement output. 0b: stulpi01 will not invert externalvbusindicator signal 1b: stulpi01 will invert externalvbusindicator signal. indicator passthru 6 rd/wr/s/c 0b controls whether the complement output is qualified with the internal vbusvalid comparator before being used in the vbus state in the rx cmd. 0b: complement output signal is qualified with the internal vbusvalid comparator. 1b: complement output signal is not qualified with the internal vbusvalid comparator. interface protect disable 7 rd/wr/s/c 0b controls circuitry for protecting the ulpi interface when the link 3-states stp and data. this bit is not intended to affect the operation of the holding state. refer to section 3.12 of ulpi specification 1.1 for more details. 0b: enables the interface protect circuit (default). 1b: disables the interface protect circuit. interface protection circuit cons ists of pull-down resistors on data and pull-up resistor on stp.
ulpi registers STULPI01A - stulpi01b 34/44 table 19. otg control register 0ah-0ch(read), 0ah(write), 0bh(set), 0ch(clear) (controls utmi + otg functions of the phy) field name bits access reset description idpullup 0 rd/wr/s/c 0b connects a pull-up to the id line and enables sampling of the signal level. 0b: disables sampling of id line. 1b: enables sampling of id line. dppulldown 1 rd/wr/s/c 1b enables the 15kohm pull-down resistor on dp. 0b: pull-down resistor not connected to dp. 1b: pull-down resistor connected to dp. dmpulldown 2 rd/wr/s/c 1b enables the 15kohm pull-down resistor on dm. 0b: pull-down resistor not connected to dm. 1b: pull-down resistor connected to dm. dischrgvbus 3 rd/wr/s/c 0b discharges v bus through a resistor. if the link sets this bit to 1, it waits for an rx cmd indicating sessend has transition from 0 to 1, and then resets this bit to 0 to stop the discharge. 0b: do not discharge v bus 1b: discharge v bus chrgvbus 4 rd/wr/s/c 0b charge v bus through a resistor. used for v bus pulsing srp. 0b: do not charge v bus 1b: charge v bus drvvbus 5 rd/wr/s/c 0b signals the internal charge pump or external supply to drive 5v on v bus . 0b: do not drive v bus (default) 1b: drive 5v on v bus drvvbus external 6 rd/wr/s/c 0b selects between the internal and the external 5v v bus supply. 0b: drive v bus using the internal charge pump (default). 1b: drive v bus using external supply. useexternal vbusindicator 7 rd/wr/s/c 0b tells stulpi01 to use an external v bus over-current indicator. 0b: use the internal otg comparator or internal v bus valid indicator (default) 1b: use external v bus valid indicator signal
STULPI01A - stulpi01b ulpi registers 35/44 table 20. usb interrupt enable rising register 0dh-0fh(read), 0dh(write), 0eh(set), 0fh(clear) (if set, the bits in this register cause an interrupt event notification to be generated when the corresponding phy signal changes from low to high. by default, all transitions are enabled. rxactive and rxerror must always be communicated immediately and so are not included in this register. interrupt circuitry can be powered down in any mode when bo th rising and falling edge enables are disabled. to ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.) field name bits access reset description host disconnect rise 0 rd/wr/s/c 1b generates an interrupt event notification when host disconnect changes from low to high. applicable only in host mode (dppulldown and dmpulldown both set to 1b). vbusvalid rise 1 rd/wr/s/c 1b generates an interrupt event notification when vbusvalid changes from low to high. sessvalid rise 2 rd/wr/s/c 1b generate an interrupt event notification when sessvalid changes from low to high. sessvalid is the same as utmi+ avalid. sessend rise 3 rd/wr/s/c 1b generates an interrupt event notification when sessend changes from low to high. id rise 4 rd/wr/s/c 1b generates an interrupt event notification when id changes from low to high. id is valid 50ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd/wr/s/c 0b reserved.
ulpi registers STULPI01A - stulpi01b 36/44 table 21. usb interrupt enable falling register address: 10h-12h (read), 10h (write), 11h (set), 12h (clear) (if set, the bits in this register cause an interrupt event notification to be generated when the corresponding phy signal changes from high to low. by default, all transitions are enabled. rxactive and rxerror must always be communicated immediately and so are not included in this register. interrupt circuitry can be powered down in any mode when bo th rising and falling edge enables are disabled. to ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.) field name bits access reset description host disconnect fall 0 rd/wr/s/c 1b generates an interrupt event notification when the host disconnect changes from high to low. applicable only in host mode. vbusvalid fall 1 rd/wr/s/c 1b generates an interrupt event notification when vbusvalid changes from high to low. sessvalid fall 2 rd/wr/s/c 1b generates an interrupt event notification when sessvalid changes from high to low. sessvalid is the same as utmi+ avalid. sessend fall 3 rd/wr/s/c 1b generates an interrupt event notification when sessend changes from high to low. id fall 4 rd/wr/s/c 1b generates an interrupt event notification when id changes from high to low. id is valid 50ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd/wr/s/c 0b reserved table 22. usb interrupt status register address: 13h (read-only) (indicates the current value of the interrupt source signal. interrupt circuitry can be powered down in any mode when both rising and falling edge enables are di sabled. to ensure interr upts are detectable when clock is powered down, the link should enable both rising and falling edges.) field name bits access reset description host disconnect 0rd0b current value of utmi+ host disconnect output. applicable only in host mode . automatically reset to 0b when low power mode is entered. vbusvalid 1 rd 0b current value of utmi+vbusvalid output. sessvalid 2rd0b current value of utmi+sessvalid output. sessvalid is the same as utmi+ avalid. sessend 3 rd 0b current value of utmi+sessend output. id 4rd0b current value of utmi+id outp ut. id is valid 50ms after idpullup is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd 0b reserved
STULPI01A - stulpi01b ulpi registers 37/44 table 23. usb interrupt latch register address: 14h (read-only with auto clear) (these bits are set by the stulpi01 when an unmasked change occurs on the corresponding internal signal. the stulpi01 will automatically clear all bits wh en the link reads this register, or when low power mode is entered. the stulpi01 also clears this register when serial mode or car kit mode is entered regardless of the value of clocksuspendm. the interrupt circuitry is powered down in any mode when both rising and falling edge enables are disabled. to ensure the interrupts are detectable when the clock is powered down, the link should e nable both rising and falling edges. the stulpi01 follows the rules in ta bl e 2 0 for setting any latch register bit. it is important to note that if the register read data is returned to the link in the same cycle that a usb interrupt latch bit is to be set, the interrupt condition is given immediately in the register read data and the latch bit is not set. note that it is optional for the link to read the usb interrupt latch register in synchronous mode because the rx cmd byte already indicates the interrupt source directly.) field name bits access reset description host disconnect latch 0rd 0b set to 1b by the stulpi01 when an unmasked event occurs on host disconnect. cleared when this register is read. applicable only in host mode. vbusvalid latch 1rd 0b set to 1b by the stulpi01 when an unmasked event occurs on vbusvalid. cleared when this register is read. sessvalid latch 2rd 0b set to 1b by the stulpi01 when an unmasked event occurs on sessvalid. cleared when this register is read. sessvalid is the same as utmi+avalid. sessend latch 3rd 0b set to 1b by the stulpi01 when an unmasked event occurs on sessend. cleared when this register is read. id latch 4rd 0b set to 1b by the stulpi01 when an unmasked event occurs on id. cleared when this register is read. id is valid 50ms after id is set to 1b, otherwise id is undefined and should be ignored. reserved 7:5 rd 0b reserved table 24. setting rules for interrupt latch register input conditions resultant value of latch register bit register read data returned in current clock cycle interrupt latch bit is to be set in current clock cycle no no 0 no yes 1 ye s n o 0 ye s ye s 0
ulpi registers STULPI01A - stulpi01b 38/44 table 25. debug register address: 15h (read-only) (indicates the current value of various signals useful for debugging) field name bits access reset description linestate0 0 rd 0b contains the current value of linestate(0) linestate1 1 rd 0b contains the current value of linestate(1) reserved 7:2 rd 0b reserved table 26. scratch register address: 16h-18h (read), 16h (write), 17h (set), 18h (clear). field name bits access reset description scratch 7:0 rd/wr/s/c 00b empty register byte for testing purposes. the software can read, write, set, and clear this register and the stulpi01 functionality will not be affected. table 27. carkit control register address: 19h-1bh (read), 19h (write), 1ah (set), 1bh (clear). field name bits access reset description reserved 0 rd/wr/s/c 0b reserved 1 rd/wr/s/c 0b txden 2 rd/wr/s/c 0b enables txd signal in car kit mode rxden 3 rd/wr/s/c 0b enables rxd signal in car kit mode reserved 4 rd/wr/s/c 0b reserved 5 rd/wr/s/c 0b reserved 6 rd/wr/s/c 0b reserved 7 rd/wr/s/c 0b
STULPI01A - stulpi01b package mechanical data 39/44 9 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
package mechanical data STULPI01A - stulpi01b 40/44 dim. mm. mil s . min. typ. max. min. typ. max. a 1.0 1.1 1.16 39 .4 4 3 . 3 45.7 a1 0.25 9 . 8 a2 0.7 8 0. 8 6 3 0.7 33 . 9 b 0.25 0. 3 00. 3 5 9 . 8 11. 8 1 3 . 8 d 3 .5 3 .6 3 .7 1 3 7. 8 141.7 145.7 d1 2.5 98 .4 e 3 .5 3 .6 3 .7 1 3 7. 8 141.7 145.7 e1 2.5 98 .4 e0.5 1 9 .7 f 0.55 21.7 tfbga 3 6 mechanical data 7 9 41410/b
STULPI01A - stulpi01b package mechanical data 41/44 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 9 0.154 bo 3 . 9 0.154 ko 1.50 0.05 9 po 3 . 9 4.1 0.154 0.161 p7. 98 .1 0. 3 11 0. 3 1 9 tape & reel tfbga 3 6 mechanical data
order codes STULPI01A - stulpi01b 42/44 10 order codes table 28. order codes order code key differences package packaging STULPI01Atbr (1) 1. all these versions need digital external clock on xi pin; xo pin must be left fl oating or grounded (crystal is not supported) . f osc =19.2mhz, csn/pwrdn=0 ?on? tfbga36 (3.6x3.6mm typ) 3000 parts per reel stulpi01btbr (1) f osc =26mhz, csn/pwrdn=0 ?on? tfbga36 (3.6x3.6mm typ) 3000 parts per reel
STULPI01A - stulpi01 b revision history 43/44 11 revision history table 29. document revision history date revision changes 20-jun-2008 1 first release.
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