 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| user?s manual v850/sb1 tm , v850/sb2 tm 32-bit single-chip microcontroller hardware pd703030a pd703034a pd703030ay pd703034ay pd703031a pd703035a pd703031ay pd703035ay pd703032a pd703036a pd703032ay pd703036ay pd703033a pd703037a pd703033ay pd703037ay pd70f3032a pd70f3035a pd70f3032ay pd70f3035ay pd70f3033a pd70f3037a pd70f3033ay pd70f3037ay printed in japan document no. u13850ej4v0um00 (4th edition) date published april 2001 n cp(k) 1998 ? 1999 , 2000
user?s manual u13850ej4v0um 2 [memo] user?s manual u13850ej4v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. v850 family, v850/sa1, and v850/sb1, v850/sb2, iebus, and inter equipment bus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. 4 user?s manual u13850ej4v0um license not needed: pd70f3032a, 70f3032ay, 70f3033a, 70f3033ay, 70f3035a, 70f3035ay, 70f3037a, 70f3037ay the customer must judge the need for license: pd703030a, 703030ay, 703031a, 703031ay, 703032a, 703032ay, 703033a, 703033ay, 703034a, 703034ay, 703035a, 703035ay, 703036a, 703036ay, 703037a, 703037ay m8e 00. 4 the information in this document is current as of january, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? user?s manual u13850ej4v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2 6 user?s manual u13850ej4v0um major revisions in this edition page description p. 33 modification of 1.2.3 ordering information (v850/sb1) p. 43 modification of 1.3.3 ordering information (v850/sb2) p. 62 modification of description in 2.3 (5) p40 to p47 (port 4) p. 63 modification of description in 2.3 (6) p50 to p57 (port 5) p. 63 modification of description in 2.3 (7) p60 to p65 (port 6) p. 64 modification of description in 2.3 (9) p90 to p96 (port 9) p. 67 modification of caution in 2.3 (11) (b) (ii) wait (wait) p. 67 addition of 2.3 (14) clkout (clock out) p. 154 addition of 5.8 (1) acknowledging interrupt servicing after execution of ei instruction p. 173 addition of 6.6 notes on power save function p. 177 modification of caution in 7.1.3 (2) capture/compare registers n0 (cr00, cr10) p. 178 modification of caution in 7.1.3 (3) capture/compare registers n1 (cr01, cr11) p. 206 modification of figure 7-34 data hold timing of capture register p. 206 addition of 7.2.7 (6) (c) one-shot pulse output function p. 348 modification of figure 11-2 a/d converter mode register 1 (adm1) p. 356 addition of description in 11.5 low power consumption mode p. 423 addition of caution in chapter 18 flash memory p. 444 addition of table 19-5 acknowledge signal output condition of control field p. 452 addition of description 19.1.8 bit format p. 457 modification of caution in 19.3.2 (1) (a) communication enable flag (eniebus) p. 463 addition of note in figure 19-18 timing of intie2 interrupt generation in locked state (for (4) and (5)) p. 464 addition of remark in 19.3.2 (6) iebus telegraph length register (dlr) p. 466 addition of remark in 19.3.2 (7) iebus data register (dr) p. 466 addition of description in 19.3.2 (7) (a) when transmission unit p. 467 modification of description in 19.3.2 (8) (a) slave request flag (slvrq) p. 468 addition of caution in 19.3.2 (8) (b) arbitration result flag (arbit) p. 469 addition of description for caution in 19.3.2 (8) (e) lock status flag (lock) p. 470 addition of table 19-8 reset condition of each flag of isr register p. 480 addition of 19.4.3 communication error source processing list p. 490 modification of figure 19-34 master transmission (interval of interrupt occurrence) p. 491 modification of figure 19-35 master reception (interval of interrupt occurrence) p. 492 modification of figure 19-36 slave transmission (interval of interrupt occurrence) p. 493 modification of figure 19-37 slave reception (interval of interrupt occurrence) the mark shows major revised points. user?s manual u13850ej4v0um 7 introduction readers this manual is intended for users who wish to understand the functions of the v850/sb1 and v850/sb2 and design application systems using the v850/sb1 or v850/sb2. purpose this manual is intended to give users to an understanding of the hardware functions described in the organization below. organization the v850/sb1, v850/sb2 user?s manual is divided into two parts: hardware (this manual) and architecture (v850 family tm user?s manual architecture). hardware architecture ? pin function ? cpu function ? internal peripheral function ? flash memory programming ? iebus controller (v850/sb2 only) ? data type ? register set ? instruction format and instruction set ? interrupt and exception ? pipeline operation how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find out the details of a register whose name is known: refer to appendix a register index . to find out the details of a function, etc., whose name is known: refer to appendix c index . to understand the details of a instruction function: refer to v850 family user?s manual architecture available separately. how to read register formats: names of bits whose numbers are enclosed in a square are defined in the device file under reserved words. to understand the overall functions of the v850/sb1 and v850/sb2: read this manual in accordance with the contents . 8 user?s manual u13850ej4v0um conventions data significance: higher digits on the left and lower digits on the right active low: xxx (overscore over pin or si gnal name) memory map address: higher addresses at the top and lower addresses at the bottom note : footnote for items marked with note in the text caution : information requiring particular attention remark : supplementary information number representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefixes indicating power of 2 (address space, memory capacity): k (kilo): 2 10 ? 1024 m (mega): 2 20 ? 1024 2 g (giga): 2 30 ? 1024 3 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. related documents for v850/sb1 and v850/sb2 document name document no. v850 family user?s manual architecture u10243e v850/sb1, v850/sb2 user?s manual hardware this manual pd703031a, 703031ay, 703033a, 703033ay, 70f3033a, 70f3033ay data sheet u14734e pd703032a, 703032ay, 70f3032a, 70f3032ay data sheet u14893e pd703034a, 703034ay, 703035a, 703035ay, 70f3035a, 70f3035ay data sheet u14780e pd703037a, 703037ay, 70f3037a, 70f3037ay data sheet u14894e user?s manual u13850ej4v0um 9 related documents for development tool (user?s manual) document name document no. ie-703002-mc (in-circuit emulator) u11595e ie-703037-mc-em1 (in-circuit emulator option board) u14151e operation u14568e c language u14566e assembly language u14567e ca850 (ver. 2.30 or later) (c compiler package) project manager u14569e id850 (ver. 2.20 or later) (integrated debugger) operation windows tm based u14580e sm850 (ver. 2.20 or later) (system simulator) operation windows based u14782e sm850 (ver. 2.00 or later) (system simulator) external part user open interface specifications u14873e basics u13430e installation u13410e rx850 (ver. 3.13 or later) (real-time os) technical u13431e fundamental u13773e installation u13774e rx850 pro (ver. 3.13) (real-time os) technical u13772e rd850 (ver. 3.01) (task debugger) u13737e rd850 pro (ver. 3.01) (task debugger) u13916e az850 (ver. 3.0) (system performance analyzer) operation u14410e pg-fp3 (flash memory programmer) u13502e user?s manual u13850ej4v0um 10 contents chapter 1 introduction ..................................................................................................... ..... 29 1.1 general ..................................................................................................................... ............. 29 1.2 v850/sb1 .................................................................................................................... ........... 31 1.2.1 features (v850/sb1) ....................................................................................................... ........31 1.2.2 application fields (v850/sb1) ............................................................................................. .....32 1.2.3 ordering information (v850/sb1)........................................................................................... ..33 1.2.4 pin configuration (top view) (v850/sb1) ..................................................................................3 4 1.2.5 function blocks (v850/sb1) ................................................................................................ ....37 1.3 v850/sb2 .................................................................................................................... ........... 41 1.3.1 features (v850/sb2) ....................................................................................................... ........41 1.3.2 application fields (v850/sb2) ............................................................................................. .....42 1.3.3 ordering information (v850/sb2)........................................................................................... ..43 1.3.4 pin configuration (top view) (v850/sb2) ..................................................................................4 4 1.3.5 function blocks (v850/sb2) ................................................................................................ ....47 chapter 2 pin functions................................................................................................... ...... 51 2.1 list of pin functions ....................................................................................................... ..... 51 2.2 pin states .................................................................................................................. ............ 58 2.3 description of pin functions............................................................................................... 5 9 2.4 i/o circuit types, i/o buffer power supply and connection of unused pins ................ 69 2.5 i/o circuit of pins......................................................................................................... ......... 71 chapter 3 cpu functions ................................................................................................... .... 73 3.1 features.................................................................................................................... ............. 73 3.2 cpu register set ............................................................................................................ ...... 74 3.2.1 program register set ...................................................................................................... ..........75 3.2.2 system register set ....................................................................................................... ...........76 3.3 operation modes ............................................................................................................. ..... 78 3.4 address space ............................................................................................................... ....... 79 3.4.1 cpu address space ......................................................................................................... ........79 3.4.2 image ..................................................................................................................... ..................80 3.4.3 wrap-around of cpu address space .......................................................................................81 3.4.4 memory map ................................................................................................................ ............82 3.4.5 area ...................................................................................................................... ...................83 3.4.6 external expansion mode................................................................................................... ......90 3.4.7 recommended use of address space .....................................................................................93 3.4.8 peripheral i/o registers .................................................................................................. ..........95 3.4.9 specific registers........................................................................................................ ............103 chapter 4 bus control function.................................................................................... 106 4.1 features.................................................................................................................... ........... 106 4.2 bus control pins and control register............................................................................ 106 4.2.1 bus control pins .......................................................................................................... ...........106 user?s manual u13850ej4v0um 11 4.2.2 control register .......................................................................................................... ............ 107 4.3 bus access .................................................................................................................. ....... 107 4.3.1 number of access clocks................................................................................................... .... 107 4.3.2 bus width ................................................................................................................. .............. 108 4.4 memory block function..................................................................................................... 10 9 4.5 wait function............................................................................................................... ....... 110 4.5.1 programmable wait function ................................................................................................ .. 110 4.5.2 external wait function.................................................................................................... ......... 111 4.5.3 relationship between programmable wait and external wait................................................. 111 4.6 idle state insertion function ............................................................................................. 11 2 4.7 bus hold function ........................................................................................................... .. 113 4.7.1 outline of function....................................................................................................... ........... 113 4.7.2 bus hold procedure........................................................................................................ ........ 114 4.7.3 operation in power save mode .............................................................................................. 114 4.8 bus timing .................................................................................................................. ........ 115 4.9 bus priority ................................................................................................................ ......... 122 4.10 memory boundary operation condition .......................................................................... 123 4.10.1 program space ............................................................................................................ .......... 123 4.10.2 data space............................................................................................................... .............. 123 chapter 5 interrupt/exception processing function .......................................... 124 5.1 outline ..................................................................................................................... ............ 124 5.1.1 features.................................................................................................................. ............... 124 5.2 non-maskable interrupt ..................................................................................................... 1 27 5.2.1 operation ................................................................................................................. .............. 128 5.2.2 restore ................................................................................................................... ............... 130 5.2.3 np flag ................................................................................................................... ................ 131 5.2.4 noise eliminator of nmi pin............................................................................................... ..... 131 5.2.5 edge detection function of nmi pin........................................................................................ 132 5.3 maskable interrupts ......................................................................................................... .. 133 5.3.1 operation ................................................................................................................. .............. 133 5.3.2 restore ................................................................................................................... ............... 135 5.3.3 priorities of maskable interrupts ......................................................................................... ... 136 5.3.4 interrupt control register (xxicn) ........................................................................................ .... 139 5.3.5 in-service priority register (ispr)....................................................................................... .... 142 5.3.6 maskable interrupt status flag............................................................................................ .... 142 5.3.7 watchdog timer mode register (wdtm)................................................................................ 143 5.3.8 noise elimination ......................................................................................................... .......... 143 5.3.9 edge detection function ................................................................................................... ...... 145 5.4 software exception .......................................................................................................... .. 146 5.4.1 operation ................................................................................................................. .............. 146 5.4.2 restore ................................................................................................................... ............... 147 5.4.3 ep flag ................................................................................................................... ................ 148 5.5 exception trap .............................................................................................................. ..... 148 5.5.1 illegal op code definition ................................................................................................ ........ 148 5.5.2 operation ................................................................................................................. .............. 148 5.5.3 restore ................................................................................................................... ............... 150 user?s manual u13850ej4v0um 12 5.6 priority control ............................................................................................................ ....... 151 5.6.1 priorities of interrupts and exceptions................................................................................... .151 5.6.2 multiple interrupt servicing .............................................................................................. .......151 5.7 interrupt latency time ...................................................................................................... . 154 5.8 periods where interrupt is not acknowledged ............................................................... 154 5.9 key interrupt function ...................................................................................................... . 156 chapter 6 clock generation function ........................................................................ 158 6.1 outline ..................................................................................................................... ............ 158 6.2 composition................................................................................................................. ....... 159 6.3 clock output function....................................................................................................... 160 6.3.1 control registers......................................................................................................... ............160 6.4 power save functions ....................................................................................................... 1 64 6.4.1 outline................................................................................................................... .................164 6.4.2 halt mode ................................................................................................................. ...........165 6.4.3 idle mode ................................................................................................................. ............168 6.4.4 software stop mode ........................................................................................................ ....170 6.5 oscillation stabilization time............................................................................................ 17 2 6.6 notes on power save function......................................................................................... 173 chapter 7 timer/counter function ................................................................................. 174 7.1 16-bit timer (tm0, tm1)..................................................................................................... 174 7.1.1 outline................................................................................................................... .................174 7.1.2 function .................................................................................................................. ...............174 7.1.3 configuration............................................................................................................. .............176 7.1.4 timer 0, 1 control registers .............................................................................................. ......179 7.2 16-bit timer operation ...................................................................................................... . 187 7.2.1 operation as interval timer (16 bits)..................................................................................... ..187 7.2.2 ppg output operation ...................................................................................................... ......189 7.2.3 pulse width measurement................................................................................................... ...190 7.2.4 operation as external event counter ......................................................................................1 97 7.2.5 operation to output square wave ........................................................................................... 198 7.2.6 operation to output one-shot pulse........................................................................................ 200 7.2.7 cautions.................................................................................................................. ...............205 7.3 8-bit timer (tm2 to tm7) ................................................................................................... 2 09 7.3.1 functions ................................................................................................................. ..............209 7.3.2 configuration............................................................................................................. .............210 7.3.3 timer n control register .................................................................................................. ........212 7.4 8-bit timer operation ....................................................................................................... .. 218 7.4.1 operation as an interval timer (8-bit operation) .....................................................................218 7.4.2 operation as external event counter ......................................................................................2 21 7.4.3 operation as square wave output (8-bit resolution) ...............................................................222 7.4.4 operation as 8-bit pwm output............................................................................................. .223 7.4.5 operation as interval timer (16 bits)..................................................................................... ..227 7.4.6 cautions.................................................................................................................. ...............229 user?s manual u13850ej4v0um 13 chapter 8 watch timer ..................................................................................................... .... 230 8.1 function .................................................................................................................... .......... 230 8.2 configuration ............................................................................................................... ....... 231 8.3 watch timer control register........................................................................................... 232 8.4 operation................................................................................................................... .......... 234 8.4.1 operation as watch timer.................................................................................................. ..... 234 8.4.2 operation as interval timer............................................................................................... ...... 234 8.4.3 cautions.................................................................................................................. ............... 235 chapter 9 watchdog timer................................................................................................. 2 36 9.1 functions ................................................................................................................... ......... 236 9.2 configuration ............................................................................................................... ....... 238 9.3 watchdog timer control register .................................................................................... 238 9.4 operation................................................................................................................... .......... 241 9.4.1 operation as watchdog timer............................................................................................... .. 241 9.4.2 operation as interval timer............................................................................................... ...... 242 9.5 standby function control register.................................................................................. 243 chapter 10 serial interface function ......................................................................... 244 10.1 overview ................................................................................................................... .......... 244 10.2 3-wire serial i/o (csi0 to csi3) ......................................................................................... 24 4 10.2.1 configuration ............................................................................................................ ............. 245 10.2.2 csin control registers ................................................................................................... ......... 246 10.2.3 operations ............................................................................................................... .............. 249 10.3 i 2 c bus.......................................................................................................................... ....... 252 10.3.1 configuration ............................................................................................................ ............. 255 10.3.2 i 2 c control register ............................................................................................................. .... 257 10.3.3 i 2 c bus mode functions.......................................................................................................... 2 68 10.3.4 i 2 c bus definitions and control methods ................................................................................ 269 10.3.5 i 2 c interrupt requests (intiicn) ............................................................................................. 276 10.3.6 interrupt request (intiicn) generation timing and wait control .............................................. 294 10.3.7 address match detection method .......................................................................................... 2 95 10.3.8 error detection .......................................................................................................... ............. 295 10.3.9 extension code ........................................................................................................... ........... 295 10.3.10 arbitration ............................................................................................................. ................. 296 10.3.11 wake up function........................................................................................................ ........... 298 10.3.12 communication reservation ............................................................................................... .... 299 10.3.13 cautions................................................................................................................ ................. 302 10.3.14 communication operations ................................................................................................ .... 303 10.3.15 timing of data communication............................................................................................ ... 305 10.4 asynchronous serial interface (uart0, uart1) ............................................................ 312 10.4.1 configuration ............................................................................................................ ............. 312 10.4.2 uartn control registers .................................................................................................. ...... 314 10.4.3 operations ............................................................................................................... .............. 319 10.4.4 standby function ......................................................................................................... ........... 331 10.5 3-wire variable-length serial i/o (csi4) .......................................................................... 332 10.5.1 configuration ............................................................................................................ ............. 332 user?s manual u13850ej4v0um 14 10.5.2 csi4 control registers ................................................................................................... .........335 10.5.3 operations ............................................................................................................... ..............339 chapter 11 a/d converter .................................................................................................. . 344 11.1 function................................................................................................................... ............ 344 11.2 configuration .............................................................................................................. ........ 346 11.3 control registers.......................................................................................................... ...... 348 11.4 operation.................................................................................................................. ........... 351 11.4.1 basic operation .......................................................................................................... ............351 11.4.2 input voltage and conversion result ...................................................................................... .353 11.4.3 a/d converter operation mode ............................................................................................. ..354 11.5 low power consumption mode........................................................................................ 356 11.6 cautions ................................................................................................................... ........... 356 chapter 12 dma functions.................................................................................................. . 360 12.1 functions.................................................................................................................. ........... 360 12.2 transfer completion interrupt request ........................................................................... 360 12.3 control registers.......................................................................................................... ...... 360 12.3.1 dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) ............................................360 12.3.2 dma internal ram address registers 0 to 5 (dra0 to dra5) ...............................................361 12.3.3 dma byte count registers 0 to 5 (dbc0 to dbc5) .................................................................366 12.3.4 dma start factor expansion register (dmas) .........................................................................366 12.3.5 dma channel control registers 0 to 5 (dchc0 to dchc5) ....................................................367 chapter 13 real-time output function (rto) ............................................................ 369 13.1 function................................................................................................................... ............ 369 13.2 configuration .............................................................................................................. ........ 370 13.3 rto control registers...................................................................................................... . 371 13.4 operation.................................................................................................................. ........... 373 13.5 usage ...................................................................................................................... ............. 374 13.6 cautions ................................................................................................................... ........... 374 chapter 14 port function .................................................................................................. . 375 14.1 port configuration ......................................................................................................... ..... 375 14.2 port pin function.......................................................................................................... ...... 375 14.2.1 port 0 ................................................................................................................... ..................375 14.2.2 port 1 ................................................................................................................... ..................380 14.2.3 port 2 ................................................................................................................... ..................384 14.2.4 port 3 ................................................................................................................... ..................389 14.2.5 ports 4 and 5............................................................................................................ ..............393 14.2.6 port 6 ................................................................................................................... ..................396 14.2.7 ports 7 and 8............................................................................................................ ..............399 14.2.8 port 9 ................................................................................................................... ..................401 14.2.9 port 10 .................................................................................................................. .................404 14.2.10 port 11 ................................................................................................................ ..................408 14.3 setting when port pin is used for alternate function ................................................... 412 user?s manual u13850ej4v0um 15 chapter 15 reset function ................................................................................................. 416 15.1 general .................................................................................................................... ............ 416 15.2 pin operations ............................................................................................................. ....... 416 chapter 16 regulator....................................................................................................... .... 417 16.1 outline .................................................................................................................... ............. 417 16.2 operation.................................................................................................................. ........... 417 chapter 17 rom correction function .......................................................................... 418 17.1 general .................................................................................................................... ............ 418 17.2 rom correction peripheral i/o registers ........................................................................ 419 17.2.1 correction control register (corcn) ..................................................................................... 4 19 17.2.2 correction request register (corrq).................................................................................... 42 0 17.2.3 correction address registers 0 to 3 (corad0 to corad3) ................................................. 421 chapter 18 flash memory ................................................................................................... 423 18.1 features................................................................................................................... ............ 423 18.1.1 erasing unit............................................................................................................. ............... 423 18.1.2 write/read time .......................................................................................................... ............ 424 18.2 writing with flash programmer ........................................................................................ 424 18.3 programming environment ............................................................................................... 425 18.4 communication system .................................................................................................... 425 18.5 pin connection ............................................................................................................. ...... 428 18.5.1 v pp pin ........................................................................................................................... ........ 428 18.5.2 serial interface pin ..................................................................................................... ............ 428 18.5.3 reset pin ................................................................................................................ ............. 431 18.5.4 port pin (including nmi) ................................................................................................. ........ 431 18.5.5 other signal pins........................................................................................................ ............ 431 18.5.6 power supply ............................................................................................................. ............ 431 18.6 programming method ........................................................................................................ 4 32 18.6.1 flash memory control ..................................................................................................... ....... 432 18.6.2 flash memory programming mode........................................................................................ 433 18.6.3 selection of communication mode......................................................................................... 4 34 18.6.4 communication command .................................................................................................... . 434 18.6.5 resources used........................................................................................................... .......... 435 chapter 19 iebus controller (v850/sb2) ....................................................................... 436 19.1 iebus controller function................................................................................................. 4 36 19.1.1 communication protocol of iebus........................................................................................ ... 436 19.1.2 determination of bus mastership (arbitration) ......................................................................... 4 37 19.1.3 communication mode ..................................................................................................... ........ 437 19.1.4 communication address .................................................................................................. ....... 438 19.1.5 broadcasting communication ............................................................................................. ..... 438 19.1.6 transfer format of iebus ............................................................................................... .......... 439 19.1.7 transfer data .......................................................................................................... ................. 449 19.1.8 bit format............................................................................................................. .................... 452 user?s manual u13850ej4v0um 16 19.2 iebus controller configuration......................................................................................... 453 19.3 internal registers of iebus controller ............................................................................. 455 19.3.1 internal register list ................................................................................................. .................455 19.3.2 internal registers..................................................................................................... .................456 19.4 interrupt operations of iebus controller ......................................................................... 478 19.4.1 interrupt control block................................................................................................ ..............478 19.4.2 interrupt source list.................................................................................................. ................479 19.4.3 communication error source processing list ...........................................................................48 0 19.5 interrupt generation timing and main cpu processing ................................................ 482 19.5.1 master transmission .................................................................................................... ............482 19.5.2 master reception....................................................................................................... ...............484 19.5.3 slave transmission ..................................................................................................... .............486 19.5.4 slave reception........................................................................................................ ................488 19.5.5 interval of occurrence of interrupt for iebus control ................................................................49 0 appendix a register index ................................................................................................. .. 494 appendix b instruction set list....................................................................................... 501 appendix c index ........................................................................................................... ............ 508 user?s manual u13850ej4v0um 17 list of figures (1/9) figure no. title page 3-1 cpu register set ............................................................................................................ ................................74 3-2 program counter (pc)........................................................................................................ .............................75 3-3 interrupt source register (ecr)............................................................................................. .........................76 3-4 program status word (psw) ................................................................................................... .......................77 3-5 cpu address space........................................................................................................... .............................79 3-6 image on address space ...................................................................................................... ..........................80 3-7 program space............................................................................................................... .................................81 3-8 data space .................................................................................................................. ....................................81 3-9 memory map .................................................................................................................. ..................................82 3-10 internal rom area (128 kb)................................................................................................. ...........................83 3-11 internal rom/flash memory area (256 kb) .................................................................................... ................83 3-12 internal rom area (384 kb)................................................................................................. ...........................84 3-13 internal rom/flash memory area (512 kb) .................................................................................... ................84 3-14 internal ram area (12 kb) .................................................................................................. ............................86 3-15 internal ram area (16 kb) .................................................................................................. ............................86 3-16 internal ram area (20 kb) .................................................................................................. ............................87 3-17 internal ram area (24 kb) .................................................................................................. ............................87 3-18 internal peripheral i/o area ............................................................................................... ..............................88 3-19 external memory area (when expanded to 64 k, 256 k, or 1 mb)............................................................... ..89 3-20 external memory area (when expanded to 4 mb)............................................................................... ...........90 3-21 memory expansion mode register (mm) format ................................................................................. ...........91 3-22 memory address output mode register (mam) format........................................................................... .......92 3-23 application of wrap-around................................................................................................. ............................93 3-24 recommended memory map (flash memory version) .............................................................................. .....94 3-25 command register (prcmd) ................................................................................................... ....................105 3-26 system status register (sys)............................................................................................... ........................105 4-1 system control register (syc) ............................................................................................... ......................107 4-2 byte access (8 bits)........................................................................................................ ...............................108 4-3 halfword access (16 bits)................................................................................................... ...........................108 4-4 word access (32 bits) ....................................................................................................... ............................108 4-5 memory block ................................................................................................................ ................................109 4-6 data wait control register (dwc)............................................................................................ ....................110 4-7 wait control................................................................................................................ ...................................111 4-8 example of inserting wait states ............................................................................................ ......................111 4-9 bus cycle control register (bcc)............................................................................................ .....................112 4-10 bus hold procedure......................................................................................................... ..............................114 4-11 memory read ................................................................................................................ ................................115 4-12 memory write ............................................................................................................... .................................119 4-13 bus hold timing ............................................................................................................ ................................121 user?s manual u13850ej4v0um 18 list of figures (2/9) figure no. title page 5-1 non-maskable interrupt servicing............................................................................................ ..................... 128 5-2 acknowledging non-maskable interrupt request ................................................................................ ......... 129 5-3 reti instruction processing ................................................................................................. ........................ 130 5-4 np flag (np)................................................................................................................ ................................. 131 5-5 rising edge specification register 0 (egp0) format .......................................................................... ........ 132 5-6 falling edge specification register 0 (egn0) format......................................................................... ......... 132 5-7 maskable interrupt servicing ................................................................................................ ........................ 134 5-8 reti instruction processing ................................................................................................. ........................ 135 5-9 example of interrupt nesting service ........................................................................................ ................... 137 5-10 example of servicing interrupt requests generated simultaneously .......................................................... 1 39 5-11 interrupt control register (xxicn) format.................................................................................. ................... 140 5-12 in-service priority register (ispr) format ................................................................................. .................. 142 5-13 interrupt disable flag (id)................................................................................................ ............................. 142 5-14 watchdog timer mode register (wdtm) format ................................................................................. ....... 143 5-15 noise elimination control register (ncc) ................................................................................... ................. 144 5-16 software exception processing .............................................................................................. ...................... 146 5-17 reti instruction processing ................................................................................................ ......................... 147 5-18 ep flag (ep) ............................................................................................................... .................................. 148 5-19 illegal op code ............................................................................................................ ................................. 148 5-20 exception trap processing .................................................................................................. ......................... 149 5-21 reti instruction processing ................................................................................................ ......................... 150 5-22 pipeline operation at interrupt request acknowledgement .................................................................... ..... 154 5-23 key return mode register (krm) ............................................................................................. ................... 156 5-24 key return block diagram................................................................................................... ......................... 157 6-1 clock generator............................................................................................................. ............................... 159 6-2 format of processor clock control register (pcc) ............................................................................ ......... 160 6-3 format of power save control register (psc)................................................................................. ............ 162 6-4 format of oscillation stabilization time selection register (osts) .......................................................... .. 163 6-5 oscillation stabilization time .............................................................................................. .......................... 172 7-1 block diagram of tm0 and tm1 ................................................................................................ ................... 175 7-2 16-bit timer mode control registers 0, 1 (tmc0, tmc1) ....................................................................... ..... 180 7-3 capture/compare control registers 0, 1 (crc0, crc1)......................................................................... .... 181 7-4 16-bit timer output control registers 0, 1 (toc0, toc1)..................................................................... ...... 182 7-5 prescaler mode register 00 (prm00) .......................................................................................... ................ 183 7-6 prescaler mode register 01 (prm01) .......................................................................................... ................ 184 7-7 prescaler mode register 10 (prm10) .......................................................................................... ................ 185 7-8 prescaler mode register 11 (prm11) .......................................................................................... ................ 186 7-9 control register settings when tmn operates as interval timer............................................................... . 187 user?s manual u13850ej4v0um 19 list of figures (3/9) figure no. title page 7-10 configuration of interval timer ............................................................................................ ..........................188 7-11 timing of interval timer operation ......................................................................................... .......................188 7-12 control register settings in ppg output operation.......................................................................... ............189 7-13 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................................... ..................................190 7-14 configuration for pulse width measurement with-free running counter.....................................................191 7-15 timing of pulse width measurement with free-running counter and one capture register (with both edges specified).................................................................................................... .......................191 7-16 control register settings for measurement of two pulse widths with free-running counter.....................192 7-17 crn1 capture operation with rising edge specified .......................................................................... .........193 7-18 timing of pulse width measurement with free-running counter (with both edges specified) ...................193 7-19 control register settings for pulse width measurement with free-running counter and two capture registers ...................................................................................................................... .................................194 7-20 timing of pulse width measurement with free-running counter and two capture registers (with both edge specified) ..................................................................................................... .......................195 7-21 control register settings for pulse width measurement by restarting ........................................................ 196 7-22 timing of pulse width measurement by restarting (with rising edge specified).........................................196 7-23 control register settings in external event counter mode ................................................................... ........197 7-24 configuration of external event counter .................................................................................... ...................198 7-25 timing of external event counter operation (with rising edge specified) ...................................................1 98 7-26 control register settings in square wave output mode ....................................................................... .......199 7-27 timing of square wave output operation ..................................................................................... ...............200 7-28 control register settings for one-shot pulse output with software trigger.................................................2 01 7-29 timing of one-shot pulse output operation with software trigger ............................................................ ..202 7-30 control register settings for one-shot pulse output with external trigger.................................................. 203 7-31 timing of one-shot pulse output operation with external trigger (with rising edge specified) .................204 7-32 start timing of 16-bit timer register n .................................................................................... .....................205 7-33 timing after changing compare register during timer count operation....................................................205 7-34 data hold timing of capture register....................................................................................... ....................206 7-35 operation timing of ovfn flag.............................................................................................. .......................207 7-36 block diagram of tm2 to tm7 ................................................................................................ .......................210 7-37 tm2, tm3 timer clock selection registers 20, 21, 30, 31 (tcl20, tcl21, tcl30, and tcl31) ................213 7-38 tm4, tm5 timer clock selection registers 40, 41, 50, 51 (tcl40, tcl41, tcl50, and tcl51) ................214 7-39 tm6, tm7 timer clock selection registers 60, 61, 70, 71 (tcl60, tcl61, tcl70, and tcl71) ................215 7-40 8-bit timer mode control registers 2 to 7 (tmc2 to tmc7)................................................................... ......217 7-41 timing of interval timer operation ......................................................................................... .......................218 7-42 timing of external event counter operation (when rising edge is set)......................................................2 21 7-43 square wave output operation timing ........................................................................................ ................222 7-44 timing of pwm output ....................................................................................................... ...........................225 7-45 timing of operation based on crn0 transitions .............................................................................. ............226 user?s manual u13850ej4v0um 20 list of figures (4/9) figure no. title page 7-46 cascade connection mode with 16-bit resolution ............................................................................. .......... 228 7-47 start timing of timer n .................................................................................................... ............................. 229 7-48 timing after compare register changes during timer count operation .................................................... 229 8-1 block diagram of watch timer ................................................................................................ ..................... 230 8-2 watch timer mode control register (wtnm) .................................................................................... .......... 232 8-3 watch timer clock selection register (wtncs)............................................................................... ......... 233 8-4 operation timing of watch timer/interval timer .............................................................................. ............ 235 8-5 watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) ........................................ 235 9-1 block diagram of watchdog timer ............................................................................................. .................. 236 9-2 oscillation stabilization time selection register (osts).................................................................... ......... 238 9-3 watchdog timer clock selection register (wdcs).............................................................................. ....... 239 9-4 watchdog timer mode register (wdtm)......................................................................................... ............ 240 9-5 oscillation stabilization time selection register (osts).................................................................... ......... 243 10-1 block diagram of 3-wire serial i/o......................................................................................... ...................... 245 10-2 serial operation mode registers 0 to 3 (csim0 to csim3).................................................................... ...... 247 10-3 serial clock selection registers 0 to 3 (csis0 to csis3)................................................................... ......... 248 10-4 csimn setting (operation stop mode) ........................................................................................ ................. 249 10-5 csimn setting (3-wire serial i/o mode)..................................................................................... .................. 250 10-6 timing of 3-wire serial i/o mode........................................................................................... ....................... 251 10-7 block diagram of i 2 c.............................................................................................................................. ....... 253 10-8 serial bus configuration example using i 2 c bus ......................................................................................... 254 10-9 iic control register n (iiccn) ............................................................................................ .......................... 258 10-10 iic status register n (iicsn) ........................................................................................... ........................... 262 10-11 iic clock selection register n (iiccln)................................................................................... ..................... 265 10-12 iic function expansion register n (iicxn) ................................................................................. .................. 266 10-13 iic clock expansion register n (iiccen) ................................................................................... .................. 266 10-14 iic shift register n (iicn)............................................................................................... ............................... 268 10-15 slave address register n (svan)........................................................................................... ...................... 268 10-16 pin configuration diagram................................................................................................. ........................... 269 10-17 i 2 c bus?s serial data transfer timing ............................................................................................ .............. 269 10-18 start conditions .......................................................................................................... .................................. 270 10-19 address................................................................................................................... ...................................... 270 10-20 transfer direction specification .......................................................................................... .......................... 271 10-21 ack signal................................................................................................................ .................................... 272 10-22 stop condition ............................................................................................................ .................................. 273 10-23 wait signal............................................................................................................... ..................................... 274 10-24 arbitration timing example................................................................................................ ........................... 297 user?s manual u13850ej4v0um 21 list of figures (5/9) figure no. title page 10-25 communication reservation timing.......................................................................................... ....................300 10-26 timing for accepting communication reservations ........................................................................... ...........300 10-27 communication reservation flow chart ...................................................................................... .................301 10-28 master operation flow chart............................................................................................... ..........................303 10-29 slave operation flow chart................................................................................................ ...........................304 10-30 example of master to slave communication (when 9-clock wait is selected for both master and slave) .306 10-31 example of slave to master communication (when 9-clock wait is selected for both master and slave) .309 10-32 block diagram of uartn.................................................................................................... ...........................313 10-33 asynchronous serial interface mode registers 0, 1 (asim0, asim1) .......................................................... .315 10-34 asynchronous serial interface status registers 0, 1 (asis0, asis1)........................................................ ...316 10-35 baud rate generator control registers 0, 1 (brgc0, brgc1)................................................................. ..317 10-36 baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) ...........................................318 10-37 asimn setting (operation stop mode) ....................................................................................... ...................319 10-38 asimn setting (asynchronous serial interface mode)........................................................................ ...........320 10-39 asisn setting (asynchronous serial interface mode) ........................................................................ ...........321 10-40 brgcn setting (asynchronous serial interface mode) ........................................................................ .........322 10-41 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) .................................................323 10-42 error tolerance (when k = 16), including sampling errors.................................................................. .........325 10-43 format of transmit/receive data in asynchronous serial interface .......................................................... ...326 10-44 timing of asynchronous serial interface transmit completion interrupt ..................................................... .328 10-45 timing of asynchronous serial interface receive completion interrupt ...................................................... .329 10-46 receive error timing ...................................................................................................... ...............................330 10-47 block diagram of csi4 ..................................................................................................... .............................333 10-48 variable-length serial i/o shift register 4 (sio4) ........................................................................ ................333 10-49 when transfer bit length other than 16 bits is set ........................................................................ ............334 10-50 variable-length serial control register 4 (csim4) ......................................................................... ..............335 10-51 variable-length serial setting register 4 (csib4)......................................................................... ...............336 10-52 baud rate generator source clock selection register 4 (brgcn4)...........................................................3 37 10-53 baud rate generator output clock selection register 4 (brgck4)............................................................ 338 10-54 csim4 setting (operation stop mode) ....................................................................................... ...................339 10-55 csim4 setting (3-wire variable-length serial i/o mode) .................................................................... .........340 10-56 csib4 setting (3-wire variable-length serial i/o mode).................................................................... ..........341 10-57 timing of 3-wire variable-length serial i/o mode .......................................................................... ..............342 10-58 timing of 3-wire variable-length serial i/o mode (when csib4 = 08h) .....................................................34 3 11-1 block diagram of a/d converter............................................................................................. .......................345 11-2 a/d converter mode register 1 (adm1) ....................................................................................... ................348 11-3 analog input channel specification register (ads).......................................................................... ............350 11-4 a/d converter mode register 2 (adm2) ....................................................................................... ................350 11-5 basic operation of a/d converter ........................................................................................... ......................352 user?s manual u13850ej4v0um 22 list of figures (6/9) figure no. title page 11-6 relationship between analog input voltage and a/d conversion result..................................................... 353 11-7 a/d conversion by hardware start (with falling edge specified) ............................................................. ... 354 11-8 a/d conversion by software start ........................................................................................... ..................... 355 11-9 handling of analog input pin ............................................................................................... ......................... 357 11-10 a/d conversion end interrupt generation timing............................................................................ ............. 358 11-11 handling of av dd pin ........................................................................................................................... ......... 359 12-1 format of dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) ................................................ 360 12-2 format of dma internal ram address registers 0 to 5 (dra0 to dra5) .................................................... 361 12-3 correspondence between dran setting value and internal ram (12 kb).................................................. 362 12-4 correspondence between dran setting value and internal ram (16 kb).................................................. 363 12-5 correspondence between dran setting value and internal ram (20 kb).................................................. 364 12-6 correspondence between dran setting value and internal ram (24 kb).................................................. 365 12-7 format of dma byte count registers 0 to 5 (dbc0 to dbc5) ................................................................... .. 366 12-8 dma start factor expansion register (dmas)................................................................................. ............ 366 12-9 format of dma channel control registers 0 to 5 (dchc0 to dchc5)........................................................ 367 13-1 block diagram of rto ....................................................................................................... ........................... 369 13-2 configuration of real-time output buffer registers ......................................................................... ........... 370 13-3 format of real-time output port mode register (rtpm) ....................................................................... ..... 371 13-4 format of real-time output port control register (rtpc).................................................................... ...... 372 13-5 example of operation timing of rto (when extr = 0, byte = 0) ............................................................ 373 14-1 format of port 0 (p0) ...................................................................................................... .............................. 375 14-2 port 0 mode register (pm0) ................................................................................................. ........................ 377 14-3 pull-up resistor option register 0 (pu0)................................................................................... .................. 377 14-4 rising edge specification register 0 (egp0)................................................................................ ............... 378 14-5 falling edge specification register 0 (egn0) ............................................................................... ............... 378 14-6 block diagram of p00 to p07................................................................................................ ........................ 379 14-7 port 1 (p1)................................................................................................................ ..................................... 380 14-8 port 1 mode register (pm1) ................................................................................................. ........................ 381 14-9 pull-up resistor option register 1 (pu1)................................................................................... .................. 381 14-10 port 1 function register (pf1) ............................................................................................ ......................... 382 14-11 block diagram of p10 to p12, p14, and p15 ................................................................................. ............... 382 14-12 block diagram of p13 ...................................................................................................... ............................. 383 14-13 port 2 (p2)............................................................................................................... ...................................... 384 14-14 port 2 mode register (pm2) ................................................................................................ ......................... 385 14-15 pull-up resistor option register 2 (pu2).................................................................................. ................... 386 14-16 port 2 function register (pf2) ............................................................................................ ......................... 386 14-17 block diagram of p20 to p22, p24, and p25 ................................................................................. ............... 387 user?s manual u13850ej4v0um 23 list of figures (7/9) figure no. title page 14-18 block diagram of p23, p26, and p27 ........................................................................................ ....................388 14-19 port 3 (p3) ............................................................................................................... ......................................389 14-20 port 3 mode register (pm3) ................................................................................................ ..........................390 14-21 pull-up resistor option register 3 (pu3) .................................................................................. ...................390 14-22 port 3 function register (pf3) ............................................................................................ ..........................391 14-23 block diagram of p30 to p32 and p35 to p37................................................................................ ...............391 14-24 block diagram of p33 and p34.............................................................................................. ........................392 14-25 ports 4 and 5 (p4 and p5) ................................................................................................. ............................393 14-26 port 4 mode register, port 5 mode register (pm4, pm5) ..................................................................... ........394 14-27 block diagram of p40 to p47 and p50 to p57................................................................................ ...............395 14-28 port 6 (p6) ............................................................................................................... ......................................396 14-29 port 6 mode register (pm6) ................................................................................................ ..........................397 14-30 block diagram p60 to p65.................................................................................................. ...........................398 14-31 ports 7 and 8 (p7 and p8) ................................................................................................. ............................399 14-32 block diagram of p70 to p77 and p80 to p83................................................................................ ...............400 14-33 port 9 (p9) ............................................................................................................... ......................................401 14-34 port 9 mode register (pm9) ................................................................................................ ..........................402 14-35 block diagram of p90 to p96............................................................................................... ..........................403 14-36 port 10 (p10) ............................................................................................................. ....................................404 14-37 port 10 mode register (pm10) .............................................................................................. ........................405 14-38 pull-up resistor option register 10 (pu10) ................................................................................ .................406 14-39 port 10 function register (pf10) .......................................................................................... ........................406 14-40 block diagram of p100 to p107............................................................................................. ........................407 14-41 port 11 (p11) ............................................................................................................. ....................................408 14-42 port 11 mode register (pm11) .............................................................................................. ........................409 14-43 pull-up resistor option register 11 (pu11) ................................................................................ .................410 14-44 port alternate-function control register (pac) ............................................................................ ................410 14-45 block diagram of p110 to p113............................................................................................. ........................411 15-1 system reset timing........................................................................................................ .............................416 16-1 regulator .................................................................................................................. .....................................417 17-1 block diagram of rom correction ............................................................................................ ....................418 17-2 correction control register (corcn)........................................................................................ ...................419 17-3 correction request register (corrq)........................................................................................ .................420 17-4 correction address registers 0 to 3 (corad0 to corad3)..................................................................... ...421 17-5 rom correction operation and program flow.................................................................................. ............422 user?s manual u13850ej4v0um 24 list of figures (8/9) figure no. title page 18-1 environment required for writing programs to flash memory .................................................................. .. 425 18-2 communication with dedicated flash programmer (uart0)...................................................................... . 425 18-3 communication with dedicated flash programmer (csi0) ....................................................................... ... 426 18-4 communication with dedicated flash programmer (csi0 + hs) ................................................................. 426 18-5 v pp pin connection example ........................................................................................................ ................ 428 18-6 conflict of signals (serial interface input pin) ........................................................................... ................... 429 18-7 malfunction of other device................................................................................................ .......................... 430 18-8 conflict of signals (reset pin)............................................................................................ ........................ 431 18-9 procedure for manipulating flash memory .................................................................................... ............... 432 18-10 flash memory programming mode............................................................................................ .................. 433 18-11 communication command ..................................................................................................... ...................... 434 19-1 iebus transfer signal format............................................................................................... ........................ 439 19-2 master address field ....................................................................................................... ............................. 440 19-3 slave address field ........................................................................................................ .............................. 441 19-4 control field.............................................................................................................. .................................... 443 19-5 telegraph length field ..................................................................................................... ............................ 445 19-6 data field................................................................................................................. ..................................... 446 19-7 bit configuration of slave status .......................................................................................... ........................ 450 19-8 configuration of lock address.............................................................................................. ........................ 451 19-9 bit format of iebus........................................................................................................ ............................... 452 19-10 iebus controller block diagram ............................................................................................ ....................... 453 19-11 iebus control register (bcr) .............................................................................................. ........................ 456 19-12 iebus unit address register (uar) format .................................................................................. ............... 459 19-13 iebus slave address register (sar) format................................................................................. .............. 459 19-14 iebus partner address register (par) format ............................................................................... ............. 460 19-15 iebus control data register (cdr) format .................................................................................. ............... 461 19-16 interrupt generation timing (for (1), (3), and (4)) ....................................................................... .................. 462 19-17 interrupt generation timing (for (2) and (5))............................................................................. .................... 463 19-18 timing of intie2 interrupt generation in locked state (for (4) and (5))................................................... .... 463 19-19 timing of intie2 interrupt generation in locked state (for (3)) ........................................................... ........ 464 19-20 iebus telegraph length register (dlr) format .............................................................................. ............ 465 19-21 iebus data register (dr) format ........................................................................................... ..................... 466 19-22 iebus unit status register (usr) .......................................................................................... ...................... 467 19-23 example of broadcasting communication flag operation ...................................................................... ..... 468 19-24 iebus interrupt status register (isr) ..................................................................................... ...................... 471 19-25 iebus slave status register (ssr) format.................................................................................. ................ 475 19-26 iebus success count register (scr) format ................................................................................. ............ 476 19-27 iebus communication count register (ccr) format ........................................................................... ....... 477 19-28 iebus clock selection register (ieclk) format ............................................................................. ............. 477 user?s manual u13850ej4v0um 25 list of figures (9/9) figure no. title page 19-29 configuration of interrupt control block.................................................................................. .......................478 19-30 master transmission ....................................................................................................... ..............................482 19-31 master reception.......................................................................................................... .................................484 19-32 slave transmission ........................................................................................................ ...............................486 19-33 slave reception........................................................................................................... ..................................488 19-34 master transmission (interval of interrupt occurrence) .................................................................... ............490 19-35 master reception (interval of interrupt occurrence) ....................................................................... ..............491 19-36 slave transmission (interval of interrupt occurrence) ..................................................................... .............492 19-37 slave reception (interval of interrupt occurrence) ........................................................................ ...............493 user?s manual u13850ej4v0um 26 list of tables (1/3) table no. title page 1-1 product lineup of v850/sb1 and v850/sb2 ..................................................................................... ............. 30 2-1 pin i/o buffer power supply ................................................................................................. .......................... 51 2-2 differences of pins between v850/sb1 and v850/sb2........................................................................... ....... 51 2-3 pin operating state in operation mode ....................................................................................... ................... 58 3-1 program registers ........................................................................................................... ............................... 75 3-2 system register numbers ..................................................................................................... ......................... 76 3-3 interrupt/exception table................................................................................................... ............................. 85 3-4 differences in peripheral i/o registers of v850/sb1 and v850/sb2 ............................................................ .95 4-1 bus control pins ............................................................................................................ ............................... 106 4-2 number of access clocks..................................................................................................... ........................ 107 4-3 bus priority................................................................................................................ .................................... 122 5-1 interrupt source list....................................................................................................... ............................... 125 5-2 interrupt control register (xxicn) .......................................................................................... ....................... 141 5-3 priorities of interrupts and exceptions ..................................................................................... ..................... 151 5-4 description of key return detection pin..................................................................................... .................. 156 6-1 operating statuses in halt mode ............................................................................................ .................. 166 6-2 operating statuses in idle mode ............................................................................................ ................... 168 6-3 operating statuses in software stop mode ................................................................................... ............ 170 7-1 configuration of timers 0 and 1............................................................................................. ....................... 176 7-2 valid edge of tin0 pin and capture trigger of crn0 .......................................................................... ......... 177 7-3 valid edge of tin1 pin and capture trigger of crn0 .......................................................................... ......... 177 7-4 tin0 pin valid edge and crn1 capture trigger ................................................................................ ........... 178 7-5 configuration of timers 2 to 7.............................................................................................. ......................... 210 8-1 interval time of interval timer ............................................................................................. ......................... 231 8-2 configuration of watch timer ................................................................................................ ....................... 231 8-3 interval time of interval timer ............................................................................................. ......................... 234 9-1 inadvertent program loop detection time of watchdog timer................................................................... . 237 9-2 interval time of interval timer ............................................................................................. ......................... 237 9-3 configuration of watchdog timer ............................................................................................. .................... 238 9-4 inadvertent program loop detection time of watchdog timer................................................................... . 241 9-5 interval time of interval timer ............................................................................................. ......................... 242 user?s manual u13850ej4v0um 27 list of tables (2/3) table no. title page 10-1 configuration of csin ...................................................................................................... ..............................245 10-2 configuration of i 2 cn ............................................................................................................................. ........255 10-3 selection clock setting.................................................................................................... ..............................267 10-4 intiicn generation timing and wait control ................................................................................. ...............294 10-5 extension code bit definitions ............................................................................................. .........................296 10-6 status during arbitration and interrupt request generation timing .......................................................... ...297 10-7 wait periods ............................................................................................................... ...................................299 10-8 configuration of uartn..................................................................................................... ............................312 10-9 relationship between main clock and baud rate .............................................................................. ..........324 10-10 receive error causes...................................................................................................... ..............................330 10-11 configuration of csi4 ..................................................................................................... ...............................332 11-1 configuration of a/d converter............................................................................................. .........................346 12-1 internal ram area usable in dma ............................................................................................ ....................361 13-1 configuration of rto....................................................................................................... ..............................370 13-2 operation when real-time output buffer registers are manipulated .........................................................37 1 13-3 operation mode and output trigger of real-time output port ................................................................. ....372 14-1 pin i/o buffer power supplies .............................................................................................. .........................375 14-2 port 0 alternate function pins ............................................................................................. ..........................376 14-3 port 1 alternate function pins ............................................................................................. ..........................380 14-4 port 2 alternate function pins ............................................................................................. ..........................384 14-5 port 3 alternate function pins ............................................................................................. ..........................389 14-6 alternate function pins of ports 4 and 5 ................................................................................... ....................393 14-7 port 6 alternate function pins ............................................................................................. ..........................396 14-8 alternate function pins of ports 7 and 8 ................................................................................... ....................399 14-9 port 9 alternate function pins ............................................................................................. ..........................401 14-10 port 10 alternate function pins ........................................................................................... ..........................404 14-11 port 11 alternate function pins ........................................................................................... ..........................408 14-12 setting when port pin is used for alternate function...................................................................... .............412 18-1 signal generation of dedicated flash programmer (pg-fp3)................................................................... ...427 18-2 pins used in serial interfaces ............................................................................................. ..........................428 18-3 list of communication modes ................................................................................................ .......................434 18-4 flash memory control command............................................................................................... ...................435 18-5 response command ........................................................................................................... ..........................435 user?s manual u13850ej4v0um 28 list of tables (3/3) table no. title page 19-1 transfer rate and maximum number of transfer bytes in communication mode 1.................................... 437 19-2 contents of control bits ................................................................................................... ............................. 442 19-3 control field for locked slave unit ........................................................................................ ...................... 443 19-4 control field for unlocked slave unit ...................................................................................... ..................... 443 19-5 acknowledge signal output condition of control field ....................................................................... ......... 444 19-6 contents of telegraph length bit ........................................................................................... ...................... 445 19-7 internal registers of iebus controller..................................................................................... ...................... 455 19-8 reset conditions of flags in isr register.................................................................................. .................. 470 19-9 interrupt source list...................................................................................................... ................................ 479 19-10 communication error source processing list ............................................................................... .............. 480 b-1 symbols in operand description .............................................................................................. .................... 501 b-2 symbols used for op code .................................................................................................... ...................... 502 b-3 symbols used for operation description...................................................................................... ................ 502 b-4 symbols used for flag operation............................................................................................. .................... 503 b-5 condition codes ............................................................................................................. .............................. 503 user?s manual u13850ej4v0um 29 chapter 1 introduction the v850/sb1 and v850/sb2 are products in nec?s v850 family of single-chip microcontrollers designed for low power operation. 1.1 general the v850/sb1 and v850/sb2 are 32-bit single-chip microcontrollers that include the v850 family?s cpu core, and peripheral functions such as rom/ram, a timer/counter, a serial interface, an a/d converter, a timer, and dma controller. based on the v850/sa1?, the v850/sb1 and v850/sb2 feature various additions, including 3 to 5 v i/o interface support, and rom correction. for v850/sb2, based on the v850/sb1?, the peripheral functions of automobile lan (iebus? (inter equipment bus?)) are added. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850/sb1 and v850/sb2 have multiply, saturation operation, and bit manipulation instructions realized with a hardware multiplier for digital servo control. moreover, as a real-time control system, the v850/sb1 and v850/sb2 enable the realization of extremely high cost-performance for applications that require low power consumption, such as audio equipment, car audio systems, and vcrs. table 1-1 shows the outlines of the v850/sb1 and v850/sb2 product lineup. chapter 1 introduction user?s manual u13850ej4v0um 30 table 1-1. product lineup of v850/sb1 and v850/sb2 product name rom commercial name part number on-chip i 2 c type size ram size package on-chip iebus pd703031a none pd703031ay available mask rom 128 kb 12 kb 100-pin qfp (14 20) /100-pin lqfp (14 14) pd703033a mask rom pd70f3033a none flash memory pd703033ay mask rom pd70f3033ay available flash memory 256 kb 16 kb 100-pin qfp (14 20) /100-pin lqfp (14 14) pd703030a none pd703030ay available mask rom 384 kb 20 kb 100-pin qfp (14 20) pd703032a mask rom pd70f3032a none flash memory pd703032ay mask rom v850/sb1 pd70f3032ay available flash memory 512 kb 24 kb 100-pin qfp (14 20) none pd703034a none pd703034ay available mask rom 128 kb 12 kb 100-pin qfp (14 20) /100-pin lqfp (14 14) pd703035a mask rom pd70f3035a none flash memory pd703035ay mask rom pd70f3035ay available flash memory 256 kb 16 kb 100-pin qfp (14 20) /100-pin lqfp (14 14) pd703036a none pd703036ay available mask rom 384 kb 20 kb 100-pin qfp (14 20) pd703037a mask rom pd70f3037a none flash memory pd703037ay mask rom v850/sb2 pd70f3037ay available flash memory 512 kb 24 kb 100-pin qfp (14 20) available remark the part numbers of the v850/sb1 and v850/sb2 are described as follows in this manual. ? pd70303xa, pd70303xay: mask rom products mask rom products of v850/sb1: x = 0 to 3 mask rom products of v850/sb2: x = 4 to 7 ? pd70f303wa, pd70f303way: flash memory products flash memory products of v850/sb1: w = 2, 3 flash memory products of v850/sb2: w = 5, 7 ? pd70303xay, pd70f303way: y products (products with on-chip i 2 c) y products of v850/sb1: x = 0 to 3, w = 2, 3 y products of v850/sb2: x = 4 to 7, w = 5, 7 chapter 1 introduction user?s manual u13850ej4v0um 31 1.2 v850/sb1 1.2.1 features (v850/sb1) { number of instructions: 74 { minimum instruction execution time 50 ns (operating at 20 mhz, external power supply 5 v, regulator output 3.3 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 100 ns (operating at 20 mhz) (able to execute instructions in parallel continuously without creating any register hazards). saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expandability: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplex) address bus: separate output enabled 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703031a, 703031ay (mask rom: 128 kb/ram: 12 kb) pd703033a, 703033ay (mask rom: 256 kb/ram: 16 kb) pd703030a, 703030ay (mask rom: 384 kb/ram: 20 kb) pd703032a, 703032ay (mask rom: 512 kb/ram: 24 kb) pd70f3033a, 70f3033ay (flash memory: 256 kb/ram: 16 kb) pd70f3032a, 70f3032ay (flash memory: 512 kb/ram: 24 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 37 sources ( pd703030a, 703031a, 703032a, 703033a, 70f3032a, 70f3033a) 38 sources ( pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, 70f3033ay) software exceptions: 32 sources exception trap: 1 source { i/o lines total: 83 (12 input ports and 71 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 2 channels (pwm output) 8-bit timer: 6 channels (4 pwm outputs, cascade connection enabled) { watch timer when operating under subsystem or main system clock: 1 channel operation using the subsystem or main system clock is also possible in the idle mode. { watchdog timer 1 channel chapter 1 introduction user?s manual u13850ej4v0um 32 { serial interface (sio) asynchronous serial interface (uart) clocked serial interface (csi) i 2 c bus interface (i 2 c) (only for pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, and 70f3033ay) 8-/16-bit variable-length serial interface csi/uart: 2 channels csi/i 2 c: 2 channels csi (8-/16-bit valuable): 1 channel dedicated baud rate generator: 3 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram internal peripheral i/o: 6 channels { real-time output port (rtp) 8 bits 1 channel or 4 bits 2 channels { rom correction modifiable 4 points { regulator 4.0 v to 5.5 v input internal 3.3 v { key return function 4 to 8 selecting enabled, falling edge fixed { clock generator during main system clock or subsystem clock operation 5-level cpu clock (including slew rate and sub operations) { power-saving functions halt/idle/stop modes { package 100-pin plastic lqfp (fine pitch, 14 14) 100-pin plastic qfp (14 20) { cmos structure all static circuits 1.2.2 application fields (v850/sb1) av equipment example : audio, car audio equipment, vcr, and tv. chapter 1 introduction user?s manual u13850ej4v0um 33 1.2.3 ordering information (v850/sb1) part number package internal rom pd703031agc- xxx-8eu pd703031agf- xxx-3ba pd703031aygc- xxx-8eu pd703031aygf- xxx-3ba pd703033agc- xxx-8eu pd703033agf- xxx-3ba pd703033aygc- xxx-8eu pd703033aygf- xxx-3ba pd703030agf- xxx-3ba note pd703030aygf- xxx-3ba note pd703032agf- xxx-3ba pd703032aygf- xxx-3ba pd70f3033agc-8eu pd70f3033agf-3ba pd70f3033aygf-8eu pd70f3033aygf-3ba pd70f3032agf-3ba pd70f3032aygf-3ba 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) mask rom (128 kb) mask rom (128 kb) mask rom (128 kb) mask rom (128 kb) mask rom (256 kb) mask rom (256 kb) mask rom (256 kb) mask rom (256 kb) mask rom (384 kb) mask rom (384 kb) mask rom (512 kb) mask rom (512 kb) flash memory (256 kb) flash memory (256 kb) flash memory (256 kb) flash memory (256 kb) flash memory (512 kb) flash memory (512 kb) note in planning remarks 1. indicates rom code suffix. 2. romless devices are not provided. chapter 1 introduction user?s manual u13850ej4v0um 34 1.2.4 pin configuration (top view) (v850/sb1) 100-pin plastic lqfp (fine pitch) (14 14) ? pd703031agc- xxx-8eu ? pd70f3033agc-8eu ? pd703031aygc- xxx-8eu ? pd70f3033aygc-8eu ? pd703033agc- xxx-8eu ? pd703033aygc- xxx-8eu p20/si2/sda1 note 2 p14/so1/txd0 p13/si1/rxd0 p11/so0 p10/si0/sda0 note 2 p07/intp6 p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p107/rtp7/kr7/a12 p110/wait/a1 p111/a2 p112/a3 p113/a4 xt1 xt2 regc x2 x1 v ss v dd p94/astb p40/ad0 p41/ad1 p42/ad2 p43/ad3 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 p21/so2 p23/rxd1/si3 p24/txd1/so3 ev dd ev ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p33/ti11/so4 p34/to0/a13/sck4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/kr0/a5 p101/rtp1/kr1/a6 p102/rtp2/kr2/a7 p103/rtp3/kr3/a8 p104/rtp4/kr4/a9 p105/rtp5/kr5/a10 p106/rtp6/kr6/a11 p71/ani1 p70/ani0 a v ss a v ref a v dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p22/sck2/scl1 note 2 reset clkout p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p95/hldak p96/hldrq p15/sck1/asck0 p12/sck0/scl0 note 2 p25/asck1/sck3 p32/ti10/si4 p06/intp5/rtptrg notes 1. ic ( pd703031a, 703031ay, 703033a, 703033ay): connect directly to v ss . v pp ( pd70f3033a, 70f3033ay): connect to v ss in normal operation mode. 2 . scl0, scl1, sda0, and sda1 are available only for pd703031ay, 703033ay, and 70f3033ay. chapter 1 introduction user?s manual u13850ej4v0um 35 100-pin plastic qfp (14 20) ? pd703030agf- xxx-3ba ? pd703032agf- xxx-3ba ? pd70f3032agf-3ba ? pd703030aygf- xxx-3ba ? pd703032aygf- xxx-3ba ? pd70f3032aygf-3ba ? pd703031agf- xxx-3ba ? pd703033agf- xxx-3ba ? pd70f3033agf-3ba ? pd703031aygf- xxx-3ba ? pd703033aygf- xxx-3ba ? pd70f3033aygf-3ba p13/si1/rxd0 p11/so0 p10/si0/sda0 note 2 p07/intp6 p06/intp5/rtptrg p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p111/a2 p112/a3 p113/a4 xt1 xt2 regc x2 x1 v ss v dd p94/astb p40/ad0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 p21/so2 p23/rxd1/si3 p24/txd1/so3 ev dd ev ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p33/ti11/so4 p34/to0/a13/sck4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/kr0/a5 p101/rtp1/kr1/a6 p102/rtp2/kr2/a7 p103/rtp3/kr3/a8 p104/rtp4/kr4/a9 p105/rtp5/kr5/a10 p106/rtp6/kr6/a11 p71/ani1 p70/ani0 a v ss a v ref a v dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p22/sck2/scl1 note 2 reset clkout p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p95/hldak p96/hldrq p12/sck0/scl0 note 2 p25/asck1/sck3 p32/ti10/si4 26 27 28 29 30 p14/so1/txd0 p20/si2/sda1 note 2 p107/rtp7/kr7/a12 p110/wait/a1 p43/ad3 p42/ad2 p41/ad1 80 79 78 77 76 p73/ani3 p72/ani2 p15/sck1/asck0 notes 1. ic ( pd703030a, 703030ay, 703031a, 703031ay, 703032a, 703032ay, 703033a, 703033ay): connect directly to v ss . v pp ( pd70f3032a, 70f3032ay, 70f3033a, 70f3033ay): connect to v ss in normal operation mode. 2 . scl0, scl1, sda0, and sda1 are available only for pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, and 70f3033ay. chapter 1 introduction user?s manual u13850ej4v0um 36 pin names (v850/sb1) a1 to a21: address bus p70 to p77: port 7 ad0 to ad15: address/data bus p80 to p83: port 8 adtrg: ad trigger input p90 to p96: port 9 ani0 to ani11: analog input p100 to p107: port 10 asck0, asck1: asynchronous serial clock p110 to p113: port 11 astb: address strobe rd: read av dd : analog v dd regc: regulator control av ref : analog reference voltage reset: reset av ss : analog v ss rtp0 to rtp7: real-time output port bv dd : power supply for bus interface rtptrg: rtp trigger bv ss : ground for bus interface r/w: read/write status clkout: clock output rxd0, rxd1: receive data dstb: data strobe sck0 to sck4: serial clock ev dd : power supply for port scl0, scl1: serial clock ev ss : ground for port sda0, sda1: serial data hldak: hold acknowledge si0 to si4: serial input hldrq: hold request so0 to so4: serial output ic: internally connected ti00, ti01, ti10, intp0 to intp6: interrupt request from peripherals ti11, ti2 to ti5: timer i nput kr0 to kr7 : key return to0 to to5: timer output lben: lower byte enable txd0,txd1: transmit data nmi: non-maskable interrupt request uben: upper byte enable p00 to p07: port 0 v dd : power supply p10 to p15: port 1 v pp : programming power supply p20 to p27: port 2 v ss : ground p30 to p37: port 3 wait: wait p40 to p47: port 4 wrh: write strobe high level data p50 to p57: port 5 wrl: write strobe low level data p60 to p65: port 6 x1, x2: crystal for main clock xt1, xt2: crystal for subclock chapter 1 introduction user?s manual u13850ej4v0um 37 1.2.5 function blocks (v850/sb1) (1) internal block diagram intp0 to intp6 nmi intc ti2/to2 ti3/to3 ti4/to4 ti5/to5 sio so0 si0/sda0 n o t e 3 timer/counter ti00,ti01, ti10,ti11 so1/txd0 si1/rxd0 so4 si4 csi0/i 2 c0 note 4 csi1/uart0 variable length csi4 watchdog timer note 1 rom cpu note 2 multiplier 16 16 32 ram pc 32-bit barrel shifter system register general-purpose registers 32 bits 32 instruction queue bcu a stb ( p94 ) a16 to a21 (p60 to p65) ad0 to ad15 (p40 to p47, p50 to p57) a/d converter rtp ports cg clkout x1 x2 xt1 v dd v ss bv dd bv ss ev dd ani0 to ani11 av ref av ss av dd adtrg rtp0 to rtp7 p110 to p113 p100 to p107 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 sck0/scl0 n o t e 3 sck1/asck0 sck4 reset xt2 hldak ( p95 ) hldrq ( p96 ) wait ( p110 ) uben ( p91 ) alu 16-bit timer: tm0, tm1 8-bit timer: tm2 to tm7 to0,to1 dmac: 6 ch watch timer p80 to p83 p90 to p96 ev ss dstb/rd ( p93 ) r/w /wrh ( p92 ) lben/wrl ( p90 ) rtptrg a13 to a15 (p34 to p36) a1 to a12 (p100 to p107, p110 to p113 ) so2 si2/sda1 n o t e 3 csi2/i 2 c1 note 4 sck2/scl1 n o t e 3 so3/txd1 si3/rxd1 csi3/uart1 sck3/asck1 key return kr0 to kr7 rom correction v pp n o t e 5 regulator regc ic n o t e 6 3.3 v notes 1. pd703031a, 703031ay: 128 kb (mask rom) pd703033a, 703033ay: 256 kb (mask rom) pd703030a, 703030ay: 384 kb (mask rom) pd703032a, 703032ay: 512 kb (mask rom) pd70f3033a, 70f3033ay: 256 kb (flash memory) pd70f3032a, 70f3032ay: 512 kb (flash memory) 2. pd703031a, 703031ay: 12 kb pd703033a, 703033ay, 70f3033a, 70f3033ay: 16 kb pd703030a, 703030ay: 20 kb pd703032a, 703032ay, 70f3032a, 70f3032ay: 24 kb 3. sda0, sda1, scl0, and scl1 pins are available only for pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, and 70f3033ay. 4. i 2 c function is available only for pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, and 70f3033ay. 5. pd70f3032a, 70f3032ay, 70f3033a, 70f3033ay 6. pd703030a, 703030ay, 703031a, 703031ay, 703032a, 703032ay, 703033a, 703033ay chapter 1 introduction user?s manual u13850ej4v0um 38 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as the multiplier (16 bits 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (c) rom this consists of a mask rom or flash memory mapped to the address space starting at 00000000h. the rom capacity varies depending on the product. the rom capacity of each product is shown below. pd703031a, 703031ay: 128 kb (mask rom) pd703033a, 703033ay: 256 kb (mask rom) pd70f3033a, 70f3033ay: 256 kb (flash memory) pd703030a, 703030ay: 384 kb (mask rom) pd703032a, 703032ay: 512 kb (mask rom) pd70f3032a, 70f3032ay: 512 kb (flash memory) rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram the ram capacity and mapping addresses vary depending on the product. the ram capacity of each product is shown below. pd703031a, 703031ay: 12 kb (mapping starts at ffffc000h) pd703033a, 703033ay, 70f3033a, 70f3033ay: 16 kb (mapping starts at ffffb000h) pd703030a, 703030ay: 20 kb (mapping starts at ffffa000h) pd703032a, 703032ay, 70f3032a, 70f3032ay: 24 kb (mapping starts at ffff9000h) ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators; each for main system clock (f xx ) and for subsystem clock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). chapter 1 introduction user?s manual u13850ej4v0um 39 (g) timer/counter a two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8- bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. the two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. the two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) watch timer this timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 khz subsystem clock or the 16.777 mhz main system clock). at the same time, the watch timer can be used as an interval timer for the main system clock. (i) watchdog timer a watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs. (j) serial interface (sio) the v850/sb1 includes three kinds of serial interfaces: asynchronous serial interfaces (uart0, uart1), clocked serial interfaces (csi0 to csi3), and an 8-/16-bit variable-length serial interface (csi4). these plus the i 2 c bus interfaces (i 2 c0, i 2 c1) comprise five channels. two of these channels are switchable between the uart and csi and another two switchable between csi and i 2 c. for uart0 and uart1, data is transferred via the txd0, txd1, rxd0, and rxd1 pins. for csi0 to csi3, data is transferred via the so0 to so3, si0 to si3, and sck0 to sck3 pins. for csi4, data is transferred via the so4, si4, and sck4 pins. for i 2 c0 and i 2 c1, data is transferred via the sda0, sda1, scl0, and scl1 pins. i 2 c0 and i 2 c1 are equipped only in the pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, and 70f3033ay. for uart and csi4, a dedicated baud rate generator is equipped. (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion uses the successive approximation method. (l) dma controller a six-channel dma controller is equipped. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (m) real-time output port (rtp) the rtp is a real-time output function that transfers previously set 8-bit data to an output latch when an external trigger signal occurs or when there is a coincidence signal in a timer compare register. it can also be used for 4-bit 2 channels. chapter 1 introduction user?s manual u13850ej4v0um 40 (n) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger, rtp trigger port 1 6-bit i/o serial interface port 2 8-bit i/o serial interface, timer i/o port 3 8-bit i/o timer i/o, external address bus, serial interface port 4 8-bit i/o external address/data bus port 5 8-bit i/o port 6 6-bit i/o external address bus port 7 8-bit input a/d converter analog input port 8 4-bit input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o real-time output port, external address bus, key return input port 11 4-bit i/o general- purpose port wait control, external address bus chapter 1 introduction user?s manual u13850ej4v0um 41 1.3 v850/sb2 1.3.1 features (v850/sb2) { number of instructions: 74 { minimum instruction execution time 79 ns (operating at 12.58 mhz, external power supply 5 v, regulator output 3.0 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 158 ns (operating at 12.58 mhz) (able to execute instructions in parallel continuously without creating any register hazards). saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expandability: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplex) address bus: separate output enabled 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703034a, 703034ay (mask rom: 128 kb/ram: 12 kb) pd703035a, 703035ay (mask rom: 256 kb/ram: 16 kb) pd703036a, 703036ay (mask rom: 384 kb/ram: 20 kb) pd703037a, 703037ay (mask rom: 512 kb/ram: 24 kb) pd70f3035a, 70f3035ay (flash memory: 256 kb/ram: 16 kb) pd70f3037a, 70f3037ay (flash memory: 512 kb/ram: 24 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 39 sources ( pd703034a, 703035a, 703036a, 703037a, 70f3035a, 70f3037a) 40 sources ( pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, 70f3037ay) software exceptions: 32 sources exception trap: 1 source { i/o lines total: 83 (12 input ports and 71 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 2 channels (pwm output) 8-bit timer: 6 channels (four pwm outputs, cascade connection enabled) { watch timer when operating under subsystem or main system clock: 1 channel operation using the subsystem or main system clock is also possible in the idle mode. { watchdog timer 1 channel { serial interface (sio) asynchronous serial interface (uart) clocked serial interface (csi) chapter 1 introduction user?s manual u13850ej4v0um 42 i 2 c bus interface (i 2 c) (only for pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, and 70f3037ay) 8-/16-bit variable-length serial interface csi/uart: 2 channels csi/i 2 c: 2 channels csi (8-/16-bit valuable): 1 channel dedicated baud rate generator: 3 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram internal peripheral i/o: 6 channels { real-time output port (rtp) 8 bits 1 channel or 4 bits 2 channels { rom correction modifiable 4 points { regulator 4.0 v to 5.5 v input internal 3.0 v { key return function 4 to 8 selecting enabled, falling edge fixed { clock generator during main system clock or subsystem clock operation 5-level cpu clock (including slew rate and sub operations) { power-saving functions halt/idle/stop modes { iebus controller 1 ch { package 100-pin plastic lqfp (fine pitch, 14 14) 100-pin plastic qfp (14 20) { cmos structure all static circuits 1.3.2 application fields (v850/sb2) av equipment example : audio, car audio equipment, vcr, and tv. chapter 1 introduction user?s manual u13850ej4v0um 43 1.3.3 ordering information (v850/sb2) part number package internal rom pd703034agc- xxx-8eu 100-pin plastic lqfp (fine pitch) (14 14) mask rom (128 kb) pd703034agf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (128 kb) pd703034aygc- xxx-8eu 100-pin plastic lqfp (fine pitch) (14 14) mask rom (128 kb) pd703034aygf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (128 kb) pd703035agc- xxx-8eu 100-pin plastic lqfp (fine pitch) (14 14) mask rom (256 kb) pd703035agf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (256 kb) pd703035aygc- xxx-8eu 100-pin plastic lqfp (fine pitch) (14 14) mask rom (256 kb) pd703035aygf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (256 kb) pd703036agf- xxx-3ba note 100-pin plastic qfp (14 20) mask rom (384 kb) pd703036aygf- xxx-3ba note 100-pin plastic qfp (14 20) mask rom (384 kb) pd703037agf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (512 kb) pd703037aygf- xxx-3ba 100-pin plastic qfp (14 20) mask rom (512 kb) pd70f3035agc-8eu 100-pin plastic lqfp (fine pitch) (14 14) flash memory (256 kb) pd70f3035agf-3ba 100-pin plastic qfp (14 20) flash memory (256 kb) pd70f3035aygf-8eu 100-pin plastic lqfp (fine pitch) (14 14) flash memory (256 kb) pd70f3035aygf-3ba 100-pin plastic qfp (14 20) flash memory (256 kb) pd70f3037agf-3ba 100-pin plastic qfp (14 20) flash memory (512 kb) pd70f3037aygf-3ba 100-pin plastic qfp (14 20) flash memory (512 kb) note in planning remarks 1. indicates rom code suffix. 2. romless devices are not provided. chapter 1 introduction user?s manual u13850ej4v0um 44 1.3.4 pin configuration (top view) (v850/sb2) 100-pin plastic lqfp (fine pitch) (14 14) ? pd703034agc- xxx-8eu ? pd70f3035agc-8eu ? pd703034aygc- xxx-8eu ? pd70f3035aygc-8eu ? pd703035agc- xxx-8eu ? pd703035aygc- xxx-8eu p20/si2/sda1 note 2 p14/so1/txd0 p13/si1/rxd0 p11/so0 p10/si0/sda0 note 2 p07/intp6 p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p107/rtp7/kr7/a12 p110/wait/a1 p111/a2 p112/a3 p113/a4 xt1 xt2 regc x2 x1 v ss v dd p94/astb p40/ad0 p41/ad1 p42/ad2 p43/ad3 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 p21/so2 p23/rxd1/si3 p24/txd1/so3 ev dd ev ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p33/ti11/so4 p34/to0/a13/sck4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/kr0/a5 p101/rtp1/kr1/a6 p102/rtp2/kr2/a7 p103/rtp3/kr3/a8 p104/rtp4/kr4/a9/ier x p105/rtp5/kr5/a10/iet x p106/rtp6/kr6/a11 p71/ani1 p70/ani0 a v ss a v ref a v dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p22/sck2/scl1 note 2 reset clkout p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p95/hldak p96/hldrq p15/sck1/asck0 p12/sck0/scl0 note 2 p25/asck1/sck3 p32/ti10/si4 p06/intp5/rtptrg notes 1. ic ( pd703034a, 703034ay, 703035a, 703035ay): connect directly to v ss . v pp ( pd70f3035a, 70f3035ay): connect to v ss in normal operation mode. 2. scl0, scl1, sda0, and sda1 are available only for pd703034ay, 703035ay, and 70f3035ay. chapter 1 introduction user?s manual u13850ej4v0um 45 100-pin plastic qfp (14 20) ? pd703034agf- xxx-3ba ? pd703036agf- xxx-3ba ? pd70f3035agf-3ba ? pd703034aygf- xxx-3ba ? pd703036aygf- xxx-3ba ? pd70f3035aygf-3ba ? pd703035agf- xxx-3ba ? pd703037agf- xxx-3ba ? pd70f3037agf-3ba ? pd703035aygf- xxx-3ba ? pd703037aygf- xxx-3ba ? pd70f3037aygf-3ba p13/si1/rxd0 p11/so0 p10/si0/sda0 note 2 p07/intp6 p06/intp5/rtptrg p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p111/a2 p112/a3 p113/a4 xt1 xt2 regc x2 x1 v ss v dd p94/astb p40/ad0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 p21/so2 p23/rxd1/si3 p24/txd1/so3 ev dd ev ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p33/ti11/so4 p34/to0/a13/sck4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/kr0/a5 p101/rtp1/kr1/a6 p102/rtp2/kr2/a7 p103/rtp3/kr3/a8 p104/rtp4/kr4/a9/ierx p105/rtp5/kr5/a10/ietx p106/rtp6/kr6/a11 p71/ani1 p70/ani0 a v ss a v ref a v dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p22/sck2/scl1 note 2 reset clkout p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p95/hldak p96/hldrq p12/sck0/scl0 note 2 p25/asck1/sck3 p32/ti10/si4 26 27 28 29 30 p14/so1/txd0 p20/si2/sda1 note 2 p107/rtp7/kr7/a12 p110/wait/a1 p43/ad3 p42/ad2 p41/ad1 80 79 78 77 76 p73/ani3 p72/ani2 p15/sck1/asck0 notes 1. ic ( pd703034a, 703034ay, 703035a, 703035ay, 703036a, 703036ay, 703037a, 703037ay): connect directly to v ss . v pp ( pd70f3035a, 70f3035ay, 70f3037a, 70f3037ay): connect to v ss in normal operation mode. 2. scl0, scl1, sda0, and sda1 are available only for pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, and 70f3037ay. chapter 1 introduction user?s manual u13850ej4v0um 46 pin names (v850/sb2) a1 to a21: address bus p70 to p77: port 7 ad0 to ad15: address/data bus p80 to p83: port 8 adtrg: ad trigger input p90 to p96: port 9 ani0 to ani11: analog input p100 to p107: port 10 asck0, asck1: asynchronous serial clock p110 to p113: port 11 astb: address strobe rd: read av dd : analog v dd regc: regulator control av ref : analog reference voltage reset: reset av ss : analog v ss rtp0 to rtp7: real-time output port bv dd : power supply for bus interface rtptrg: rtp trigger bv ss : ground for bus interface r/w: read/write status clkout: clock output rxd0, rxd1: receive data dstb: data strobe sck0 to sck4: serial clock ev dd : power supply for port scl0, scl1: serial clock ev ss : ground for port sda0, sda1: serial data hldak: hold acknowledge si0 to si4: serial input hldrq: hold request so0 to so4: serial output ic: internally connected ti00, ti01, ti10, ierx: iebus receive data ti11, ti2 to ti5: timer input ietx: iebus transmit data to0 to to5: timer output intp0 to intp6: interrupt request from peripherals txd0,txd1: transmit data kr0 to kr7 : key return uben: upper byte enable lben: lower byte enable v dd : power supply nmi: non-maskable interrupt request v pp : programming power supply p00 to p07: port 0 v ss : ground p10 to p15: port 1 wait: wait p20 to p27: port 2 wrh: write strobe high level data p30 to p37: port 3 wrl: write strobe low level data p40 to p47: port 4 x1, x2: crystal for main clock p50 to p57: port 5 xt1, xt2: crystal for subclock p60 to p65: port 6 chapter 1 introduction user?s manual u13850ej4v0um 47 1.3.5 function blocks (v850/sb2) (1) internal block diagram intp0 to intp6 nmi intc ti2/to2 ti3/to3 ti4/to4 ti5/to5 sio so0 si0/sda0 n o t e 3 timer/counter ti00,ti01, ti10,ti11 so1/txd0 si1/rxd0 so4 si4 csi0/i 2 c0 note 4 csi1/uart0 variable length csi4 watchdog timer note 1 rom cpu note 2 multiplier 16 16 32 ram pc 32-bit barrel shifter system register general-purpose registers 32 bits 32 instruction queue bcu a stb ( p94 ) a16 to a21 (p60 to p65) ad0 to ad15 (p40 to p47, p50 to p57) a/d converter rtp ports cg clkout x1 x2 xt1 v dd v ss bv dd bv ss ev dd ani0 to ani11 av ref av ss av d d adtrg rtp0 to rtp7 p110 to p113 p100 to p107 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 sck0/scl0 n o t e 3 sck1/asck0 sck4 reset xt2 hldak ( p95 ) hldrq ( p96 ) wait ( p110 ) uben ( p91 ) alu 16-bit timer: tm0, tm1 8-bit timer: tm2 to tm7 to0,to1 dmac: 6 ch watch timer p80 to p83 p90 to p96 ev ss dstb/rd ( p93 ) r/w /wrh ( p92 ) lben/wrl ( p90 ) rtptrg a13 to a15 (p34 to p36) a1 to a12 (p100 to p107, p110 to p113 ) so2 si2/sda1 n o t e 3 csi2/i 2 c1 note 4 sck2/scl1 n o t e 3 so3/txd1 si3/rxd1 csi3/uart1 sck3/asck1 key return kr0 to kr7 rom correction v pp n o t e 6 regulator regc ic n o t e 6 3.0 v iebus ietx ierx notes 1. pd703034a, 703034ay: 128 kb (mask rom) pd703035a, 703035ay: 256 kb (mask rom) pd703036a, 703036ay: 384 kb (mask rom) pd703037a, 703037ay: 512 kb (mask rom) pd70f3035a, 70f3035ay: 256 kb (flash memory) pd70f3037a, 70f3037ay: 512 kb (flash memory) 2. pd703034a, 703034ay: 12 kb pd703035a, 703035ay, 70f3035a, 70f3035ay: 16 kb pd703036a, 703036ay: 20 kb pd703037a, 703037ay, 70f3037a, 70f3037ay: 24 kb 3. sda0, sda1, scl0, and scl1 pins are available only for pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, and 70f3037ay 4. i 2 c function is available only for pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, and 70f3037ay 5. pd70f3035a, 70f3035ay, 70f3037a, 70f3037ay 6. pd703034a, 703034ay, 703035a, 703035ay, 703036a, 703036ay, 703037a, 703037ay chapter 1 introduction user?s manual u13850ej4v0um 48 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as the multiplier (16 bits 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (c) rom this consists of a mask rom or flash memory mapped to the address space starting at 00000000h. the rom capacity varies depending on the product. the rom capacity of each product is shown below. pd703034a, 703034ay: 128 kb (mask rom) pd703035a, 703035ay: 256 kb (mask rom) pd70f3035a, 70f3035ay: 256 kb (flash memory) pd703036a, 703036ay: 384 kb (mask rom) pd703037a, 703037ay: 512 kb (mask rom) pd70f3037a, 70f3037ay: 512 kb (flash memory) rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram the ram capacity and mapping addresses vary depending on the product. the ram capacity of each product is shown below. pd703034a, 703034ay: 12 kb (mapping starts at ffffc000h) pd703035a, 703035ay, 70f3035a, 70f3035ay: 16 kb (mapping starts at ffffb000h) pd703036a, 703036ay: 20 kb (mapping starts at ffffa000h) pd703037a, 703037ay, 70f3037a, 70f3037ay: 24 kb (mapping starts at ffff9000h) ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators; each for main system clock (f xx ) and for subsystem clock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). chapter 1 introduction user?s manual u13850ej4v0um 49 (g) timer/counter a two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8- bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. the two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. the two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) watch timer this timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 khz subsystem clock or the 16.777 mhz main system clock). at the same time, the watch timer can be used as an interval timer for the main system clock. (i) watchdog timer a watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs. (j) serial interface (sio) the v850/sb2 includes three kinds of serial interfaces: asynchronous serial interfaces (uart0, uart1), clocked serial interfaces (csi0 to csi3), and an 8-/16-bit variable-length serial interface (csi4). these plus the i 2 c bus interfaces (i 2 c0, i 2 c1) comprise five channels. two of these channels are switchable between the uart and csi and another two switchable between csi and i 2 c. for uart0 and uart1, data is transferred via the txd0, txd1, rxd0, and rxd1 pins. for csi0 to csi3, data is transferred via the so0 to so3, si0 to si3, and sck0 to sck3 pins. for csi4, data is transferred via the so4, si4, and sck4 pins. for i 2 c0 and i 2 c1, data is transferred via the sda0, sda1, scl0, and scl1 pins. i 2 c0 and i 2 c1 are equipped only in the pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, 70f3037ay. for uart and csi4, a dedicated baud rate generator is equipped. (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion uses the successive approximation method. (l) dma controller a six-channel dma controller is equipped. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (m) real-time output port (rtp) the rtp is a real-time output function that transfers previously set 8-bit data to an output latch when an external trigger signal occurs or when there is a coincidence signal in a timer compare register. it can also be used for 4-bit 2 channels. chapter 1 introduction user?s manual u13850ej4v0um 50 (n) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger, rtp trigger port 1 6-bit i/o serial interface port 2 8-bit i/o serial interface, timer i/o port 3 8-bit i/o timer i/o, external address bus, serial interface port 4 8-bit i/o external address/data bus port 5 8-bit i/o port 6 6-bit i/o external address bus port 7 8-bit input a/d converter analog input port 8 4-bit input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o real-time output port, external address bus, key return input, iebus data i/o port 11 4-bit i/o general- purpose port wait control, external address bus (o) iebus controller iebus controller is a small-scale digital data transfer system aiming at data transfer among units. iebus controller is incorporated only in the v850/sb2. user?s manual u13850ej4v0um 51 chapter 2 pin functions 2.1 list of pin functions the names and functions of pins of the v850/sb1 and v850/sb2 are described below with dividing into port pins and non-port pins. there are three types of power supplies for the pin i/o buffers: av dd , bv dd , and ev dd . the relationship between these power supply and the pins is described below. table 2-1. pin i/o buffer power supply power supply corresponded pins usable voltage range av dd port 7, port 8 4.5 v av dd 5.5 v bv dd port 4, port 5, port 6, port 9, clkout 3.0 v bv dd 5.5 v ev dd port 0, port 1, port 2, port 3, port 10, port 11, reset 3.0 v ev dd 5.5 v caution the electrical specifications in the case of 3.0 v to up to 4.0 v are different from those for 4.0 v to 5.5 v. differences of pins between the v850/sb1 and v850/sb2 are shown below. table 2-2. differences of pins between v850/sb1 and v850/sb2 v850/sb1 v850/sb2 pin pd703030a, pd703031a, pd703032a, pd703033a pd70f3032a, pd70f3033a pd703030ay, pd703031ay, pd703032ay, pd703033ay pd70f3032ay, pd70f3033ay pd703034a, pd703035a, pd703036a, pd703037a pd70f3035a, pd70f3037a pd703034ay, pd703035ay, pd703036ay, pd703037ay pd70f3035ay, pd70f3037ay ic available none available none available none available none v pp none available none available none available none available sda0, sda1 none available none available scl0, scl1 none available none available ierx none available ietx none available chapter 2 pin functions user?s manual u13850ej4v0um 52 (1) port pins (1/3) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 i/o yes port 0 8-bit i/o port input/output mode can be specified in 1-bit units. intp6 p10 si0/sda0 p11 so0 p12 sck0/scl0 p13 si1/rxd0 p14 so1/txd0 p15 i/o yes port 1 6-bit i/o port input/output mode can be specified in 1-bit units. sck1/asck0 p20 si2/sda1 p21 so2 p22 sck2/scl1 p23 si3/rxd1 p24 so3/txd1 p25 sck3/asck1 p26 ti2/to2 p27 i/o yes port 2 8-bit i/o port input/output mode can be specified in 1-bit units. ti3/to3 remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 53 (2/3) pin name i/o pull function alternate function p30 ti00 p31 ti01 p32 ti10/si4 p33 ti11/so4 p34 to0/a13/sck4 p35 to1/a14 p36 ti4/to4/a15 p37 i/o yes port 3 8-bit i/o port input/output mode can be specified in 1-bit units. ti5/to5 p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output mode can be specified in 1-bit units. ad7 p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output mode can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output mode can be specified in 1-bit units. a21 remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 54 (3/3) pin name i/o pull function alternate function p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output mode can be specified in 1-bit units. hldrq p100 rtp0/a5/kr0 p101 rtp1/a6/kr1 p102 rtp2/a7/kr2 p103 rtp3/a8/kr3 p104 rtp4/a9/kr4/ierx p105 rtp5/a10/kr5/ietx p106 rtp6/a11/kr6 p107 i/o yes port 10 8-bit i/o port input/output mode can be specified in 1-bit units. rtp7/a12/kr7 p110 a1/wait p111 a2 p112 a3 p113 i/o yes port 11 4-bit i/o port input/output mode can be specified in 1-bit units. a4 remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 55 (2) non-port pins (1/3) pin name i/o pull function alternate function a1 p110/wait a2 to a4 p111 to p113 a5 to a8 p100/rtp0/kr0 to p103/rtp3/kr3 a9 p104/rtp4/kr4/ierx a10 p105/rtp5/kr5/ietx a11, a12 p106/rtp6/kr6 to p107/rtp7/kr7 a13 p34/to0/sck4 a14 p35/to1 a15 output yes lower address bus used for external memory expansion p36/ti4/to4 a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p50 to p57 adtrg input yes a/d converter external trigger input p05/intp4 ani0 to ani7 input no p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 p15/sck1 asck1 input yes serial clock input for uart0 and uart1 p25/sck3 astb output no external address strobe signal output p94 av dd ?? positive power supply for a/d converter and alternate-function port ? av ref input ? reference voltage input for a/d converter ? av ss ?? ground potential for a/d converter and alternate-function port ? bv dd ?? positive power supply for bus interface and alternate-function port ? bv ss ?? ground potential for bus interface and alternate-function port ? clkout output ? internal system clock output ? dstb output no external data strobe signal output p93/rd ev dd ?? power supply for i/o port and alternate-function pin (except for bus interface) ? ev ss ?? ground potential for i/o port and alternate-function pin (except for bus interface) ? hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 ierx input iebus data input (v850/sb2 only) p104/rtp4/kr4/a9 ietx output yes iebus data output (v850/sb2 only) p105/rtp5/kr5/a10 intp0 to intp3 external interrupt request input (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 input yes external interrupt request input (digital noise elimination) p06/rtptrg remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 56 (2/3) pin name i/o pull function alternate function intp6 external interrupt request input (digital noise elimination for remote control) p07 kr0 to kr3 p100/a5/rtp0 to p103/a8/rtp3 kr4 p104/a9/rtp4/ierx kr5 p105/a10/rtp5/ietx kr6, kr7 input yes key return input p106/a11/rtp6 to p107/a12/rtp7 lben output no external data bus?s lower byte enable signal output p90/wrl ic ?? internally connected ( pd70303xa and 70303xay only) ? nmi input yes non-maskable interrupt request input p00 rd output no read strobe signal output p93/dstb regc ?? capacitor connection for regulator output stabilization ? reset input ? system reset input ? rtp0 to rtp3 p100/a5/kr0 to p103/a8/kr3 rtp4 p104/a9/kr4/ierx rtp5 p105/a10/kr5/ietx rtp6, rtp7 output yes real-time output port p106/a11/kr6, p107/a12/kr7 rtptrg input yes rtp external trigger input p06/intp5 r/w output no external read/write status output p92/wrh rxd0 p13/si1 rxd1 input yes serial receive data input for uart0 and uart1 p23/si3 sck0 p12/scl0 sck1 p15/asck0 sck2 p22/scl1 sck3 serial clock i/o (3-wire type) for csi0 to csi3 p25/asck1 sck4 i/o yes serial clock i/o for variable-length csi4 (3-wire type) p34/to0/a13 scl0 p12/sck0 scl1 i/o yes serial clock i/o for i 2 c0 and i 2 c1 ( pd70303xay and 70f303way only) p22/sck2 sda0 p10/si0 sda1 i/o yes serial transmit/receive data i/o for i 2 c0 and i 2 c1 ( pd70303xay and 70f303way only) p20/si2 si0 p10/sda0 si1 p13/rxd0 si2 p20/sda1 si3 serial receive data input (3-wire type) for csi0 to csi3 p23/rxd1 si4 input yes serial receive data input (3-wire type) for variable-length csi4 p32/ti10 so0 output yes serial transmit data output (3-wire type) for csi0 to csi3 p11 remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 57 (3/3) pin name i/o pull function alternate function so1 p14/txd0 so2 p21 so3 serial transmit data output (3-wire type) for csi0 to csi3 p24/txd1 so4 output yes serial transmit data output for variable-length csi4 (3-wire type) p33/ti11 ti00 shared as external capture trigger input and external count clock input for tm0 p30 ti01 external capture trigger input for tm0 p31 ti10 shared as external capture trigger input and external count clock input for tm1 p32/si4 ti11 external capture trigger input for tm1 p33/so4 ti2 external count clock input for tm2 p26/to2 ti3 input yes external count clock input for tm3 p27/to3 ti4 external count clock input for tm4 p36/to4/a15 ti5 input yes external count clock input for tm5 p37/to5 to0, to1 pulse signal output for tm0, tm1 p34/a13/sck4/p35/ a14 to2 pulse signal output for tm2 p26/ti2 to3 pulse signal output for tm3 p27/ti3 to4 pulse signal output for tm4 p36/ti4/a15 to5 output yes pulse signal output for tm5 p37/ti5 txd0 p14/so1 txd1 output yes serial transmit data output for uart0 and uart1 p24/so3 uben output no higher byte enable signal output for external data bus p91 v dd ?? positive power supply pin ? v pp ?? high-voltage apply pin for program write/verify ( pd70f303wa and 70f303way only) ? v ss ?? gnd potential ? wait input yes control signal input for inserting wait in bus cycle p110/a1 wrh higher byte write strobe signal output for external data bus p92/r/w wrl output no lower byte write strobe signal output for external data bus p90/lben x1 input ? x2 ? no resonator connection for main clock ? xt1 input ? xt2 ? no resonator connection for subsystem clock ? remark pull: on-chip pull-up resistor chapter 2 pin functions user?s manual u13850ej4v0um 58 2.2 pin states the operating states of various pins are described below with reference to their operation modes. table 2-3. pin operating state in operation mode operation mode pin reset stop mode idle mode halt mode bus hold idle state ad0 to ad15 hi-z hi-z hi-z hi-z hi-z hi-z a1 to a15 hi-z held held held held held a16 to a21 hi-z hi-z hi-z held hi-z held lben, uben hi-z hi-z hi-z held hi-z held r/w hi-z hi-z hi-z h hi-z h dstb, wrl, wrh, rd hi-z hi-z hi-z h hi-z h astb hi-z hi-z hi-z h hi-z h hldrq ??? operating operating operating hldak hi-z hi-z hi-z operating l operating wait ?????? clkout hi-z l l operating note operating note operating note note ?l? when in clock output inhibit mode remark hi-z: high impedance held: state is held during previously set external bus cycle l: low-level output h: high-level output ? : input without being sampled chapter 2 pin functions user?s manual u13850ej4v0um 59 2.3 description of pin functions (1) p00 to p07 (port 0) ??? 3-state i/o port 0 is an 8-bit i/o port in which input and output can be set in 1-bit units for input or output. p00 to p07 can function as i/o port pins and can also function as nmi inputs, external interrupt request inputs, external triggers for the a/d converter, and external triggers for the real-time output port. port/control mode can be selected for each bit, and the pin?s valid edge is specified by the egp0 and egn0 registers. (a) port mode p00 to p07 can be set in 1-bit units as input or output pins according to the contents of the port 0 mode register (pm0). (b) control mode (i) nmi (non-maskable interrupt request) ??? input this is a non-maskable interrupt request signal input pin. (ii) intp0 to intp6 (interrupt request from peripherals) ??? input these are external interrupt request input pins. (iii) adtrg (ad trigger input) ??? input this is the a/d converter?s external trigger input pin. this pin is controlled with a/d converter mode register 1 (adm1). (iv) rtptrg (real-time port trigger input) ??? input this is the real-time output port?s external trigger input pin. this pin is controlled with the real-time output port control register (rtpc). chapter 2 pin functions user?s manual u13850ej4v0um 60 (2) p10 to p15 (port 1) ??? 3-state i/o port 1 is a 6-bit i/o port in which input and output can be specified in 1-bit units. p10 to p15 can function as i/o port pins and can also operate as input or output pins for the serial interface. port/control mode can be selected for each bit. p10 to p12, p14, and p15 can select normal output and n-ch open-drain output. (a) port mode p10 to p15 can be set in 1-bit units as input or output pins according to the contents of the port 1 mode register (pm1). (b) control mode (i) si0, si1 (serial input 0, 1) ??? input these are the serial receive data input pins of csi0 and csi1. (ii) so0, so1 (serial output 0, 1) ??? output these are the serial transmit data output pins of csi0 and csi1. (iii) sck0, sck1 (serial clock 0, 1) ??? 3-state i/o these are the serial clock i/o pins for csi0 and csi1. (iv) sda0 (serial data 0) ??? i/o this is the serial transmit/receive data i/o pin for i 2 c0 ( pd70303xay and 70f303way only). (v) scl0 (serial clock 0) ??? i/o this is the serial clock i/o pin for i 2 c0 ( pd70303xay and 70f303way only). (vi) rxd0 (receive data 0) ??? input this is the serial receive data pin of uart0. (vii) txd0 (transmit data 0) ??? output this is the serial transmit data pin of uart0. (viii) asck0 (asynchronous serial clock 0) ??? input this is the serial baud rate clock pin of uart0. chapter 2 pin functions user?s manual u13850ej4v0um 61 (3) p20 to p27 (port 2) ??? 3-state i/o port 2 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p20 to p27 can function as i/o port pins, input or output pins for the serial interface, and input or output for the timer/counter. port/control mode can be selected for each bit. p20 to p22, p24 and p25 can select normal output and n-ch open-drain output. (a) port mode p20 to p27 can be set in 1-bit units as input or output pins according to the contents of the port 2 mode register (pm2). (b) control mode (i) si2, si3 (serial input 2, 3) ??? input these are the serial receive data input pins of csi2 and csi3. (ii) so2, so3 (serial output 2, 3) ??? output these are the serial transmit data output pins of csi2 and csi3. (iii) sck2, sck3 (serial clock 2, 3) ??? 3-state i/o these are the serial clock i/o pins of csi2 and csi3. (iv) sda1 (serial data 1) ... i/o this is the serial transmit/receive data i/o pin for i 2 c1 ( pd70303xay and 70f303way only). (v) scl1 (serial clock 1) ... i/o this is the serial clock i/o pin for i 2 c1 ( pd70303xay and 70f303way only). (vi) rxd1 (receive data 1) ... input this is the serial receive data input pin of uart1. (vii) txd1 (transmit data 1) ... output this is the serial transmit data output pin of uart1. (viii) asck1 (asynchronous serial clock 1) ... input this is the serial baud rate clock input pin of uart1. (ix) ti2 and ti3 (timer input 2, 3) ... input these are the external counter clock input pins for timer 2 and timer 3. (x) to2 and to3 (timer output 2, 3) ... output these are the external counter clock output pins for timer 2 and timer 3. chapter 2 pin functions user?s manual u13850ej4v0um 62 (4) p30 to p37 (port 3) ??? 3-state i/o port 3 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p30 to p37 can function as i/o port pins, input or output pins for the timer/counter, an address bus (a13 to a15) when memory is expanded externally, and serial interface i/o. port/control mode can be selected for each bit. p31 and p32 can select normal output and n-ch open-drain output. (a) port mode p30 to p37 can be set in 1-bit units as input or output pins according to the contents of the port 3 mode register (pm3). (b) control mode (i) ti00, ti01, ti10, ti11, ti4, ti5 (timer input 00, 01, 10, 11, 4, 5) ??? input these pins accept external count clock input from timer 0, timer 1, timer 4, and timer 5. (ii) to0, to1, to4, to5 (timer output 0, 1, 4, 5) ??? output these are the pulse signal output pins of timer 0, timer 1, timer 4, and timer 5. (iii) a13 to a15 (address 13 to 15) ??? output these comprise the address bus that is used for external access. these pins operate as the a13 to a15 bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. (iv) si4 (serial input 4) ??? input this is the serial receive data input pin of csi4. (v) so4 (serial output 4) ??? output this is the serial transmit data output pin for csi4. (vi) sck4 (serial clock 4) ??? 3-state i/o this is the i/o pin for csi4 serial clock. (5) p40 to p47 (port 4) ??? 3-state i/o port 4 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p40 to p47 can function as i/o port pins and as a time division address/data bus (ad0 to ad7) when memory is expanded externally. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as a reference. (a) port mode p40 to p47 can be set in 1-bit units as input or output pins according to the contents of the port 4 mode register (pm4). chapter 2 pin functions user?s manual u13850ej4v0um 63 (b) control mode (external expansion mode) p40 to p47 can be set as ad0 to ad7 according to the contents of the memory expansion register (mm). (i) ad0 to ad7 (address/data 0 to 7) ??? 3-state i/o these comprise the multiplexed address/data bus that is used for external access. at the address timing (t1 state), these pins operate as ad0 to ad7 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the lower 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle as inactive, these pins go into a high-impedance state. (6) p50 to p57 (port 5) ??? 3-state i/o port 5 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p50 to p57 can function as i/o port pins and as a time division address/data bus (ad8 to ad15) when memory is expanded externally. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as reference. (a) port mode p50 to p57 can be set in 1-bit units as input or output pins according to the contents of the port 5 mode register (pm5). (b) control mode (external expansion mode) p50 to p57 can be set as ad8 to ad15 according to the contents of the memory expansion register (mm). (i) ad8 to ad 1 5 (address/data 8 to 1 5) ??? 3-state i/o these comprise the multiplexed address/data bus that is used for external access. at the address timing (t1 state), these pins operate as ad8 to ad15 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the higher 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle as inactive, these pins go into a high-impedance state. (7) p60 to p65 (port 6) ??? 3-state i/o port 6 is a 6-bit i/o port in which input and output pins can be specified in 1-bit units. p60 to p65 can function as i/o port pins and as address buses (a16 to a21) when memory is expanded externally. the higher 2 bits of port 6 are ignored when data is written to the port in 8-bit units. when data is read from the port, 00 is read from these bits. port/control mode can be selected for each 2 bits. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as reference. (a) port mode p60 to p65 can be set in 1-bit units as input or output pins according to the contents of the port 6 mode register (pm6). (b) control mode p60 to p65 can be set as a16 to a21 according to the contents of the memory expansion register (mm). chapter 2 pin functions user?s manual u13850ej4v0um 64 (i) a16 to a21 (address 16 to 21) ??? output these comprise an address bus that is used for external access. these pins operate as the higher 6-bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. (8) p70 to p77 (port 7), p80 to p83 (port 8) ??? input port 7 is an 8-bit input-only port in which all pins are fixed as input pins. port 8 is a 4-bit input-only port. p70 to p77 and p80 to p83 can function as input ports and as analog input pins for the a/d converter. however, they cannot be switched between these input port and analog input pin. (a) port mode p70 to p77 and p80 to p83 are input-only pins. (b) control mode (external expansion mode) p70 to p77 also function as pins ani0 to ani7 and p80 to p83 also function as ani8 to ani11, but these alternate functions are not switchable. (i) ani0 to ani11 (analog input 0 to 11) ??? input these are analog input pins for the a/d converter. connect a capacitor between these pins and av ss to prevent noise-related operation faults. also, do not apply voltage that is outside the range for av ss and av ref to pins that are being used as inputs for the a/d converter. if it is possible for noise above the av ref range or below the av ss to enter, clamp these pins using a diode that has a small v f value. (9) p90 to p96 (port 9) ??? 3-state i/o port 9 is a 7-bit i/o port in which input and output can be specified in 1-bit units. p90 to p96 can function as i/o port pins, control signal output pins, and bus hold control signal output pins when memory is expanded externally. during 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a ?0? during a read operation. the i/o signal level uses the bus interface power supply pins bv dd and bv ss as a reference. (a) port mode p90 to p96 can be set in 1-bit units as input or output pins according to the contents of the port 9 mode register (pm9). (b) control mode (external expansion mode) p90 to p96 can be set to operate as control signal outputs for external memory expansion according to the contents of the memory expansion register (mm). (i) lben (lower byte enable) ??? output this is a lower byte enable signal output pin for an external 16-bit data bus. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. chapter 2 pin functions user?s manual u13850ej4v0um 65 (ii) uben (upper byte enable) ??? output this is an upper byte enable signal output pin for an external 16-bit data bus. during byte access of even-numbered addresses, these pins are set as inactive (high level). the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. access uben lben ad0 word access 0 0 0 half word access 0 0 0 byte access even-numbered address 1 0 0 odd-numbered address 0 1 1 (iii) r/w (read/write status) ??? output this is an output pin for the status signal pin that indicates whether the bus cycle is a read cycle or write cycle during external access. high level is set during the read cycle and low level is set during the write cycle. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. high level is set when the timing sets the bus cycle as inactive. (iv) dstb (data strobe) ??? output this is an output pin for the external data bus?s access strobe signal. output becomes active (low level) during the t2 and tw states of the bus cycle. output becomes inactive (high level) when the timing sets the bus cycle as inactive. (v) astb (address strobe) ??? output this is an output pin for the external address bus?s latch strobe signal. output becomes active (low level) in synchronization with the falling edge of the clock during the t1 state of the bus cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the t3 state of the bus cycle. output becomes inactive when the timing sets the bus cycle as inactive. (vi) hldak (hold acknowledge) ??? output this is an output pin for the acknowledge signal that indicates high impedance status for the address bus, data bus, and control bus when the v850/sb1 or v850/sb2 receives a bus hold request. the address bus, data bus, and control bus are set to high impedance status when this signal is active. (vii) hldrq (hold request) ??? input this is an input pin by which an external device requests the v850/sb1 or v850/sb2 to release the address bus, data bus, and control bus. this pin accepts asynchronous input for clkout. when this pin is active, the address bus, data bus, and control bus are set to high impedance status. this occurs either when the v850/sb1 or v850/sb2 completes execution of the current bus cycle or immediately if no bus cycle is being executed, then the hldak signal is set as active and the bus is released. (viii) wrl (write strobe low level data) ??? output this is a write strobe signal output pin for the lower data in an external 16-bit data bus. output occurs during the write cycle, similar to dstb. chapter 2 pin functions user?s manual u13850ej4v0um 66 (ix) wrh (write strobe high level data) ??? output this is a write strobe signal output pin for the higher data in an external 16-bit data bus. output occurs during the write cycle, similar to dstb. (x) rd (read) ??? output this is a read strobe signal output pin for an external 16-bit data bus. output occurs during the read cycle, similar to dstb. (10) p100 to p107 (port 10) ??? 3-state i/o port 10 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p100 to p107 can function as i/o port pins, a real-time output port, an address bus (a5 to a12) when memory is expanded externally, a key return input and iebus data i/o (v850/sb2 only). p100 to p107 can select normal output and n-ch open-drain output. (a) port mode p100 to p107 can be set in 1-bit units as input or output pins according to the contents of the port 10 mode register (pm10). (b) control mode (i) rtp0 to rtp7 (real-time output port 0 to 7) ??? output these pins comprise a real-time output port. (ii) a5 to a12 (address 5 to 12) ??? output these comprise the address bus that is used for external access. these pins operate as a5 to a12 bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. (iii) kr0 to kr7 (key return 0 to 7) ... input these are key return input pins. their operations are specified by the key return mode register (krm). (iv) ierx (iebus receive data) ... input this is an iebus data input signal. this pin is only for v850/sb2. (v) ietx (iebus transmit data) ... output this is an iebus data output signal. this pin is only for v850/sb2. (11) p110 to p113 (port 11) ??? 3-state i/o port 11 is a 4-bit i/o port in which input and output can be specified in 1-bit units. p110 to p113 can function as i/o port pins, an address bus (a1 to a4) when memory is expanded externally, and the control signal (wait) that inserts waits into the bus cycle. (a) port mode p110 to p113 can be set in 1-bit units as inputs or outputs according to the contents of the port 11 mode register (pm11). chapter 2 pin functions user?s manual u13850ej4v0um 67 (b) control mode (i) a1 to a4 (address 1 to 4) ??? output these comprise the address bus that is used for external access. these pins operate as the lower 4- bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained. (ii) wait (wait) ??? input this is an input pin for the control signal used to insert waits into the bus cycle. this pin is sampled at the falling edge of the clock during the t2 or tw state of the bus cycle. on/off switching of the wait function is performed by the port alternate function control register (pac). caution because the supply voltage to the i/o buffer of the wait pin is ev dd , if the voltage of ev dd and that of bv dd differ, use ev dd as the voltage of the external wait signal, instead of bv dd . (12) reset (reset) ??? input reset input is asynchronous input for a signal that has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/start operations, this pin can also be used to cancel a standby mode (halt, idle, or stop mode). (13) regc (regulator control) ... input this pin is used to connect the regulator-use capacitor. (14) clkout (clock out) ? output this pin outputs the bus clock generated internally. (15) x1 and x2 (crystal) these pins are used to connect the resonator that generates the system clock. (16) xt1, xt2 (crystal for sub clock) these pins are used to connect the resonator that generates the sub clock. (17) av dd (analog v dd ) this is the analog power supply pin for the a/d converter and alternate-function ports. (18) av ss (analog v ss ) this is the ground pin for the a/d converter and alternate-function ports. (19) av ref (analog reference voltage) ? input this is the reference voltage supply pin for the a/d converter. (20) bv dd (power supply for bus interface) this is the positive power supply pin for the bus interface and alternate-function ports. chapter 2 pin functions user?s manual u13850ej4v0um 68 (21) bv ss (ground for bus interface) this is the ground pin for the bus interface. (22) ev dd (power supply for port) this is the positive power supply pin for i/o ports and alternate-function pins (except for the alternate-function ports of the bus interface). (23) ev ss (ground for port) this is the ground pin for i/o ports and alternate-function pins (except for the alternate-function ports of the bus interface). (24) v dd (power supply) these are the positive power supply pins. all v dd pins should be connected to a positive power source. (25) v ss (ground) these are the ground pins. all v ss pins should be grounded. (26) v pp (programming power supply) this is the positive power supply pin used for flash memory programming mode. this pin is used in the pd70f303wa and 70f303way. connect to v ss in normal operating mode. (27) ic (internally connected) this is an internally connected pin used in the pd70303xa and 70303xay. connect directly to v ss in normal operating mode. chapter 2 pin functions user?s manual u13850ej4v0um 69 2.4 i/o circuit types, i/o buffer power supply and connection of unused pins (1/2) pin alternate function i/o buffer power supply i/o circuit type recommended connection method p00 nmi p01 to p04 intp0 to intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 intp6 ev dd 8-a p10 si0/sda0 10-a p11 so0 26 p12 sck0/scl0 10-a p13 si1/rxd0 8-a p14 so1/txd0 26 p15 sck1/asck0 ev dd 10-a p20 si2/sda1 10-a p21 so2 26 p22 sck2/scl1 p23 si3/rxd1 10-a p24 so3/txd1 26 p25 sck3/asck1 10-a p26, p27 ti2/to2, ti3/to3 ev dd 8-a p30, p31 ti00, ti01 p32, p33 ti10/si4, ti11/so4 p34 to0/a13/sck4 8-a p35 to1/a14 5-a p36 ti4/to4/a15 p37 ti5/to5 ev dd 8-a input: individually connect to ev dd or ev ss via a resistor output: leave open p40 to p47 ad0 to ad7 p50 to p57 ad8 to ad15 p60 to p65 a16 to a21 bv dd 5 input: individually connect to bv dd or bv ss via a resistor output: leave open p70 to p77 ani0 to ani7 p80 to p83 ani8 to ani11 av dd 9 individually connect to av dd or av ss via a resistor chapter 2 pin functions user?s manual u13850ej4v0um 70 (2/2) pin alternate function i/o buffer power supply i/o circuit type recommended connection method p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq bv dd 5 input: individually connect to ev dd or ev ss via a resistor output: leave open p100 to p103 rtp0/a5/kr0 to rtp3/a8/kr3 p104 rtp4/a9/kr4/ierx p105 rtp5/a10/kr5/ietx p106, p107 rtp6/a11/kr6, rtp7/a12/kr7 ev dd 10-a p110 a1/w ait p111 to p113 a2 to a4 ev dd 5-a input: individually connect to ev dd or ev ss via a resistor output: leave open av ref ??? connect to av ss via a resistor clkout ? bv dd 4 leave open reset ? ev dd 2 ? x1 ??? ? x2 ??? ? xt1 ?? 16 connect to v ss via a resistor xt2 ?? 16 leave open v pp note 1 ??? connect to v ss ic note 2 ??? connect directly to v ss v ss ??? ? av dd ??? ? av ss ??? ? bv dd ??? ? bv ss ??? ? ev dd ??? ? ev ss ??? ? notes 1. pd70f303wa, 70f303way 2. pd70303xa, 70303xay chapter 2 pin functions user?s manual u13850ej4v0um 71 2.5 i/o circuit of pins (1/2) type 2 schmitt-triggered input with hysteresis characteristics type 5-a type 4 push-pull output that can be set for high impedance output (both p-ch and n-ch off). type 8-a type 5 type 9 pullup enable input enable in/out data output disable n - ch p - ch p-ch v dd v dd in out output disable n-ch data p-ch v dd pullup enable in/out data output disable n-ch p-ch p-ch v dd v dd output disable input enable in/out data n- ch p-ch v dd + - n- ch p-ch input enable v ref (threshold voltage) comparator chapter 2 pin functions user?s manual u13850ej4v0um 72 (2/2) type 10-a type 26 type 16 pullup enable in/out data open drain output disable n-ch p-ch p-ch v dd v dd pullup enable in/out data open drain output disable n-ch p-ch p-ch v dd v dd p-ch xt1 xt2 feedback cut-off user?s manual u13850ej4v0um 73 chapter 3 cpu functions the cpu of the v850/sb1 and v850/sb2 is based on risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 features ? minimum instruction execution time: v850/sb1: 50 ns (@ 20 mhz internal operation) v850/sb2: 79 ns (@ 12.58 mhz internal operation) ? address space: 16 mb linear ? thirty-two 32-bit general-purpose registers ? internal 32-bit architecture ? five-stage pipeline control ? multiplication/division instructions ? saturated operation instructions ? one-clock 32-bit shift instruction ? load/store instruction with long/short format ? four types of bit manipulation instructions ? set1 ?clr1 ?not1 ?tst1 chapter 3 cpu functions user?s manual u13850ej4v0um 74 3.2 cpu register set the cpu registers of the v850/sb1 and v850/sb2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers are 32 bits wide. for details, refer to v850 family user?s manual architecture . figure 3-1. cpu register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address register stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) pc program counter psw program status word ecr exception cause register fepc fepsw fatal error pc fatal error psw eipc eipsw exception/interrupt pc exception/interrupt psw 31 0 31 0 31 0 31 0 31 0 31 0 system register set program register set chapter 3 cpu functions user?s manual u13850ej4v0um 75 3.2.1 program register set the program register set includes general-purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. also, r1, r3, r4, r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer register to indicate the start of the text area note r6 to r29 address/data variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution note area in which program code is mapped. (2) program counter (pc) this register holds the address of the instruction under execution. the lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. if a carry occurs from bit 23 to 24, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. figure 3-2. program counter (pc) after reset: 00000000h symbol 31 24 23 1 0 pc fixed to 0 instruction address under execution 0 chapter 3 cpu functions user?s manual u13850ej4v0um 76 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. table 3-2. system register numbers no. system register name usage operation 0eipc 1eipsw interrupt status saving registers these registers save the pc and psw when an exception or interrupt occurs. because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. 2fepc 3fepsw nmi status saving registers these registers save pc and psw when nmi occurs. 4 ecr interrupt source register if exception, maskable interrupt, or nmi occurs, this register will contain information referencing the interrupt source. the higher 16 bits of this register are called fecc, to which exception code of nmi is set. the lower 16 bits are called eicc, to which exception code of exception/interrupt is set. 5 psw program status word a program status word is a collection of flags that indicate program status (instruction execution result) and cpu status. 6 to 31 reserved to read/write these system registers, specify a system register number indicated by the system register load/store instruction (ldsr or stsr instruction). (1) interrupt source register (ecr) figure 3-3. interrupt source register (ecr) after reset: 00000000h symbol 31 16 15 0 ecr fecc eicc fecc exception code of nmi (for exception code, refer to table 5-1 .) eicc exception code of exception/interrupt chapter 3 cpu functions user?s manual u13850ej4v0um 77 (2) program status word (psw) figure 3-4. program status word (psw) after reset: 00000020h symbol31 876543210 psw rfu np ep id sat cy ov s z rfu reserved field (fixed to 0). np indicates that nmi processing is in progress. this flag is set when nmi is accepted, and disables multiple interrupts. ep indicates that trap processing is in progress. this flag is set when trap is generated. moreover, interrupt requests can be accepted when this bit is sets. id indicates that accepting external interrupt request is disabled. sat this flag is set if the result of executing saturated operation instruction overflows. if overflow does not occur, value of previous operation is held. cy this flag is set if carry or borrow occurs as result of operation. if carry or borrow does not occur, it is reset. ov this flag is set if overflow occurs during operation. if overflow does not occur, it is reset. s this flag is set if the result of operation is negative. it is reset if the result is positive. z this flag is set if the result of operation is zero. if the result is not zero, it is reset. chapter 3 cpu functions user?s manual u13850ej4v0um 78 3.3 operation modes the v850/sb1 and v850/sb2 have the following operation modes. (1) normal operation mode (single-chip mode) after the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal rom, and instruction processing written in the internal rom is started. however, external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register (mm) by instruction. (2) flash memory programming mode this mode is provided only in the pd70f3032a, 70f3032ay, 70f3033a, 70f3033ay, 70f3035a, 70f3035ay, 70f3037a, 70f3037ay. the internal flash memory is programmable or erasable when the v pp voltage is applied to the v pp pin. v pp operation mode 0 normal operation mode 7.8 v flash memory programming mode v dd setting prohibited chapter 3 cpu functions user?s manual u13850ej4v0um 79 3.4 address space 3.4.1 cpu address space the cpus of the v850/sb1 and v850/sb2 are of 32-bit architecture and support up to 4 gb of linear address space (data space) during operand addressing (data access). when referencing instruction addresses, linear address space (program space) of up to 16 mb is supported. the cpu address space is shown below. figure 3-5. cpu address space ffffffffh cpu address space program area (16 mb linear) data area (4 gb linear) 01000000h 00ffffffh 00000000h chapter 3 cpu functions user?s manual u13850ej4v0um 80 3.4.2 image the core cpu supports 4 gb of ?virtual? addressing space, or 256 memory blocks, each containing 16 mb memory locations. in actuality, the same 16 mb block is accessed regardless of the values of bits 31 to 24 of the cpu address. the image of the virtual addressing space is shown below. because the higher 8 bits of a 32-bit cpu address are ignored and the cpu address is only seen as a 24-bit external physical address, the physical location xx000000h is equally referenced by multiple address values 00000000h, 01000000h, 02000000h, ... fe000000h, ff000000h. figure 3-6. image on address space ffffffffh ff000000h feffffffh image cpu address space image image image image fe000000h fdffffffh 02000000h 01ffffffh 01000000h 00ffffffh 00000000h physical address space internal peripheral i/o internal ram (access prohibited) internal rom xxffffffh xx000000h chapter 3 cpu functions user?s manual u13850ej4v0um 81 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address 00ffffffh are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instruction can be fetched from the 4 kb area of 00fff000h to 00ffffffh because this area is defined as peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. figure 3-7. program space 00fffffeh 00ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. figure 3-8. data space fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ? ) direction chapter 3 cpu functions user?s manual u13850ej4v0um 82 3.4.4 memory map the v850/sb1 and v850/sb2 reserve areas as shown below. figure 3-9. memory map xxffffffh internal peripheral i/o area internal ram area (reserved) on-chip flash memory/ rom area internal peripheral i/o area internal ram area external memory area on-chip flash memory/ rom area single-chip mode single-chip mode (external expansion mode) 16 mb 1 mb 4 kb xxfff000h xxffefffh xx100000h xx0fffffh xx000000h xxff8000h xxff7fffh 28 kb chapter 3 cpu functions user?s manual u13850ej4v0um 83 3.4.5 area (1) internal rom/flash memory area an area of 1 mb maximum is reserved for the internal rom/flash memory area. (a) v850/sb1 ( pd703031a, 703031ay), v850/sb2 ( pd703034a, 703034ay) 128 kb are available for the addresses xx000000h to xx01ffffh. addresses xx020000h to xx0fffffh are an access-prohibited area figure 3-10. internal rom area (128 kb) x x 0 f f f f f h x x 0 2 0 0 0 0 h x x 0 1 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom (b) v850/sb1 ( pd703033a, 703033ay, 70f3033a, 70f3033ay) v850/sb2 ( pd703035a, 703035ay, 70f3035a, 70f3035ay) 256 kb are available for the addresses xx000000h to xx03ffffh. addresses xx040000h to xx0fffffh are an access-prohibited area figure 3-11. internal rom/flash memory area (256 kb) x x 0 f f f f f h x x 0 4 0 0 0 0 h x x 0 3 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom/ flash memory chapter 3 cpu functions user?s manual u13850ej4v0um 84 (c) v850/sb1 ( pd703030a, 703030ay), v850/sb2 ( pd703036a, 703036ay) 384 kb are available for the addresses xx000000h to xx05ffffh. addresses xx060000h to xx0fffffh are an access-prohibited area figure 3-12. internal rom area (384 kb) x x 0 f f f f f h x x 0 6 0 0 0 0 h x x 0 5 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom (b) v850/sb1 ( pd703032a, 703032ay, 70f3032a, 70f3032ay) v850/sb2 ( pd703037a, 703037ay, 70f3037a, 70f3037ay) 512 kb are available for the addresses xx000000h to xx07ffffh. addresses xx080000h to xx0fffffh are an access-prohibited area figure 3-13. internal rom/flash memory area (512 kb) x x 0 f f f f f h x x 0 8 0 0 0 0 h x x 0 7 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom/ flash memory chapter 3 cpu functions user?s manual u13850ej4v0um 85 interrupt/exception table the v850/sb1 and v850/sb2 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed. the sources of interrupts/exceptions, and the corresponding addresses are shown below. table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00000000h reset 000001d0h inttm6 00000010h nmi 000001e0h inttm7 00000020h intwdt 000001f0h intiic0 note /intcsi0 00000040h trap0n (n = 0 to f) 00000200h intser0 00000050h trap1n (n = 0 to f) 00000210h intsr0/intcsi1 00000060h ilgop 00000220h intst0 00000080h intwdtm 00000230h intcsi2 00000090h intp0 00000240h intiic1 note 000000a0h intp1 00000250h intser1 000000b0h intp2 00000260h intsr1/intcsi3 000000c0h intp3 00000270h intst1 000000d0h intp4 00000280h intcsi4 000000e0h intp5 00000290h intie1 (v850/sb2 only) 000000f0h intp6 000002a0h intie2 (v850/sb2 only) 00000140h intwtni 000002b0h intad 00000150h inttm00 000002c0h intdma0 00000160h inttm01 000002d0h intdma1 00000170h inttm10 000002e0h intdma2 00000180h inttm11 000002f0h intdma3 00000190h inttm2 00000300h intdma4 000001a0h inttm3 00000310h intdma5 000001b0h inttm4 00000320h intwtn 000001c0h inttm5 00000330h intkr note available only for the pd70303xay and 70f303way. chapter 3 cpu functions user?s manual u13850ej4v0um 86 (2) internal ram area an area of 28 kb maximum is reserved for the internal ram area. (a) v850/sb1 ( pd703031a, 703031ay), v850/sb2 ( pd703034a, 703034ay) 12 kb are available for the addresses xxffc000h to xxffefffh. addresses xxff8000h to xxffbfffh are an access-prohibited area figure 3-14. internal ram area (12 kb) x x f f e f f f h x x f f c 0 0 0 h x x f f b f f f h x x f f 8 0 0 0 h access-prohibited area internal ram (b) v850/sb1 ( pd703033a, 703033ay, 70f3033a, 70f3033ay) v850/sb2 ( pd703035a, 703035ay, 70f3035a, 70f3035ay) 16 kb are available for the addresses xxffb000h to xxffefffh. addresses xxff8000h to xxffafffh are an access-prohibited area figure 3-15. internal ram area (16 kb) x x f f e f f f h x x f f b 0 0 0 h x x f f a f f f h x x f f 8 0 0 0 h access-prohibited area internal ram chapter 3 cpu functions user?s manual u13850ej4v0um 87 (c) v850/sb1 ( pd703030a, 703030ay), v850/sb2 ( pd703036a, 703036ay) 20 kb are available for the addresses xxffa000h to xxffefffh. addresses xxff8000h to xxff9fffh are an access-prohibited area figure 3-16. internal ram area (20 kb) x x f f e f f f h x x f f a 0 0 0 h x x f f 9 f f f h x x f f 8 0 0 0 h access-prohibited area internal ram (b) v850/sb1 ( pd703032a, 703032ay, 70f3032a, 70f3032ay) v850/sb2 ( pd703037a, 703037ay, 70f3037a, 70f3037ay) 24 kb are available for the addresses xxff9000h to xxffefffh. addresses xxff8000h to xxff8fffh are an access-prohibited area figure 3-17. internal ram area (24 kb) x x f f e f f f h x x f f 9 0 0 0 h x x f f 8 f f f h x x f f 8 0 0 0 h access-prohibited area internal ram chapter 3 cpu functions user?s manual u13850ej4v0um 88 (3) internal peripheral i/o area a 4 kb area of addresses fff000h to ffffffh is reserved as an internal peripheral i/o area. the v850/sb1 and v850/sb2 are provided with a 1 kb area of addresses fff000h to fff3ffh as a physical internal peripheral i/o area, and its image can be seen on the rest of the area (fff400h to ffffffh). peripheral i/o registers associated with the operation mode specification and the state monitoring for the internal peripherals are all memory-mapped to the internal peripheral i/o area. program fetches are not allowed in this area. figure 3-18. internal peripheral i/o area xxffffffh xxfffc00h xxfffbffh xxfff800h xxfff7ffh xxfff400h xxfff3ffh xxfff000h image image image physical internal peripheral i/o 3ffh 000h image peripheral i/o cautions 1. the least significant bit of an address is not decoded since all registers reside on an even address. if an odd address (2n + 1) in the peripheral i/o area is referenced (accessed in byte units), the register at the next lowest even address (2n) will be accessed. 2. if a register that can be accessed in byte units is accessed in half-word units, the higher 8 bits become undefined, if the access is a read operation. if a write access is made, only the data in the lower 8 bits is written to the register. 3. if a register with n address that can be accessed only in half-word units is accessed in word units, the operation is replaced with two half-word operations. the first operation (lower 16 bits) accesses to the register with n address and the second operation (higher 16 bits) accesses to the register with n + 2 address. 4. if a register with n address that can be accessed in word units is accessed with a word operation, the operation is replaced with two half-word operations. the first operation (lower 16 bits) accesses to the register with n address and the second operation (higher 16 bits) accesses to the register with n + 2 address. 5. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. chapter 3 cpu functions user?s manual u13850ej4v0um 89 (4) external memory the v850/sb1 and v850/sb2 can use an area of up to 16 mb (xx100000h to xxff7fffh) for external memory accesses (in single-chip mode: external expansion). 64 k, 256 k, 1 m, or 4 mb of physical external memory can be allocated when the external expansion mode is specified. in the area of other than the physical external memory, the image of the physical external memory can be seen. the internal ram area and internal peripheral i/o area are not subject to external memory access. figure 3-19. external memory area (when expanded to 64 k, 256 k, or 1 mb) xxffffffh xx000000h physical external memory xffffh 00000h internal peripheral i/o internal ram image image image internal rom xxff7fffh xx100000h external memory chapter 3 cpu functions user?s manual u13850ej4v0um 90 figure 3-20. external memory area (when expanded to 4 mb) xxffffffh xxff7fffh image internal peripheral i/o internal ram image image image internal rom xxc00000h xxbfffffh xx800000h xx7fffffh xx100000h xx0fffffh xx400000h xx3fffffh xx000000h physical external memory external memory 3fffffh 000000h 3.4.6 external expansion mode the v850/sb1 and v850/sb2 allow external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. to connect an external device, the port pins must be set in the external expansion mode by using the memory expansion mode register (mm). the address bus (a1 to a15) is set to multiplexed output with data bus (d1 to d15), though separate output is also available by setting the memory address output mode register (mam) (see the user?s manual of relevant in-circuit emulator about debugging when using the separate bus). caution because the a1 pin and wait pin are alternate-function pins, the wait function by the wait pin cannot be used when using a separate bus (programmable wait can be used however). similarly, a separate bus cannot be used when the wait function by the wait pin is being used. because the v850/sb1 and v850/sb2 are fixed to single-chip mode in the normal operation mode, the port alternate pins become the port mode, thereby the external memory cannot be used. when the external memory is used (external expansion mode), specify the mm register by the program. chapter 3 cpu functions user?s manual u13850ej4v0um 91 (1) memory expansion mode register (mm) this register sets the mode of each pin of ports 4, 5, 6, and 9. in the external expansion mode, an external device can be connected to the external memory area of up to 4 mb. however, the external device cannot be connected to the internal ram area, internal peripheral i/o area, and internal rom area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed). the mm register can be read/written in 8- or 1-bit units. however, bits 4 to 7 are fixed to 0. figure 3-21. memory expansion mode register (mm) format after reset: 00h r/w address: fffff04ch symbol 7 6 5 4 <3> <2> <1> <0> mm 0 0 0 0 mm3 mm2 mm1 mm0 mm3 p95 and p96 operation modes 0 port mode 1 external expansion mode (hldak: p95, hldrq: p96) note mm2 mm1 mm0 address space port 4 port 5 port 6 port 9 000 ? port mode 0 1 1 64 kb ad0 to ad8 to lben, expansion mode ad7 ad15 uben, 1 0 0 256 kb a16, r/w, dstb, expansion mode a17 astb, 1 0 1 1 mb a18, wrl, expansion mode a19 wrh, rd 11 4 mb a20, expansion mode a21 other than above rfu (reserved) note before switching to the external expansion mode, be sure to set 1 to p95 and p96 of port 9 (p9). remark for the details of the operation of each port pin, refer to 2.3 description of pin functions . chapter 3 cpu functions user?s manual u13850ej4v0um 92 (2) memory address output mode register (mam) sets the mode of ports 3, 10, and 11. separate output can be set for the address bus (a1 to a15) in the external expansion mode. the mam register can be written in 8-bit units. if read is performed, undefined values will be read. however, bits 3 to 7 are fixed to 0. figure 3-22. memory address output mode register (mam) format after reset: 00h w address: fffff068h symbol76543210 mam 0 0 0 0 0 mam2 mam1 mam0 mam2 mam1 mam0 address space port 11 port 10 port 3 000 ? port mode 0 1 0 32 bytes 0 1 1 512 bytes 100 8 kb 1 0 1 16 kb 1 1 0 32 kb 1 1 1 64 kb a1 to a4 a5 to a8 a9 to a12 a13 a14 a15 caution debugging the memory address output mode register (mam) an in-circuit emulator is not available. also, setting the mam register by software cannot switch to the separate bus. for details, refer to the relevant user?s manual of in-circuit emulator. remark for details of the operation of each port, see 2.3 description of pin functions . the separate path outputs are output from p34 to p36, p100 to p107, and p110 to p113. the procedure for performing separate path output is shown below. <1> set the pn bit of port m (pm) used for separate output to 0 (m = 3, 10, 11). <2> set the pmn bit of the port m mode register (pmm) to 0 (output mode) (m = 3, 10, 11). <3> when the port to be used for the separate path is used as an alternate-function pin for other than the separate path, turn off the function used by the alternate-function pin. <4> set the memory address output mode register (mam). <5> set the memory expansion mode register (mm). remark m = 3: n = 34 to 36 m = 10: n = 100 to 107 m = 11: n = 110 to 113 chapter 3 cpu functions user?s manual u13850ej4v0um 93 3.4.7 recommended use of address space the architectures of the v850/sb1 and v850/sb2 require that a register that serves as a pointer be secured for address generation in operand data accessing for data space. the address in this pointer register 32 kb can be accessed directly from instruction. however, general-purpose register used as a pointer register is limited. therefore, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved because instructions for calculating pointer addresses are not required. to enhance the efficiency of using the pointer in connection with the memory maps of the v850/sb1 and v850/sb2, the following points are recommended: (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. therefore, a continuous 16 mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space for the efficient use of resources to be performed through the wrap-around feature of the data space, the continuous 8 mb address spaces 00000000h to 007fffffh and ff800000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850/sb1 or v850/sb2, 16 mb physical address space is seen as 256 images in the 4 gb cpu address space. the highest bit (bit 23) of this 24-bit address is assigned as address sign-extended to 32 bits. (a) application of wrap-around for example, when r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended, 16-bit displacement value. all resources including on-chip hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. figure 3-23. application of wrap-around internal rom area internal peripheral i/o area internal ram area 4 kb 28 kb 0001ffffh 00007fffh (r =) 00000000h fffff000h ffff8000h 32 kb chapter 3 cpu functions user?s manual u13850ej4v0um 94 figure 3-24. recommended memory map (flash memory version) ffffffffh fffff400h fffff3ffh 00000000h 16 mb 8 mb internal rom internal rom external memory internal ram internal peripheral i/o note program space data space internal peripheral i/o internal ram external memory internal peripheral i/o internal ram access-prohibited area external memory external memory internal rom xxffffffh xxfff400h xxfff3ffh xxfff000h xxffefffh xxffb000h xxffafffh xxff8000h xxff7fffh xx100000h xx0fffffh xx040000h xx03ffffh xx800000h xx7fffffh xx000000h fffff000h ffffefffh ffff8000h ffff7fffh ff800000h ff7fffffh 01000000h 00ffffffh 00fff000h 00ffefffh 00ff8000h 00ff7fffh 00800000h 007fffffh 00100000h 000fffffh 00040000h 0003ffffh note this area cannot be used as a program area. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map for v850/sb1 ( pd70f3033a, 70f3033ay), v850/sb2 ( pd70f3035a, 70f3035ay). chapter 3 cpu functions user?s manual u13850ej4v0um 95 3.4.8 peripheral i/o registers the differences in the peripheral i/o registers of the v850/sb1 and v850/sb2 are shown below. table 3-4. differences in peripheral i/o registers of v850/sb1 and v850/sb2 v850/sb1 v850/sb2 peripheral i/o register function register name symbol pd703030a, pd703031a, pd703032a, pd703033a, pd70f3032a, pd70f3033a pd703030ay, pd703031ay, pd703032ay, pd703033ay, pd70f3032a y pd70f3033a y pd703034a, pd703035a, pd703036a, pd703037a, pd70f3035a, pd70f3037a pd703034ay, pd703035ay, pd703036ay, pd703037ay, pd70f3035ay, pd70f3037a y interrupt control register iicic1 none available none available iic control registers 0, 1 iicc0, iicc1 none available none available iic status registers 0, 1 iics0, iics1 none available none available iic clock selection registers 0, 1 iiccl0, iiccl1 none available none available slave address registers 0, 1 sva0, sva1 none available none available iic shift registers 0, 1 iic0, iic1 none available none available iic function expansion registers 0, 1 iicx0, iicx1 none available none available iic clock expansion registers 0, 1 iicce0, iicce1 none available none available interrupt control register iebic1, iebic2 none available iebus control register bcr none available iebus unit address register uar none available iebus slave address register sar none available iebus partner address register par none available iebus control data register cdr none available iebus telegraph length register dlr none available iebus data register dr none available iebus unit status register usr none available iebus interrupt status register isr none available iebus slave status register ssr none available iebus communication success counter scr none available iebus transfer register ccr none available iebus clock selection register ieclk none available chapter 3 cpu functions user?s manual u13850ej4v0um 96 (1/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff000h port 0 p0 ? fffff002h port 1 p1 ? fffff004h port 2 p2 ? fffff006h port 3 p3 ? fffff008h port 4 p4 ? fffff00ah port 5 p5 ? fffff00ch port 6 p6 r/w ? 00h note fffff00eh port 7 p7 ? fffff010h port 8 p8 r ? undefined fffff012h port 9 p9 ? fffff014h port 10 p10 ? fffff016h port 11 p11 ? 00h note fffff020h port 0 mode register pm0 ? ffh fffff022h port 1 mode register pm1 ? 3fh fffff024h port 2 mode register pm2 ? fffff026h port 3 mode register pm3 ? fffff028h port 4 mode register pm4 ? fffff02ah port 5 mode register pm5 ? ffh fffff02ch port 6 mode register pm6 ? 3fh fffff032h port 9 mode register pm9 ? 7fh fffff034h port 10 mode register pm10 ? ffh fffff036h port 11 mode register pm11 ? 1fh fffff040h port alternate function control register pac ? fffff04ch memory expansion mode register mm ? 00h fffff060h data wait control register dwc ffffh fffff062h bus cycle control register bcc aaaah fffff064h system control register syc r/w ? fffff068h memory address output mode register mam w 00h fffff070h power save control register psc ? c0h fffff074h processor clock control register pcc ? 03h fffff078h system status register sys ? fffff080h pull-up resistor option register 0 pu0 ? fffff082h pull-up resistor option register 1 pu1 ? fffff084h pull-up resistor option register 2 pu2 ? fffff086h pull-up resistor option register 3 pu3 ? fffff094h pull-up resistor option register 10 pu10 r/w ? 00h note resetting initializes registers to input mode and 00h cannot actually be read. chapter 3 cpu functions user?s manual u13850ej4v0um 97 (2/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff096h pull-up resistor option register 11 pu11 ? fffff0a2h port 1 function register pf1 ? fffff0a4h port 2 function register pf2 ? fffff0a6h port 3 function register pf3 ? fffff0b4h port 10 function register pf10 ? fffff0c0h rising edge specification register 0 egp0 ? fffff0c2h falling edge specification register 0 egn0 ? 00h fffff100h interrupt control register wdtic ? fffff102h interrupt control register pic0 ? fffff104h interrupt control register pic1 ? fffff106h interrupt control register pic2 ? fffff108h interrupt control register pic3 ? fffff10ah interrupt control register pic4 ? fffff10ch interrupt control register pic5 ? fffff10eh interrupt control register pic6 ? fffff118h interrupt control register wtniic ? fffff11ah interrupt control register tmic00 ? fffff11ch interrupt control register tmic01 ? fffff11eh interrupt control register tmic10 ? fffff120h interrupt control register tmic11 ? fffff122h interrupt control register tmic2 ? fffff124h interrupt control register tmic3 ? fffff126h interrupt control register tmic4 ? fffff128h interrupt control register tmic5 ? fffff12ah interrupt control register tmic6 ? fffff12ch interrupt control register tmic7 ? fffff12eh interrupt control register csic0 r/w ? 47h fffff130h interrupt control register seric0 ? fffff132h interrupt control register csic1 ? fffff134h interrupt control register stic0 ? fffff136h interrupt control register csic2 ? fffff138h interrupt control register note iicic1 ? fffff13ah interrupt control register seric1 ? fffff13ch interrupt control register csic3 ? fffff13eh interrupt control register stic1 ? note available only for the pd70303xay and 70f303way. chapter 3 cpu functions user?s manual u13850ej4v0um 98 (3/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff140h interrupt control register csic4 ? fffff142h interrupt control register iebic1 ? fffff144h interrupt control register iebic2 ? fffff146h interrupt control register adic ? fffff148h interrupt control register dmaic0 ? fffff14ah interrupt control register dmaic1 ? fffff14ch interrupt control register dmaic2 ? fffff14eh interrupt control register dmaic3 ? fffff150h interrupt control register dmaic4 ? fffff152h interrupt control register dmaic5 ? fffff154h interrupt control register wtnic ? fffff156h interrupt control register kric ? 47h fffff166h in-service priority register ispr r ? 00h fffff170h command register prcmd w fffff180h dma peripheral i/o address register 0 dioa0 fffff182h dma internal ram address register 0 dra0 fffff184h dma byte count register 0 dbc0 undefined fffff186h dma channel control register 0 dchc0 ? 00h fffff190h dma peripheral i/o address register 1 dioa1 fffff192h dma internal ram address register 1 dra1 fffff194h dma byte count register 1 dbc1 undefined fffff196h dma channel control register 1 dchc1 ? 00h fffff1a0h dma peripheral i/o address register 2 dioa2 fffff1a2h dma internal ram address register 2 dra2 fffff1a4h dma byte count register 2 dbc2 undefined fffff1a6h dma channel control register 2 dchc2 ? 00h fffff1b0h dma peripheral i/o address register 3 dioa3 fffff1b2h dma internal ram address register 3 dra3 undefined fffff1b4h dma byte count register 3 dbc3 fffff1b6h dma channel control register 3 dchc3 ? 00h fffff1c0h dma peripheral i/o address register 4 dioa4 undefined fffff1c2h dma internal ram address register 4 dra4 fffff1c4h dma byte count register 4 dbc4 fffff1c6h dma channel control register 4 dchc4 ? 00h fffff1d0h dma peripheral i/o address register 5 dioa5 undefined fffff1d2h dma internal ram address register 5 dra5 r/w chapter 3 cpu functions user?s manual u13850ej4v0um 99 (4/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff1d4h dma byte count register 5 dbc5 undefined fffff1d6h dma channel control register 5 dchc5 r/w ? 00h fffff200h 16-bit timer register 0 tm0 r fffff202h 16-bit capture/compare register 00 cr00 note fffff204h 16-bit capture/compare register 01 cr01 note 0000h fffff206h prescaler mode register 00 prm00 fffff208h 16-bit timer mode control register 0 tmc0 ? fffff20ah capture/compare control register 0 crc0 ? fffff20ch timer output control register 0 toc0 ? fffff20eh prescaler mode register 01 prm01 r/w 00h fffff210h 16-bit timer register 1 tm1 r fffff212h 16-bit capture/compare register 10 cr10 note fffff214h 16-bit capture/compare register 11 cr11 note 0000h fffff216h prescaler mode register 10 prm10 fffff218h 16-bit timer mode control register 1 tmc1 ? fffff21ah capture/compare control register 1 crc1 ? fffff21ch timer output control register 1 toc1 ? fffff21eh prescaler mode register 11 prm11 r/w 00h fffff240h 8-bit counter 2 tm2 r fffff242h 8-bit compare register 2 cr20 fffff244h timer clock selection register 20 tcl20 00h fffff246h 8-bit timer mode control register 2 tmc2 r/w ? 04h fffff24ah 16-bit counter 23 (during cascade connection only) tm23 r fffff24ch 16-bit compare register 23 (during cascade connection only) cr23 0000h fffff24eh timer clock selection register 21 tcl21 r/w fffff250h 8-bit counter 3 tm3 r fffff252h 8-bit compare register 3 cr30 r/w fffff254h timer clock selection register 30 tcl30 00h fffff256h 8-bit timer mode control register 3 tmc3 ? 04h fffff25eh timer clock selection register 31 tcl31 fffff260h 8-bit counter 4 tm4 r fffff262h 8-bit compare register 4 cr40 r/w fffff264h timer clock selection register 40 tcl40 00h fffff266h 8-bit timer mode control register 4 tmc4 ? 04h note in compare mode: r/w in capture mode: r chapter 3 cpu functions user?s manual u13850ej4v0um 100 (5/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff26ah 16-bit counter 45 (during cascade connection only) tm45 r 0000h fffff26ch 16-bit compare register 45 (during cascade connection only) cr45 fffff26eh timer clock selection register 41 tcl41 r/w fffff270h 8-bit counter 5 tm5 r fffff272h 8-bit compare register 5 cr50 fffff274h timer clock selection register 50 tcl50 00h fffff276h 8-bit timer mode control register 5 tmc5 ? 04h fffff27eh timer clock selection register 51 tcl51 r/w fffff280h 8-bit counter 6 tm6 r fffff282h 8-bit compare register 6 cr60 fffff284h timer clock selection register 60 tcl60 00h fffff286h 8-bit timer mode control register 6 tmc6 r/w ? 04h fffff28ah 16-bit counter 67 (during cascade connection only) tm67 r fffff28ch 16-bit compare register 67 (during cascade connection only) cr67 0000h fffff28eh timer clock selection register 61 tcl61 r/w fffff290h 8-bit counter 7 tm7 r fffff292h 8-bit compare register 7 cr70 fffff294h timer clock selection register 70 tcl70 00h fffff296h 8-bit timer mode control register 7 tmc7 ? 04h fffff29eh timer clock selection register 71 tcl71 fffff2a0h serial i/o shift register 0 sio0 fffff2a2h serial operation mode register 0 csim0 ? fffff2a4h serial clock selection register 0 csis0 r/w 00h fffff2b0h serial i/o shift register 1 sio1 fffff2b2h serial operation mode register 1 csim1 ? fffff2b4h serial clock selection register 1 csis1 fffff2c0h serial i/o shift register 2 sio2 fffff2c2h serial operation mode register 2 csim2 ? fffff2c4h serial clock selection register 2 csis2 fffff2d0h serial i/o shift register 3 sio3 fffff2d2h serial operation mode register 3 csim3 ? fffff2d4h serial clock selection register 3 csis3 ? fffff2e0h variable-length serial i/o shift register 4 sio4 0000h chapter 3 cpu functions user?s manual u13850ej4v0um 101 (6/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff2e2h variable-length serial control register 4 csim4 ? fffff2e4h variable-length serial setting register 4 csib4 ? fffff2e6h baud rate generator source clock selection register 4 brgcn4 00h fffff2e8h baud rate generator output clock selection register 4 brgck4 7fh fffff300h asynchronous serial interface mode register 0 asim0 r/w ? fffff302h asynchronous serial interface status register 0 asis0 r ? fffff304h baud rate generator control register 0 brgc0 r/w 00h fffff306h transmission shift register 0 txs0 w fffff308h reception buffer register 0 rxb0 r ffh fffff30eh baud rate generator mode control register 00 brgmc00 fffff310h asynchronous serial interface mode register 1 asim1 r/w ? fffff312h asynchronous serial interface status register 1 asis1 r ? fffff314h baud rate generator control register 1 brgc1 r/w 00h fffff316h transmission shift register 1 txs1 w fffff318h reception buffer register 1 rxb1 r ffh fffff31eh baud rate generator mode control register 10 brgmc10 fffff320h baud rate generator mode control register 01 brgmc01 fffff322h baud rate generator mode control register 11 brgmc11 fffff340h iic control register 0 note iicc0 r/w ? fffff342h iic state register 0 note iics0 r ? fffff344h iic clock selection register 0 note iiccl0 ? fffff346h slave address register 0 note sva0 fffff348h iic shift register 0 note iic0 r/w 00h fffff34ah iic function expansion register 0 note iicx0 ? fffff34ch iic clock expansion register 0 note iicce0 fffff350h iic control register 1 note iicc1 ? fffff352h iic state register 1 note iics1 r ? fffff354h iic clock selection register 1 note iiccl1 r/w ? fffff356h slave address register 1 note sva1 fffff358h iic shift register 1 note iic1 fffff35ah iic function expansion register 1 note iicx1 ? fffff35ch iic clock expansion register 1 note iicce1 fffff360h watch timer mode register wtnm ? fffff364h watch timer clock selection register wtncs note available only for the pd70303xay and 70f303way. chapter 3 cpu functions user?s manual u13850ej4v0um 102 (7/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff36ch correction control register corcn ? fffff36eh correction request register corrq ? 00h fffff370h correction address register 0 corad0 fffff374h correction address register 1 corad1 fffff378h correction address register 2 corad2 fffff37ch correction address register 3 corad3 00000000h fffff380h oscillation stable time selection register osts 04h fffff382h watchdog timer clock selection register wdcs 00h fffff384h watchdog timer mode register wdtm ? fffff38eh dma start factor expansion register dmas ? fffff3a0h real-time output buffer register l rtbl fffff3a2h real-time output buffer register h rtbh fffff3a4h real-time output port mode register rtpm ? fffff3a6h real-time output port control register rtpc ? fffff3c0h a/d converter mode register 1 adm1 ? fffff3c2h analog input channel specification register ads r/w ? fffff3c4h a/d conversion result register adcr 0000h fffff3c6h a/d conversion result register h (higher 8 bits) adcrh r fffff3c8h a/d converter mode register 2 adm2 ? fffff3d0h key return mode register krm ? fffff3d4h noise elimination control register ncc fffff3e0h iebus control register v850/sb2 bcr ? 00h fffff3e2h iebus unit address register v850/sb2 uar fffff3e4h iebus slave address register v850/sb2 sar r/w fffff3e6h iebus partner address register v850/sb2 par r 0000h fffff3e8h iebus control data register v850/sb2 cdr fffff3eah iebus telegraph length register v850/sb2 dlr 01h fffff3ech iebus data register v850/sb2 dr r/w fffff3eeh iebus unit status register v850/sb2 usr r ? fffff3f0h iebus interrupt status register v850/sb2 isr r/w ? 00h fffff3f2h iebus slave status register v850/sb2 ssr r ? 41h fffff3f4h iebus communication success counter v850/sb2 scr 01h fffff3f6h iebus transfer counter v850/sb2 ccr 20h fffff3f8h iebus clock selection register v850/sb2 ieclk r/w 00h chapter 3 cpu functions user?s manual u13850ej4v0um 103 3.4.9 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the system status register (sys). the v850/sb1 and v850/sb2 have two specific registers, the power save control register (psc) and processor clock control register (pcc). for details of the psc register, refer to 6.3.1 (2) power save control register (psc), and for details of the pcc register, refer to 6.3.1 (1) processor clock control register (pcc). the following sequence shows the data setting of the specific registers. <1> disable dma operation. <2> set the psw np bit to 1 (interrupt disabled). <3> write any 8-bit data in the command register (prcmd). <4> write the set data in the specific registers (by the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> return the psw np bit to 0 (interrupt disable canceled). <6> insert the nop instructions (2 or 5 instructions). <7> if necessary, enable dma operation. no special sequence is required when reading the specific registers. cautions 1. if an interrupt request or a dma request is accepted between the time prcmd is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (prerr bit of sys register is 1) may occur. therefore, set the np bit of psw to 1 (<2>) to disable the acceptance of int/nmi or to disable dma transfer. the above also applies when a bit manipulation instruction is used to set a specific register. moreover, to ensure that the execution routine following release of the stop/idle mode is performed correctly, insert the nop instruction as a dummy instruction (<6>). if the value of the id bit of psw does not change as the result of execution of the instruction to return the np bit to 0 (<5>), insert two nop instructions, and if the value of the id bit of psw changes, insert five nop instructions. chapter 3 cpu functions user?s manual u13850ej4v0um 104 a description example is given below. [description example]: in case of psc register ldsr rx,5 ; np bit = 1 st.b r0,prcmd [r0] ; write to prcmd st.b rd,psc [r0] ; psc register setting ldsr ry,5 ; np bit = 0 nop ; dummy instruction (2 or 5 instructions) . . . nop (next instruction) ; execution routine following cancellation of stop/idle mode . . . rx: value to be written to psw ry: value to be written back to psw rd: value to be set to psc when saving the value of psw, the value of psw prior to setting the np bit must be transferred to the ry register. cautions 2. the instructions (<5> interrupt disable cancel, <6> nop instruction) following the store instruction for the psc register for setting the software stop mode and idle mode are executed before a power save mode is entered. 3. always stop the dma prior to accessing special registers. chapter 3 cpu functions user?s manual u13850ej4v0um 105 (1) command register (prcmd) the command register (prcmd) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. this register can be written in 8-bit units. it becomes undefined values in a read cycle. occurrence of illegal store operations can be checked by the prerr bit of the sys register. figure 3-25. command register (prcmd) after reset: undefined w address: fffff170h symbol76543210 prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 regn registration code 0/1 any 8-bit data (2) system status register (sys) this register is allocated with status flags showing the operating state of the entire system. this register can be read/written in 8- or 1-bit units. figure 3-26. system status register (sys) after reset: 00h r/w address: fffff078h symbol765<4>3210 sys 0 0 0 prerr 0 0 0 0 prerr detection of protection error 0 protection error does not occur 1 protection error occurs operation conditions of prerr flag are shown as follows. (a) set conditions (prerr = 1) (1) when a write operation to the specific register took place in a state where the store instruction operation for the recent peripheral i/o was not a write operation to the prcmd register. (2) when the first store instruction operation following a write operation to the prcmd register is to any peripheral i/o register apart from specific registers. (b) reset conditions: (prerr = 0) (1) when 0 is written to the prerr flag of the sys register. (2) at system reset. user?s manual u13850ej4v0um 106 chapter 4 bus control function the v850/sb1 and v850/sb2 are provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 4.1 features ? address bus (capable of separate output) ? 16-bit data bus ? able to be connected to external devices via the pins those have alternate-functions as ports ? wait function ? programmable wait function, capable of inserting up to 3 wait states per 2 blocks ? external wait control through wait input pin ? idle state insertion function ? bus mastership arbitration function ? bus hold function 4.2 bus control pins and control register 4.2.1 bus control pins the following pins are used for interfacing to external devices: table 4-1. bus control pins external bus interface function corresponding port (pins) address/data bus (ad0 to ad7) port 4 (p40 to p47) address/data bus (ad8 to ad15) port 5 (p50 to p57) address bus (a1 to a4) port 11 (p110 to p113) address bus (a5 to a12) port 10 (p100 to p107) address bus (a13 to a15) port 3 (p34 to p36) address bus (a16 to a21) port 6 (p60 to p65) read/write control (lben, uben, r/w, dstb, wrl, wrh, rd) port 9 (p90 to p93) address strobe (astb) port 9 (p94) bus hold control (hldrq, hldak) port 9 (p95, p96) external wait control (wait) port 11 (p110) the bus interface function of each pin is enabled by specifying the memory expansion mode register (mm) or the memory address output mode register (mam). for the details of specifying an operation mode of the external bus interface, refer to 3.4.6 (1) memory expansion mode register (mm) and for (2) memory address output mode register (mam). caution for debugging using the separate bus, refer to the user?s manual of corresponding in-circuit emulator. chapter 4 bus control function user?s manual u13850ej4v0um 107 4.2.2 control register (1) system control register (syc) this register switches control signals for bus interface. the system control register can be read/written in 8-bit or 1-bit units. figure 4-1. system control register (syc) after reset: 00h r/w address: fffff064h symbol 76 54 321 <0> syc0000000bic bic bus interface control 0 dstb, r/w, lben, uben signal outputs 1 rd, wrl, wrh, uben signal outputs 4.3 bus access 4.3.1 number of access clocks the number of basic clocks necessary for accessing each resource is as follows: table 4-2. number of access clocks peripheral i/o (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) peripheral i/o (16 bits) external memory (16 bits) instruction fetch 1 3 disabled 3 + n operand data access 3 1 3 3 + n remarks 1. unit: clock/access 2. n: number of wait insertions chapter 4 bus control function user?s manual u13850ej4v0um 108 4.3.2 bus width cpu carries out peripheral i/o access and external memory access in 8-bit, 16-bit, or 32-bit. the following shows the operation for each access. (1) byte access (8 bits) byte access is divided into two types, the access to even address and the access to odd address. figure 4-2. byte access (8 bits) 0 7 0 7 8 15 byte data external data bus (a) access to even address 0 7 0 7 8 15 byte data external data bus (b) access to odd address (2) halfword access (16 bits) in halfword access to external memory, data is dealt with as it is because the data bus is fixed to 16 bits. figure 4-3. halfword access (16 bits) 00 15 15 halfword data external data bus (3) word access (32 bits) in word access to external memory, lower halfword is accessed first and then the higher halfword is accessed. figure 4-4. word access (32 bits) 0 15 0 15 16 31 word data external data bus first 0 15 0 15 16 31 word data external data bus second chapter 4 bus control function user?s manual u13850ej4v0um 109 4.4 memory block function the 16 mb memory space is divided into memory blocks of 1 mb units. the programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. figure 4-5. memory block block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 internal peripheral i/o area internal ram area external memory area ffffffh f00000h efffffh e00000h dfffffh d00000h cfffffh c00000h bfffffh b00000h afffffh a00000h 9fffffh 900000h 8fffffh 800000h 7fffffh 700000h 6fffffh 600000h 5fffffh 500000h 4fffffh 400000h 3fffffh 300000h 2fffffh 200000h 1fffffh 100000h 0fffffh 000000h internal rom area chapter 4 bus control function user?s manual u13850ej4v0um 110 4.5 wait function 4.5.1 programmable wait function to facilitate interfacing with low-speed memories and i/o devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. the number of wait states can be programmed by using data wait control register (dwc). immediately after the system has been reset, three data wait insertion states are automatically programmed for all memory blocks. (1) data wait control register (dwc) this register can be read/written in 16-bit units. figure 4-6. data wait control register (dwc) after reset: ffffh r/w address: fffff060h symbol1514131211109876543210 dwc number of wait states to be inserted 00 0 01 1 10 2 11 3 n blocks into which wait states are inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area. it is not subject to programmable wait control, regardless of the setting of dwc, and is always accessed without wait states. the internal ram area of block 15 is not subject to programmable wait control and is always accessed without wait states. the on-chip peripheral i/o area of this block is not subject to programmable wait control, either. the only wait control is dependent upon the execution of each peripheral function. dw61 dw00 dw01 dw10 dw11 dw20 dw21 dw30 dw31 dw40 dw41 dw50 dw51 dw60 dw70 dw71 dwn0 dwn1 chapter 4 bus control function user?s manual u13850ej4v0um 111 4.5.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (wait) to synchronize with the external device. the external wait signal is data wait only, and does not affect the access times of the internal rom, internal ram, and on-chip peripheral i/o areas, similar to programmable wait. input of the external wait signal can be done asynchronously to clkout and is sampled at the falling edge of the clock in the t2 and tw states of a bus cycle. if the setup/hold time at sampling timing is not satisfied, the wait state may or may not be inserted in the next state. caution because the a1 pin and wait pin are alternate-function pins, the wait function by the wait pin cannot be used when using a separate bus (programmable wait can be used, however). similarly, a separate bus cannot be used when the wait function by the wait pin is being used. 4.5.3 relationship between programmable wait and external wait a wait cycle is inserted as a result of an or operation between the wait cycle specified by the set value of programmable wait and the wait cycle controlled by the wait pin. in other words, the number of wait cycles is determined by those that have much more cycles than the other. figure 4-7. wait control wait control programmable wait wait by wait pin for example, if the number of programmable wait and the timing of the wait pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-8. example of inserting wait states clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark { : valid sampling timing chapter 4 bus control function user?s manual u13850ej4v0um 112 4.6 idle state insertion function to facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (ti) can be inserted into the current bus cycle after the t3 state. the bus cycle following continuous bus cycles starts after one idle state. specifying insertion of the idle state is programmable by using the bus cycle control register (bcc). immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. figure 4-9. bus cycle control register (bcc) after reset: aaaah r/w address: fffff062h symbol1514131211109876543210 bcc idle state insert specification 0 not inserted 1 inserted n blocks into which idle state is inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area; therefore, no idle state can be specified. the internal ram area and on-chip peripheral i/o area of block 15 are not subject to insertion of the idle state. be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. if these bits are set to 1, the operation is not guaranteed. 0 bc01 0 bc11 0 bc21 0 bc31 0 bc41 0 bc51 0 bc61 0 bc71 bcn1 chapter 4 bus control function user?s manual u13850ej4v0um 113 4.7 bus hold function 4.7.1 outline of function when the mm3 bit of the memory expansion mode register (mm) is set (1), the hldrq and hldak pin functions of p95 and p96 become valid. when the hldrq pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state note , and the bus is released (bus hold status). when the hldrq pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. during bus hold period, the internal operation continues until the next external memory access. the bus hold status can be recognized by that the hldak pin becomes active (low). this feature can be used to design a system where two or more bus masters exist, such as when multi-processor configuration is used and when a dma controller is connected. bus hold request is not acknowledged between the first and the second word access, and not acknowledged between read access and write access in read modify write access of bit manipulation instruction either. note a1 to a15 are retained when a separate bus is used. chapter 4 bus control function user?s manual u13850ej4v0um 114 4.7.2 bus hold procedure the procedure of the bus hold function is illustrated below. figure 4-10. bus hold procedure hldrq hldak < 1 >< 2 >< 3 >< 4 >< 5 >< 7 >< 8 >< 9 > < 6 > <1>hldrq = 0 accepted <2>all bus cycle start request pending <3>end of current bus cycle <4>bus idle status <5>hldak = 0 <6>hldrq = 1 accepted <7>hldak = 1 <8>clears bus cycle start request pending <9>start of bus cycle nomal status bus hold status normal status 4.7.3 operation in power save mode in the stop or idle mode, the system clock is stopped. consequently, the bus hold status is not set even if the hldrq pin becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold status is set. when the hldrq pin becomes inactive, the hldak pin becomes inactive. as a result, the bus hold status is cleared, and the halt mode is set again. chapter 4 bus control function user?s manual u13850ej4v0um 115 4.8 bus timing the v850/sb1 and v850/sb2 can execute the read/write control for an external device by the following two modes. ? mode using dstb, r/w, lben, uben, and astb signals ? mode using rd, wrl, wrh, and astb signals set these modes by using the bic bit of the system control register (syc) (see figure 4-1 ). figure 4-11. memory read (1/4) (a) 0 wait t1 t2 t3 clkout (output) a16 to a21 (output) ad0 to ad15 (input/output) address data address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) h a1 to a15 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 116 figure 4-11. memory read (2/4) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (input/output) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) t3 data h a1 to a15 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 117 figure 4-11. memory read (3/4) (c) 0 wait, idle state t1 t2 t3 clkout (output) a1 to a15 (output) ad0 to ad15 (input/output) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) h ti data a16 to a21 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 118 figure 4-11. memory read (4/4) (d) 1 wait, idle state t1 t2 tw clkout (output) a1 to a15 (output) ad0 to ad15 (input/output) address address astb (output) r/w (output) dstb, rd (output) uben, lben (output) wait (input) wrh, wrl (output) t3 data ti h a16 to a21 (output) address remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 119 figure 4-12. memory write (1/2) (a) 0 wait t1 t2 t3 clkout (output) a16 to a21 (output) ad0 to ad15 (input/output) address data note address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd (output) wrh, wrl (output) h a1 to a15 (output) address note ad0 to ad7 output invalid data when odd address byte data is accessed. ad8 to ad15 output invalid data when even address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 120 figure 4-12. memory write (2/2) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (input/output) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd (output) wrh, wrl (output) t3 data note address h a1 to a15 (output) address note ad0 to ad7 output invalid data when odd address byte data is accessed. ad8 to ad15 output invalid data when even address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 121 figure 4-13. bus hold timing clkout (output) r/w (output) dstb, rd, wrh, wrl (output) uben, lben (output) wait (input) hldrq (input) t2 t3 th th th th ti t1 hldak (output) a16 to a21 (output) a1 to a15 (output) ad0 to ad15 (input/output) address address address data address astb (output) undefined address note 1 note 2 notes 1. if hldrq signal is inactive (high-level) at this sampling timing, bus hold state is not entered. 2. if transferred to bus hold status after a write cycle, high-level may be output momentarily from the r/w pin immediately before hldak signal changes from high-level to low-level. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken line indicates the high-impedance state. chapter 4 bus control function user?s manual u13850ej4v0um 122 4.9 bus priority there are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). the bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order. the instruction fetch cycle may be inserted in between the read access and write access in read-modify-write access. no instruction fetch cycle or bus hold is inserted between the lower half-word access and higher half-word access of word access operations. table 4-3. bus priority external bus cycle priority bus hold 1 operand data access 2 instruction fetch (branch) 3 instruction fetch (continuous) 4 chapter 4 bus control function user?s manual u13850ej4v0um 123 4.10 memory boundary operation condition 4.10.1 program space (1) do not execute branch to the on-chip peripheral i/o area or continuous fetch from the internal ram area to peripheral i/o area. if branch or instruction fetch is executed nevertheless, the nop instruction code is continuously fetched and not fetched from external memory. (2) a prefetch operation straddling over the on-chip peripheral i/o area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal ram area. 4.10.2 data space only the address aligned at the half-word boundary (when the least significant bit of the address is ?0?)/word boundary (when the lowest 2 bits of the address are ?0?) boundary is accessed by data half-word (16 bits)/word (32 bits) long. therefore, access that straddles over the memory or memory block boundary does not take place. for the details, refer to v850 family user?s manual architecture . user?s manual u13850ej4v0um 124 chapter 5 interrupt/exception processing function 5.1 outline the v850/sb1 and v850/sb2 are provided with a dedicated interrupt controller (intc) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 37 to 40 sources. an interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependent on program execution. generally, an exception takes precedence over an interrupt. the v850/sb1 and v850/sb2 can process interrupt requests from the internal peripheral hardware and external sources. moreover, exception processing can be started (exception trap) by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code). 5.1.1 features ? interrupts ? non-maskable interrupts: 2 sources ? maskable interrupts: (the number of maskable interrupt sources differs depending on the product) (v850/sb1) pd703030a, 703031a, 703032a, 703033a, 70f3032a, 70f3033a: 37 sources pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, 70f3033ay: 38 sources (v850/sb2) pd703034a, 703035a, 703036a, 703037a, 70f3035a, 70f3037a: 39 sources pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, 70f3037ay: 40 sources ? 8 levels of programmable priorities ? mask specification for the interrupt request according to priority ? mask can be specified to each maskable interrupt request. ? noise elimination, edge detection, and valid edge of external interrupt request signal can be specified. ? exceptions ? software exceptions: 32 sources ? exception trap: 1 source (illegal op code exception) interrupt/exception sources are listed in table 5-1. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 125 table 5-1. interrupt source list (1/2) type classifi- cation default priority name trigger inter- rupt source exception code handler address restored pc interrupt control register reset interrupt ? reset reset input ? 0000h 00000000h unde- fined ? interrupt ? nmi nmi pin input ? 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdtovf non-maskable wdt 0020h 00000020h nextpc ? exception ? trap0n note 1 trap instruction ? 004nh note 1 00000040h nextpc ? software exception exception ? trap1n note 1 trap instruction ? 005nh note 1 00000050h nextpc ? exception trap exception ? ilgop illegal op code ? 0060h 00000060h nextpc ? 0 intwdtm wdtovf maskable wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin pin 00f0h 000000f0h nextpc pic6 8 intwtni watch timer prescaler wt 0140h 00000140h nextpc wtniic 9 inttm00 inttm00 tm0 0150h 00000150h nextpc tmic00 10 inttm01 inttm01 tm0 0160h 00000160h nextpc tmic01 11 inttm10 inttm10 tm1 0170h 00000170h nextpc tmic10 12 inttm11 inttm11 tm1 0180h 00000180h nextpc tmic11 13 inttm2 tm2 compare match/ovf tm2 0190h 00000190h nextpc tmic2 14 inttm3 tm3 compare match/ovf tm3 01a0h 000001a0h nextpc tmic3 15 inttm4 tm4 compare match/ovf tm4 01b0h 000001b0h nextpc tmic4 16 inttm5 tm5 compare match/ovf tm5 01c0h 000001c0h nextpc tmic5 17 inttm6 tm6 compare match/ovf tm6 01d0h 000001d0h nextpc tmic6 18 inttm7 tm7 compare match/ovf tm7 01e0h 000001e0h nextpc tmic7 19 intiic0 note 2 / intcsi0 i 2 c interrupt/ csi0 transmit end i 2 c/ csi0 01f0h 000001f0h nextpc csic0 20 intser0 uart0 serial error uart0 0200h 00000200h nextpc seric0 21 intsr0/ intcsi1 uart0 receive end/ csi1 transmit end uart0/ csi1 0210h 00000210h nextpc csic1 maskable interrupt 22 intst0 uart0 transmit end uart0 0220h 00000220h nextpc stic0 notes 1. n: 0 to fh 2. available only for the pd70303xay and 70f303way. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 126 table 5-1. interrupt source list (2/2) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register 23 intcsi2 csi2 transmit end csi2 0230h 00000230h nextpc csic2 24 intiic1 note 1 i 2 c1 interrupt i 2 c1 0240h 00000240h nextpc iicic1 25 intser1 uart1 serial error uart1 0250h 00000250h nextpc seric1 26 intsr1/ intcsi3 uart1 receive end/ csi3 transmit end uart1/ csi3 0260h 00000260h nextpc csic3 27 intst1 uart1 transmit end uart1 0270h 00000270h nextpc stic1 28 intcsi4 csi4 transmit end csi4 0280h 00000280h nextpc csic4 29 intie1 note 2 iebus transfer end iebus 0290h 00000290h nextpc iebic1 30 intie2 note 2 iebus communication end iebus 02a0h 000002a0h nextpc iebic2 31 intad a/d conversion end a/d 02b0h 000002b0h nextpc adic 32 intdma0 dma0 transfer end dma0 02c0h 000002c0h nextpc dmaic0 33 intdma1 dma1 transfer end dma1 02d0h 000002d0h nextpc dmaic1 34 intdma2 dma2 transfer end dma2 02e0h 000002e0h nextpc dmaic2 35 intdma3 dma3 transfer end dma3 02f0h 000002f0h nextpc dmaic3 36 intdma4 dma4 transfer end dma4 0300h 00000300h nextpc dmaic4 37 intdma5 dma5 transfer end dma5 0310h 00000310h nextpc dmaic5 38 intwtn watch timer ovf wt 0320h 00000320h nextpc wtnic maskable interrupt 39 intkr key return interrupt kr 0330h 00000330h nextpc kric notes 1. available only for the pd70303xay and 70f303way. 2. available only for the v850/sb2. remarks 1. default priority: priority when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is granted during the divh (division) instruction execution is the value of the pc of the current instruction (divh). 2. the execution address of the illegal instruction when an illegal op code exception occurs is calculated with (restored pc ? 4). 3. a restored pc of interrupt/exception other than reset is the value of the pc (when an event occurred) + 1. 4. non-maskable interrupts (intwdt) and maskable interrupts (intwdtm) are set by the wdtm4 bit of the watchdog timer mode register (wdtm). chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 127 5.2 non-maskable interrupt a non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (di state). an nmi is not subject to priority control and takes precedence over all other interrupts. the following two non-maskable interrupt requests are available in the v850/sb2. ? nmi pin input (nmi) ? non-maskable watchdog timer interrupt request (intwdt) when the valid edge specified by rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0) is detected in the nmi pin, an interrupt occurs. intwdt functions as the non-maskable interrupt (intwdt) only in the state that the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 1. while the service routine of the non-maskable interrupt is being executed (psw.np = 1), the acknowledgement of another non-maskable interrupt request is kept pending. the pending nmi is acknowledged after the original service routine of the non-maskable interrupt under execution has been terminated (by the reti instruction), or when psw.np is cleared to 0 by the ldsr instruction. note that if two or more nmi requests are input during the execution of the service routine for an nmi, the number of nmis that will be acknowledged after psw.np goes to ??0??, is only one. caution if psw.np is cleared to 0 by the ldsr instruction during non-maskable interrupt servicing, the interrupt afterwards cannot be acknowledged correctly. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 128 5.2.1 operation if the non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher half-word (fecc) of ecr. (4) sets the np and id bits of psw and clears the ep bit. (5) loads the handler address (00000010h, 00000020h) of the non-maskable interrupt routine to the pc, and transfers control. figure 5-1. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 00000010h, 00000020h intc accepted cpu processing psw. np 1 0 chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 129 figure 5-2. acknowledging non-maskable interrupt request (a) if a new nmi request is generated while an nmi service routine is executing: main routine nmi request nmi request (psw. np = 1) nmi request pending because psw. np = 1 pending nmi request processed (b) if a new nmi request is generated twice while an nmi service routine is executing: main routine nmi request nmi request held pending because nmi service program is being processed held pending because nmi service program is being processed nmi request only one nmi request is acknowledged even though two or more nmi requests are generated chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 130 5.2.2 restore execution is restored from non-maskable interrupt servicing by the reti instruction. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from fepc and fepsw, respectively, because the ep bit of psw is 0 and the np bit of psw is 1. (2) transfers control back to the address of the restored pc and psw. how the reti instruction is processed is shown below. figure 5-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during the non- maskable interrupt service, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 131 5.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt (nmi) servicing is under execution. this flag is set when the nmi interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. figure 5-4. np flag (np) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z np nmi servicing state 0 no nmi interrupt servicing 1 nmi interrupt currently servicing 5.2.4 noise eliminator of nmi pin nmi pin noise is eliminated by the noise eliminator with analog delay. therefore, a signal input to the nmi pin is not detected as an edge, unless it maintains its input level for a certain period. the edge is detected after a certain period has elapsed. nmi pin is used for canceling the software stop mode. in the software stop mode, noise elimination does not use system clock for noise elimination because the internal system clock is stopped. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 132 5.2.5 edge detection function of nmi pin the nmi pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, detects neither rising nor falling edge. rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0) specify the valid edge of the non-maskable interrupt (nmi). these two registers can be read/written in 1-bit or 8-bit units. after reset, the valid edge of the nmi pin is set to the ?detects neither rising nor falling edge? state. therefore, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p00 as an output port, set the nmi valid edge to ?detects neither rising nor falling edge?. figure 5-5. rising edge specification register 0 (egp0) format after reset: 00h r/w address: fffff0c0h symbol <7> <6> <5> <4> <3> <2> <1> <0> egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n rising edge valid control 0 no interrupt request signal occurs at the rising edge 1 interrupt request signal occurs at the rising edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control figure 5-6. falling edge specification register 0 (egn0) format after reset: 00h r/w address: fffff0c2h symbol <7> <6> <5> <4> <3> <2> <1> <0> egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n falling edge valid control 0 no interrupt request signal occurs at the falling edge 1 interrupt request signal occurs at the falling edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 133 5.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850/sb1 and v850/sb2 have 37 to 40 maskable interrupt sources (see 5.1.1 features ). if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupts is dis- abled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt servicing routine, the interrupt enabled (ei) status is set which enables interrupts having a higher priority to immediately interrupt the current service routine in progress. note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to use multiple interrupts, it is necessary to save eipc and eipsw to memory or a register before executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (intwdtm). 5.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower half-word of ecr (eicc). (4) sets the id bit of psw and clears the ep bit. (5) loads the corresponding handler address to the pc, and transfers control. the int input masked by intc and the int input that occurs during the other interrupt servicing (when psw.np = 1 or psw.id = 1) are internally kept pending. when the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, the pending int is input to start the new maskable interrupt servicing. how the maskable interrupts are serviced is shown below. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 134 figure 5-7. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id pc intc accepted cpu processing mask? yes no psw. id = 0 priority higher than that of interrupt currently serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? interrupt enable mode? restored pc psw exception code 0 1 handler address chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 135 5.3.2 restore to restore execution from the maskable interrupt servicing, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from eipc and eipsw because the ep bit of psw is 0 and the np bit of psw is 0. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-8. reti instruction processing reti instruction restores original processing pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the maskable interrupt service, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 136 5.3.3 priorities of maskable interrupts the v850/sb1 and v850/sb2 provide a multiple interrupt service in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by interrupt priority level specification bit (xxprn). when two or more interrupts having the same priority level specified by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request types (default priority level) be- forehand. for more information, refer to table 5-1. the programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to ??1??. therefore, when multiple interrupts are to be used, clear the id flag to ??0?? beforehand (for example, by placing the ei instruction into the interrupt service program) to set the interrupt enable mode. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 137 figure 5-9. example of interrupt nesting service (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 138 figure 5-9. example of interrupt nesting process (2/2) main routine ei interrupt request i (level 2) servicing of i processing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 139 figure 5-10. example of servicing interrupt requests generated simultaneously main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b ? servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. nmi request notes 1. higher default priority 2. lower default priority 5.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. the interrupt control register can be read/written in 8- or 1-bit units. caution if the following three conditions conflict, interrupt servicing is executed twice. however, when dma is not used, interrupt servicing is not executed twice. ? execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) ? an interrupt via hardware of the same interrupt control register (xxicn) as the interrupt request flag (xxifn) is generated ? dma is started during execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) two workarounds using software are shown below. ? insert a di instruction before the software-based bit manipulation instruction and an ei instruction after it, so that jumping to an interrupt immediately after the bit manipulation instruction execution does not occur. ? when an interrupt request is acknowledged, since the hardware becomes interrupt disabled (di state), clear the interrupt request flag (xxifn) before executing the ei instruction in each interrupt servicing routine. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 140 figure 5-11. interrupt control register (xxicn) format after reset: 47h r/w address: fffff100h to fffff156h symbol<7><6>543210 xxicn xxifn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 xxifn interrupt request flag note 0 interrupt request not generated 1 interrupt request generated xxmkn interrupt mask flag 0 enables interrupt servicing 1 disables interrupt servicing (pending) xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) note automatically reset by hardware when interrupt request is acknowledged. remark xx: identification name of each peripheral unit (wdt, p, wtni, tm, cs, ser, st, ad, dma, wtn, iic, ieb, kr) n: peripheral unit number (see table 5-2 ) chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 141 address and bit of each interrupt control register is as follows: table 5-2. interrupt control register (xxicn) bit address register <7><6>543210 fffff100h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff102h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff104h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff106h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff108h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff10ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff10ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff10eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff118h wtniic wtniif wtnimk 0 0 0 wtnipr2 wtnipr1 wtnipr0 fffff11ah tmic00 tmif00 tmmk00 0 0 0 tmpr002 tmpr001 tmpr000 fffff11ch tmic01 tmif01 tmmk01 0 0 0 tmpr012 tmpr011 tmpr010 fffff11eh tmic10 tmif10 tmmk10 0 0 0 tmpr102 tmpr101 tmpr100 fffff120h tmic11 tmif11 tmmk11 0 0 0 tmpr112 tmpr111 tmpr110 fffff122h tmic2 tmif2 tmmk2 0 0 0 tmpr22 tmpr21 tmpr20 fffff124h tmic3 tmif3 tmmk3 0 0 0 tmpr32 tmpr31 tmpr30 fffff126h tmic4 tmif4 tmmk4 0 0 0 tmpr42 tmpr41 tmpr40 fffff128h tmic5 tmif5 tmmk5 0 0 0 tmpr52 tmpr51 tmpr50 fffff12ah tmic6 tmif6 tmmk6 0 0 0 tmpr62 tmpr61 tmpr60 fffff12ch tmic7 tmif7 tmmk7 0 0 0 tmpr72 tmpr71 tmpr70 fffff12eh csic0 csif0 csmk0 0 0 0 cspr02 cspr01 cspr00 fffff130h seric0 serif0 sermk0 0 0 0 serpr02 serpr01 serpr00 fffff132h csic1 csif1 csmk1 0 0 0 cspr12 cspr11 cspr10 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h csic2 csif2 csmk2 0 0 0 cspr22 cspr21 cspr20 fffff138h iicic1 note 1 iicif1 iicmk1 0 0 0 iicpr12 iicpr11 iicpr10 fffff13ah seric1 serif1 sermk1 0 0 0 serpr12 serpr11 serpr10 fffff13ch csic3 csif3 csmk3 0 0 0 cspr32 cspr31 cspr30 fffff13eh stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff140h csic4 csif4 csmk4 0 0 0 cspr42 cspr41 cspr40 fffff142h iebic1 note 2 iebif1 iebmk1 0 0 0 iebpr12 iebpr11 iebpr10 fffff144h iebic2 note 2 iebif2 iebmk2 0 0 0 iebpr22 iebpr21 iebpr20 fffff146h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff148h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff14ah dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff14ch dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff14eh dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff150h dmaic4 dmaif4 dmamk4 0 0 0 dmapr42 dmapr41 dmapr40 fffff152h dmaic5 dmaif5 dmamk5 0 0 0 dmapr52 dmapr51 dmapr50 fffff154h wtnic wtnif wtnmk 0 0 0 wtnpr2 wtnpr1 wtnpr0 fffff156h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 notes 1. available only for the pd70303xay and 70f303way. 2. available only for the v850/sb2. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 142 5.3.5 in-service priority register (ispr) this register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset when execution is returned from non-maskable processing or exception processing. this register can be only read in 8- or 1-bit units. figure 5-12. in-service priority register (ispr) format after reset: 00h r address: fffff166h symbol <7> <6> <5> <4> <3> <2> <1> <0> ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 isprn indicates priority of interrupt currently acknowledged 0 interrupt request with priority n not acknowledged 1 interrupt request with priority n acknowledged remark n: 0 to 7 (priority level) 5.3.6 maskable interrupt status flag the interrupt disable status flag (id) of the psw controls the enabling and disabling of maskable interrupt requests. as a status flag, it also displays the current maskable interrupt acknowledgment condition. figure 5-13. interrupt disable flag (id) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z id specifies maskable interrupt servicing note 0 maskable interrupt acknowledgement enabled 1 maskable interrupt acknowledgement disabled (pending) note interrupt disable flag (id) function it is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgement disabled period (id = 1) can be acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 143 5.3.7 watchdog timer mode register (wdtm) read/write is available in 8- or 1-bit units (for details, refer to chapter 9 watchdog timer ). figure 5-14. watchdog timer mode register (wdtm) format after reset: 00h r/w address: fffff384h symbol<7>6543210 wdtm run 0 0 wdtm4 0 0 0 0 run watchdog timer operation control 0 count operation stop 1 count start after clearing wdtm4 timer mode selection/interrupt control by wdt 0 interval timer mode 1 wdt mode caution if 1 is set to run or wdtm4 bit, no operation other than the reset input is available for clearing this register. 5.3.8 noise elimination (1) noise elimination of intp0 to intp3 pins intp0 to intp3 pins incorporate the noise eliminator that functions via an analog delay. therefore, a signal input to each pin is not detected as an edge, unless it maintains its input level for a certain period. an edge is detected after a certain period has elapsed. (2) noise elimination of intp4 and intp5 pins intp4 and intp5 pins incorporate the digital noise eliminator. if an input level of the intp pin is detected with the sampling clock (f xx ) and the same level is not detected three successive times, the input pulse is eliminated as a noise. note the followings: ? in the case that the input pulse width is between 2 and 3 clocks, whether the input pulse is detected as a valid edge or eliminated as a noise is indefinite. ? to securely detect the level as a pulse, the same level input of 3 clocks or more is required. ? when a noise is generated in synchronization with a sampling clock, this may not be recognized as a noise. in this case, eliminate the noise by adding a filter to the input pin. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 144 (3) noise elimination of intp6 pin the intp6 pin incorporates a digital noise eliminator. the sampling clock for digital sampling can be selected from among f xx , f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . sampling is performed 3 times. the noise elimination control register (ncc) selects the clock to be used. remote control signals can be received effectively with this function. f xt can be used for the noise elimination clock. in this case, the intp6 external interrupt function is enabled in the idle/stop mode. this register can be read/written in 8- or 1-bit units. caution after the sampling clock has been changed, it takes sampling clock 3 clocks to initialize the noise eliminator. for that reason, if an intp6 valid edge was input within these 3 clocks, an interrupt request may occur. therefore, be careful of the following things when using the interrupt and dma functions. ? ? ? ? when using the interrupt function, after the sampling clock 3 clocks have elapsed, allow the interrupt after the interrupt request flag (bit 7 of pic6) has been cleared. ? ? ? ? when using the dma function, after the sampling clock 3 clocks have elapsed, allow dma by setting bit 0 of dchcn. figure 5-15. noise elimination control register (ncc) after reset: 00h r/w address: fffff3d4h 7 6543210 ncc 00 000 ncs2 ncs1 ncs0 reliably eliminated noise width note 1 ncs2 ncs1 ncs0 noise elimination clock f xx = 20 mhz note 2 f xx = 12.58 mhz 000 f xx 100 ns 158 ns 001 f xx /64 6.4 s 10.1 s 010 f xx /128 12.8 s 20.3 s 011 f xx /256 25.6 s 40.6 s 100 f xx /512 51.2 s 81.3 s 101 f xx /1024 102.4 s 162.7 s 110 setting prohibited 111 f xt 61 s notes 1. since sampling is preformed three times, the reliably eliminated noise width is 2 noise elimination clock. 2. only for the v850/sb1. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 145 5.3.9 edge detection function valid edges of the intp0 to intp6 pins can be selected for each pin from the following four types. ? rising edge ? falling edge ? both rising and falling edges ? detects neither rising nor falling edge the validity of the rising edge is controlled by rising edge specification register 0 (egp0), and the validity of the falling edge is controlled by falling edge specification register 0 (egn0). refer to figures 5-5 and 5-6 for details of egp0 and egn0. after reset, the valid edge of the nmi pin is set to the ?detects neither rising nor falling edge? state. therefore, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p01 to p07 as output ports, set valid edges of intp0 to intp6 to ?detects neither rising nor falling edge? or mask the interrupt request. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 146 5.4 software exception a software exception is generated when the cpu executes the trap instruction, and can be always accepted. ? trap instruction format: trap vector (where vector is 0 to 1fh) for details of the instruction function, refer to the v850 family user?s manual architecture. 5.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of psw. (5) loads the handler address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. how a software exception is processed is shown below. figure 5-16. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing handler address: 00000040h (vector = 0nh) 00000050h (vector = 1nh) chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 147 5.4.2 restore to restore or return execution from the software exception service routine, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-17. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception process, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 148 5.4.3 ep flag the ep flag in psw is a status flag used to indicate that exception processing is in progress. it is set when on exception occurs, and the interrupt is disabled. figure 5-18. ep flag (ep) after reset: 00000020h symbol 31 8 7 6 5 4 3 2 1 0 psw 0 np ep id sat cy ov s z ep exception processing 0 exception processing is not in progress 1 exception processing is in progress 5.5 exception trap the exception trap is an interrupt that is requested when illegal execution of an instruction takes place. in the v850/sb1 or v850/sb2, an illegal op code exception (ilgop: ilegal opcode trap) is considered as an exception trap. ? illegal op code exception: occurs if the sub op code field of an instruction to be executed next is not a valid op code. 5.5.1 illegal op code definition an illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111b and bits 23 to 26 being 0011b to 1111b. figure 5-19. illegal op code 15 16 17 23 22 x 21 x 20 xxxxx x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 x: don?t care 5.5.2 operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code (0060h) to the lower 16 bits (eicc) of ecr. (4) sets the ep and id bits of psw. (5) loads the handler address (00000060h) for the exception trap routine to the pc, and transfers control. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 149 how the exception trap is processed is shown below. figure 5-20. exception trap processing exception trap (ilgop) occurs eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 00000060h cpu processing exception processing chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 150 5.5.3 restore to restore or return execution from the exception trap, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 5-21. reti instruction processing reti instruction jump to pc pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the exception trap process, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 151 5.6 priority control 5.6.1 priorities of interrupts and exceptions table 5-3. priorities of interrupts and exceptions reset nmi int trap ilgop reset * * * * nmi int trap ilgop reset: reset nmi: non-maskable interrupt int: maskable interrupt trap: software exception ilgop: illegal op code exception *: item on the left ignores the item above. : item on the left is ignored by the item above. : item above is higher than the item on the left in priority. : item on the left is higher than the item above in priority. 5.6.2 multiple interrupt servicing multiple interrupt servicing is a function that allows the nesting of interrupts. if a higher priority interrupt is generated and acknowledged, it will be allowed to stop a current interrupt service routine in progress. execution of the original routine will resume once the higher priority interrupt routine is completed. if an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be kept pending. multiple interrupt servicing control is performed when it is in the state of interrupt acknowledgement (id = 0). even in an interrupt servicing routine, this control must be set in the state of acknowledgement (id = 0). if a maskable interrupt acknowledgement or exception is generated during a service program of maskable interrupt or exception, eipc and eipsw must be saved. the following example shows the procedure of interrupt nesting. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 152 (1) to acknowledge maskable interrupts in service program service program of maskable interrupt or exception (2) to generate exception in service program service program of maskable interrupt or exception ... ... ? saves eipc to memory or register ? saves eipsw to memory or register ? ei instruction (enables interrupt acknowledgement) ... ... ? di instruction (disables interrupt acknowledgement) ? restores saved value to eipsw ? restores saved value to eipc ? reti instruction ... ... ? saves eipc to memory or register ? saves eipsw to memory or register ? ei instruction (enables interrupt acknowledgement) ... ? trap instruction ? illegal op code ... ? restores saved value to eipsw ? restores saved value to eipc ? reti instruction acknowledges interrupt such as intp input. acknowledges exception such as trap instruction. acknowledges exception such as illegal op code. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 153 priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. to set a priority level, write values to the xxprn0 to xxprn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt request. at reset, the interrupt request is masked by the xxmkn bit, and the priority level is set to 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt servicing has been completed and the reti instruction has been executed. caution in the non-maskable interrupt servicing routine (time until the reti instruction is executed), maskable interrupts are not acknowledged but are suspended. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 154 5.7 interrupt latency time the following table describes the interrupt latency time (from interrupt request generation to start of interrupt servicing). figure 5-22. pipeline operation at interrupt request acknowledgement system clock if id ifx idx ifx ex mem int1 int2 int3 if id ex mem wb int4 wb interrupt request instruction 1 instruction 2 instruction 3 interrupt acknowledge operation instruction (start instruction of interrupt servicing routine) 7 to 14 system clocks 4 system clocks int1 to int4: interrupt acknowledge processing if x : invalid instruction fetch id x : invalid instruction decode interrupt latency time (system clock) internal interrupt external interrupt condition minimum 11 13 maximum 18 20 time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: ? in idle/stop mode ? external bus is accessed ? two or more interrupt request non-sample instructions are executed in succession ? access to interrupt control register 5.8 periods where interrupt is not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between interrupt non-sample instruction and next instruction. interrupt request non-sample instruction ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (vs. psw) (1) acknowledging interrupt servicing after execution of ei instruction the v850/sb1 and v850/sb2 require at least seven clocks to identify an interrupt request from when the interrupt request was generated until it is acknowledged. because subsequent instructions are executed during this period, the interrupt is disabled if the di instruction (which disables interrupts) is executed. as a result, all the interrupt requests are held pending until the ei instruction (which enables interrupts) is executed again. chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 155 even when the ei instruction is executed, a period of time is required to identify an interrupt. consequently, at least seven clocks are required until an interrupt request is acknowledged after the ei instruction has been executed. if the di instruction is executed before the duration of the seven clocks elapses after the ei instruction has been executed, therefore, the interrupt is held pending. to accurately acknowledge an interrupt, insert an instruction that requires seven clocks or more to be executed in between the ei and di instructions. however, the following instructions are not included. ? idle/stop mode setting instructions ? ei and di instructions ? reti instruction ? ldsr instruction (vs. psw register) ? instruction that accesses interrupt control register (xxicn) example when the ei instruction processing is not valid [program example] di ; mk flag = 0 (enables interrupt requests) . . . . . ; interrupt request occurs (if flag = 1) . ei jr lp1 ; ei instruction 7 clocks have not elapsed before di instruction is executed (3 clocks). . . . . . . lp1: di ; interrupt request is not acknowledged. . . . [example of prevention program] di ; mk flag = 0 (enables interrupt requests) . . . . . ; interrupt request occurs (if flag = 1) . ei nop ; 1 system clock nop ; 1 system clock nop ; 1 system clock nop ; 1 system clock jr lp1: ; 3 system clocks (branches to lp1 routine) . . . . . . di ; interrupt servicing is executed at the 8th system clock after execution of ei instruction. . . . chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 156 5.9 key interrupt function key interrupt can be generated by inputting a falling edge to key input pins (kr0 to kr7) by means of setting the key return mode register (krm). the key return mode register (krm) includes 5 bits. the krm0 bit controls the kr0 to kr3 signals in 4-bit units and the krm4 to krm7 bits control corresponding signals from kr4 to kr7 (arbitrary setting from 4 to 8 bits is possible). this register can be read/written in 8- or 1-bit units. figure 5-23. key return mode register (krm) after reset: 00h r/w address: fffff3d0h <7> <6> <5> <4> 3 2 1 <0> krm krm7 krm6 krm5 krm4 0 0 0 krm0 krmn key return mode control 0 does not detect key return signal 1 detects key return signal caution if the key return mode register (krm) is changed, an interrupt request flag may be set. to avoid this flag to be set, change the krm register after disabling interrupts, and then, permit interrupts after clearing the interrupt request flag. table 5-4. description of key return detection pin flag pin description krm0 controls kr0 to kr3 signals in 4-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units chapter 5 interrupt/exception processing function user?s manual u13850ej4v0um 157 figure 5-24. key return block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 000 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 user?s manual u13850ej4v0um 158 chapter 6 clock generation function 6.1 outline the clock generator is a circuit that generates the clock pulses that are supplied to the cpu and peripheral hardware. there are two types of system clock oscillators. (1) main system clock oscillator the oscillator of v850/sb1 has an oscillation frequency of 2 to 20 mhz. the oscillator of v850/sb2 has an oscillation frequency of 6 to 12.58 mhz. oscillation can be stopped by executing a stop instruction or by setting the processor clock control register (pcc). oscillation is also stopped during a reset. in idle mode, supplying the peripheral clock to the clock timer only is possible. therefore, in idle mode, it is possible to operate the clock timer without using the subsystem clock oscillator. cautions 1. when the main oscillator is stopped by inputting a reset or executing a stop instruction, the oscillation stabilization time is secured after the stop mode is canceled. this oscillation stabilization time is set via the oscillation stabilization time selection register (osts). the watchdog timer is used as the timer that counts the oscillation stabilization time. 2. if the main system clock halt is released by clearing mck to 0 after the main system clock is stopped by setting the mck bit in the pcc register to 1, the oscillation stabilization time is not secured. (2) subsystem clock oscillator this circuit has an oscillation frequency of 32.768 khz. its oscillation is not stopped when the stop instruction is executed, neither is it stopped when a reset is input. when the subsystem clock oscillator is not used, the frc bit in the processor clock control register (pcc) can be set to disable use of the internal feedback resistor. this enables the current consumption to be kept low in the stop mode. chapter 6 clock generation function user?s manual u13850ej4v0um 159 6.2 composition figure 6-1. clock generator f xt f xt f xx /8 f xx stop, mck frc prescaler prescaler x2 x1 xt2 xt1 idle main system clock oscillator subsystem clock oscillator idle control idle control selector clock supplied to watch timer, etc. clock supplied to peripheral hardware halt halt control cpu clock (f cpu ) clkout f xx /4 f xx /2 chapter 6 clock generation function user?s manual u13850ej4v0um 160 6.3 clock output function this function outputs the cpu clock via the clkout pin. when clock output is enabled, the cpu clock is output via the clkout pin. when it is disabled, a low-level signal is output via the clkout pin. output is stopped in the idle or stop mode (fixed to low level). this function is controlled via the dclk1 and dclk0 bits in the psc register. the high-impedance status is set during the reset period. after reset is canceled, low level is output. caution while clkout is output, changing the cpu clock (ck2 to ck0 bits of pcc register) is disabled. 6.3.1 control registers (1) processor clock control register (pcc) this is a specific register. it can be written to only when a specified combination of sequences is used (see 3.4.9 specific registers ). this register can be read/written in 8- or 1-bit units. figure 6-2. format of processor clock control register (pcc) after reset: 03h r/w address: fffff074h <7> <6> 5 4 3 <2> 1 0 pcc frc mck 0 0 0 ck2 ck1 ck0 frc selection of internal feedback resistor for sub clock 0use 1 do not use mck operation of main clock (main system clock) 0 operate 1stop ck2 note ck1 ck0 selection of cpu clock 000f xx 001f xx /2 010f xx /4 011f xx /8 1xxf xt (sub clock) note if manipulating ck2, do so in 1-bit units. in the case of 8-bit manipulation, do not change the values of ck1 and ck0. chapter 6 clock generation function user?s manual u13850ej4v0um 161 cautions 1. while clkout is output, do not change the cpu clock (the value of the ck2 to ck0 in the pcc register). 2. even if the mck bit is set to 1 during main clock operation, the main clock is not stopped. the cpu clock stops after the sub clock is selected. remark x: don?t care (a) example of main clock operation sub clock operation setup <1> ck2 1: bit manipulation instructions are recommended. do not change ck1 and ck0. <2> sub clock operation: the maximum number of the following instructions is required before sub clock operation after the ck2 bit is set. (cpu clock frequency before setting / sub clock frequency) 2 therefore, insert the wait described above using a program. <3> mck 1: only when the main clock is stopped. (b) example of sub clock operation main clock operation setup <1> mck 0: main clock oscillation start <2> insert wait using a program and wait until the main clock oscillation stabilizing time elapses. <3> ck2, ck1, ch0 cpu clock <4> main clock operation: if ck1 and ch0 are not changed from value of the cpu clock selected before the sub clock operation, a maximum of two instructions is required. if ck1 and ck0 are changed, a maximum of ten instructions is required chapter 6 clock generation function user?s manual u13850ej4v0um 162 (2) power save control register (psc) this is a specific register. it can be written to only when a specified combination of sequences is used. for details, see 3.4.9 specific registers . this register can be read/written in 8- or 1-bit units. figure 6-3. format of power save control register (psc) after reset: c0h r/w address: fffff070h 76543<2><1>0 psc dclk1 dclk0 0 0 0 idle stp 0 dclk1 dclk0 specification of clkout pin?s operation 00 output enabled 01 setting prohibited 10 setting prohibited 11 output disabled (when reset) idle idle mode setting 0 normal mode 1 idle mode note 1 stp stop mode setting 0 normal mode 1 stop mode note 2 notes 1. when idle mode is canceled, this bit is automatically reset to 0. 2. when stop mode is canceled, this bit is automatically reset to 0. caution the bits in dclk0 and dclk1 should be manipulated in 8-bit units. chapter 6 clock generation function user?s manual u13850ej4v0um 163 (3) oscillation stabilization time selection register (osts) this register can be read/written in 8-bit units. figure 6-4. format of oscillation stabilization time selection register (osts) after reset: 04h r/w address: fffff380h 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 selection of oscillation stabilization time f xx osts2 osts1 osts0 clock 20 mhz note 12.58 mhz 0002 14 /f xx 819.2 s1.3 ms 0012 16 /f xx 3.3 ms 5.2 ms 0102 17 /f xx 6.6 ms 10.4 ms 0112 18 /f xx 13.1 ms 20.8 ms 1002 19 /f xx 26.2 ms 41.6 ms other than above setting prohibited note only for v850/sb1. chapter 6 clock generation function user?s manual u13850ej4v0um 164 6.4 power save functions 6.4.1 outline this product provides the following power saving functions. these modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. (1) halt mode when in this mode, the clock?s oscillator continues to operate but the cpu?s operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. this enables the system?s total power consumption to be reduced. a special-purpose instruction (the halt instruction) is used to switch to halt mode. (2) idle mode this mode stops the entire system by stopping the cpu?s operating clock as well as the operating clock for on- chip peripheral functions while the clock oscillator is still operating. however, the sub clock continues to operate and supplies a clock to the on-chip peripheral functions. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when the power saving control register (psc)?s idle bit is set to 1, the system switches to idle mode. (3) software stop mode this mode stops the entire system by stopping a clock oscillator that is not for a sub clock system. the sub clock continues to be supplied to keep on-chip peripheral functions operating. if a sub clock is not used, ultra low power consumption mode (leak current only) is set. stop mode setting is prohibited if the cpu is operating via the sub clock. if the psc register?s stp bit is set to 1, the system enters stop mode. (4) sub clock operation under this mode, the cpu clock is set to operate using the sub clock and the pcc register?s mck bit is set to 1 to set low power consumption mode in which the entire system operates using only the sub clock. when halt mode has been set, the cpu?s operating clock is stopped so that power consumption can be reduced. when idle mode has been set, the cpu?s operating clock and some peripheral functions (dmac and bcu) are stopped, so that power consumption can be reduced even lower than when in halt mode. chapter 6 clock generation function user?s manual u13850ej4v0um 165 6.4.2 halt mode (1) settings and operating states when in this mode, the clock?s oscillator continues to operate but the cpu?s operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. when halt mode is set while the cpu is idle, it enables the system?s total power consumption to be reduced. when in halt mode, execution of programs is stopped but the contents of all registers and on-chip ram are retained as they were just before halt mode was set. in addition, all on-chip peripheral functions that do not depend on instruction processing by the cpu continue operating. halt mode can be set by executing the halt instruction. it can be set when the cpu is operating via either the main clock or sub clock. the operating statuses in the halt mode are listed in table 6-1. (2) cancellation of halt mode halt mode can be canceled by an nmi request, an unmasked maskable interrupt request, or a reset input. (a) cancellation by interrupt request halt mode is canceled regardless of the priority level when an nmi request or an unmasked maskable interrupt request occurs. however, the following occurs if halt mode was set as part of an interrupt servicing routine. (i) only halt mode is canceled when an interrupt request that has a lower priority level than the interrupt currently being serviced occurs, and the lower-priority interrupt request is not acknowledged. the interrupt request itself is retained. (ii) when an interrupt request (including nmi request) that has a higher priority level than the interrupt currently being serviced occurs, halt mode is canceled and the interrupt request is acknowledged. (b) cancellation by reset pin input this is the same as for normal reset operations. chapter 6 clock generation function user?s manual u13850ej4v0um 166 table 6-1. operating statuses in halt mode (1/2) halt mode setting when cpu operates with main clock when cpu operates with sub clock item when subclock does not exist when subclock exists when main clock?s oscillation continues when main clock?s oscillation is stopped cpu stopped rom correction stopped clock generator oscillation for main clock and sub clock clock supply to cpu is stopped 16-bit timer (tm0) operating operates when intwti is selected as count clock (f xt is selected for watch timer) 16-bit timer (tm1) operating stopped 8-bit timer (tm2) operating stopped 8-bit timer (tm3) operating stopped 8-bit timer (tm4) operating operates when f xt is selected for count clock 8-bit timer (tm5) operating operates when f xt is selected for count clock 8-bit timer (tm6) operating stopped 8-bit timer (tm7) operating stopped watch timer operates when main clock is selected for count clock operating operates when f xt is selected for count clock watchdog timer operating (interval timer only) csi0 to csi3 operating operates when an external clock is selected as the serial clock i 2 c0 note , i 2 c1 note operating stopped serial interface uart0, uart1 operating operates when an external clock is selected as the serial clock csi4 operating operates when an external clock is selected as the serial clock iebus (v850/sb2 only) operating stopped a/d converter operating stopped dma0 to dma5 operating real-time output operating note available only for the pd70303xay, 70f303way. chapter 6 clock generation function user?s manual u13850ej4v0um 167 table 6-1. operating statuses in halt mode (2/2) halt mode setting when cpu operates with main clock when cpu operates with sub clock item when subclock does not exist when subclock exists when main clock?s oscillation continues when main clock?s oscillation is stopped port function held external bus interface only bus hold function operates nmi operating intp0 to intp3 operating intp4 and intp5 operating st opped external interrupt request intp6 operating operation when sampling clock f xt is selected key return function operating ad0 to ad15 high impedance note a16 to a21 lben, uben held note (high impedance when hldak = 0) r/w high level output note (high impedance when hldak = 0) dstb, wrl, wrh, rd astb in external expansion mode hldak operating note even when the halt instruction has been executed, the instruction fetch operation continues until the on-chip instruction prefetch queue becomes full. once it is full, operation stops according to the status shown in table 6-1. chapter 6 clock generation function user?s manual u13850ej4v0um 168 6.4.3 idle mode (1) settings and operating states this mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. supply to the sub clock continues. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when in idle mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before idle mode was set. in addition, on-chip peripheral function are stopped (except for peripheral functions that are operating with the sub clock). external bus hold requests (hldrq) are not acknowledged. when the power saving control register (psc)?s idle bit is set to 1, the system switches to idle mode. the operating statuses in idle mode are listed in table 6-2. (2) cancellation of idle mode idle mode can be canceled by a non-maskable interrupt, an unmasked interrupt request, or a reset input. table 6-2. operating statuses in idle mode (1/2) idle mode settings w hen sub clock exists when sub clock does not exist cpu stopped rom correction stopped clock generator both a main clock and sub clock oscillator clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected as count clock (f xt is selected for watch timer) stopped 16-bit timer (tm1) stopped 8-bit timer (tm2) stopped 8-bit timer (tm3) stopped 8-bit timer (tm4) operates when f xt is selected for count clock stopped 8-bit timer (tm5) operates when f xt is selected for count clock stopped 8-bit timer (tm6) stopped 8-bit timer (tm7) stopped watch timer operating watchdog timer stopped csi0 to csi3 operates when an external clock is selected as the serial clock i 2 c0 note , i 2 c1 note stopped uart0, uart1 operates when an external clock is selected as the serial clock serial interface csi4 operates when an external clock is selected as the serial clock iebus (v850/sb2 only) stopped a/d converter stopped dma0 to dma5 stopped real-time output operates when inttm4 or inttm5 is selected (when tm4 or tm5 is operating) stopped port function held note available only for the pd70303xay, 70f303way. item chapter 6 clock generation function user?s manual u13850ej4v0um 169 table 6-2. operating statuses in idle mode (2/2) idle mode settings when sub clock exists when sub clock does not exist external bus interface stopped nmi operating intp0 to intp3 operating intp4 and intp5 st opped external interrupt request intp6 operates when f xt is selected for sampling clock stopped key return operating ad0 to ad15 a16 to a21 lben, uben r/w dstb, wrl, wrh, rd astb in external expansion mode hldak high impedance item chapter 6 clock generation function user?s manual u13850ej4v0um 170 6.4.4 software stop mode (1) settings and operating states this mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock. the sub clock oscillator continues operating and the on-chip sub clock supply is continued. when the frc bit in the processor clock control register (pcc) is set to 1, the sub clock oscillator?s on-chip feedback resistor is cut. this sets ultra low power consumption mode in which the only current is the device?s leak current. in this mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before software stop mode was set. this mode can be set only when the main clock is being used as the cpu clock. this mode is set when the stp bit in the power saving control register (psc) has been set to 1. do not set this mode when the sub clock has been selected as the cpu clock. the operating statuses for software stop mode are listed in table 6-3. (2) cancellation of software stop mode software stop mode can be canceled by an non-maskable interrupt, an unmasked interrupt request, or a reset input. when the stop mode is canceled, an oscillation stabilization time is secured. table 6-3. operating statuses in software stop mode (1/2) stop mode settings item when sub clock exists when sub clock does not exist cpu stopped rom correction stopped clock generator oscillation for main clock is stopped and oscillation for sub clock continues clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected for count clock (f xt is selected as count clock for watch timer) stopped 16-bit timer (tm1) stopped 8-bit timer (tm2) stopped 8-bit timer (tm3) stopped 8-bit timer (tm4) operates when f xt is selected for count clock stopped 8-bit timer (tm5) operates when f xt is selected for count clock stopped (operation disabled) 8-bit timer (tm6) stopped 8-bit timer (tm7) stopped watch timer operates when f xt is selected for count clock stopped watchdog timer stopped csi0 to csi3 operates when an external clock is selected as the serial clock i 2 c0 note , i 2 c1 note stopped uart0, uart1 operates when an external clock is selected as the serial clock serial interface csi4 operates when an external clock is selected as the serial clock iebus (v850/sb2 only) stopped a/d converter stopped note available only for the pd70303xay and 70f303way. chapter 6 clock generation function user?s manual u13850ej4v0um 171 table 6-3. operating statuses in software stop mode (2/2) mode settings item when sub clock exists when sub clock does not exist dma0 to dma5 stopped real-time output operates when inttm4 or inttm5 has been selected (when tm4 or tm5 is operating) stopped port function held external bus interface stopped nmi operating intp0 to intp3 operating intp4 and intp5 st opped external interrupt request intp6 operates when f xt is selected for the noise eliminator stopped key return operating ad0 to ad15 a16 to a21 lben, uben r/w dstb, wrl, wrh, rd astb in external expansion mode hldak high impedance chapter 6 clock generation function user?s manual u13850ej4v0um 172 6.5 oscillation stabilization time the following shows methods for specifying the length of oscillation stabilization time required to stabilize the oscillator following cancellation of stop mode. (1) cancellation by non-maskable interrupt or by unmasked interrupt request stop mode is canceled by a non-maskable interrupt or an unmasked interrupt request. when an interrupt is input, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse for stabilization of the oscillator?s clock output. oscillation stabilization time = ? ? wdt count time after the specified amount of time has elapsed, system clock output starts and processing branches to the interrupt handler address. figure 6-5. oscillation stabilization time stop mode is set oscillator is stopped interrupt input oscillation wave main clock stop status count time value of time base counter (2) use of reset pin to allocate time (reset pin input) for allocating time with reset pin, refer to chapter 15 reset function . chapter 6 clock generation function user?s manual u13850ej4v0um 173 6.6 notes on power save function if the v850/sb1 or v850/sb2 is used under the following conditions, the address indicated by the program counter (pc) differs from the address that actually reads an instruction after the power save mode has been released. of the instructions 4 to 16 bytes after the instruction that writes data to the psc register, the cpu may ignore 4 or 8 bytes of the instruction and execute wrong instructions. [conditions] (i) if the power save mode (idle or stop mode) is set while an instruction is being executed on the external rom (ii) if the power save mode is released by an interrupt request (iii) if the subsequent instruction is executed while an interrupt request is being held pending after the power save mode has been released conditions in which an interrupt request is held pending: ? if the np flag of the psw register is ?1? (during nmi servicing/set by software) ? if the id flag of the psw register is ?1? (during interrupt request servicing/di instruction/set by software) ? if the power save mode is released by an interrupt request with a priority the same as or lower than the interrupt request being serviced even though interrupts are enabled (ei status) therefore, use the v850/sb1 and v850/sb2 under the following conditions: [conditions] (i) do not use a power save mode (idle or stop mode) while an instruction is being executed on the external rom (ii) take the following measures using software if a power save mode is used while an instruction is being executed on the external rom: ? insert six nop instructions 4 bytes after the instruction that writes data to the psc register. ? insert the br $+2 instruction to eliminate the difference in the address of the cpu after the nop instructions. [example of prevention program] ldsr rx, 5 ; sets value of rx to psw. st.b r0, prcmd[r0] ; writes data to prcmd. st.b rd, psc[r0] ; sets psc register. ldsr ry, 5 ; returns value of psw. nop ; six nop instructions or more nop nop nop nop br $+2 ; eliminates difference of pc remark it is assumed that the following values have already been set: rd : psc set value, rx : value written to psw, ry : value written back to psw user?s manual u13850ej4v0um 174 chapter 7 timer/counter function 7.1 16-bit timer (tm0, tm1) 7.1.1 outline ? 16-bit capture/compare registers: 2 (crn0, crn1) ? independent capture/trigger inputs: 2 (tin0, tin1) ? support of output of capture/match interrupt request signals (inttmn0, inttmn1) ? event input (shared with tin0) via digital noise eliminator and support of edge specifications ? timer output operated by match detection: 1/each (ton) when using the p34/to0 and p35/to1 pins as to0 and to1 (timer outputs), set the value of port 3 (p3) to 0 (port mode output) and the port 3 mode register (pm3) to 0. the ored value of the output of a port and a timer is output. remark n = 0, 1 7.1.2 function tm0 and tm1 have the following functions: ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square wave output ? one-shot pulse output figure 7-1 shows the block diagram. chapter 7 timer/counter function user?s manual u13850ej4v0um 175 figure 7-1. block diagram of tm0 and tm1 internal bus internal bus tin1 noise eliminator count clock note tin0 toen tocn1 lvrn lvsn tocn4 ospen osptn ovfn tmcn1 tmcn2 prescaler mode register n0 (prmn0) prmn1 prmn0 tmcn3 crcn0 crcn1 crcn2 capture/compare control register n (crcn) 16-bit capture/compare register n0 (crn0) output controller 16-bit timer register (tmn) 16-bit capture/compare register n1 (crn1) crcn2 match match clear 16-bit timer mode control register n (tmcn) ton inttmn1 inttmn0 3 timer output control register n (tocn) f xx /2 selector selector selector selector prmn2 prescaler mode register n1 (prmn1) noise eliminator noise eliminator note count clock is set by the prmn0, prmn1 registers. remark n = 0, 1 (1) interval timer generates an interrupt at predetermined time intervals. (2) ppg output can output the square wave whose frequency and output-pulse width can be changed arbitrarily. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counter can measure the number of pulses of a signal input from an external source. chapter 7 timer/counter function user?s manual u13850ej4v0um 176 (5) square wave output can output a square wave of any frequency. (6) one-shot pulse output can output a one-shot pulse with any output pulse width. 7.1.3 configuration timers 0 and 1 include the following hardware. table 7-1. configuration of timers 0 and 1 item configuration timer registers 16 bits 2 (tm0, tm1) registers capture/compare registers: 16 bits 2 (crn0, crn1) timer outputs 2 (to0, to1) control registers 16-bit timer mode control registers 0, 1 (tmc0, tmc1) capture/compare control registers 0, 1 (crc0, crc1) 16-bit timer output control registers 0, 1 (toc0, toc1) prescaler mode registers n0, n1 (prmn0, prmn1) (1) 16-bit timer registers 0, 1 (tm0, tm1) tmn is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmcn3 and tmcn2 are cleared <3> if valid edge of tin0 is input in the clear & start mode entered by inputting the valid edge of tin0 <4> if tmn and crn0 match each other in the clear & start mode entered upon a match between tmn and crn0 <5> if osptn is set or if the valid edge of tin0 is input in the one-shot pulse output mode chapter 7 timer/counter function user?s manual u13850ej4v0um 177 (2) capture/compare registers n0 (cr00, cr10) crn0 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by using bit 0 (crcn0) of the crcn register. (a) when using crn0 as compare register the value set to crn0 is always compared with the count value of the tmn register. when the values of the two match, an interrupt request (inttmn0) is generated. when tmn is used as an interval timer, crn0 can also be used as a register that holds the interval time. (b) when using crn0 as capture register the valid edge of the tin0 or tin1 pin can be selected as a capture trigger. the valid edge for tin0 or tin1 is set by using the prmn0 register. when the valid edge for tin0 pin is specified as the capture trigger, refer to table 7-2. when the valid edge for tin1 pin is specified as the capture trigger, refer to table 7-3. table 7-2. valid edge of tin0 pin and capture trigger of crn0 esn01 esn00 valid edge of tin0 pin crn0 capture trigger 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation remark n = 0, 1 table 7-3. valid edge of tin1 pin and capture trigger of crn0 esn11 esn10 valid edge of tin1 pin crn0 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1 crn0 is set by using a 16-bit memory manipulation instruction. the value of this register is undefined after the reset signal is input. caution set crn0 to a value other than 0000h in the clear & start mode entered upon a match between tmn and crn0. in the free-running mode or the tin0 valid edge clear mode, however, an interrupt request (inttmn0) is generated after an overflow (ffffh) when 0000h is set to crn0. chapter 7 timer/counter function user?s manual u13850ej4v0um 178 (3) capture/compare register n1 (cr01, cr11) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 (crcn2) of the crcn register. (a) when using crn1 as compare register the value set to crn1 is always compared with the count value of tmn. when the values of the two match, an interrupt request (inttmn1) is generated. (b) when using crn1 as capture register the valid edge of the tin1 pin can be selected as a capture trigger. the valid edge of tin1 is specified by the prmn0 register. when the capture trigger is specified as the valid edge of tin0, the relationship between the tin0 valid edge and the crn1 capture trigger is as follows. table 7-4. tin0 pin valid edge and crn1 capture trigger esn01 esn00 tin0 pin valid edge crn1 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1 crn1 is set by using a 16-bit memory manipulation instruction. the value of this register is undefined after the reset signal is input. caution set crn1 to a value other than 0000h in the clear & start mode entered upon a match between tmn and crn0. in the free-running mode or the tin1 valid edge clear mode, however, an interrupt request (inttmn1) is generated after an overflow (ffffh) when 0000h is set to crn1. chapter 7 timer/counter function user?s manual u13850ej4v0um 179 7.1.4 timer 0, 1 control registers the registers to control timers 0, 1 are shown below. ? 16-bit timer mode control register n (tmcn) ? capture/compare control register n (crcn) ? 16-bit timer output control register n (tocn) ? prescaler mode registers n0, n1 (prmn0, prmn1) (1) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn specifies the operation mode of the 16-bit timer; and the clear mode, output timing, and overflow detection of 16-bit timer register n. tmcn is set by an 8-/1-bit memory manipulation instruction. reset input clears tmc0 and tmc1 to 00h. caution 16-bit timer register n starts operating when a value other than 0, 0 (operation stop mode) is set to tmcn2 and tmcn3. to stop the operation, set 0, 0 to tmcn2 and tmcn3. chapter 7 timer/counter function user?s manual u13850ej4v0um 180 figure 7-2. 16-bit timer mode control registers 0, 1 (tmc0, tmc1) after reset: 00h r/w address: fffff208h, fffff218h 7654321<0> tmcn 0 0 0 0 tmcn3 tmcn2 tmcn1 ovfn (n = 0, 1) tmcn3 tmcn2 tmcn1 selects operation mode and clear mode selects ton output timing generation of interrupt 0 0 0 operation stops (tmn is cleared to 0) not affected does not generate 001 0 1 0 free-running mode match between tmn and crn0 or match between tmn and crn1 0 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 0 0 clears and starts at valid edge of tin0 match between tmn and crn0 or match between tmn and crn1 1 0 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 1 0 clears and starts on match between tmn and crn0 match between tmn and crn0 or match between tmn and crn1 1 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 ovfn detection of overflow of 16-bit timer register n 0 does not overflow 1overflows generates on match between tmn and crn0 and match between tmn and crn1 chapter 7 timer/counter function user?s manual u13850ej4v0um 181 cautions 1. when the bit other than the ovfn flag is written, be sure to stop the timer operation. 2. the valid edge of the tin0 pin is set by using prescaler mode register n0 (prmn0). 3. when a mode in which the timer is cleared and started on a match between tmn and crn0, the ovfn flag is set to 1 when the count value of tmn changes from ffffh to 0000h with crn0 set to ffffh. remark ton: output pin of timer n tin0: input pin of timer n tmn: 16-bit timer register n crn0: compare register n0 crn1: compare register n1 (2) capture/compare control registers 0, 1 (crc0, crc1) crcn controls the operation of capture/compare register n (crn0 and crn1). crcn is set by an 8-/1-bit memory manipulation instruction. reset input clears crc0 and crc1 to 00h. figure 7-3. capture/compare control registers 0, 1 (crc0, crc1) after reset: 00h r/w address: fffff20ah, fffff21ah 76543210 crcn 0 0 0 0 0 crcn2 crcn1 crcn0 (n = 0, 1) crcn2 selects operation mode of crn1 0 operates as compare register 1 operates as capture register crcn1 selects capture trigger of crn0 0 captured at valid edge of tin1 1 captured in reverse phase of valid edge of tin0 crcn0 selects operation mode of crn0 0 operates as compare register 1 operates as capture register cautions 1. before setting crcn, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on a match between tmn and crn0 is selected by 16-bit timer mode control register n (tmcn), do not specify crn0 as a capture register. 3. when both the rising edge and falling edge are specified for the tin0 valid edge, the capture operation does not work. 4. for the capture trigger, a pulse longer than twice the count clock selected by prescaler mode registers 0n, 1n (prm0n, prm1n) is required in order that the signals from tin0 and t2n1 perform the capture operation correctly. chapter 7 timer/counter function user?s manual u13850ej4v0um 182 (3) 16-bit timer output control registers 0, 1 (toc0, toc1) tocn controls the operation of the timer n output controller by setting or resetting the r-s flip-flop (lv0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. tocn is set by an 8-/1-bit memory manipulation instruction. reset input clears toc0 and toc1 to 00h. figure 7-4. 16-bit timer output control registers 0, 1 (toc0, toc1) after reset: 00h r/w address: fffff20ch, fffff21ch 7 <6> <5> 4 <3> <2> 1 <0> tocn 0 osptn ospen tocn4 lvsn lvrn tocn1 toen (n = 0, 1) osptn controls output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 uses one-shot pulse trigger ospen controls one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output note tocn4 controls timer output f/f on coincidence between crn1 and tmn 0 disables reverse timer output f/f 1 enables reverse timer output f/f lvsn lvrn sets status of timer output f/f of timer 0 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tocn1 controls timer output f/f on coincidence between crn0 and tmn 0 disables reverse timer output f/f 1 enables reverse timer output f/f toen controls output of timer n 0 disables output (output is fixed to 0 level) 1 enables output note the one-shot pulse output operates only in the free-running mode and in the clear & start mode at tin0 valid edge. chapter 7 timer/counter function user?s manual u13850ej4v0um 183 cautions 1. before setting tocn, be sure to stop the timer operation. 2. lvsn and lvrn are 0 when read after data have been set to them. 3. osptn is 0 when read because it is automatically cleared after data has been set. 4. do not set osptn (to 1) when other than one-shot pulse output. (4) prescaler mode registers 00, 01 (prm00, prm01) prm0n selects a count clock of the 16-bit timer (tm0) and the valid edge of ti0n input. prm00 and prm01 are set by an 8-bit memory manipulation instruction. reset input clears prm00 and prm01 to 00h. figure 7-5. prescaler mode register 00 (prm00) after reset: 00h r/w address: fffff206h 76543210 prm00 es011 es010 es001 es000 0 0 prm01 prm00 es011 es010 selects valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es001 es000 selects valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prm02 note 1 prm01 prm00 count clock 20 mhz note 3 12.58 mhz 000f xx /2 100 ns 158 ns 001f xx /16 800 ns 1.3 s 0 1 0 intwtni ?? 0 1 1 ti00 valid edge note 2 ?? 100f xx /4 200 ns 318 ns 101f xx /64 3.2 s5.1 s 110f xx /256 12.8 s 20.3 s 1 1 1 setting prohibited ?? notes 1. bit 0 of the prm01 register 2. the external clock requires a pulse longer than twice that of the internal clock (f xx /2). 3. only for the v850/sb1. chapter 7 timer/counter function user?s manual u13850ej4v0um 184 figure 7-6. prescaler mode register 01 (prm01) after reset: 00h r/w address: fffff20eh 76543210 prm010000000 prm02 note note set together with bits 0 and 1 of the prm00 register. (see figure 7-5 ) cautions 1. when selecting the valid edge of ti0n as the count clock, do not specify the valid edge of ti0n to clear and start the timer and as a capture trigger. 2. before setting data to prm0n, always stop the timer operation. 3. if the 16-bit timer (tm0) operation is enabled by specifying the rising edge or both edges for the valid edge of the ti0n pin while the ti0n pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up ti0n pin. however, the rising edge is not detected when operation is enabled after it has been stopped. chapter 7 timer/counter function user?s manual u13850ej4v0um 185 (5) prescaler mode registers 10, 11 (prm10, prm11) prm1n selects a count clock of the 16-bit timer (tm1) and the valid edge of ti1n input. prm10 and prm11 are set by an 8-bit memory manipulation instruction. reset input clears prm10 and prm11 to 00h. figure 7-7. prescaler mode register 10 (prm10) after reset: 00h r/w address: fffff216h 76543210 prm10 es111 es110 es101 es100 0 0 prm11 prm10 es111 es110 selects valid edge of ti11 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es101 es100 selects valid edge of ti10 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prm12 note 1 prm11 prm10 count clock 20 mhz note 3 12.58 mhz 000f xx /2 100 ns 158 ns 001f xx /4 200 ns 318 ns 010f xx /16 800 ns 1.3 s 0 1 1 ti10 valid edge note 2 ?? 100f xx /32 1.6 s2.5 s 101f xx /128 6.4 s 10.2 s 110f xx /256 12.8 s 20.3 s 1 1 1 setting prohibited ?? notes 1. bit 0 of the prm11 register 2. the external clock requires a pulse longer than twice that of the internal clock (f xx /2). 3. only for the v850/sb1. chapter 7 timer/counter function user?s manual u13850ej4v0um 186 figure 7-8. prescaler mode register 11 (prm11) after reset: 00h r/w address: fffff21eh 76543210 prm110000000 prm12 note note set together with bits 0 and 1 of the prm10 register. (see figure 7-7 ) cautions 1. when selecting the valid edge of ti1n as the count clock, do not specify the valid edge of ti1n to clear and start the timer and as a capture trigger. 2. before setting data to prm1n, always stop the timer operation. 3. if the 16-bit timer (tm1) operation is enabled by specifying the rising edge or both edges for the valid edge of the ti1n pin while the ti1n pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up ti1n pin. however, the rising edge is not detected when operation is enabled after it has been stopped. chapter 7 timer/counter function user?s manual u13850ej4v0um 187 7.2 16-bit timer operation 7.2.1 operation as interval timer (16 bits) tmn operates as an interval timer when 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) are set as shown in figure 7-9 (n = 0, 1). in this case, tmn repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register n (crn0). when the count value of tmn matches with the set value of crn0, the value of tmn is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttmn0) is generated. the count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (prmn0 and prmn1) of prescaler mode register n0 (prmn0) and by bits 0 (prmn2) of prescaler mode register n1 (prmn1). figure 7-9. control register settings when tmn operates as interval timer (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the interval timer function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 188 figure 7-10. configuration of interval timer note the count clock is set by the prmn0 and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to ports. 2. n = 0, 1 figure 7-11. timing of interval timer operation tmn count value crn0 0000h 0001h n n n n n n n 0000h 0001h 0000h 0001h count start clear clear interrupt acknowledgement interrupt acknowledgement inttmn0 ton interval time interval time interval time count clock t remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0,1 tin0 noise eliminator 16-bit capture/compare register n0 (crn0) count clock note selector 16-bit timer register n (tmn) ovfn clear circuit inttmn0 f xx /2 chapter 7 timer/counter function user?s manual u13850ej4v0um 189 7.2.2 ppg output operation tmn can be used for ppg (programmable pulse generator) output by setting 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) as shown in figure 7-12. the ppg output function outputs a square wave from the ton pin with a cycle specified by the count value set in advance to 16-bit capture/compare register n0 (crn0) and a pulse width specified by the count value set in advance to 16-bit capture/compare register n1 (crn1). figure 7-12. control register settings in ppg output operation (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00010/10/111 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. disables one-shot pulse output. cautions 1. make sure that 0000h < crn1 < crn0 ffffh is set to crn0 and crn1. 2. ppg output set the pulse cycle to (crn0 setup value + 1). duty factor is (crn1 setup value + 1)/(crn0 setup value + 1). : don?t care chapter 7 timer/counter function user?s manual u13850ej4v0um 190 7.2.3 pulse width measurement 16-bit timer register n (tmn) can be used to measure the pulse widths of the signals input to the tin0 and tin1 pins. measurement can be carried out with tmn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the tin0 pin. (1) pulse width measurement with free-running counter and one capture register if the edge specified by prescaler mode register n0 (prmn0) is input to the tin0 pin when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 7-13 ), the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the edge is specified by using bits 6 and 7 (esn10 and esn11) of prescaler mode register n0 (prmn0). the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode register n0, n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be removed. figure 7-13. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0/1 0 crn0 as compare register crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 191 figure 7-14. configuration for pulse width measurement with free-running counter note the count clock is set by the prmn0 and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to ports. 2. n = 0, 1 figure 7-15. timing of pulse width measurement with free-running counter and one capture register (with both edges specified) t value loaded to crn1 tin0 pin input tmn count value 0000h 0001h d0 ffffh d1 0000h d2 d3 inttmn1 d0 ovfn ( d1 ? d0 ) t (10000h ? d1 + d2) t count clock d1 d2 d3 (d3 ? d2) t d0 + 1 d1 + 1 remark n = 0, 1 16-bit capture/compare register n1 (crn1) 16-bit timer register n (tmn) internal bus count clock note tin0 selector ovfn inttmn1 chapter 7 timer/counter function user?s manual u13850ej4v0um 192 (2) measurement of two pulse widths with free-running counter the pulse widths of the two signals respectively input to the tin0 and tin1 pins can be measured when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 7-16 ). when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of the tmn is loaded to 16-bit capture/compare register n1 (crn1) and an external interrupt request signal (inttmn1) is set. when the edge specified by bits 6 and 7 (esn10 and esn11) in prmn0 is input to the tin1 pin, the value of tmn is loaded to 16-bit capture/compare register n0 (crn0), and an external interrupt request signal (inttmn0) is set. the edges of the tin0 and tin1 pins are specified by bits 4 and 5 (esn00 and esn01) and bits 6 and 7 (esn10 and esn11) of prmn0, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode register n0, n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be removed. figure 7-16. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn00000101 crn0 as capture register captures valid edge of tin1 pin to crn0. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 193 ? capture operation (free-running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 7-17. crn1 capture operation with rising edge specified count clock tmn tin0 crn1 inttmn1 n + 1 n n ? 1 n ? 2 n ? 3 n rising edge detection remark n = 0, 1 figure 7-18. timing of pulse width measurement with free-running counter (with both edges specified) t value loaded to crn1 (d1 ? d0) t (10000h ? d1 + d2) t(d3 ? d2) t (10000h ? d1 + (d2 + 1) t 0000h 0001h d0 count clock tmn count value tin0 pin input inttmn1 tin1 pin input inttmn0 ovfn value loaded to crn0 d0 + 1 d1 d1 + 1 ffffh 0000h d2 d2 + 1 d2 + 2 d3 d0 d1 d2 d1 d2 + 1 remark n = 0, 1 chapter 7 timer/counter function user?s manual u13850ej4v0um 194 (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 7-19 ), the pulse width of the signal input to the tin0 pin can be measured. when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the value of tmn is also loaded to 16-bit capture/compare register n0 (crn0) when an edge reverse to the one that triggers capturing to crn1 is input. the edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n (prmn0). the rising or falling edge can be specified. the valid edge of tin0 is detected through sampling at a count clock cycle selected by prescaler mode register n0, n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be removed. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform its capture operation. figure 7-19. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn00000111 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0 pin. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 195 figure 7-20. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) t ( d1 ? d0 ) t ( 10000h ? d1 + d2 ) t ( d3 ? d2 ) t ovfn 0001h 0000h d0 d1 count clock tmn count value tin0 pin input inttmn1 value loaded to crn1 value loaded to crn0 d0 + 1 d1 + 1 0000h ffffh d2 d2 + 1 d3 d0 d1 d2 d3 remark n = 0, 1 (4) pulse width measurement by restarting when the valid edge of the tin0 pin is detected, the pulse width of the signal input to the tin0 pin can be measured by clearing 16-bit timer register n (tmn) once and then resuming counting after loading the count value of tmn to 16-bit capture/compare register n1 (crn1). (see figure 7-22 ) the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising or falling edge can be specified. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode register n0, n1 (prmn0, prmn1) and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be removed. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform its capture operation. chapter 7 timer/counter function user?s manual u13850ej4v0um 196 figure 7-21. control register settings for pulse width measurement by restarting (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000100/10 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn00000111 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 7.1.4 timer 0, 1 control registers . figure 7-22. timing of pulse width measurement by restarting (with rising edge specified) t (d1 + 1) t (d2 + 1) t 0001h 0000h d0 d2 d1 count clock tmn count value tin0 pin input inttmn1 d0 d2 value loaded to crn1 value loaded to crn0 d1 0001h 0000h 0001h 0000h remark n = 0, 1 chapter 7 timer/counter function user?s manual u13850ej4v0um 197 7.2.4 operation as external event counter tmn can be used as an external event counter that counts the number of clock pulses input to the tin0 pin from an external source by using 16-bit timer register n (tmn). each time the valid edge specified by prescaler mode register n0 (prmn0) has been input, tmn is incremented. when the count value of tmn matches with the value of 16-bit capture/compare register n0 (crn0), tmn is cleared to 0, and an interrupt request signal (inttmn0) is generated. the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle of f xx /2, and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be removed. figure 7-23. control register settings in external event counter mode (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 198 figure 7-24. configuration of external event counter internal bus 16-bit capture/compare register n (crn0) 16-bit timer/counter n (tmn) ovfn count clock note selector inttmn0 16-bit capture/compare register n1 (crn1) noise eliminator valid edge of tin0 f xx /2 match clear note the count clock is set by the prmn0 and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to ports. 2. n = 0, 1 figure 7-25. timing of external event counter operation (with rising edge specified) tin0 pin input tmn count value crn0 inttmn0 0001h 0000h n ? 1n n 0003h 0002h 0005h 0004h 0001h 0000h 0003h 0002h caution read tmn when reading the count value of the external event counter. remark n = 0, 1 7.2.5 operation to output square wave tmn can be used to output a square wave with any frequency at an interval specified by the count value set in advance to 16-bit capture/compare register n0 (crn0). by setting bits 0 (toen) and 1 (tocn1) of 16-bit timer output control register n (tocn) to 1, the output status of the ton pin is reversed at an interval specified by the count value set in advance to crn1. in this way, a square wave of any frequency can be output. chapter 7 timer/counter function user?s manual u13850ej4v0um 199 figure 7-26. control register settings in square wave output mode (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 1 crn0 as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00000/10/111 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. does not reverse output on match between tmn and crn1. disables one-shot pulse output. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square wave output function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 200 figure 7-27. timing of square wave output operation count clock tmn count value crn0 inttmn0 0002h 0001h 0000h n ? 1 n n n ? 1 n ton pin output 0002h 0001h 0000h 0000h remark n = 0, 1 7.2.6 operation to output one-shot pulse tmn can output a one-shot pulse in synchronization with a software trigger and an external trigger (tin0 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 7-28, and by setting bit 6 (osptn) of tocn by software. by setting osptn to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted active at the count value (n) set in advance to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted inactive at the count value (m) set in advance to 16-bit capture/compare register n0 (crn0) note . even after the one-shot pulse has been output, tmn continues its operation. to stop tmn, tmcn must be reset to 00h. note this is an example when n < m. when n > m, the output is assertied active by crn0 and deasserted inactive by crn1. caution do not set osptn to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is complete. chapter 7 timer/counter function user?s manual u13850ej4v0um 201 figure 7-28. control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn00000100 free-running mode (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn0000000/10 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. sets one-shot pulse output mode. set to 1 for output. caution do not set crn0 and crn1 to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the one- shot pulse output function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 202 figure 7-29. timing of one-shot pulse output operation with software trigger count clock tmn count value 0000h 0001h 0000h n + 1 n m + 2 n ? 1m ? 1m + 1 n m crn1 set value n crn0 set value m osptn inttmn1 inttmn0 ton pin output sets 0ch to tmcn (tmn count starts) n m n m n m caution 16-bit timer register n starts operating as soon as values other than 0, 0 (operation stop mode) have been set to tmcn2 and tmcn3. remark n = 0, 1 n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 7-30, and by using the valid edge of the tin0 pin as an external trigger. the valid edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the tin0 pin is detected, the 16-bit timer/event counter is cleared and started, and the output is asserted active at the count value set in advance to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted inactive at the count value set in advance to 16-bit capture/compare register n0 (crn0) note . note this is an example when n < m. when n > m, the output is assertied active by crn0 and deasserted inactive by crn1. caution even if the external trigger is generated again while the one-shot pulse is output, it is ignored. chapter 7 timer/counter function user?s manual u13850ej4v0um 203 figure 7-30. control register settings for one-shot pulse output with external trigger (a) 16-bit timer mode control registers 0, 1 (tmc0, tmc1) tmcn3 tmcn2 tmcn1 ovfn tmcn00001000 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1 (crc0, crc1) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1 (toc0, toc1) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. sets one-shot pulse output mode. caution do not set crn0 and crn1 to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the one- shot pulse output function. for details, refer to 7.1.4 timer 0, 1 control registers . chapter 7 timer/counter function user?s manual u13850ej4v0um 204 figure 7-31. timing of one-shot pulse output operation with external trigger (with rising edge specified) count clock tmn count value 0000h 0001h n + 1 m + 2 n + 2 m ? 1m + 1 m value to set crn1 n value to set crn0 m tin0 pin input inttmn1 inttmn0 ton pin output sets 08h to tmcn (tmn count starts) 0000h n m ? 2 n m n m n m caution 16-bit timer register n starts operating as soon as values other than 0, 0 (operation stop mode) have been set to tmcn2 and tmcn3. remark n = 0, 1 n < m chapter 7 timer/counter function user?s manual u13850ej4v0um 205 7.2.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit timer register n (tmn) is started asynchronously to the count pulse. figure 7-32. start timing of 16-bit timer register n remark n = 0, 1 (2) 16-bit capture/compare register setting (clear & start mode on match between tmn and crn0) set 16-bit capture/compare registers n0, n1 (crn0, crn1) to a value other than 0000h (the 1-pulse count operation is disabled when these registers are used as event counters). (3) setting compare register during timer count operation if the value to which the current value of 16-bit capture/compare register n0 (crn0) has been changed is less than the value of 16-bit timer register n (tmn), tmn continues counting, overflows, and starts counting again from 0. if the new value of crn0 (m) is less than the old value (n), the timer must be reset and then restarted after the value of crn0 has been changed. figure 7-33. timing after changing compare register during timer count operation tmn count value ffffh 0001h 0002h 0000h count pulse x ? 1 n m crn0 x remarks 1. n > x > m 2. n = 0, 1 count pulse tmn count value 0004h 0003h 0002h 0001h 0000h timer starts chapter 7 timer/counter function user?s manual u13850ej4v0um 206 (4) data hold timing of capture register if the valid edge is input to the tin0 pin while 16-bit capture/compare register n1 (crn1) is being read, crn1 performs the capture operation, but this capture value is not guaranteed. however, the interrupt request signal (inttmn1) is set as a result of detection of the valid edge. figure 7-34. data hold timing of capture register tmn count value count pulse n + 1 nn + 2 m + 2 m + 1 m x n+1 a capture operation is performed but not guaranteed. edge input inttmn1 capture read signal crn1 interrupt value capture operation remark n = 0, 1 (5) setting valid edge before setting the valid edge of the tin0 pin, stop the timer operation by resetting bits 2 and 3 (tmcn2 and tmcn3) of 16-bit timer mode control register n to 0, 0. set the valid edge by using bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). (6) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is being output, do not set osptn to 1. to output a one-shot pulse again, wait until the interrupt inttmn0, which occurs on a match with crn0, or inttmn1, which occurs on a match with crn1, has occurred. (b) one-shot pulse output with external trigger if the external trigger occurs while a one-shot pulse is being output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output function of timer 0 or 1 by software trigger, the level of the tin0 pin or the pin multiplexed with it must not be changed. even in this case, the external trigger remains valid. consequently, the timer is cleared and started by the level of the tin0 pin or the pin multiplexed with it, and a pulse is output when it is not expected. chapter 7 timer/counter function user?s manual u13850ej4v0um 207 (7) operation of ovfn flag (a) ovfn flag set the ovfn flag is set to 1 in the following case: select a mode in which the timer is cleared and started on a match between tmn and crn0, a mode in which it is cleared and started by the valid edge of tin0, or free-running mode. set crn0 to ffffh. when tmn counts up from ffffh to 0000h figure 7-35. operation timing of ovfn flag remark n = 0, 1 (b) clear ovfn flag even if the ovfn flag is cleared before the next count clock is counted (before tmn become 0001h) after tmn has overflowed, the ovfn flag is set again and the clear becomes invalid. (8) conflict operation (a) if the read period and capture trigger input conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, if the read period and capture trigger input conflict, the capture trigger has priority. the read data of crn0 and crn1 is undefined. (b) if the match timings of the write period and tmn conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, because match detection cannot be performed correctly if the match timings of the write period and 16-bit timer register n (tmn) conflict, do not write to crn0 and crn1 close to the match timing. (9) timer operation (a) crn1 capture even if 16-bit timer register n (tmn) is read, a capture to 16-bit capture/compare register n1 (crn1) is not performed. (b) acknowledgement of tin0 and tin1 pins when the timer is stopped, input signals to the tin0 and tin1 pins are not acknowledged, regardless of the cpu operation. count pulse crn0 0001h 0000h ffffh fffeh ffffh tmn ovfn inttmn0 chapter 7 timer/counter function user?s manual u13850ej4v0um 208 (c) one-shot pulse output the one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid edge of the tin0 pin. the one-shot pulse cannot be output in the clear & start mode on a match of tmn and crn0 because an overflow does not occur. (10) capture operation (a) if the valid edge of tin0 is specified for the count clock when the valid edge of tin0 is specified for the count clock, the capture register with tin0 specified as a trigger will not operate correctly. (b) if both rising and falling edges are selected as the valid edge of tin0, a capture operation is not performed. (c) to capture the signals correctly from tin0 and tin1 the capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 (prmn0, prmn1) in order to correctly capture the signals from tin1 and tin0. (d) interrupt request input although a capture operation is performed a the falling edge of the count clock, interrupt request inputs (inttmn0, inttmn1) are generated at the falling edge of the next count clock. (11) compare operation (a) when rewriting crn0 and crn1 during timer operation when rewriting 16-bit timer capture/compare registers n0 and n1 (crn0, crn1), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) when crn0 and crn1 are set to compare mode when crn0 and crn1 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. (12) edge detection (a) when the tin0 or tin1 pin is high level immediately after a system reset when the tin0 or tin1 pin is high level immediately after a system reset, if the valid edge of the tin0 or tin1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (tmn) is then enabled, the rising edge will be detected immediately. care is therefore needed when the tin0 or tin1 pin is pulled up. however, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the tin0 valid edge is used as a count clock or a capture trigger. the former is sampled by f xx /2, and the latter is sampled by the count clock selected using prescaler mode registers n0 or n1 (prmn0, prmn1). detecting the valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice. chapter 7 timer/counter function user?s manual u13850ej4v0um 209 7.3 8-bit timer (tm2 to tm7) 7.3.1 functions 8-bit timer n has the following two modes (n = 2 to 7). ? mode using timer alone (individual mode) ? mode using the cascade connection (16-bit resolution: cascade connection mode) caution do not access following registers when not using the cascade connection. ? 16-bit counters (tm23, tm45, tm67) ? 16-bit compare registers (cr23, cr45, cr67) these two modes are described next. (1) mode using timer alone (individual mode) the timer operates as an 8-bit timer/event counter. it can have the following functions. ? interval timer ? external event counter ? square wave output ? pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting tm2 and tm3 or tm4 and tm5 in cascade. it can have the following functions. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution the timer operates as a 16-bit timer/event counter by connecting tm6 and tm7 in cascade. ? interval timer with 16-bit resolution chapter 7 timer/counter function user?s manual u13850ej4v0um 210 figure 7-36. block diagram of tm2 to tm7 notes 1. the count clock is set by the tcln register. 2. clock of serial interface (tm2 and tm3 only) remarks 1. ? ] ? is a signal that can be directly connected to the port. 2. n = 2 to 7, m = 2 to 5 7.3.2 configuration timer n includes the following hardware. table 7-5. configuration of timers 2 to 7 item configuration timer registers 8-bit counters 2 to 7 (tm2 to tm7) 16-bit counters 23, 45, 67 (tm23, tm45, tm67): only when connecting in cascade registers 8-bit compare registers 2 to 7 (cr20 to cr70) 16-bit compare registers 23, 45, 67 (cr23, cr45, cr67): only when connecting in cascade timer outputs to2 to to5 control registers timer clock selection registers 20 to 70 and 21 to 71 (tcl20 to tcl70 and tcl21 to tcl71) 8-bit timer mode control registers 2 to 7 (tmc2 to tmc7) 8-bit compare register n (crn0) 8-bit counter n (tmn) match ovf mask circuit tcen selector clear /4 tcln2 tcln1 tcln0 internal bus tmcn6 tmcn4 lvsm lvrm tmcm1 toem s q r invert level s r inv q selector inttmn selector tom internal bus selector count clock n o t e 1 tim tcln3 note 2 timer clock selection register n0, n1 (tcln0, tcln1) timer mode control n0, n1 (tcln0, tcln1) chapter 7 timer/counter function user?s manual u13850ej4v0um 211 (1) 8-bit counters 2 to 7 (tm2 to tm7) tmn is an 8-bit read-only register that counts the count pulses. the counter is incremented synchronous to the rising edge of the count clock. tm2 and tm3 or tm5 and tm6 can be connected in cascade and used as 16-bit timers. when tmm and tmm+1 are connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. however, since they are connected via the internal 8-bit bus, tmm and tmm+1 are read separately. consequently, they should be read twice one compared to allow for count variation. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 00h. (1) reset is input. (2) tcen is cleared. (3) tmn and crn0 match in the clear and start mode that occurs when tmn and crn0 match. caution when connected in cascade, these registers become 00h even when tcen in the lower timers (tm2, tm4, tm6) is cleared. remark n = 2 to 7 m = 2, 4, 6 (2) 8-bit compare registers 2 to 7 (cr20 to cr70) the value set in crn0 is always compared to the count in 8-bit counter n (tmn). if the two values match, an interrupt request (inttmn) is generated (except in the pwm mode). the value of crn0 can be set in the range of 00h to ffh, and can be written during counting. when tmm and tmm+1 are connected in cascade and used as a 16-bit timer, crm0 and cr (m+1) 0 operate as a 16-bit compare register. this register generates an interrupt request (inttmm) when the counter value and register value are compared as 16 bits and match. since the inttmm+1 interrupt request is also generated at that time, mask the inttmm+1 interrupt request when tmm and tmm+1 are used connected in cascade. caution if data is set in a cascade connection, always set after stopping the timer. remark n = 2 to 7 m = 2, 4, 6 chapter 7 timer/counter function user?s manual u13850ej4v0um 212 7.3.3 timer n control register the following two types of registers control timer n. ? timer clock selection registers n0, n1 (tcln0, tcln1) ? 8-bit timer mode control register n (tmcn) (1) timer clock selection registers 20 to 71 and 21 to 71 (tcl20 to tcl70 and tcl21 to tcl71) these registers set the count clock of timer n. tcln0 and tcln1 are set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. chapter 7 timer/counter function user?s manual u13850ej4v0um 213 figure 7-37. tm2, tm3 timer clock selection registers 20, 21, 30, 31 (tcl20, tcl21, tcl30, and tcl31) after reset: 00h r/w address: fffff244h, fffff254h 76543210 tcln0 0 0 0 0 0 tcln2 tcln1 tcln0 (n = 2, 3) after reset: 00h r/w address: fffff24eh, fffff25eh 76543210 tcln10000000tcln3 (n = 2, 3) count clock selection f xx tcln3 tcln2 tcln1 tcln0 count clock 20 mhz note 12.58 mhz 0000tin fa lling edge ?? 0001tin rising edge ?? 0010f xx /4 200 ns 318 ns 0011f xx /8 400 ns 636 ns 0100f xx /16 800 ns 1.3 s 0101f xx /32 1.6 s2.5 s 0110f xx /128 6.4 s 10.2 s 0111f xx /512 25.6 s 40.7 s 1000setting prohibited ?? 1001setting prohibited ?? 1010f xx /64 3.2 s5.1 s 1011f xx /256 12.8 s 20.3 s 1100setting prohibited ?? 1101setting prohibited ?? 1110setting prohibited ?? 1111setting prohibited ?? note only for the v850/sb1. cautions 1. when tcln0 and tcln1 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 to in tcln0 to 0, and bits 1 to 7 in tcln1 to 0. remark when connected in cascade, the settings of tcl33 to tcl30 of tm3 are invalid. chapter 7 timer/counter function user?s manual u13850ej4v0um 214 figure 7-38. tm4, tm5 timer clock selection registers 40, 41, 50, 51 (tcl40, tcl41, tcl50, and tcl51) after reset: 00h r/w address: fffff264h, fffff274h 76543210 tcln0 0 0 0 0 0 tcln2 tcln1 tcln0 (n = 4, 5) after reset: 00h r/w address: fffff26eh, fffff27eh 76543210 tcln10000000tcln3 (n = 4, 5) count clock selection f xx tcln3 tcln2 tcln1 tcln0 count clock 20 mhz note 12.58 mhz 0000tin fa lling edge ?? 0001tin rising edge ?? 0010f xx /4 200 ns 318 ns 0011f xx /8 400 ns 636 ns 0100f xx /16 800 ns 1.3 s 0101f xx /32 1.6 s2.5 s 0110f xx /128 6.4 s 10.2 s 0111f xt (sub clock) 30.5 s 30.5 s 1000setting prohibited ?? 1001setting prohibited ?? 1010f xx /64 3.2 s5.1 s 1011f xx /256 12.8 s 20.3 s 1100setting prohibited ?? 1101setting prohibited ?? 1110setting prohibited ?? 1111setting prohibited ?? note only for the v850/sb1. cautions 1. when tcln0 and tcln1 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 of tcln0 and bits 1 to 7 of tcln1 to 0. remark when connected in cascade, the settings of tcl53 to tcl50 of tm5 are invalid. chapter 7 timer/counter function user?s manual u13850ej4v0um 215 figure 7-39. tm6, tm7 timer clock selection registers 60, 61, 70, 71 (tcl60, tcl61, tcl70, and tcl71) after reset: 00h r/w address: fffff284h, fffff294h 76543210 tcln0 0 0 0 0 0 tcln2 tcln1 tcln0 (n = 6, 7) after reset: 00h r/w address: fffff28eh, fffff29eh 76543210 tcln10000000tcln3 (n = 6, 7) count clock selection f xx tcln3 tcln2 tcln1 tcln0 count clock 20 mhz note 12.58 mhz 0000 setting prohibited ?? 0001 setting prohibited ?? 0010 f xx /4 200 ns 318 ns 0011 f xx /8 400 ns 636 ns 0100 f xx /16 800 ns 1.3 s 0101 f xx /32 1.6 s2.5 s 0110 f xx /64 3.2 s5.1 s 0111 f xx /128 6.4 s 10.2 s 1000 setting prohibited ?? 1001 setting prohibited ?? 1010 f xx /256 12.8 s 20.3 s 1011 f xx /512 25.6 s 40.7 s 1100 setting prohibited ?? 1101 setting prohibited ?? 1110 setting prohibited ?? 1111 tm0 overflow signal ?? note only for the v850/sb1. cautions 1. when tcln0 and tcln1 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 of tcln0 and bits 1 to 7 of tcln1 to 0. remark when connected in cascade, the settings of tcl73 to tcl70 of tm7 are invalid. chapter 7 timer/counter function user?s manual u13850ej4v0um 216 (2) 8-bit timer mode control registers 2 to 7 (tmc2 to tmc7) the tmcn register makes the following six settings. (1) controls the counting by 8-bit counter n (tmn) (2) selects the operating mode of 8-bit counter n (tmn) (3) selects the individual mode or cascade connection mode (4) sets the state of the timer output flip-flop (5) controls the timer flip-flop or selects the active level in the pwm (free-running) mode (6) controls timer output tmcn is set by an 8-/1-bit memory manipulation instruction. reset input sets these registers to 04h (although the state of hardware is initialized to 04h, 00h is read when reading). chapter 7 timer/counter function user?s manual u13850ej4v0um 217 figure 7-40. 8-bit timer mode control registers 2 to 7 (tmc2 to tmc7) after reset: 04h r/w address: tmc2 fffff246h tmc5 fffff276h tmc3 fffff256h tmc6 fffff286h tmc4 fffff266h tmc7 fffff296h <7> 6 5 4 <3> <2> 1 <0> tmcn tcen tmcn6 0 tmcn4 lvsm lvrm tmcm1 toem (n = 2 to 7, m = 2 to 5) tcen tmn count operation control 0 counting is disabled after the counter is cleared to 0 (prescaler disabled) 1 start count operation tmcn6 tmn operating mode selection 0 clear & start mode when tmn and crn0 match 1 pwm (free-running) mode tmcn4 individual mode or cascade connection mode selection 0 individual mode (fixed to 0 when n = 2, 4, 6) 1 cascade connection mode (connection to lower timer) lvsm lvrm setting state of timer output flip-flop 0 0 not change 0 1 reset timer output flip-flop to 0 1 0 set timer output flip-flop to 1 1 1 setting prohibited other than pwm (free-running) mode (tmcn6 = 0) pwm (free-running) mode (tmcn6 = 1) tmcm1 controls timer f/f selects active level 0 disable inversion operation active high 1 enable inversion operation active low toem timer output control 0 disable output (port mode) 1 enable output cautions 1. when using as the timer output pin (tom), set the port value to 0 (port mode output). an ored value of the timer output value is output. 2. since tom and tim share the same pin, only one of the functions can be used. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tcem = 0. 2. if lvsm and lvrm are read after setting data, 0 is read. chapter 7 timer/counter function user?s manual u13850ej4v0um 218 7.4 8-bit timer operation 7.4.1 operation as an interval timer (8-bit operation) the timer operates as an interval timer that repeatedly generates interrupts at the interval of the preset count in 8- bit compare register n (crn0). if the count in 8-bit counter n (tmn) matches the value set in crn0, simultaneous to clearing the value of tmn to 0 and continuing the count, the interrupt request signal (inttmn) is generated. the tmn count clock can be selected by bits 0 to 2 (tcln0 to tcln2) in timer clock selection register n0 (tcln0) and by bit 0 (tcln3) in timer clock selection register n1 (tcln1) (n = 2 to 7). setting method (1) set each register. ? tcln0, tcln1: selects the count clock. ? crn0: compare value ? tmcn: selects the clear and start mode when tmn and crn0 match. (tmcn = 0000 xxx0b, x is don?t care) (2) when tcen = 1 is set, counting starts. (3) when the values of tmn and crn0 match, inttmn is generated (tmn is cleared to 00h). (4) then, inttmn is repeatedly generated at the same interval. when counting stops, set tcen = 0. figure 7-41. timing of interval timer operation (1/3) basic operation tmn count value crn0 00h 01h n 00h 01h 00h 01h n n count start clear clear nn n n interrupt acknowledgement interrupt acknowledgement tcen inttmn ton interval time interval time interval time count clock t remarks 1. interval time = (n + 1) t; n = 00h to ffh 2. n = 2 to 7 chapter 7 timer/counter function user?s manual u13850ej4v0um 219 figure 7-41. timing of interval timer operation (2/3) when crn0 = 00h remark n = 2 to 7 when crn0 = ffh 01h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tmn crn0 tcen inttmn ton interrupt acknowledgement interval time t interrupt acknowledgement remark n = 2 to 7 count clock crn0 tcen inttmn ton tmn 00h 00h 00h 00h 00h interval time t chapter 7 timer/counter function user?s manual u13850ej4v0um 220 figure 7-41. timing of interval timer operation (3/3) operated by crn0 transition (m < n) remark n = 2 to 7 operated by crn0 transition (m > n) remark n = 2 to 7 count clock crn0 tcen inttmn ton tmn 00h ffh m m 00h 00h n n m crn0 transition tmn overflows since m < n crn0 tcen inttmn ton tmn n m crn0 transition m 01h 00h m ? 1 n 01h 00h n n ? 1 count clock chapter 7 timer/counter function user?s manual u13850ej4v0um 221 7.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to tin. each time a valid edge specified with timer clock selection register n0, n1 (tcln0, tcln1) is input, tmn is incremented. the edge setting can be selected to be either a rising or falling edge. if the total of tmn and the value of 8-bit compare register n (crn0) match, tmn is cleared to 0 and the interrupt request signal (inttmn) is generated. inttmn is generated each time the tmn value matches the crn0 value. remark n = 2 to 5 figure 7-42. timing of external event counter operation (when rising edge is set) tin tmn count value 0005 0004 0003 0002 0001 0000 n ? 1 n crn0 inttmn n 0000 0001 0002 0003 remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 222 7.4.3 operation as square wave output (8-bit resolution) a square wave having any frequency is output at the interval preset in 8-bit compare register n (crn0). by setting bit 0 (toen) of 8-bit timer mode control register n (tmcn) to 1, the output state of ton is inverted with the count preset in crn0 as the interval. therefore, a square wave output having any frequency (duty factor = 50%) is possible. setting method (1) set the registers. ? sets the port latch and port mode register to 0 ? tcln0, tcln1: selects the count clock ? crn0: compare value ? tmcn: clear and start mode when tmn and crn0 match lvsn lvrn setting state of timer output flip-flop 1 0 high level output 0 1 low level output inversion of timer output flip-flop enabled timer output enabled toen = 1 (2) when tcen = 1 is set, the counter starts operating. (3) if the values of tmn and crn0 match, the timer output flip-flop inverts. also, inttmn is generated and tmn is cleared to 00h. (4) then, the timer output flip-flop is inverted at the same interval to output a square wave from ton. remark n = 2 to 5 figure 7-43. square wave output operation timing 00h 00h 01h 02h n ? 1 n 01h 02h n n ? 1 n 00h count clock crn0 ton tmn count value count start note the initial value of ton output can be set with tmcn register bits 3 and 2 (lvsn, lvrn). remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 223 7.4.4 operation as 8-bit pwm output by setting bit 6 (tmcn6) of 8-bit timer mode control register n (tmcn) to 1, the timer operates as a pwm output. pulses with the duty factor determined by the value set in 8-bit compare register n (crn0) are output from ton. set the width of the active level of the pwm pulse in crn0. the active level can be selected by bit 1 (tmcn1) in tmcn. the count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of timer clock selection register n0 (tcln0) and by bit 0 (tcln3) of timer clock selection register n1 (tcln1). the pwm output can be enabled and disabled by bit 0 (toen) of tmcn. caution crn0 can be rewritten only once in one period while in the pwm mode. remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 224 (1) basic operation of the pwm output setting method (1) set the port latch and port mode register n to 0. (2) set the active level width in 8-bit compare register n (crn0). (3) select the count clock with timer clock selection register n0, n1 (tcln0, tcln1). (4) set the active level in bit 1 (tmcn1) of tmcn. (5) if bit 7 (tcen) of tmcn is set to 1, counting starts. when counting stops, set tcen to 0. pwm output operation (1) when counting starts, the pwm output (output from ton) outputs the inactive level until an overflow occurs. (2) when the overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until crn0 and the count of 8-bit counter n (tmn) match. (3) the pwm output after crn0 and the count match is the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tcen = 0, the pwm output goes to the inactive level. remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 225 (a) basic operation of pwm output figure 7-44. timing of pwm output basic operation (active level = h) count clock 00h tmn crn0 tcen inttmn ton active level inactive level active level 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n when crn0 = 0 count clock tmn crn0 tcen inttmn ton inactive level inactive level 00h 01h ffh 00h 01h 02h n n + 1 n + 2 ffh 00h 01h 02h m 00h 00h when crn0 = ffh count clock tmn crn0 tcen inttmn ton inactive level inactive level active level a ctive level inactive level 00h 01h ffh 00h 01h 02h n n + 1 n + 2 ffh 00h 01h 02h m 00h ffh remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 226 (b) operation based on crn0 transitions figure 7-45. timing of operation based on crn0 transitions when the crn0 value changes from n to m before tmn overflows inttmn n + 1 02h 01h 00h ffh nn + 2 tmn crn0 tcen ton count clock crn0 transition (n m) m + 1 m n m h m + 2 02h 01h 00h ffh m + 1 m m + 2 when the crn0 value changes from n to m after tmn overflows inttmn n + 1 02h 01h 00h ffh n n + 2 tmn crn0 tcen ton count clock crn0 transition (n m) n + 1 n nm h n + 2 02h 01h 00h ffh m + 1 m m + 2 03h n when the crn0 value changes from n to m within two clocks (00h, 01h) immediately after tmn overflows inttmn n + 1 02h 01h 00h ffh n n + 2 tmn crn0 tcen ton count clock crn0 transition (n m) n + 1 n nm h n + 2 02h 01h 00h ffh m + 1 m m + 2 03h n remark n = 2 to 5 chapter 7 timer/counter function user?s manual u13850ej4v0um 227 7.4.5 operation as interval timer (16 bits) (1) cascade connection (16-bit timer) mode the v850/sb1 and v850/sb2 provide a 16-bit register that can be used when connecting in cascade. the available registers are as follows. tm2, tm3 cascade connection: 16-bit counter tm23 (address: fffff24ah) 16-bit compare register cr23 (address: fffff24ch) tm4, tm5 cascade connection: 16-bit counter tm45 (address: fffff26ah) 16-bit compare register cr45 (address: fffff26ch) tm6, tm7 cascade connection: 16-bit counter tm67 (address: fffff28ah) 16-bit compare register cr67 (address: fffff28ch) by setting bit 4 (tmcn4) of 8-bit timer mode control register n (tmcn) to 1, the timer enters the timer/counter mode with 16-bit resolution (n = 2 to 7). with the count preset in 8-bit compare register n (crn0) as the interval, the timer operates as an interval timer by repeatedly generating interrupts (n = 2 to 7). the following shows a setting method when using tm2 and tm3. when using tm4 and tm5 or tm6 and tm7, substitute them for tm2 and tm3. setting method (tm2, tm3 cascade connection) (1) setting registers ? tcl20, tcl21: select the count clock for tm2 (setting not necessary for tm3 because of cascade connection). ? cr20, cr30: compare value (00h to ffh can be set for compare values) ? tmc2: selects clear & start mode on a match of tm2 and cr2 (x: don?t care) [tm2 tmc2 = 0000 xxx0b, tm3 tmc3 = 0001 xxx0b] (2) set the tce3 bit of tmc3 to 1. after that, set the tce2 bit of tmc2 to 1 to start the count operation. (3) when the tm23 and cr23 values of the timer connected in cascade match, inttm2 of tm2 is generated (tm2 and tm3 are cleared to 00h). (4) imttm2 is then repeatedly generated at the same interval. cautions 1. when 8-bit timers (tm2, tm3) are connected in cascade and used as a 16-bit timer (tm23), change the setting value of the compare register (cr23) after stopping the count operation of the 8-bit timers connected in cascade. if the value of cr23 is changed without stopping the timers, the values of the higher 8 bits (tm3) become undefined. 2. even during cascade connection, the interrupt request (inttm3) of higher timer 3 (tm3) is generated when the count value of higher timer 3 (tm3) matches cr30. be sure to mask tm3 to disable this interrupt. 3. to set the tcen bit, set tce2 after tce3 is set. 4. the count can be started or stopped by setting the tce2 bit of tmc2. chapter 7 timer/counter function user?s manual u13850ej4v0um 228 a timing example of the cascade connection mode with 16-bit resolution is shown below. figure 7-46. cascade connection mode with 16-bit resolution n + 1 n 00h 01h tmn count clock enable operation starting count 00h ffh ffh 01h 00h ffh 00h 00h n 01h 00h a 00h tmn + 1 01h m m ? 1 02h 00h 00h b crn0 n cr(n+1)0 m tcen tcen + 1 inttmn ton interval time operation stopped interrupt generation level inverted counter cleared remark n = 2, 4, 6 chapter 7 timer/counter function user?s manual u13850ej4v0um 229 7.4.6 cautions (1) error when the timer starts the time until the match signal is generated after the timer starts has a maximum error of one clock. the reason is the starting of 8-bit counter n (tmn) is asynchronous with respect to the count pulse. figure 7-47. start timing of timer n remark n = 2 to 7 (2) operation after the compare register is changed while the timer is counting if the value after 8-bit compare register n (crn0) changes is less than the value of 8-bit timer register (tmn), counting continues, overflows, and counting starts again from 0. consequently, when the value (m) after crn0 changes is less than the value (n) before the change, the timer must restart after crn0 changes (n = 2 to 5). figure 7-48. timing after compare register changes during timer count operation tmn count value n count pulse crn0 x ? 1 x ffh 00h 01h 02h m remarks 1. n > x > m 2. n = 2 to 5 caution except when the tin input is selected, always set tcen = 0 before setting the stop state. (3) tmn read out during timer operation since reading out tmn during operation occurs while the selected clock is temporarily stopped, select some high or low level waveform that is longer than the selected clock (n = 2 to 7). 00h 01h 02h 03h 04h timer starts tmn count value count pulse user?s manual u13850ej4v0um 230 chapter 8 watch timer 8.1 function the watch timer has the following functions: ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 8-1. block diagram of watch timer f w /2 10 selector 11-bit prescaler f w /2 8 f w /2 7 f w /2 6 f w /2 5 f w /2 4 5-bit counter intwtn intwtni wtnm0 wtnm1 wtnm3 wtnm4 wtnm5 wtnm6 wtnm7 watch timer mode control register (wtnm) f xx internal bus clear clear wtnm2 f xt f w /2 9 f w /2 11 wtncs1 wtncs0 selector selector selector watch timer clock selection register (wtncs) 3 f w remark f xx : main system clock frequency f xt : subsystem clock frequency f w : watch timer clock frequency chapter 8 watch timer user?s manual u13850ej4v0um 231 (1) watch timer the watch timer generates an interrupt request (intwtn) at time intervals of 0.5 seconds or 0.25 seconds by using the main system clock or subsystem clock. (2) interval timer the watch timer generates an interrupt request (intwtni) at time intervals specified in advance. table 8-1. interval time of interval timer interval time f xt = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.4 ms remark f w : watch timer clock frequency 8.2 configuration the watch timer includes the following hardware. table 8-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control registers watch timer mode control register (wtnm) watch timer clock selection register (wtncs) chapter 8 watch timer user?s manual u13850ej4v0um 232 8.3 watch timer control register the watch timer mode control register (wtnm) and watch timer clock selection register (wtncs) control the watch timer. the watch timer should be operated after setting the count clock and interval time. (1) watch timer mode control register (wtnm) this register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. wtnm is set by an 8-/1-bit memory manipulation instruction. reset input clears wtnm to 00h. figure 8-2. watch timer mode control register (wtnm) after reset: 00h r/w address: fffff360h 765432<1><0> wtnm wtnm7 wtnm6 wtnm5 wtnm4 wtnm3 wtnm2 wtnm1 wtnm0 wtnm6 wtnm5 wtnm4 selects interval time of prescaler 0002 4 /f w (488 s) 0012 5 /f w (977 s) 0102 6 /f w (1.95 ms) 0112 7 /f w (3.91 ms) 1002 8 /f w (7.81 ms) 1012 9 /f w (15.6 ms) 1102 10 /f w (31.2 ms) 1112 11 /f w (62.4 ms) wtnm3 wtnm2 selects set time of watch flag 002 14 /f w (0.5 s) 012 13 /f w (0.25 s) 102 5 /f w (977 s) 112 4 /f w (488 s) wtm1 controls operation of 5-bit counter 0 clears after operation stops 1starts wtnm0 enables operation of watch timer 0 stops operation (clears both prescaler and 5-bit counter) 1 enables operation chapter 8 watch timer user?s manual u13850ej4v0um 233 remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz. 3. for the settings of wtnm7, refer to figure 8-3 . (2) watch timer clock selection register (wtncs) this register selects the count clock of the watch timer. wtncs is set using an 8-bit memory manipulation instruction. reset input clears wtncs to 00h. caution do not change the count clock during a watch timer operation. figure 8-3. watch timer clock selection register (wtncs) after reset: 00h r/w address: fffff364h 76543210 wtncs000000wtncs1wtncs0 wtncs1 wtncs0 wtnm7 selection of count clock main clock frequency 000f xx /2 7 4.194 mhz 001f xt (sub clock) ? 010f xx /3 2 6 6.291 mhz 011f xx /2 8 8.388 mhz 1 0 0 setting prohibited ? 1 0 1 setting prohibited ? 110f xx /3 2 7 12.582 mhz 111f xx /2 9 16.776 mhz note note only for the v850/sb1. remark wtnm7 is bit 7 of the wtnm register chapter 8 watch timer user?s manual u13850ej4v0um 234 8.4 operation 8.4.1 operation as watch timer the watch timer operates with time intervals of 0.5 seconds with the subsystem clock (32.768 khz). the watch timer generates an interrupt request at fixed time intervals. the count operation of the watch timer is started when bits 0 (wtnm0) and 1 (wtnm1) of the watch timer mode control register (wtnm) are set to 1. when these bits are cleared to 0, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. setting the wtnm1 bit to 0 can clear the watch timer. an error of up to 15.6 ms may occur at this time. setting the wtnm0 bit to 0 can clear the interval timer. however, an error up to 0.5 sec. may occur after a watch timer overflow (intwtn) because the 5-bit counter is also cleared. 8.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. the interval time can be selected by bits 4 to 6 (wtnm4 to wtnm6) of the watch timer mode control register (wtnm). table 8-3. interval time of interval timer wtnm6 wtnm5 wtnm4 interval time f w = 32.768 khz 000 2 4 1/f w 488 s 001 2 5 1/f w 977 s 010 2 6 1/f w 1.95 ms 011 2 7 1/f w 3.91 ms 100 2 8 1/f w 7.81 ms 101 2 9 1/f w 15.6 ms 110 2 10 1/f w 31.2 ms 111 2 11 1/f w 62.4 ms remark f w : watch timer clock frequency chapter 8 watch timer user?s manual u13850ej4v0um 235 figure 8-4. operation timing of watch timer/interval timer start 5-bit counter overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) count clock f w or f w /2 9 watch timer interrupt intwtn interval timer interrupt intwtni nt nt remark f w : watch timer clock frequency ( ): f w = 32.768 khz n: interval timer operation counts 8.4.3 cautions it takes some time to generate the first watch timer interrupt request (intwtn) after operation is enabled (wrnm1 and wtnm0 bits of wtnm register = 1). figure 8-5. watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) it takes 0.515625 s to generate the first intwtn (2 9 1/32.768 = 0.015625 s longer). intwtn is then generated every 0.5 s. 0.5 s 0.5 s 0.515625 s wtnm0, wtnm1 intwtn user?s manual u13850ej4v0um 236 chapter 9 watchdog timer 9.1 functions the watchdog timer has the following functions. ? watchdog timer ? interval timer ? selecting the oscillation stabilization time caution use the watchdog timer mode register (wdtm) to select the watchdog timer mode or the interval timer mode. figure 9-1. block diagram of watchdog timer internal bus osts0 osts1 osts2 osts wdtm4 run wdtm wdcs wdcs0 wdcs1 wdcs2 3 intwdt note 1 intwdtm note 2 3 output controller prescaler selector f xx /2 22 f xx /2 10 f xx /2 20 f xx /2 19 f xx /2 18 f xx /2 17 f xx /2 16 f xx /2 15 f xx /2 14 run clear osc selector notes 1. in watchdog timer mode 2. in interval timer mode remark f xx : main clock frequency chapter 9 watchdog timer user?s manual u13850ej4v0um 237 (1) watchdog timer mode this mode detects inadvertent program loop. when inadvertent program loop is detected, a non-maskable interrupt can be generated. table 9-1. inadvertent program loop detection time of watchdog timer inadvertent program loop detection time clock f xx = 20 mhz note f xx = 12.58 mhz 2 14 /f xx 819.2 s1.3 ms 2 15 /f xx 1.6 ms 2.6 ms 2 16 /f xx 3.3 ms 5.2 ms 2 17 /f xx 6.6 ms 10.4 ms 2 18 /f xx 13.1 ms 20.8 ms 2 19 /f xx 26.2 ms 41.6 ms 2 20 /f xx 52.4 ms 83.3 ms 2 22 /f xx 209.7 ms 333.4 ms note only for the v850/sb1. (2) interval timer mode interrupts are generated at a preset time interval. table 9-2. interval time of interval timer interval time clock f xx = 20 mhz note f xx = 12.58 mhz 2 14 /f xx 819.2 s1.3 ms 2 15 /f xx 1.6 ms 2.6 ms 2 16 /f xx 3.3 ms 5.2 ms 2 17 /f xx 6.6 ms 10.4 ms 2 18 /f xx 13.1 ms 20.8 ms 2 19 /f xx 26.2 ms 41.6 ms 2 20 /f xx 52.4 ms 83.3 ms 2 22 /f xx 209.7 ms 333.4 ms note only for the v850/sb1. chapter 9 watchdog timer user?s manual u13850ej4v0um 238 9.2 configuration the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers oscillation stabilization time selection register (osts) watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) 9.3 watchdog timer control register the registers to control the watchdog timer is shown below. ? oscillation stabilization time selection register (osts) ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register (wdtm) (1) oscillation stabilization time selection register (osts) this register selects the oscillation stabilization time after a reset is applied or the stop mode is released until the oscillation is stable. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 9-2. oscillation stabilization time selection register (osts) after reset: 04h r/w address: fffff380h 765 4 3 21 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz note 12.58 mhz 0002 14 /f xx 819.2 s1.3 ms 0012 16 /f xx 3.3 ms 5.2 ms 0102 17 /f xx 6.6 ms 10.4 ms 0112 18 /f xx 13.1 ms 20.8 ms 1002 19 /f xx (after reset) 26.2 ms 41.6 ms other than above setting prohibited note only for the v850/sb1. chapter 9 watchdog timer user?s manual u13850ej4v0um 239 (2) watchdog timer clock selection register (wdcs) this register selects the overflow times of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input clears wdcs to 00h. figure 9-3. watchdog timer clock selection register (wdcs) after reset: 00h r/w address: fffff382h 7654321 0 wdcs00000wdcs2wdcs1wdcs0 watchdog timer/interval timer overflow time f xx wdcs2 wdcs1 wdcs0 clock 20 mhz note 12.58 mhz 0002 14 /f xx 819.2 s1.3 ms 0012 15 /f xx 1.6 ms 2.6 ms 0102 16 /f xx 3.3 ms 5.2 ms 0112 17 /f xx 6.6 ms 10.4 ms 1002 18 /f xx 13.1 ms 20.8 ms 1012 19 /f xx 26.2 ms 41.6 ms 1102 20 /f xx 52.4 ms 83.3 ms 1112 22 /f xx 209.7 ms 333.4 ms note only for the v850/sb1. chapter 9 watchdog timer user?s manual u13850ej4v0um 240 (3) watchdog timer mode register (wdtm) this register sets the operating mode of the watchdog timer, and enables and disables counting. wdtm is set by an 8-/1-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 9-4. watchdog timer mode register (wdtm) after reset: 00h r/w address: fffff384h <7>6543210 wdtm run 0 0 wdtm4 0 0 0 0 run operating mode selection for the watchdog timer note 1 0 disable count 1 clear count and start counting wdtm4 operating mode selection for the watchdog timer note 2 0 interval timer mode (if an overflow occurs, a maskable interrupt intwdtm is generated.) 1 watchdog timer mode 1 (if an overflow occurs, a non-maskable interrupt intwdt is generated.) notes 1. once run is set (1), the register cannot be cleared (0) by software. therefore, when the count starts, the count cannot be stopped except by reset input. 2. once wdtm4 is set (1), the register cannot be cleared (0) by software. caution if run is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 2 10 /f xx seconds less than the set time. chapter 9 watchdog timer user?s manual u13850ej4v0um 241 9.4 operation 9.4.1 operation as watchdog timer set bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 1 to operate as a watchdog timer to detect an inadvertent program loop. setting bit 7 (run) of wdtm to 1 starts the count. after counting starts, if run is set to 1 again within the set time interval for inadvertent program loop detection, the watchdog timer is cleared and counting starts again. if run is not set to 1 and the inadvertent program loop detection time has elapsed, a non-maskable interrupt (intwdt) is generated (no reset functions). the watchdog timer stops running in the stop mode and idle mode. consequently, set run to 1 and clear the watchdog timer before entering the stop mode or idle mode. do not set the watchdog timer when operating the halt mode since the watchdog timer running in halt mode. cautions 1. the actual inadvertent program loop detection time may be up to 2 10 /f xx seconds less than the set time. 2. when the sub clock is selected for the cpu clock, the watchdog timer stops (retains) counting. table 9-4. inadvertent program loop detection time of watchdog timer inadvertent program loop detection time clock f xx = 20 mhz note f xx = 12.58 mhz 2 14 /f xx 819.2 s1.3 ms 2 15 /f xx 1.6 ms 2.6 ms 2 16 /f xx 3.3 ms 5.2 ms 2 17 /f xx 6.6 ms 10.4 ms 2 18 /f xx 13.1 ms 20.8 ms 2 19 /f xx 26.2 ms 41.6 ms 2 20 /f xx 52.4 ms 83.3 ms 2 22 /f xx 209.7 ms 333.4 ms note only for the v850/sb1. chapter 9 watchdog timer user?s manual u13850ej4v0um 242 9.4.2 operation as interval timer set bit 4 (wdtm4) to 0 in the watchdog timer mode register (wdtm) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. when operating as an interval timer, the interrupt mask flag (wdtmk) of the wdtic register and the priority setting flag (wdtpr0 to wdtpr2) become valid, and a maskable interrupt (intwdtm) can be generated. the default priority of intwdtm has the highest priority setting of the maskable interrupts. the interval timer continues operating in the halt mode and stops in the stop mode and idle mode. therefore, after the run bit of wdtm register is set to 1 and the interval timer is cleared before entering the stop mode/idle mode, execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as reset is not input. 2. the interval time immediately after being set by wdtm may be up to 2 10 /f xx seconds less than the set time. 3. when the sub clock is selected for the cpu clock, the watchdog timer stops (retains) counting. table 9-5. interval time of interval timer interval time clock f xx = 20 mhz note f xx = 12.58 mhz 2 14 /f xx 819.2 s 1.3 ms 2 15 /f xx 1.6 ms 2.6 ms 2 16 /f xx 3.3 ms 5.2 ms 2 17 /f xx 6.6 ms 10.4 ms 2 18 /f xx 13.1 ms 20.8 ms 2 19 /f xx 26.2 ms 41.6 ms 2 20 /f xx 52.4 ms 83.3 ms 2 22 /f xx 209.7 ms 333.4 ms note only for the v850/sb1. chapter 9 watchdog timer user?s manual u13850ej4v0um 243 9.5 standby function control register the wait time from releasing the stop mode until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 9-5. oscillation stabilization time selection register (osts) after reset: 04h r/w address: fffff380h 76543210 osts00000osts2osts1osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz note 12.58 mhz 0002 14 /f xx 819.2 s 1.3 ms 0012 16 /f xx 3.3 ms 5.2 ms 0102 17 /f xx 6.6 ms 10.4 ms 0112 18 /f xx 13.1 ms 20.8 ms 1002 19 /f xx (after reset) 26.2 ms 41.6 ms other than above setting prohibited note only for the v850/sb1. caution the wait time at the release of the stop mode does not include the time (a in the figure below) until clock oscillation starts after releasing the stop mode when reset is input or an interrupt is generated. vss stop mode release a voltage waveform at x1 pin user?s manual u13850ej4v0um 244 chapter 10 serial interface function 10.1 overview the v850/sb1 and v850/sb2 incorporate the following serial interfaces. ? channel 0: 3-wire serial i/o (csi0)/i 2 c0 note ? channel 1: 3-wire serial i/o (csi1)/asynchronous serial interface (uart0) ? channel 2: 3-wire serial i/o (csi2)/i 2 c1 note ? channel 3: 3-wire serial i/o (csi3)/asynchronous serial interface (uart1) ? channel 4: 8 to 16-bit variable-length 3-wire serial i/o (csi4) note i 2 c0 and i 2 c1 support multimaster ( pd70303xay and 70f303way only). either 3-wire serial i/o or i 2 c can be used as a serial interface. 10.2 3-wire serial i/o (csi0 to csi3) csin (n = 0 to 3) has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sckn), serial output line (son), and serial input line (sin). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. chapter 10 serial interface function user?s manual u13850ej4v0um 245 10.2.1 configuration csin includes the following hardware. table 10-1. configuration of csin item configuration registers serial i/o shift registers 0 to 3 (sio0 to sio3) control registers serial operation mode registers 0 to 3 (csim0 to csim3) serial clock selection registers 0 to 3 (csis0 to csis3) figure 10-1. block diagram of 3-wire serial i/o tmx output clock selection sckn son sin intcsin internal bus selector 8 serial clock controller serial clock counter serial i/o shift register n (sion) interrupt generator remarks 1. n = 0 to 3 2. tmx output is as follows: when n = 0 or 3: tm2 when n = 1 or 2: tm3 (1) serial i/o shift registers 0 to 3 (sio0 to sio3) sion is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sion is set by an 8-bit memory manipulation instruction. when ?1? is set to bit 7 (csien) of serial operation mode register n (csimn), a serial operation can be started by writing data to or reading data from sion. when transmitting, data written to sion is output via the serial output (son). when receiving, data is read from the serial input (sin) and written to sion. reset input clears these registers to 00h. caution do not execute sion accesses except for the accesses that become transfer start trigger during transfer operation (read is disabled when mode = 0 and write is disabled when mode = 1). chapter 10 serial interface function user?s manual u13850ej4v0um 246 10.2.2 csin control registers csin uses is controlled by the following registers. ? serial operation mode register n (csimn) ? serial clock selection register n (csisn) (1) serial operation mode registers 0 to 3 (csim0 to csim3) csimn is used to enable or disable serial interface channel n?s serial clock, operation modes, and specific operations. csimn can be set by an 8-/1-bit memory manipulation instruction. reset input clears these registers to 00h. chapter 10 serial interface function user?s manual u13850ej4v0um 247 figure 10-2. serial operation mode registers 0 to 3 (csim0 to csim3) after reset: 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h csim3 fffff2d2h <7>6543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 3) sion operation enable/disable specification csien shift register operation serial counter port 0 operation disable clear port function note 1 1 operation enable count operation enable serial function + port function note 2 transfer operation mode flag moden operation mode transfer start trigger son output 0 transmit/receive mode sion write normal output 1 receive-only mode sion read port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 at n = 0, 3: output of to2 at n = 1, 2: output of to3 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 notes 1. the sin, son, and sckn pins are used as port function pins when csien = 0 (sion operation stop status). 2. when csien = 1 (sion operation enable status), the port function is available for the sin pin when only using the transmit function and son pin when only using the receive function. caution do not perform bit manipulation of scln1 and scln0. remarks 1. refer to figure 10-3 for the scln2 bit. 2. when the output of the timer is selected as the clock, it is not necessary to set the p26/to2/ti2 and p27/to3/ti3 pins in the timer output mode. chapter 10 serial interface function user?s manual u13850ej4v0um 248 (2) serial clock selection registers 0 to 3 (csis0 to csis3) csisn is used to set serial interface channel n?s serial clock. csisn can be set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 10-3. serial clock selection registers 0 to 3 (csis0 to csis3) after reset : 00h r/w address: csis0 fffff2a4h csis1 fffff2b4h csis2 fffff2c4h csis3 fffff2d4h 76543210 csisn0000000scln2 (n = 0 to 3) remark refer to figure 10-2 for the setting of the scln2 bit. chapter 10 serial interface function user?s manual u13850ej4v0um 249 10.2.3 operations csin has the following two operation modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode does not perform serial transfers and can therefore reduce power consumption. when in operation stop mode, if sin, son, and sckn pin are also used as i/o ports, they can be used as normal i/o ports as well. (a) register settings operation stop mode are set via the csien bit of serial operation mode register n (csimn). figure 10-4. csimn setting (operation stop mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h csim3 fffff2d2h 76543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 3) sion operation enable/disable specification csien shift register operation serial counter port 0 operation disable clear port function chapter 10 serial interface function user?s manual u13850ej4v0um 250 (2) 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sckn), serial output line (son), and serial input line (sin). (a) register settings 3-wire serial i/o mode is set via serial operation mode register n (csimn). figure 10-5. csimn setting (3-wire serial i/o mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim2 fffff2c2h csim3 fffff2d2h 76543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0 to 3) sion operation enable/disable specification csien shift register operation serial counter port 1 operation enable count operation enable serial function + port function transfer operation mode flag moden operation mode transfer start trigger son output 0 transmit/receive mode write to sion normal output 1 receive-only mode read from sion port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 when n = 0, 3: to2 when n = 1, 2: to3 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 remark refer to figure 10-3 for the scln2 bit. chapter 10 serial interface function user?s manual u13850ej4v0um 251 (b) communication operations in 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received in synchronization with the serial clock. serial i/o shift register n (sion) is shifted in synchronization with the falling edge of the serial clock. transmission data is held in the son latch and is output from the son pin. data that is received via the sin pin in synchronization with the rising edge of the serial clock is latched to sion. completion of an 8-bit transfer automatically stops operation of sion and sets the interrupt request flag (intcsin). figure 10-6. timing of 3-wire serial i/o mode si0 di7 di6 di5 di4 di3 di2 di1 di0 intcsin serial clock 1 so0 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the serial clock?s falling edge (c) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial i/o shift register n (sion). ? the sion operation control bit (csien) = 1 ? after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. the transfer data to sion is set as follows. ? transmit/receive mode when csien = 1 and moden = 0, transfer starts when writing to sion. ? receive-only mode when csien = 1 and moden = 1, transfer starts when reading from sion. caution after data has been written to sion, transfer will not start even if the csien bit value is set to ?1?. completion of an 8-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsin). chapter 10 serial interface function user?s manual u13850ej4v0um 252 10.3 i 2 c bus to use the i 2 c bus function, set the p10/sda0, p12/scl0, p20/sda1, and p22/scl1 pins to n-ch open drain output. the products with an on-chip i 2 c bus are shown below. ? v850/sb1: pd703030ay, 703031ay, 703032ay, 703033ay, 70f3032ay, 70f3033ay ? v850/sb2: pd703034ay, 703035ay, 703036ay, 703037ay, 70f3035ay, 70f3037ay the i 2 c0 and i 2 c1 have the following two modes. ? operation stop mode ? i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scln) line and a serial data bus (sdan) line. this mode complies with the i 2 c bus format and the master device can output ?start condition?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since scln and sdan are open drain outputs, the i 2 cn requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 253 figure 10-7. block diagram of i 2 c internal bus iic status register n (iicsn) iic control register n (iiccn) slave address register n (svan) noise eliminator noise eliminator match signal iic shift register n (iicn) so latch iicen d q set clear cl1, cl0 sdan scln n-ch open- drain output n-ch open- drain output data hold time correction circuit ack detector wake-up controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiicn f xx tmx output lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn start condition detector internal bus cldn dadn smcn dfcn cln1 cln0 clxn iiccen1 iiccen0 iic clock selection register n (iiccln) iic function expansion register n (iicxn) iic clock expansion register n (iiccen) remarks 1. n = 0, 1 2. tmx output n = 0: tm2 output n = 1: tm3 output chapter 10 serial interface function user?s manual u13850ej4v0um 254 a serial bus configuration example is shown below. figure 10-8. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 chapter 10 serial interface function user?s manual u13850ej4v0um 255 10.3.1 configuration i 2 cn includes the following hardware (n = 0, 1). table 10-2. configuration of i 2 cn item configuration registers iic shift registers 0 and 1 (iic0, iic1) slave address registers 0 and 1 (sva0, sva1) control registers iic control registers 0 and 1 (iicc0, iicc1) iic status registers 0 and 1 (iics0, iics1) iic clock selection registers 0 and 1 (iiccl0, iiccl1) iic clock expansion registers 0 and 1 (iicce0, iicce1) iicc function expansion registers 0 and 1 (iicx0, iicx1) (1) iic shift registers 0 and 1 (iic0, iic1) iicn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. iicn can be used for both transmission and reception (n = 0, 1). write and read operations to iicn are used to control the actual transmit and receive operations. iicn is set by an 8-bit memory manipulation instruction. reset input clears iic0 and iic1 to 00h. (2) slave address registers 0 and 1 (sva0, sva1) svan sets local addresses when in slave mode. svan is set by an 8-bit memory manipulation instruction (n = 0, 1). reset input clears sva0 and sva1 to 00h. (3) so latch the so latch is used to retain the sdan pin?s output level (n = 0, 1). (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (svan) or when an extension code is received (n = 0, 1). (5) clock selector this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. chapter 10 serial interface function user?s manual u13850ej4v0um 256 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtimn bit note ) ? interrupt request generated when a stop condition is detected (set by spien bit note ) note wtimn bit: bit 3 of iic control register n (iiccn) spien bit: bit 4 of iic control register n (iiccn) remark n = 0, 1 (8) serial clock controller in master mode, this circuit generates the clock output via the scln pin from a sampling clock (n = 0, 1). (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock. chapter 10 serial interface function user?s manual u13850ej4v0um 257 10.3.2 i 2 c control register i 2 c0 and i 2 c1 are controlled by the following registers. ? iic control registers 0, 1 (iicc0, iicc1) ? iic status registers 0, 1 (iics0, iics1) ? iic clock selection registers 0, 1 (iiccl0, iiccl1) ? iic clock expansion registers 0, 1 (iicce0, iicce1) ? iic function expansion registers 0, 1 (iicx0, iicx1) the following registers are also used. ? iic shift registers 0, 1 (iic0, iic1) ? slave address registers 0, 1 (sva0, sva1) (1) iic control registers 0, 1 (iicc0, iicc1) iiccn is used to enable/disable i 2 c operations, set wait timing, and set other i 2 c operations. iiccn can be set by an 8-/1-bit memory manipulation instruction (n = 0, 1). reset input clears iiccn to 00h. caution in i 2 c0, i 2 c1 bus mode, set the port 1 mode register (pm1) and port 2 mode register (pm2) as follows. in addition, set each output latch to 0. ? set p10 (sda0) to output mode (pm10 = 0) ? set p12 (scl0) to output mode (pm12 = 0) ? set p20 (sda1) to output mode (pm20 = 0) ? set p22 (scl1) to output mode (pm22 = 0) chapter 10 serial interface function user?s manual u13850ej4v0um 258 figure 10-9. iic control register n (iiccn) (1/4) after reset: 00h r/w address: fffff340h, fffff350h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) iicen i 2 cn operation enable/disable specification 0 stops operation. presets iic status register n (iicsn). stops internal operation. 1 enables operation. condition for clearing (iicen = 0) condition for setting (iicen = 1) ? cleared by instruction ? when reset is input ? set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scln and sdan lines are set to high impedance. the following flags are cleared. ? stdn ? ackdn ? trcn ? coin ? excn ? mstsn ? sttn ? sptn the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lreln = 0) note condition for setting (lreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction note this flag?s signal is invalid when iicen = 0. remark stdn: bit 1 of iic state register n (iicsn) ackdn: bit 2 of iic state register n (iicsn) trcn: bit 3 of iic state register n (iicsn) coin: bit 4 of iic state register n (iicsn) excn: bit 5 of iic state register n (iicsn) mstsn: bit 7 of iic state register n (iicsn) chapter 10 serial interface function user?s manual u13850ej4v0um 259 figure 10-9. iic control register n (iiccn) (2/4) after reset: 00h r/w address: fffff340h, fffff350h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) wreln wait cancellation control 0 does not cancel wait 1 cancels wait. this setting is automatically cleared after wait is canceled. condition for clearing (wreln = 0) note condition for setting (wreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction spien enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spien = 0) note condition for setting (spien = 1) ? cleared by instruction ? when reset is input ? set by instruction wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clo cks, clock output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clo cks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. this bit?s setting is invalid during an address transfer and is valid as the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn = 0) note condition for setting (wtimn = 1) ? cleared by instruction ? when reset is input ? set by instruction note this flag?s signal is invalid when iicen = 0. chapter 10 serial interface function user?s manual u13850ej4v0um 260 figure 10-9. iic control register n (iiccn) (3/4) after reset: 00h r/w address: fffff340h, fffff350h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) acken acknowledge control 0 disable acknowledge. 1 enable acknowledge. during the ninth clock period, the sda line is set to low level. however, the ack is invalid during address transfers and is valid when excn = 1. condition for clearing (acken = 0) note condition for setting (acken = 1) ? cleared by instruction ? when reset is input ? set by instruction sttn start condition trigger 0 does not generate a start condition. 1 when bus is released (in stop mode): generates a start condition (for starting as master). the sdan line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scln is changed to low level. when bus is not used: this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. in the wait state (when master device) generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the ackn period. set during the wait period. ? cannot be set at the same time as sptn condition for clearing (sttn = 0) condition for setting (sttn = 1) ? cleared by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lreln = 1 ? when iicen = 0 ? cleared when reset is input ? set by instruction note this flag?s signal is invalid when iicen = 0. remark bit 1 (sttn) is 0 if it is read immediately after data setting. chapter 10 serial interface function user?s manual u13850ej4v0um 261 figure 10-9. iic control register n (iiccn) (4/4) after reset: 00h r/w address: fffff340h, fffff350h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device?s transfer). after the sdan line goes to low level, either set the scln line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sdan line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing ? for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and during the wait period after slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ackn period. set during the wait period. ? cannot be set at the same time as sttn. ? sptn can be set only when in master mode note ? when wtimn has been set to 0, if sptn is set during the wait period that follows output of eight clo cks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtimn should be changed from 0 to 1 during the wait period following output of eight clocks, and sptn should be set during the wait period that follows output of the ninth clock. condition for clearing (sptn = 0) condition for setting (sptn = 1) ? cleared by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lreln = 1 ? when iicen = 0 ? cleared when reset is input ? set by instruction note set sptn only in master mode. however, sptn must be set and a stop condition generated before the first stop condition is detected following the switch to operation enable status. for details, see 10.3.13 cautions . caution when bit 3 (trcn) of iic status register n (iicsn) is set to 1, wreln is set during the ninth clock and wait is canceled, after which trcn is cleared and the sdan line is set to high impedance. remark bit 0 (sptn) is 0 if it is read immediately after data setting. chapter 10 serial interface function user?s manual u13850ej4v0um 262 (2) iic status registers 0, 1 (iics0, iics1) iicsn indicates the status of the i 2 cn bus. iicsn can be set by an 8-/1-bit memory manipulation instruction. iicsn is a read-only register (n = 0, 1). reset input sets iicsn to 00h. figure 10-10. iic status register n (iicsn) (1/3) after reset: 00h r address: fffff342h, fffff352h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn = 0) condition for setting (mstsn = 1) ? when a stop condition is detected ? when aldn = 1 ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when a start condition is generated aldn detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. mstsn is cleared. condition for clearing (aldn = 0) condition for setting (aldn = 1) ? automatically cleared after iicsn is read note ? when iicen changes from 1 to 0 ? when reset is input ? when the arbitration result is a ?loss?. note this register is also cleared when a bit manipulation instruction is executed for bits other than iicsn. remark lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 10 serial interface function user?s manual u13850ej4v0um 263 figure 10-10. iic status register n (iicsn) (2/3) after reset: 00h r address: fffff342h, fffff352h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn = 0) condition for setting (excn = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). coin detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coin = 0) condition for setting (coin = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the received address matches the local address (svan) (set at the rising edge of the eighth clock). trcn detection of transmit/receive status 0 receive status (other than transmit status). the sdan line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sdan line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn = 0) condition for setting (trcn = 1) ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? cleared by wreln = 1 note ? when aldn changes from 0 to 1 ? when reset is input master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) note trcn is cleared and sdan line become high impedance when bit 5 (wreln) of iic control register n (iiccn) is set and wait state is released at ninth clock with bit 3 (trcn) of iic status register n (iicsn) = 1. remark wreln: bit 5 of iic control register n (iiccn) lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 10 serial interface function user?s manual u13850ej4v0um 264 figure 10-10. iic status register n (iicsn) (3/3) after reset: 00h r address: fffff342h, fffff352h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) ackdn detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? after the sdan line is set to low level at the rising edge of the scln?s ninth clock stdn detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn = 0) condition for setting (stdn = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input when a start condition is detected spdn detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spdn = 0) condition for setting (spdn = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iicen changes from 1 to 0 ? when reset is input when a stop condition is detected remark lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 10 serial interface function user?s manual u13850ej4v0um 265 (3) iic clock selection registers 0, 1 (iiccl0, iiccl1) iiccln is used to set the transfer clock for the i 2 cn bus. iiccln can be set by an 8-/1-bit memory manipulation instruction. bits smcn, cln1 and cln0 are set using clxn bit of iic function expansion register n (iicxn) in combination with bits iiccen1 and iiccen0 of iic clock expansion register n (iiccen) (n = 0, 1) (see 10.3.2 (6) i 2 cn transfer clock setting method ). reset input clears iiccln to 00h. figure 10-11. iic clock selection register n (iiccln) after reset: 00h r/w note address: fffff344h, fffff354h 76 <5> <4> 3210 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0, 1) cldn detection of scln line level (valid only when iicen = 1) 0 scln line was detected at low level. 1 scln line was detected at high level. condition for clearing (cldn = 0) condition for setting (cldn = 1) ? when the scln line is at low level ? when iicen = 0 ? when reset is input ? when the scln line is at high level dadn detection of sdan line level (valid only when iicen = 1) 0 sdan line was detected at low level. 1 sdan line was detected at high level. condition for clearing (dadn = 0) condition for setting (dadn = 1) ? when the sdan line is at low level ? when iicen = 0 ? when reset is input ? when the sdan line is at high level smcn operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfcn switching (on/off). note bits 4 and 5 are read only bits. remark iicen: bit 7 of iic control register n (iiccn) chapter 10 serial interface function user?s manual u13850ej4v0um 266 (4) iic function expansion registers 0, 1 (iicx0, iicx1) these registers set the function expansion of i 2 cn (valid only in high-speed mode). iicxn is set with a 1-/8-bit memory manipulation instruction. set the clxn bit in combination with the smcn, dfcn, cln1, and the cln0 bits of iic clock selection register n (iiccln) and the iiccen1 and iiccen0 bits of iic clock expansion register n (iiccen) (see 10.3.2 (6) i 2 cn transfer clock setting method ) (n = 0, 1). reset input clears these registers to 00h. figure 10-12. iic function expansion register n (iicxn) (5) iic clock expansion registers 0, 1 (iicce0, iicce1) these registers set the transfer clock expansion of i 2 cn. iiccen is set with an 8-bit memory manipulation instruction. set the iiccen1 and iiccen0 bits in combination with the smcn, cln1, and cln0 bits of iic clock selection register n (iiccln) and the clxn bit of iic function expansion register n (iicxn) (see 10.3.2 (6) i 2 cn transfer clock setting method ) (n = 0, 1). reset input clears these registers to 00h. figure 10-13. iic clock expansion register n (iiccen) (6) i 2 cn transfer clock setting method the i 2 cn transfer clock frequency (f scl ) is calculated using the following expression (n = 0, 1). f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see table 10-3 selection clock setting .) t: 1/f xx t r : scln rise time t f : scln fall time for example, the i 2 cn transfer clock frequency (f scl ) when f xx = 20 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 50 ns + 200 ns + 50 ns) ? 98.5 khz after reset: 00h r/w address: fffff34ah, fffff35ah 7654321<0> iicxn0000000clxn (n = 0, 1) after reset: 00h r/w address: fffff34ch, fffff35ch 76543210 iiccen000000iiccen1iiccen0 (n = 0, 1) chapter 10 serial interface function user?s manual u13850ej4v0um 267 m x t + t r + t f m/2 x t t f t r m/2 x t scln scln inversion scln inversion scln inversion the selection clock is set using a combination of the smcn, cln1, and cln0 bits of iic clock selection register n (iiccln), the clxn bit of iic function expansion register n (iicxn), and iiccen1 and the iiccen0 bits of iic clock expansion register n (iiccen) (n = 0, 1). table 10-3. selection clock setting iiccen iicxn iiccln bit 1 bit 0 bit 0 bit 3 bit 1 bit 0 iiccen1 iiccen0 clxn smcn cln1 cln0 selection clock (f xx /m) settable main clock frequency (f xx ) range operation mode xx110xf xx /12 4.0 mhz to 4.19 mhz xx010xf xx /24 4.0 mhz to 8.38 mhz xx0110f xx /48 8.0 mhz to 16.67 mhz 010111f xx /36 12.0 mhz to 13.4 mhz 100111f xx /54 16.0 mhz to 20.0 mhz note n = 0 tm2 output/18 tm2 setting 000111 n = 1 tm3 output/18 tm3 setting high-speed mode (smcn = 1) xx0000f xx /44 2.0 mhz to 4.19 mhz xx0001f xx /86 4.19 mhz to 8.38 mhz xx0010f xx /172 8.38 mhz to 16.67 mhz 010011f xx /132 12.0 mhz to 13.4 mhz 100011f xx /198 16.0 mhz to 20.0 mhz note n = 0 tm2 output/66 tm2 setting 000011 n = 1 tm3 output/66 tm3 setting other than above setting prohibited normal mode (smcn = 0) note only for the v850/sb1. remarks 1. n = 0, 1 2. x: don?t care 3. when the output of the timer is selected as the clock, it is not necessary to set the p26/to2/ti2 and p27/to3/ti3 pins in the timer output mode. chapter 10 serial interface function user?s manual u13850ej4v0um 268 (7) iic shift registers 0, 1 (iic0, iic1) iicn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iicn during a data transfer (n = 0, 1). figure 10-14. iic shift register n (iicn) (8) slave address registers 0, 1 (sva0, sva1) svan holds the i 2 c bus?s slave addresses. it can be read from or written to in 8-bit units, but bit 0 should be fixed as 0. figure 10-15. slave address register n (svan) 10.3.3 i 2 c bus mode functions (1) pin configuration the serial clock pin (scln) and serial data bus pin (sdan) are configured as follows (n = 0, 1). scln .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sdan .............. this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull- up resistor is required. after reset: 00h r/w address: fffff346h, fffff356h 76543210 svan 0 (n = 0, 1) after reset: 00h r/w address: fffff348h, fffff358h 7654321<0> iicn (n = 0, 1) chapter 10 serial interface function user?s manual u13850ej4v0um 269 figure 10-16. pin configuration diagram v dd scl sda scl sda v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device 10.3.4 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus is shown below. figure 10-17. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scln) is continuously output by the master device. however, in the slave device, the scln?s low-level period can be extended and a wait can be inserted (n = 0, 1). chapter 10 serial interface function user?s manual u13850ej4v0um 270 (1) start condition a start condition is met when the scln pin is at high level and the sdan pin changes from high level to low level. the start conditions for the scln pin and sdan pin are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions (n = 0, 1). figure 10-18. start conditions h scl sda a start condition is output when iic control register n (iiccn)?s bit 1 (sttn) is set to 1 after a stop condition has been detected (spdn: bit 0 = 1 in the iic status register n (iicsn)). when a start condition is detected, iicsn?s bit 1 (stdn) is set to 1 (n = 0, 1). (2) addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (svan). if the address data matches the svan values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0, 1). figure 10-19. address address scln 1 sdan intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note intiicn is not generated if data other than a local address or extension code is received during slave device operation. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 271 the slave address and the eighth bit, which specifies the transfer direction as described in (3) transfer direction specification below, are together written to the iic shift register (iicn) and are then output. received addresses are written to iicn (n = 0, 1). the slave address is assigned to the higher 7 bits of iicn. (3) transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 10-20. transfer direction specification scln 1 sdan intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note intiicn is not generated if data other than a local address or extension code is received during slave device operation. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 272 (4) acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sdan line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acken) of iic control register n (iiccn) is set to 1, automatic ack signal generation is enabled (n = 0, 1). transmission of the eighth bit following the 7 address data bits causes bit 3 (trcn) of iic status register n (iicsn) to be set. when this trcn bit?s value is 0, it indicates receive mode. therefore, acken should be set to 1 (n = 0, 1). when the slave device is receiving (when trcn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acken to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acken to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sdan line (i.e., stops transmission) during transmission from the slave device. figure 10-21. ack signal scln 1 sdan 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 273 when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scln?s eighth clock regardless of the acken value. no ack signal is output if the received address is not a local address (n = 0, 1). the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output at the falling edge of the scln?s eighth clock if acken is set to 1 before wait cancellation. when 9-clock wait is selected: ack signal is automatically output at the falling edge of the scln?s eighth clock if acken has already been set to 1. (5) stop condition when the scln pin is at high level, changing the sdan pin from low level to high level generates a stop condition (n = 0, 1). a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 10-22. stop condition h scl sda remark n = 0, 1 a stop condition is generated when bit 0 (sptn) of iic control register n (iiccn) is set to 1. when the stop condition is detected, bit 0 (spdn) of iic status register n (iicsn) is set to 1 and intiicn is generated when bit 4 (spien) of iiccn is set to 1 (n = 0, 1). chapter 10 serial interface function user?s manual u13850ej4v0um 274 (6) wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scln pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). figure 10-23. wait signal (1/2) (a) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acken = 1) scl 6 sda 78 9 123 scl iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 or wrel is set to 1. transfer lines remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 275 figure 10-23. wait signal (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken = 1) scl 6 sda 789 123 scl iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl acke master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 or wrel is set to 1. output according to previously set acke value transfer lines remarks 1. acken: bit 2 of iic control register n (iiccn) wreln: bit 5 of iic control register n (iiccn) 2. n = 0, 1 a wait may be automatically generated depending on the setting for bit 3 (wtimn) of iic control register n (iiccn) (n = 0, 1). normally, when bit 5 (wreln) of iiccn is set to 1 or when ffh is written to iic shift register n (iicn), the wait status is canceled and the transmitting side writes data to iicn to cancel the wait status. the master device can also cancel the wait status via either of the following methods. ? by setting bit 1 (sttn) of iiccn to 1 ? by setting bit 0 (sptn) of iiccn to 1 chapter 10 serial interface function user?s manual u13850ej4v0um 276 10.3.5 i 2 c interrupt requests (intiicn) the following shows the value of iic status register n (iicsn) at the intiicn interrupt request generation timing and at the intiicn interrupt timing (n = 0, 1). (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b 3: iicsn = 10xxx000b (wtimn = 0) 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 10xxx110b 2: iicsn = 10xxx100b 3: iicsn = 10xxxx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 277 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn = 0 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b (wtimn = 1) 3: iicsn = 10xxxx00b (wtimn = 0) 4: iicsn = 10xxx110b (wtimn = 0) 5: iicsn = 10xxx000b (wtimn = 1) 6: iicsn = 10xxxx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxxx00b 3: iicsn = 10xxx110b 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 278 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 1010x110b 2: iicsn = 1010x000b 3: iicsn = 1010x000b (wtimn = 1) 4: iicsn = 1010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1010x110b 2: iicsn = 1010x100b 3: iicsn = 1010xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 279 (2) slave device operation (when receiving slave address data (match with svan)) (a) start ~ address ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 280 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0001x110b 4: iicsn = 0001xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 281 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0010x010b 4: iicsn = 0010x110b 5: iicsn = 0010xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 282 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 283 (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 284 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0001x110b 5: iicsn = 0001xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 285 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0010x010b 5: iicsn = 0010x110b 6: iicsn = 0010xx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 286 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 00000x10b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 287 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iicsn = 00000001b remark ? : generated only when spien = 1 n = 0, 1 (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 288 (b) when arbitration loss occurs during transmission of extension code <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 289 (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1 (b) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn?s lreln is set to 1 by software ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 290 (c) when arbitration loss occurs during data transfer <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 291 (d) when loss occurs due to restart condition during data transfer <1> not extension code (example: mismatches with svan) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care dn = d6 to d0 n = 0, 1 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn?s lreln is set to 1 by software ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care dn = d6 to d0 n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 292 (e) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iicsn = 1000x110b ? 2: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don?t care dn = d6 to d0 n = 0, 1 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 293 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 1000xx00b ? 3: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don?t care n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 294 10.3.6 interrupt request (intiicn) generation timing and wait control the setting of bit 3 (wtimn) in iic control register n (iiccn) determines the timing by which intiicn is generated and the corresponding wait control, as shown below (n = 0, 1). table 10-4. intiicn generation timing and wait control during slave device operation during master device operation wtimn address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 988 1 9 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device?s intiicn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (svan). at this point, ack is output regardless of the value set to iiccn?s bit 2 (acken). for a slave device that has received an extension code, intiicn occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of slave address register n (svan), neither intiicn nor a wait occurs. remarks 1. the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0, 1 (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wreln) of iic control register n (iiccn) to 1 ? by writing to iic shift register n (iicn) ? by start condition setting (bit 1 (sttn) of iic control register n (iiccn) = 1) ? by step condition setting (bit 0 (sptn) of iic control register n (iiccn) = 1) when an 8-clock wait has been selected (wtimn = 0), the output level of ack must be determined prior to wait cancellation. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 295 (5) stop condition detection intiicn is generated when a stop condition is detected. remark n = 0, 1 10.3.7 address match detection method when in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. an interrupt request (intiicn) occurs when a local address has been set to slave address register n (svan) and when the address set to svan matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 10.3.8 error detection in i 2 c bus mode, the status of the serial data bus (sdan) during data transmission is captured by iic shift register n (iicn) of the transmitting device, so the iicn data prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match (n = 0, 1). 10.3.9 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (excn) is set for extension code reception and an interrupt request (intiicn) is issued at the falling edge of the eighth clock (n = 0, 1). the local address stored in slave address register n (svan) is not affected. (2) if 11110xx0 is set to svan by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that intiicn occurs at the falling edge of the eighth clock (n = 0, 1). ? higher 4 bits of data match: excn = 1 note ? 7 bits of data match: coin = 1 note note excn: bit 5 of iic status register n (iicsn) coin: bit 4 of iic status register n (iicsn) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 (lreln) of iic control register n (iiccn) to 1 and the cpu will enter the next communication wait state. chapter 10 serial interface function user?s manual u13850ej4v0um 296 table 10-5. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification 10.3.10 arbitration when several master devices simultaneously output a start condition (when sttn is set to 1 before stdn is set to 1 note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. this kind of operation is called arbitration (n = 0, 1). when one of the master devices loses in arbitration, an arbitration loss flag (aldn) in iic status register n (iicsn) is set via the timing by which the arbitration loss occurred, and the scln and sdan lines are both set for high impedance, which releases the bus (n = 0, 1). the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the aldn = 1 setting that has been made by software (n = 0, 1). for details of interrupt request timing, see 10.3.5 i 2 c interrupt requests (intiicn) . note stdn: bit 1 of iic status register n (iicsn) sttn: bit 1 of iic control register n (iiccn) chapter 10 serial interface function user?s manual u13850ej4v0um 297 figure 10-24. arbitration timing example master 1 master 2 transfer lines scl sda scl sda scl sda master 1 loses arbitration hi-z hi-z remark n = 0, 1 table 10-6. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data transmission when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scln is at low level while attempting to output a restart condition chapter 10 serial interface function user?s manual u13850ej4v0um 298 notes 1. when wtimn (bit 3 of the iic control register n (iiccn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtimn = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1). 2. when there is a possibility that arbitration will occur, set spien = 1 for master device operation (n = 0, 1). remark spien: bit 5 of iic control register n (iiccn) 10.3.11 wake up function the i 2 c bus slave function is a function that generates an interrupt request (intiicn) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spien) of iic control register n (iiccn) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1). chapter 10 serial interface function user?s manual u13850ej4v0um 299 10.3.12 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lreln) of iic control register n (iiccn) was set to ?1?) (n = 0, 1). if bit 1 (sttn) of iiccn is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to iic shift register n (iicn) causes the master?s address transfer to start. at this point, iiccn?s bit 4 (spien) should be set (n = 0, 1). when sttn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0, 1). if the bus has been released............................................. a start condition is generated if the bus has not been released (standby mode)............. communication reservation to detect which operation mode has been determined for sttn, set sttn, wait for the wait period, then check the mstsn (bit 7 of iic status register n (iicsn)) (n = 0, 1). wait periods, which should be set via software, are listed in table 10-7. these wait periods can be set via the settings for bits 3, 1, and 0 (smcn, cln1, and cln0) in iic clock selection register n (iiccln) (n = 0, 1). table 10-7. wait periods smcn cln1 cln0 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 100 101 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 300 the communication reservation timing is shown below. figure 10-25. communication reservation timing 2 1 3456 2 1 3456 789 scl sda program processing hardware processing write to iic0 set spd and intiic0 stt =1 communication reservation set std output by master with bus access iicn: iic shift register n sttn: bit 1 of iic control register n (iiccn) stdn: bit 1 of iic status register n (iicsn) spdn: bit 0 of iic status register n (iicsn) remark n = 0, 1 communication reservations are accepted via the following timing. after bit 1 (stdn) of iic status register n (iicsn) is set to ?1?, a communication reservation can be made by setting bit 1 (sttn) of iic control register n (iiccn) to ?1? before a stop condition is detected (n = 0, 1). figure 10-26. timing for accepting communication reservations scl sda std spd standby mode remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 301 the communication reservation flow chart is illustrated below. figure 10-27. communication reservation flow chart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn h ei mstsn = 0? (communication reservation) note (generate start condition) ; sets stt flag (communication reservation). ; gets wait period set by software (see table 10-7 ). ; confirmation of communication reservation ; clear user flag. ; iicn write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation executes a write to iic shift register n (iicn) when a stop condition interrupt request occurs. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 302 10.3.13 cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic clock selection register n (iiccln). (b) set bit 7 (iicen) of iic control register n (iiccn). (c) set bit 0 of iiccn. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 303 10.3.14 communication operations (1) master operations the following is a flow chart of the master operations. figure 10-28. master operation flow chart remark n = 0, 1 iiccln h select transfer clock. iiccn h iicen = spien = wtimn = 1 start iicn write transfer. start iicn write transfer. wreln = 1 start reception. generate stop condition. (no slave with matching address) generate restart condition or stop condition. start data processing data processing acken = 0 no yes no no no no no no yes yes yes yes yes intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? transfer completed? intiicn = 1? ackdn = 1? trcn = 1? intiicn = 1? ackdn = 1? ; stop condition detection ; address transfer completion no (receive) yes (transmit) chapter 10 serial interface function user?s manual u13850ej4v0um 304 (2) slave operation an example of slave operation is shown below. figure 10-29. slave operation flow chart iiccn h iicen = 1 wreln = 1 start reception. detect restart condition or stop condition. start acken = 0 data processing data processing lreln = 1 no yes no no no no no no no yes no yes yes yes yes yes yes wtimn = 0 acken = 1 intiicn = 1? yes communicate? transfer completed? intiicn = 1? wtimn = 1 start iicn write transfer. intiicn = 1? excn = 1? coin = 1? trcn = 1? ackdn = 1? remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 305 10.3.15 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trcn bit (bit 3 of iic status register n (iicsn)) that specifies the data transfer direction and then starts serial communication with the slave device. iic bus shift register n (iicn)?s shift operation is synchronized with the falling edge of the serial clock (scln). the transmit data is transferred to the so latch and is output (msb first) via the sdan pin. data input via the sdan pin is captured by iicn at the rising edge of scln. the data communication timing is shown below. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 306 figure 10-30. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when exc = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 307 figure 10-30. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 308 figure 10-30. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 309 figure 10-31. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l h h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 310 figure 10-31. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 311 figure 10-31. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l h h acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) n ? ack (when spien = 1) note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 312 10.4 asynchronous serial interface (uart0, uart1) uartn (n = 0, 1) has the following two operation modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) asynchronous serial interface mode this mode enables full-duplex operation which transmits and receives one byte of data after the start bit. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. in addition, a baud rate based on divided clock input to the asckn pin can also be defined. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). 10.4.1 configuration the uartn includes the following hardware. table 10-8. configuration of uartn item configuration registers transmit shift registers 0, 1 (txs0, txs1) receive buffer registers 0, 1 (rxb0, rxb1) control registers asynchronous serial interface mode registers 0, 1 (asim0, asim1) asynchronous serial interface status registers 0, 1 (asis0, asis1) baud rate generator control registers 0, 1 (brgc0, brgc1) baud rate generator mode control registers 00, 01 (brgmc00, brgmc01) baud rate generator mode control registers 10, 11 (brgmc10, brgmc11) chapter 10 serial interface function user?s manual u13850ej4v0um 313 figure 10-32. block diagram of uartn baud rate generator f xx to f xx /2 9 txd0, txd1 asck0, asck1 rxd0, rxd1 intst0, intst1 intsr0, intsr1 0, 1 (rx0, rx1) internal bus selector 0, 1 (txs0, txs1) 8 8 receive shift registers receive buffer registers 0, 1 (rxb0, rxb1) 8 transmit control parity addition receive control parity check transmit shift registers tmx output remark tmx output is as follows: when uart0: tm2 when uart1: tm3 (1) transmit shift registers 0, 1 (txs0, txs1) txsn is the register for setting transmit data. data written to txsn is transmitted as serial data. when the data length is set as 7 bits, bit 0 to bit 6 of the data written to txsn is transmitted as serial data. writing data to txsn starts the transmit operation. txsn can be written to by an 8-bit memory manipulation instruction. it cannot be read from. reset input sets these registers to ffh. caution do not write to txsn during a transmit operation. (2) receive shift registers 0, 1 (rx0, rx1) rxn register converts serial data input via the rxd0, rxd1 pins to parallel data. when one byte of data is received at rxn, the received data is transferred to receive buffer registers 0, 1(rxb0, rxb1). rx0, rx1 cannot be manipulated directly by a program. (3) receive buffer registers 0, 1 (rxb0, rxb1) rxbn is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred. when the data length is set as 7 bits, received data is sent to bit 0 to bit 6 of rxbn. in rxbn, the msb must be set to ?0?. rxbn can be read by an 8-bit memory manipulation instruction. it cannot be written to. reset input sets rxbn to ffh. chapter 10 serial interface function user?s manual u13850ej4v0um 314 (4) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (txsn), based on the values set to asynchronous serial interface mode register n (asimn). (5) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register n (asimn). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register n (asisn) according to the type of error that is detected. 10.4.2 uartn control registers uartn uses the following registers for control function (n = 0, 1). ? asynchronous serial interface mode register n (asimn) ? asynchronous serial interface status register n (asisn) ? baud rate generator control register n (brgcn) ? baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) chapter 10 serial interface function user?s manual u13850ej4v0um 315 (1) asynchronous serial interface mode registers 0, 1 (asim0, asim1) asimn is an 8-bit register that controls uartn?s serial transfer operations. asimn can be set by an 8-/1-bit memory manipulation instruction. reset input clears these registers to 00h. figure 10-33. asynchronous serial interface mode registers 0, 1 (asim0, asim1) after reset: 00h r/w address: fffff300h, fffff310h <7><6>543210 asimn txen rxen ps1n ps0n ucln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stop port function port function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity ucln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution do not switch the operation mode until after the current serial transmit/receive operation has stopped. chapter 10 serial interface function user?s manual u13850ej4v0um 316 (2) asynchronous serial interface status registers 0, 1 (asis0, asis1) when a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. asisn can be read using an 8-/1-bit memory manipulation instruction. reset input clears these registers to 00h. figure 10-34. asynchronous serial interface status registers 0, 1 (asis0, asis1) after reset: 00h r address: fffff302h, fffff312h 76543<2><1><0> asisn 0 0 0 0 0 pen fen oven (n = 0, 1) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length has been set as two bits by setting bit 2 (sln) in asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data. chapter 10 serial interface function user?s manual u13850ej4v0um 317 (3) baud rate generator control registers 0, 1 (brgc0, brgc1) these registers set the serial clock for uartn. brgcn can be set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 10-35. baud rate generator control registers 0, 1 (brgc0, brgc1) after reset: 00h r/w address: fffff304h, fffff314h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0, 1) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 selection of input clock k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 ???????? ? ? ???????? ? ? ???????? ? ? 11111111f sck /255 255 cautions 1. the value of brgcn becomes 00h after reset. before starting operation, select a setting other than ?setting prohibited?. selecting the ?setting prohibited? setting in stop mode does not cause any problems. 2. if write is performed to brgcn during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter chapter 10 serial interface function user?s manual u13850ej4v0um 318 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) these registers set the uartn source clock. brgmcn0 and brgmcn1 are set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 10-36. baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) after reset: 00h r/w address: fffff30eh, fffff31eh 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 (n = 0, 1) after reset: 00h r/w address: fffff320h, fffff322h 76543210 brgmcn10000000tpsn3 (n = 0, 1) tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0: tm3 output at n = 1: tm2 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? caution if write is performed to brgmcn0, n1 during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgmcn0, n1 during communication processing. remarks 1. f sck : source clock of 8-bit counter 2. when the output of the timer is selected as the clock, it is not necessary to set the p26/to2/ti2 and p27/to3/ti3 pins in the timer output mode. chapter 10 serial interface function user?s manual u13850ej4v0um 319 10.4.3 operations uartn has the following two operation modes. ? operation stop mode ? asynchronous serial interface mode (1) operation stop mode in this mode serial transfers are not performed, allowing reduction in power consumption. when in operation stop mode, pins can be used as ordinary ports. (a) register settings operation stop mode settings are made via bits txen and rxen of asynchronous serial interface mode register n (asimn). figure 10-37. asimn setting (operation stop mode) after reset: 00h r/w address: fffff300h, fffff310h 76543210 asimn txen rxen ps1n ps0n cln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stop port function port function caution do not switch the operation mode until after the current serial transmit/receive operation has stopped. chapter 10 serial interface function user?s manual u13850ej4v0um 320 (2) asynchronous serial interface mode this mode enables full-duplex operation, in which one byte of data is transmitted and received after the start bit. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (a) register settings the asynchronous serial interface mode settings are made via asimn, brgcn, brgmcn0, and brgmcn1 (n = 0, 1). figure 10-38. asimn setting (asynchronous serial interface mode) after reset: 00h r/w address: fffff300h, fffff310h 76543210 asimn txen rxen ps1n ps0n cln sln isrmn 0 (n = 0, 1) txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution do not switch the operation mode until after the current serial transmit/receive operation has stopped. chapter 10 serial interface function user?s manual u13850ej4v0um 321 figure 10-39. asisn setting (asynchronous serial interface mode) after reset: 00h r address: fffff302h, fffff312h 76543210 asisn 0 0 0 0 0 pen fen oven (n = 0, 1) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length has been set as two bits by setting bit 2 (sln) in asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data. chapter 10 serial interface function user?s manual u13850ej4v0um 322 figure 10-40. brgcn setting (asynchronous serial interface mode) after reset: 00h r/w address: fffff304h, fffff314h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0, 1) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 input clock selection k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 ???????? ? ? ???????? ? ? ???????? ? ? 11111111f sck /255 255 cautions 1. before starting operation, select a setting other than ?setting prohibited?. selecting ?setting prohibited? setting in stop mode does not cause any problems. 2. if write is performed to brgcn during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter chapter 10 serial interface function user?s manual u13850ej4v0um 323 figure 10-41. brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) after reset: 00h r/w address: fffff30eh, fffff31eh 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 (n = 0, 1) after reset: 00h r/w address: fffff320h, fffff322h 76543210 brgmcn10000000tpsn3 (n = 0, 1) tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0: tm3 output at n = 1: tm2 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? caution if write is performed to brgmcn0, n1 during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgmcn0 and brgmcn1 during communication processing. remarks 1. f xx : main clock oscillation frequency 2. when the output of the timer is selected as the clock, it is not necessary to set the p26/to2/ti2 and p27/to3/ti3 pins in the timer output mode. chapter 10 serial interface function user?s manual u13850ej4v0um 324 (b) baud rate the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. chapter 10 serial interface function user?s manual u13850ej4v0um 325 figure 10-42. error tolerance (when k = 16), including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t: 8-bit counter?s source clock cycle baud rate error tolerance (when k = 16) = 100 = 4.8438 (%) 15.5 320 chapter 10 serial interface function user?s manual u13850ej4v0um 326 (3) communication operations (a) data format as shown in figure 10-43, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. asynchronous serial interface mode register n (asimn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1). figure 10-43. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. asynchronous serial interface mode register n (asimn) and baud rate generator control register n (brgcn) are used to set the serial transfer rate (n = 0, 1). if a receive error occurs, information about the receive error can be recognized by reading asynchronous serial interface status register n (asisn). chapter 10 serial interface function user?s manual u13850ej4v0um 327 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number is set an even number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?1? if the transmit data contains an even number of ?1? bits: the parity bit value is ?0? ? during reception the number of ?1? bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an odd number. (ii) odd parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number is set an odd number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?0? if the transmit data contains an even number of ?1? bits: the parity bit value is ?1? ? during reception the number of ?1? bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an even number. (iii) zero parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will be generated regardless of whether the parity bit is a ?0? or a ?1?. (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will be generated. chapter 10 serial interface function user?s manual u13850ej4v0um 328 (c) transmission the transmit operation is started when transmit data is written to transmit shift register n (txsn). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txsn, thereby emptying txsn, after which a transmit completion interrupt (intstn) is issued. the timing of the transmit completion interrupt is shown below. figure 10-44. timing of asynchronous serial interface transmit completion interrupt txdn (output) d0 d1 d2 d6 d7 parity stop start intstn (a) stop bit length: 1 txdn (output) d0 d1 d2 d6 d7 parity start intstn (b) stop bit length: 2 stop caution do not write to asynchronous serial interface mode register n (asimn) during a transmit operation. writing to asimn during a transmit operation may disable further transmit operations (in such cases, input reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intstn) or the interrupt request flag (stifn) that is set by intstn. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 329 (d) reception the receive operation is enabled when ?1? is set to bit 6 (rxen) of asynchronous serial interface mode register n (asimn), and input via the rxdn pin is sampled. the serial clock specified by asimn is used when sampling the rxdn pin. when the rxdn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxdn pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 8-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register n (rxbn) and a receive completion interrupt (intsrn) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxbn. when an error occurs, instrn is generated if bit 1 (isrmn) of asimn is cleared (0). on the other hand, intsrn is not generated if the isrmn bit is set (1). if the rxen bit is reset to 0 during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxbn and asisn do not change, nor does intsrn or intsern occur. the timing of the asynchronous serial interface receive completion interrupt is shown below. figure 10-45. timing of asynchronous serial interface receive completion interrupt caution be sure to read the contents of receive buffer register n (rxbn) even when a receive error has occurred. if the contents of rxbn are not read, an overrun error will occur during the next data receive operation and the receive error status will remain. remark n = 0, 1 rxdn (input) d0 d1 d2 d6 d7 parity stop start intsrn chapter 10 serial interface function user?s manual u13850ej4v0um 330 (e) receive error there are three types of errors during a receive operation: a pariy error, framing error, and overrun error. when, as the result of data receive, an error flag is set in asynchronous serial interface status register n (asisn), the receive error interrupt request (intsern) is generated. the receive error interrupt request is generated prior to the receive completion interrupt request (intsrn). by reading the contents of asisn during receive error interrupt servicing (intsern), it is possible to detect which error has occurred at reception. the contents of asisn are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data (if there is an error in the subsequent data, the error flag is set). table 10-10. receive error causes receive error cause asisn value parity error parity specification at transmission and receive data parity do not match. 04h framing error stop bit is not detected. 02h overrun error reception of subsequent data was completed before data was read from the receive buffer register. 01h figure 10-46. receive error timing rxdn (input) intsrn note d7 d6 d2 d1 d0 parity stop start intsern intsern (when parity error occurs) note even if a receive error occurs when the isrmn bit of asimn is set (1), intsrn is not generated. cautions 1. the contents of asynchronous serial interface status register n (asisn) are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data. to check the contents of error, always read asisn before reading rxbn. 2. be sure to read receive buffer register n (rxbn) even in receive error generation. if rxbn is not read out, an overrun error will occur during subsequent data reception and as a result receive errors will continue to occur. remark n = 0, 1 chapter 10 serial interface function user?s manual u13850ej4v0um 331 10.4.4 standby function (1) operation in halt mode serial transfer operations are performed normally. (2) operation in stop and idle modes (a) when internal clock is selected as serial clock the operations of asynchronous serial interface mode register n (asimn), transmit shift register n (txsn), and receive buffer register n (rxbn) are stopped and their values immediately before the clock stopped are hold. the txdn pin output holds the data immediately before the clock is stopped (in stop mode) during transmission. when the clock is stopped during reception, the receive data until the clock stopped are stored and subsequent receive operation is stopped. reception resumes upon clock restart. (b) when external clock is selected as serial clock serial transfer operation is performed normally. chapter 10 serial interface function user?s manual u13850ej4v0um 332 10.5 3-wire variable-length serial i/o (csi4) csi4 has the following two operation modes. (1) operation stop mode this mode is used when serial transfers are not performed. (2) 3-wire variable-length serial i/o mode (msb/lsb first switchable) this mode transfers variable data of 8 to 16 bits via three lines: serial clock (sck4), serial output (so4), and serial input (si4). since the data can be transmitted and received simultaneously in the 3-wire variable-length serial i/o mode, the processing time of data transfer is shortened. msb and lsb can be switched for the first bit of data to be transferred in serial. the 3-wire variable-length serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. 10.5.1 configuration csi4 includes the following hardware. table 10-11. configuration of csi4 item configuration register variable-length serial i/o shift register 4 (sio4) control registers variable-length serial control register 4 (csim4) variable-length serial setting register 4 (csib4) baud rate generator source clock selection register 4 (brgcn4) baud rate generator output clock selection register 4 (brgck4) chapter 10 serial interface function user?s manual u13850ej4v0um 333 figure 10-47. block diagram of csi4 baud rate generator so4 si4 intcsi4 serial clock controller selector interrupt generator serial clock counter (8-/16-bit switchable) variable-length i/o shift register 4 (8-/16-bit) sck4 direction controller internal bus (1) variable-length serial i/o shift register 4 (sio4) sio4 is a 16-bit variable register that performs parallel-serial conversion and transmit/receive (shift operations) synchronized with the serial clock. sio4 is set by a 16-bit memory manipulation instruction. the serial operation starts when data is written to or read from sio4, while the bit 7 (csie4) of variable-length serial control register 4 (csim4) is 1. when transmitting, data written to sio4 is output via the serial output (so4). when receiving, data is read from the serial input (si4) and written to sio4. reset input clears sio4 to 0000h. caution do not execute sio4 access except for the access that becomes the transfer start trigger during transfer operations (read is disabled when mode4 = 0 and write is disabled when mode4 = 1). figure 10-48. variable-length serial i/o shift register 4 (sio4) after reset: 0000h r/w address: fffff2e0h 1514131211109876543210 sio4 chapter 10 serial interface function user?s manual u13850ej4v0um 334 when the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether msb or lsb is set for the first transfer bit. any data can be set to the unused higher bits, however, in this case the received data after a serial transfer operation becomes 0. figure 10-49. when transfer bit length other than 16 bits is set (a) when transfer bit length is 10 bits and msb first (b) when transfer bit length is 12 bits and lsb first si4 so4 15 10 9 0 fixed to 0 si4 so4 fixed to 0 15 12 11 0 chapter 10 serial interface function user?s manual u13850ej4v0um 335 10.5.2 csi4 control registers csi4 uses the following type of registers for control functions. ? variable-length serial control register 4 (csim4) ? variable-length serial setting register 4 (csib4) ? baud rate generator source clock selection register 4 (brgcn4) ? baud rate generator output clock selection register 4 (brgck4) (1) variable-length serial control register 4 (csim4) this register is used to enable or disable serial interface channel 4?s serial clock, operation modes, and specific operations. csim4 can be set by an 8-/1-bit memory manipulation instruction. reset input clears csim4 to 00h. figure 10-50. variable-length serial control register 4 (csim4) after reset: 00h r/w address: fffff2e2h <7>6543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 transfer operation mode flag mode4 operation mode transfer start trigger so4 output 0 transmit/receive mode sio4 write normal output 1 receive-only mode sio4 read port function scl4 clock selection 0 external clock input (sck4) 1 brg (baud rate generator) notes 1. when csie4 = 0 (sio4 operation disabled status), the port function is available for the si4, so4, and sck4 pins. 2. when csie4 = 1 (sio4 operation enable status), the port function is available only for the si4 pin when using the transmit function only and to so4 pin when using the receive function. chapter 10 serial interface function user?s manual u13850ej4v0um 336 (2) variable-length serial setting register 4 (csib4) csib4 is used to set the operation format of the serial interface channel 4. the bit length of a variable register is set by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4. data is transferred msb first while bit 4 (dir) is 1, and is transferred lsb first while dir is 0. csib4 can be set by an 8-/1-bit memory manipulation instruction. reset input clears csib4 to 00h. figure 10-51. variable-length serial setting register 4 (csib4) after reset: 00h r/w address: fffff2e4h 7 <6> <5> <4> 3 2 1 0 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1 msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited chapter 10 serial interface function user?s manual u13850ej4v0um 337 (3) baud rate generator source clock selection register 4 (brgcn4) brgcn4 can be set by an 8-bit memory manipulation instruction. reset input clears brgcn4 to 00h. figure 10-52. baud rate generator source clock selection register 4 (brgcn4) after reset: 00h r/w address: fffff2e6h 76543210 brgcn4 0 0 0 0 0 brgn2 brgn1 brgn0 brgn2 brgn1 brgn0 source clock (f sck )n 000f xx 0 001f xx /2 1 010f xx /4 2 011f xx /8 3 100f xx /16 4 101f xx /32 5 110f xx /64 6 111f xx /128 7 chapter 10 serial interface function user?s manual u13850ej4v0um 338 (4) baud rate generator output clock selection register 4 (brgck4) brgck4 is set by an 8-bit memory manipulation instruction. reset input sets brgck4 to 7fh. figure 10-53. baud rate generator output clock selection register 4 (brgck4) after reset: 7fh r/w address: fffff2e8h 76543210 brgck4 0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 baud rate output clock k 0000000setting prohibited 0 0000001f sck /2 1 0000010f sck /4 2 0103011f sck /6 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1111110f sck /252 126 1111111f sck /254 127 the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. chapter 10 serial interface function user?s manual u13850ej4v0um 339 10.5.3 operations csi4 has the following two operation modes. ? operation stop mode ? 3-wire variable-length serial i/o mode (1) operation stop mode in this mode serial transfers are not performed and therefore power consumption can be reduced. when in operation stop mode, si4, so4, and sck4 can be used as normal i/o ports. (a) register settings operation stop mode is set via csie4 bit of variable-length serial control register 4 (csim4). while csie4 = 0 (sio4 operation stop state), the pins connected to si4, so4, or sck4 function as port pins. figure 10-54. csim4 setting (operation stop mode) after reset: 00h r/w address: fffff2e2h 76543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 0 operation disabled clear port function chapter 10 serial interface function user?s manual u13850ej4v0um 340 (2) 3-wire variable-length serial i/o mode the 3-wire variable-length serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck4), serial output line (so4), and serial input line (si4). (a) register settings the 3-wire variable-length serial i/o mode is set via variable-length serial control register 4 (csim4). figure 10-55. csim4 setting (3-wire variable-length serial i/o mode) after reset: 00h r/w address: fffff2e2h 76543210 csim4csie40000mode40scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 1 operation enabled count operation enabled serial function + port function transfer operation mode flag mode4 operation mode transfer start trigger so4 output 0 transmit/receive mode write to sio4 normal output 1 receive-only mode read from sio4 port function scl4 clock selection 0 external clock input (sck4) 1 brg (baud rate generator) chapter 10 serial interface function user?s manual u13850ej4v0um 341 the bit length of a variable-length register is set by setting bits 3 to 0 (bsel3 to bsel0) of csib4. data is transferred msb first while bit 4 (dir) is 1, and is transferred lsb first while dir is 0. figure 10-56. csib4 setting (3-wire variable-length serial i/o mode) after reset: 00h r/w address: fffff2e4h 7 <6> <5> <4> 3 2 1 0 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited chapter 10 serial interface function user?s manual u13850ej4v0um 342 (b) communication operations in the 3-wire variable-length serial i/o mode, data is transmitted and received in 8 to 16-bit units, and is specified by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4 (csib4). each bit of data is transmitted or received in synchronization with the serial clock. after transfer of all bits is completed, sic4 stops operation automatically and the interrupt request flag (intcsi4) is set. bits 6 and 5 (cmode and dmode) of variable-length serial setting register 4 (csib4) can change the attribute of the serial clock (sck4) and the phases of serial data (si4 and so4). figure 10-57. timing of 3-wire variable-length serial i/o mode sck4 (cmode = 0) sio4 (write) so4 (dmode = 1) intcsi4 sck4 (cmode = 1) so4 (dmode = 0) remark an arrow shows the si4 data fetch timing. when cmode = 0, the serial clock (sck4) stops at the high level during the operation stop, and outputs the low level during a data transfer operation. when cmode = 1, on the other hand, sck4 stops at the low level during the operation stop and outputs the high level during a data transfer operation. the phases of the so4 output timing and the s14 fetch timing can be shifted half a clock by setting dmode. however, the interrupt signal (intcsi4) is generated at the final edge of the serial clock (sck4), regardless the setting of csib4. chapter 10 serial interface function user?s manual u13850ej4v0um 343 (c) transfer start a serial transfer becomes possible when the following two conditions have been satisfied. ? the sio4 operation control bit (csie4) = 1 ? after a serial transfer, the internal serial clock is stopped. serial transfer starts when the following operation is performed after the above two conditions have been satisfied. ? transmit/transmit and receive mode (mode4 = 0) transfer starts when writing to sio4. ? receive-only mode transfer starts when reading from sio4. caution after data has been written to sio4, transfer will not start even if the csie4 bit value is set to ?1?. completion of the final-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsi4). figure 10-58. timing of 3-wire variable-length serial i/o mode (when csib4 = 08h) sck4 (cmode = 0) si4 intcsi4 12345678 transfer end so4 (dmode = 0) msb lsb msb lsb remark csib4 = 08h (cmode = 0, dmode = 0, dir = 0, bsel3 to bsel0 = 1000) user?s manual u13850ej4v0um 344 chapter 11 a/d converter 11.1 function the a/d converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ani0 to ani11). the v850/sb1 and v850/sb2 support the low power consumption mode by low-speed conversion. (1) hardware start conversion is started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 1 (adm1). one analog input channel is selected from ani0 to ani11, and a/d conversion is performed. if a/d conversion has been started by means of a hardware start, conversion stops once it has been completed, and an interrupt request (intad) is generated. if conversion has been started by means of a software start, conversion is performed repeatedly. each time conversion has been completed, intad is generated. chapter 11 a/d converter user?s manual u13850ej4v0um 345 the block diagram is shown below. figure 11-1. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 av ref av ss intad 4 ads3 ads2 ads1 ads0 adcs trg fr2 fr1 fr0 ega1 ega0 adps selector sample & hold circuit av ss voltage comparator tap selector adtrg edge detector controller a/d conversion result register (adcr) trigger enable analog input channel specification register (ads) a/d converter mode register 1 (adm1) internal bus iead a/d converter mode register 2 (adm2) successive approximation register (sar) av dd chapter 11 a/d converter user?s manual u13850ej4v0um 346 11.2 configuration the a/d converter includes the following hardware. table 11-1. configuration of a/d converter item configuration analog input 12 channels (ani0 to ani11) registers successive approximation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read control registers a/d converter mode register 1 (adm1) a/d converter mode register 2 (adm2) analog input channel specification register (ads) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (msb). when the comparison result has settled down to the least significant bit (lsb) (i.e., when the a/d conversion has been completed), the contents of the sar are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) each time a/d conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register. the higher 10 bits of this register holds the result of the a/d conversion (the lower 6 bits are fixed to 0). this register is read using a 16-bit memory manipulation instruction. reset input sets adcr to 0000h. when using only higher 8 bits of the result of the a/d conversion, adcrh is read using an 8-bit memory manipulation instruction. reset input sets adcrh to 00h. caution a write operation to a/d converter mode register 1 (adm1) and analog input channel specification register (ads) may cause the adcr contents to be undefined. after the conversion, read out the conversion result before the write operation to adm1 and ads is performed. correct conversion results may not be read if the timing is other than the above. (3) sample & hold circuit the sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) series resistor string the series resistor string is connected between av ref and av ss and generates a voltage for comparison with the analog input signal. chapter 11 a/d converter user?s manual u13850ej4v0um 347 (6) ani0 to ani11 pins these are analog input pins for the 12 channels of the a/d converter, and are used to input the analog signals to be converted into digital signals. pins other than ones selected as analog input with the analog input channel specification register (ads) can be used as input ports. caution make sure that the voltages input to ani0 to ani11 do not exceed the rated values. if a voltage higher than av ref or lower than av ss (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. (7) av ref pin this pin inputs a reference voltage to the a/d converter. the signals input to the ani0 to ani11 pins are converted into digital signals based on the voltage applied across av ref and av ss . (8) av ss pin this is the ground pin of the a/d converter. always keep the potential at this pin the same as that at the v ss pin even when the a/d converter is not in use. (9) av dd pin this is the analog power supply pin of the a/d converter. always keep the potential at this pin the same as that at the v dd pin even when the a/d converter is not in use. chapter 11 a/d converter user?s manual u13850ej4v0um 348 11.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode register 1 (adm1) ? analog input channel specification register (ads) ? a/d converter mode register 2 (adm2) (1) a/d converter mode register 1 (adm1) this register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. adm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears adm1 to 00h. figure 11-2. a/d converter mode register 1 (adm1) (1/2) after reset: 00h r/w address: fffff3c0h <7><6>54321<0> adm1 adcs trg fr2 fr1 fr0 ega1 ega0 adps adcs a/d conversion control 0 stops conversion 1 enables conversion trg software start or hardware start selection 0 software start 1 hardware start chapter 11 a/d converter user?s manual u13850ej4v0um 349 figure 11-2. a/d converter mode register 1 (adm1) (2/2) after reset: 00h r/w address: fffff3c0h <7><6>54321<0> adm1 adcs trg fr2 fr1 fr0 ega1 ega0 adps selection of conversion time f xx adps fr2 fr1 fr0 conversion time note 1 + stabilization time note 2 20 mhz note 3 12.58 mhz 0 0 0 0 168/f xx 8.4 s setting prohibited 0 0 0 1 120/f xx 6.0 s9.5 s 0 0 1 0 84/f xx setting prohibited 6.7 s 0 0 1 1 60/f xx setting prohibited setting prohibited 0 1 0 0 48/f xx setting prohibited setting prohibited 0 1 0 1 36/f xx setting prohibited setting prohibited 0 1 1 0 setting prohibited setting prohibited setting prohibited 0 1 1 1 12/f xx setting prohibited setting prohibited 1 0 0 0 168/f xx + 64/f xx 8.4 + 4.2 s setting prohibited 1 0 0 1 120/f xx + 60/f xx 6.0 + 3.0 s 9.5 + 4.8 s 1 0 1 0 84/f xx + 42/f xx setting prohibited 6.7 + 3.3 s 1 0 1 1 60/f xx + 30/f xx setting prohibited setting prohibited 1 1 0 0 48/f xx + 24/f xx setting prohibited setting prohibited 1 1 0 1 36/f xx + 18/f xx setting prohibited setting prohibited 1 1 1 0 setting prohibited setting prohibited setting prohibited 1 1 1 1 12/f xx + 6/f xx setting prohibited setting prohibited ega1 ega0 valid edge specification for external trigger signal 0 0 no edge detection 0 1 detects at falling edge 1 0 detects at rising edge 1 1 detects at both rising and falling edges adps comparator control when a/d conversion is stopped (adcs = 0) 0 comparator on 1 comparator off notes 1. conversion time (actual a/d conversion time). always set the time to 5 s conversion time 10 s. 2. stabilization time (setup time of a/d converter) each a/d conversion requires ?conversion time + stabilization time?. there is no stabilization time when adps = 0. 3. only for the v850/sb1. cautions 1. a/d converter cannot be used when the operation frequency is 2.4 to 3.6 mhz. 2. cut the current consumption by setting adps to 1 when adcs = 0. chapter 11 a/d converter user?s manual u13850ej4v0um 350 (2) analog input channel specification register (ads) ads specifies the port for inputting an analog voltage to be converted into a digital signal. ads is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears ads to 00h. figure 11-3. analog input channel specification register (ads) after reset: 00h r/w address: fffff3c2h 76543210 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel specification 0000ani0 0001ani1 0010ani2 0011ani3 0100ani4 0101ani5 0110ani6 0111ani7 1000ani8 1001ani9 1010ani10 1011ani11 other than above setting prohibited (3) a/d converter mode register 2 (adm2) adm2 specifies connection/disconnection of av dd and av ref . adm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears adm2 to 00h. figure 11-4. a/d converter mode register 2 (adm2) after reset: 00h r/w address: fffff3c8h 7654321<0> adm2 0 0 0 0 0 0 0 iead iead a/d current cut control 0 cut between av dd and av ref 1 connect between av dd and av ref chapter 11 a/d converter user?s manual u13850ej4v0um 351 11.4 operation 11.4.1 basic operation <1> select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ads). <2> the sample & hold circuit samples the voltage input to the selected analog input channel. <3> after sampling for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until it has been converted into a digital signal. <4> set the bit 9 of the successive approximation register (sar). the tap selector sets the voltage tap of the series resistor string to (1/2) av ref . <5> the voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is greater than (1/2) av ref , the msb of the sar remains set. if the analog input voltage is less than (1/2) av ref , the msb is reset. <6> next, bit 8 of the sar is automatically set, and the analog input voltage is compared again. depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows: ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the analog input voltage is compared with one of these voltage taps, and bit 8 of the sar is manipulated as follows depending on the result of the comparison. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage voltage tap: bit 8 = 0 <7> the above steps are repeated until the bit 0 of the sar has been manipulated. <8> when comparison of all the 10 bits of the sar has been completed, the valid digital value remains in the sar, and the value of the sar is transferred and latched to the a/d conversion result register (adcr). at the same time, an a/d conversion end interrupt request (intad) can be generated. caution the first conversion value immediately after starting the a/d conversion may not satisfy the ratings. chapter 11 a/d converter user?s manual u13850ej4v0um 352 figure 11-5. basic operation of a/d converter sar adcr intad conversion time sampling time sampling operation of a/d converter a/d conversion undefined conversion result conversion result a/d conversion is successively executed until bit 7 (adcs) of a/d converter mode register 1 (adm1) is reset to 0 by software. if adm1 and the analog input channel specification register (ads) are written during a/d conversion, the conversion is initialized. if adcs is set to 1 at this time, conversion is started from the beginning. reset input sets the a/d conversion result register (adcr) to 0000h. chapter 11 a/d converter user?s manual u13850ej4v0um 353 11.4.2 input voltage and conversion result the analog voltages input to the analog input pins (ani0 to ani11) and the result of the a/d conversion (contents of the a/d conversion result register (adcr)) are related as follows: adcr = int( 1024 + 0.5) or, (adcr ? 0.5) v in < (adcr + 0.5) int ( ): function that returns integer of value in ( ) v in : analog input voltage av ref :av ref pin voltage adcr: value of the a/d conversion result register (adcr) the relationship between the analog input voltage and a/d conversion result is shown below. figure 11-6. relationship between analog input voltage and a/d conversion result 113253 2043 1022 20451023 2047 1 2048 1024 20481024 2048 1024 2048 1024 20481024 2048 0 1 2 3 1021 1022 1023 a/d conversion result (adcr) input voltage/av ref v in av ref av ref 1024 av ref 1024 chapter 11 a/d converter user?s manual u13850ej4v0um 354 11.4.3 a/d converter operation mode in this mode one of the analog input channels ani0 to ani11 is selected by the analog input channel specification register (ads) and a/d conversion is executed. the a/d conversion can be started in the following two ways: ? hardware start: started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified) ? software start: started by setting a/d converter mode register 1 (adm1) the result of the a/d conversion is stored in the a/d conversion result register (adcr) and an interrupt request signal (intad) is generated at the same time. (1) a/d conversion by hardware start a/d conversion is on standby if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1. when an external trigger signal is input, the a/d converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads) into a digital signal. when the a/d conversion has been completed, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/d conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. if data with adcs set to 1 is written to adm during a/d conversion, the conversion under execution is stopped, and the a/d converter stands by until a new external trigger signal is input. if the external trigger signal is input, a/d conversion is executed again from the beginning. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 11-7. a/d conversion by hardware start (with falling edge specified) rewriting ads adcs = 1, trg = 1 rewriting ads adcs = 1, trg = 1 a/d conversion adcr intad anin standby status standby status standby status anin anin anim anim anim anin anin anin anim anim external trigger input signal remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 chapter 11 a/d converter user?s manual u13850ej4v0um 355 (2) a/d conversion by software start if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1, the a/d converter starts converting the voltage applied to an analog input pin specified by the analog input channel specification register (ads) into a digital signal. when the a/d conversion has been completed, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once a/d conversion has been started and completed, the next conversion is started immediately. a/d conversion is repeated until new data is written to ads. if ads is rewritten during a/d conversion, the conversion under execution is stopped, and conversion of the newly selected analog input channel is started. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 11-8. a/d conversion by software start rewriting ads adcs = 1, trg = 0 rewriting ads adcs = 1, trg = 0 adcs = 0 a/d conversion adcr intad anin anin anin anim anim anin anin anim ? ? ? ? ? conversion stopped. conversion result does not remain. stopped remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 chapter 11 a/d converter user?s manual u13850ej4v0um 356 11.5 low power consumption mode the v850/sb1 and v850/sb2 feature a function that can cut or connect the current between av dd and av ref . switching can be performed by setting a/d converter mode register 2 (adm2). when av dd = av ref , and when the system does not require high precision, current consumption can be reduced by connecting av dd and av ref in the normal mode or disconnecting them in standby mode after opening the av ref pin. the conversion precision of the reference voltage is reduced since the reference voltage is supplied from av dd via a switch. when the a/d converter is not used, cut the tap selector that reduces the current when a/d conversion is stopped (adcs = 0), and the supply voltage (av dd ), in order to reduce the current consumption. ? set the adps bit of a/d converter mode register 1 (adm1) to ?1?. ? clear the iead bit of a/d converter mode register 2 (adm2) to ?0?. when the adps bit is cleared to ?0? (comparator on) again, a stabilization time (5 s max.) is required until the a/d converter is started. therefore, use software to ensure that a wait time of 5 s elapses. 11.6 cautions (1) current consumption in standby mode the a/d converter stops operation in the stop and idle modes (operable in the halt mode). at this time, the current consumption of the a/d converter can be reduced by stopping the conversion (by resetting the bit 7 (adcs) of a/d converter mode register 1 (adm1) to 0). to reduce the current consumption in the stop and idle modes, set the av ref potential in the user circuit to the same value (0 v) as the av ss potential. (2) input range of ani0 to ani11 keep the input voltage of the ani0 to ani11 pins to within the rated range. if a voltage greater than av ref or lower than av ss (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the channel becomes undefined. moreover, the values of the other channels may also be affected. (3) conflict <1> conflict between writing a/d conversion result register (adcr) and reading adcr at end of conversion reading adcr takes precedence. after adcr has been read, a new conversion result is written to adcr. <2> conflict between writing adcr and external trigger signal input at end of conversion the external trigger signal is not input during a/d conversion. therefore, the external trigger signal is not accepted during writing of adcr. <3> conflict between writing of adcr and writing a/d converter mode register 1 (adm1) or analog input channel specification register (ads) when adm1 or ads write is performed immediately after adcr write following a/d conversion end, the conversion result is written to the adcr register, but the timing is such that intad is not generated. chapter 11 a/d converter user?s manual u13850ej4v0um 357 (4) countermeasures against noise to keep the resolution of 10 bits, prevent noise from being superimposed on the av ref and ani0 to ani11 pins. the higher the output impedance of the analog input source, the heavier the influence of noise. to lower noise, connecting an external capacitor as shown in figure 11-9 is recommended. figure 11-9. handling of analog input pin av ref v dd v ss av dd av ss reference voltage input clamp with diode with a low v f (0.3 v max.) if noise higher than av ref or lower than av ss may be generated. c = 100 to 1000 pf (5) ani0 to ani11 the analog input (ani0 to ani11) pins are multiplexed with port pins. to execute a/d conversion with any of ani0 to ani11 selected, do not execute an instruction that inputs data to the port during conversion; otherwise, the resolution may drop. if a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected a/d conversion result may not be obtained because of the influence of coupling noise. therefore, do not apply a pulse to the adjacent pins. (6) input impedance of av ref pin a series resistor string is connected between the av ref and av ss pins. if the output impedance of the reference voltage source is too high, the series resistor string between the av ref and av ss pins are connected in series, increasing the error of the reference voltage. chapter 11 a/d converter user?s manual u13850ej4v0um 358 (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the analog input channel specification register (ads) are changed. if the analog input pin is changed during conversion, therefore, the result of the a/d conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ads is rewritten. if adif is read immediately after ads has been rewritten, it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet. when stopping a/d conversion and then resuming, clear adif before resuming conversion. figure 11-10. a/d conversion end interrupt generation timing rewriting ads (anin conversion starts) rewriting ads (anim conversion starts) adif is set but conversion of anim is not completed. a/d conversion adcr intad anin anin anim anim anim anin anin anim remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11 chapter 11 a/d converter user?s manual u13850ej4v0um 359 (8) av dd pin the av dd pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ani0 to ani11. even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the v dd pin to the av dd pin as shown in figure 11-11. figure 11-11. handling of av dd pin av ref v dd v ss av dd av ss main power supply back-up capacitor (9) reading out a/d converter result register (adcr) a write operation to a/d converter mode register 1 (adm1) and the analog input channel specification register (ads) may cause the adcr contents to be undefined. after the conversion, read out the conversion result before the write operation to adm1 and ads is performed. incorrect conversion results may be read out at timings other than the above. user?s manual u13850ej4v0um 360 chapter 12 dma functions 12.1 functions the dma (direct memory access) controller transfers data between memory and peripheral i/os based on dma requests sent from on-chip peripheral hardware (such as the serial interface, timer, or a/d converter). this product includes six independent dma channels that can transfer data in 8-bit and 16-bit units. the maximum number of transfers is 256 (when transferring data in 8-bit units). after a dma transfer has occurred a specified number of times, dma transfer completion interrupt (intdma0 to intdma5) requests are output individually from the various channels. the priority levels of the dma channels are fixed as follows for simultaneous generation of multiple dma transfer requests. dma0 > dma1 > dma2 > dma3 > dma4 > dma5 12.2 transfer completion interrupt request after a dma transfer has occurred a specified number of times and the tcn bit in the corresponding dma channel control register (dchcn) has been set to 1, a dma transfer completion interrupt request (intdma0 to intdma5) occurs on each channel in relation to the interrupt controller. 12.3 control registers 12.3.1 dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) these registers are used to set the peripheral i/o register?s address for dma channel n. these registers are can be read/written in 16-bit units. figure 12-1. format of dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) after reset: undefined r/w address: dioa0 fffff180h dioa3 fffff1b0h dioa1 fffff190h dioa4 fffff1c0h dioa2 fffff1a0h dioa5 fffff100h 15 14 13 12 11 10 9 1 0 dioan 000000 ioan9 to ioan1 0 (n = 0 to 5) caution the following peripheral i/o registers must not be set. p4, p5, p6, p9, p11, pm4, pm5, pm6, pm9, pm11, mm, dwc, bcc, syc, psc, pcc, sys, prcmd, dioan, dran, dbcn, dchcn, corcn, corrq, coradn, interrupt control register (xxicn), ispr chapter 12 dma functions user?s manual u13850ej4v0um 361 12.3.2 dma internal ram address registers 0 to 5 (dra0 to dra5) these registers set dma channel n internal ram addresses (n = 0 to 5). since each product has a different internal ram capacity, the internal ram areas that are usable for dma differ depending on the product. the internal ram areas that can be set in dran registers for each product are shown below. table 12-1. internal ram area usable in dma product internal ram capacity ram size usable in dma ram area usable in dma v850/sb1 pd703031a, 703031ay v850/sb2 pd703034a, 703034ay 12 kb 12 kb xxffc000h to xxffefffh v850/sb1 pd703033a, 703033ay, 70f3033a, 70f3033ay v850/sb2 pd703035a, 703035ay, 70f3035a, 70f3035ay 16 kb 16 kb xxffb000h to xxffefffh v850/sb1 pd703030a, 703030ay v850/sb2 pd703036a, 703036ay 20 kb 12 kb xxffa000h to xxffbfffh, xxffe000h to xxffefffh v850/sb1 pd703032a, 703032ay, 70f3032a, 70f3032ay v850/sb2 pd703037a, 703037ay, 70f3037a, 70f3037ay 24 kb 16 kb xxff9000h to xxffbfffh, xxffe000h to xxffefffh an address is incremented after each transfer is completed, when the dadn bit of the dchdn register is 0. the incrementation value is ?1? during 8-bit transfers and ?2? during 16-bit transfers (n = 0 to 5). these registers are can be read/written in 16-bit units. figure 12-2. format of dma internal ram address registers 0 to 5 (dra0 to dra5) after reset: undefined r/w address: dra0 fffff182h dra3 fffff1b2h dra1 fffff192h dra4 fffff1c2h dra2 fffff1a2h dra5 fffff1d2h 15 14 13 0 dran 00 ran13 to ran0 (n = 0 to 5) chapter 12 dma functions user?s manual u13850ej4v0um 362 (1) correspondence between dran setting value and internal ram area (a) v850/sb1 ( pd703031a, 703031ay), v850/sb2 ( pd703034a, 703034ay) set the dran register to a value in the range of 0000h to 2fffh (n = 0 to 5). setting is prohibited for values between 3000h and 3fffh. figure 12-3. correspondence between dran setting value and internal ram (12 kb) xxffffffh xxffc000h xxffbfffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (2fffh) (0000h) 12 kb (usable for dma) cautions 1. do not set odd addresses for 16-bit transfer (dchcn register dsn = 1). 2. while the increment function is being used (dchcn register ddadn = 0), if the dran register value is set to 2fffh, it will be incremented to 3000h, and will thus become a setting-prohibited value. remark the dran register setting values are in the parentheses. chapter 12 dma functions user?s manual u13850ej4v0um 363 (b) v850/sb1 ( pd703033a, 703033ay, 70f3033a, 70f3033ay) v850/sb2 ( pd703035a, 703035ay, 70f3035a, 70f3035ay) set the dran register to a value in the range of 000h to 2fffh or 3000h to 3fffh (n = 0 to 5). figure 12-4. correspondence between dran setting value and internal ram (16 kb) xxffffffh xxffb000h xxffafffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (2fffh) (3000h) (3fffh) xxffc000h xxffbfffh (0000h) 16 kb (usable for dma) caution do not set odd addresses for 16-bit transfer (dchcn register dsn =1). remark the dran register setting values is are in the parentheses. chapter 12 dma functions user?s manual u13850ej4v0um 364 (c) v850/sb1 ( pd703030a, 703030ay), v850/sb2 ( pd703036a, 703036ay) set the dran register to a value in the range of 0000h to 0fffh or 2000h to 3fffh (n = 0 to 5). setting is prohibited for values between 1000h to 1fffh. figure 12-5. correspondence between dran setting value and internal ram (20 kb) xxffffffh xxffa000h xxff9fffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (0fffh) (2000h) (0000h) (3fffh) xxffc000h xxffbfffh 8 kb (usable for dma) 4 kb (usable for dma) xxffe000h xxffdfffh cautions 1. do not set odd addresses for 16-bit transfer (dchcn register dsn = 1). 2. while the increment function is being used (dchcn register ddadn = 0), if the dran register value is set to 0fffh, it will be incremented to 1000h, and will thus become a setting-prohibited value. remark the dran register setting values are in the parentheses. chapter 12 dma functions user?s manual u13850ej4v0um 365 (d) v850/sb1 ( pd703032a, 703032ay, 70f3032a, 70f3032ay) v850/sb2 ( pd703037a, 703037ay, 70f3037a, 70f3037ay) set the dran register to a value in the range of 0000h to 0fffh or 1000h to 3fffh (n = 0 to 5). figure 12-6. correspondence between dran setting value and internal ram (24 kb) xxffffffh xxff9000h xxff8fffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (0fffh) (1000h) (0000h) (3fffh) xxffc000h xxffbfffh 12 kb (usable for dma) 4 kb (usable for dma) xxffe000h xxffdfffh caution do not set odd addresses for 16-bit transfer (dchcn register dsn =1). remark the dran register setting values are in the parentheses. chapter 12 dma functions user?s manual u13850ej4v0um 366 12.3.3 dma byte count registers 0 to 5 (dbc0 to dbc5) these are 8-bit registers that are used to set the number of transfers for dma channel n. the remaining number of transfers is retained during the dma transfers. a value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer. the transfers are ended when a borrow operation occurs. accordingly, ?number of transfers ? 1? should be set for byte (8-bit) transfers and ?(number of transfers ? 1) 2? should be set for 16-bit transfers. these registers are can be read/written in 8-bit units. figure 12-7. format of dma byte count registers 0 to 5 (dbc0 to dbc5) after reset: undefined r/w address: dbc0 fffff184h dbc3 fffff1b4h dbc1 fffff194h dbc4 fffff1c4h dbc2 fffff1a4h dbc5 fffff1d4h 76543210 dbcn bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 (n = 0 to 5) caution values set to bit 0 are ignored during 16-bit transfers. 12.3.4 dma start factor expansion register (dmas) this is an 8-bit register for expanding the factors that start dma. the dma start factor is decided according to the combination of ttypn1 and ttypn0 of the dchcn register. for setting bits dmas2 to dmas0, refer to 12.3.5 dma channel control registers 0 to 5 (dchc0 to dchc5) (n = 0 to 5). this register can be read/written in 8/1-bit units. figure 12-8. dma start factor expansion register (dmas) after reset: 00h r/w address: fffff38eh 76543210 dmas 0 0 0 0 0 dmas2 dmas1 dmas0 chapter 12 dma functions user?s manual u13850ej4v0um 367 12.3.5 dma channel control registers 0 to 5 (dchc0 to dchc5) these registers are used to control the dma transfer operation mode for dma channel n. these registers are can be read/written in 1-bit or 8-bit units. figure 12-9. format of dma channel control registers 0 to 5 (dchc0 to dchc5) (1/2) after reset: 00h r/w address: dchc0 fffff186h dchc3 fffff1b6h dchc1 fffff196h dchc4 fffff1c6h dchc2 fffff1a6h dchc5 fffff1d6h <7> 6 <5> 4 3 <2> <1> <0> dchcn tcn 0 ddadn ttypn1 ttypn0 tdirn dsn enn (n = 0 to 5) tcn dma transfer completed/not completed note 1 0not completed 1 completed ddadn internal ram address count direction control 0 increment 1 address is fixed channel n dmas2 dmas1 dmas0 ttypn1 ttypn0 dma transfer start factor setting 00 intcsi0/intiic0 note 2 0 1 intcsi1/intsr0 10intad 0xxx 1 1 inttm00 000 intcsi0/intiic0 note 2 1 0 0 intcsi1/intsr0 0 1 intst0 10intp0 1xx x 1 1 inttm10 000 intiic1 note 2 1 0 0 intcsi3/intsr1 01intp6 1 0 intie1 (v850/sb2 only) 2x x x 11intad 000 intiic1 note 2 1 0 0 intcsi3/intsr1 01intcsi2 1 0 intie1 (v850/sb2 only) 3 x xx 1 1 inttm4 chapter 12 dma functions user?s manual u13850ej4v0um 368 figure 12-9. format of dma channel control registers 0 to 5 (dchc0 to dchc5) (2/2) after reset: 00h r/w address: dchc0 fffff186h dchc3 fffff1b6h dchc1 fffff196h dchc4 fffff1c6h dchc2 fffff1a6h dchc5 fffff1d6h <7> 6 <5> 4 3 <2> <1> <0> dchcn tcn 0 ddadn ttypn1 ttypn0 tdirn dsn enn (n = 0 to 5) channel n dmas2 dmas1 dmas0 ttypn1 ttypn0 dma transfer start factor setting 0 0 intst1 01intcsi4 10intad 4xxx 1 1 inttm2 0 0 intcsi3/intsr1 01intcsi4 10intcsi2 5xxx 1 1 inttm6 tdirn transfer direction control between peripheral i/os and internal ram note 3 0 from internal ram to peripheral i/os 1 from peripheral i/os to internal ram dsn control of transfer data size for dma transfer note 3 0 8-bit transfer 1 16-bit transfer enn control of dma transfer enable/disable status note 4 0 disable 1 enable (reset to 0 after dma transfer is completed) notes 1. tcn (n = 0 to 5) is set to 1 when a specified number of transfers are completed, and is cleared to 0 when a write instruction is executed. 2. intiic0 and intiic1 are available only in the pd70303xay and 70f303way. 3. make sure that the transfer format conforms to the peripheral i/o register specifications (access- enabled data size, read/write, etc.) for the dma peripheral i/o address register (dioan). 4. after the specified number of transfer is completed, this bit is cleared to 0. user?s manual u13850ej4v0um 369 chapter 13 real-time output function (rto) 13.1 function the real-time output function transfers preset data to real-time output buffer registers (rtbl, rtbh), and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signals without jitter, it is suitable for controlling a stepping motor. the real-time output port can be set in port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 13-1. block diagram of rto internal bus output latch rtp7 rtp6 rtp5 rtp4 rtp3 rtp2 rtp1 rtp0 rtpoe rtpeg byte extr rtptrg output trigger controller inttm4 inttm5 real-time output port control register (rtpc) 4 real-time output buffer register, higher 4 bits (rtbh) real-time output buffer register, lower 4 bits (rtbl) real-time output port mode register (rtpm) chapter 13 real-time output function (rto) user?s manual u13850ej4v0um 370 13.2 configuration rto includes the following hardware. table 13-1. configuration of rto item configuration registers real-time output buffer registers (rtbl, rtbh) control registers real-time output port mode register (rtpm) real-time output port control register (rtpc) (1) real-time output buffer registers (rtbl, rtbh) rtbl and rtbh are 4-bit registers that hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area as shown in figure 13- 2. if an operation mode of 4 bits 2 channels is specified, data can be individually set to rtbl and rtbh. the data of both the registers can be read all at once by specifying the address of either of the registers. if an operation mode of 8 bits 1 channel is specified, 8-bit data can be set to both rtbl and rtbh respectively by writing the data to either of the registers. the data of both the registers can be read all at once by specifying the address of either of the registers. figure 13-2 shows the configuration of rtbl and rtbh, and table 13-2 shows the operation to be performed when rtbl and rtbh are manipulated. figure 13-2. configuration of real-time output buffer registers higher 4 bits lower 4 bits rtbl rtbh chapter 13 real-time output function (rto) user?s manual u13850ej4v0um 371 table 13-2. operation when real-time output buffer registers are manipulated read note 1 write note 2 operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl rtbh rtbl invalid rtbl 4 bits 2 channels rtbh rtbh rtbl rtbh invalid rtbl rtbh rtbl rtbh rtbl 8 bits 1 channel rtbh rtbh rtbl rtbh rtbl notes 1. only the bits set in the real-time output port mode (rtpm) can be read. if a bit set in the port mode is read, 0 is read. 2. set output data to rtbl and rtbh after setting the real-time output port until the real-time output trigger is generated. 13.3 rto control registers rto is controlled by using the following two types of registers. ? real-time output port mode register (rtpm) ? real-time output port control register (rtpc) (1) real-time output port mode register (rtpm) this register selects real-time output port mode or port mode in 1-bit units. rtpm is set by an 8-/1-bit memory manipulation instruction. reset input clears rtpm to 00h. figure 13-3. format of real-time output port mode register (rtpm) after reset: 00h r/w address: fffff3a4h 76543210 rtpm rtpm7 rtpm6 rtpm5 rtpm4 rtpm3 rtpm2 rtpm1 rtpm0 rtpmn selection of real-time output port (n = 0 to 7) 0 port mode 1 real-time output port mode cautions 1. set a port pin to the output mode when it is used as a real-time output port pin. 2. data cannot be set to the output latch for a port pin set as a real-time output port pin. to set an initial value, therefore, set the data to the output latch before setting the port pin to the real-time output port mode. chapter 13 real-time output function (rto) user?s manual u13850ej4v0um 372 (2) real-time output port control register (rtpc) this register sets the operation mode and output trigger of the real-time output port. the relationship between the operation mode and output trigger of the real-time output port is as shown in table 13- 3. rtpc is set by an 8-/1-bit memory manipulation instruction. reset input clears rtpc to 00h. figure 13-4. format of real-time output port control register (rtpc) after reset: 00h r/w address: fffff3a6h <7> <6> <5> <4> 3 2 1 0 rtpc rtpoe rtpeg byte extr 0 0 0 0 rtpoe control of operation of real-time output port 0 disables operation note 1 enables operation rtpeg valid edge of rtptrg 0 falling edge 1 rising edge byte operation mode of real-time output port 04 bits 2 channels 18 bits 1 channel extr control of real-time output by rtptrg signal 0 does not use rtptrg as real-time output trigger 1 uses rtptrg as real-time output trigger note rtp0 to rtp7 output 0 if the real-time output operation is disabled (rtpoe = 0). table 13-3. operation mode and output trigger of real-time output port byte extr operation mode rtbh port output rtbl port output 0 0 4 bits 2 channels inttm5 inttm4 1 inttm4 rtptrg 1 0 8 bits 1 channel inttm4 1 rtptrg chapter 13 real-time output function (rto) user?s manual u13850ej4v0um 373 13.4 operation if the real-time output operation is enabled by setting the bit 7 (rtpoe) of the real-time output port control register (rtpc) to 1, the data of the real-time output buffer registers (rtbh and rtbl) is transferred to the output latch in synchronization with the generation of the selected transmit trigger (set by extr and byte note ). of the transferred data, only the data of the bits specified in the real-time output mode by the real-time output port mode register (rtpm) is output from the bits of rtp0 to rtp7. the bits specified in the port mode by rtpm output 0. if the real-time output operation is disabled by clearing rtpoe to 0, rtp0 to rtp7 output 0 regardless of the setting of rtpm. note extr: bit 4 of the real-time output port control register (rtpc) byte: bit 5 of the real-time output port control register (rtpc) figure 13-5. example of operation timing of rto (when extr = 0, byte = 0) inttm5 (internal) inttm4 (internal) cpu operation rtbh rtbl rt output latch (h) rt output latch (l) a b a b a b a b d01 d02 d03 d04 d11 d12 d13 d14 d01 d02 d03 d04 d11 d12 d13 d14 a: software processing by interrupt request input to inttm5 (rtbh write) b: software processing by interrupt request input to inttm4 (rtbl write) chapter 13 real-time output function (rto) user?s manual u13850ej4v0um 374 13.5 usage (1) disable the real-time output operation. clear bit 7 (rtpoe) of the real-time output port control register (rtpc) to 0. (2) initialization ? set the initial value to the output latch. ? specify the real-time output port mode or port mode in 1-bit units. set the real-time output port mode register (rtpm). ? selects a trigger and valid edge. set bits 4, 5, and 6 (extr, byte, and rtpeg) of rtpc. ? set the initial value that is the same as the output latch to the real-time output buffer registers (rtbh and rtbl). (3) enable the real-time output operation. set rtpoe to 1. (4) set the output latch of ports (p100 to p107) to 0, and the next output to rtbh and rtbl until the selected transfer trigger is generated. (5) set the next real-time output value to rtbh and rtbl by interrupt servicing corresponding to the selected trigger. 13.6 cautions (1) before performing initialization, disable the real-time output operation by clearing bit 7 (rtpoe) of the real-time output port control register (rtpc) to 0. (2) once the real-time output operation is disabled (rtpoe = 0), be sure to set the initial value that is the same as the output latch to the real-time output buffer registers (rtbh and rtbl) before enabling the real-time output operation (rtpoe = 0 1). user?s manual u13850ej4v0um 375 chapter 14 port function 14.1 port configuration the v850/sb1 and v850/sb2 include 83 i/o port pins from ports 0 to 11 (12 ports are input only). there are three power supplies for the i/o buffers; av dd , bv dd , and ev dd , which are described below. table 14-1. pin i/o buffer power supplies power supply corresponding pins usable voltage range av dd port 7, port 8 4.5 v av dd 5.5 v bv dd port 4, port 5, port 6, port 9, clkout 3.0 v bv dd 5.5 v ev dd port 0, port 1, port 2, port 3, port 10, port 11, reset 3.0 v ev dd 5.5 v caution the electrical specifications in the case of 3.0 v to up to 4.0 v are different from those for 4.0 v to 5.5 v. 14.2 port pin function 14.2.1 port 0 port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). when using p00 to p04 as the nmi or intp0 to intp3 pins, noise is eliminated by the analog noise eliminator. when using p05 to p07 as the intp4/adtrg, intp5/rtptrg, and intp6 pins, noise is eliminated by the digital noise eliminator. figure 14-1. format of port 0 (p0) after reset: 00h r/w address: fffff000h 76543210 p0 p07 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0, 1) 0 outputs 0 1 outputs 1 remark in input mode: when the p0 register is read, the pin levels at that time are read. writing to p0 writes the values to that register. this does not affect the input pins. in output mode: when the p0 register is read, the p0 register?s values are read. writing to p0 writes the values to that register, and those values are immediately output. chapter 14 port function user?s manual u13850ej4v0um 376 port 0 includes the following alternate functions. table 14-2. port 0 alternate function pins pin name alternate function i/o pull note remark p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 analog noise elimination p05 intp4/adtrg p06 intp5/rtptrg port 0 p07 intp6 i/o yes digital noise elimination note software pull-up function (1) function of p0 pins port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 0 mode register (pm0). in output mode, the values set to each bit are output to the port 0 register (p0). when using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for nmi requests). when using this port in input mode, the pin statuses can be read by reading the p0 register. also, the p0 register (output latch) values can be read by reading the p0 register while in output mode. the valid edge of nmi and intp0 to intp6 are specified via rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0). a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 0 (pu0). when a reset is input, the settings are initialized to input mode. also, the valid edge of each interrupt request becomes invalid (nmi and intp0 to intp6 do not function immediately after reset). (2) noise elimination (a) elimination of noise from nmi and intp0 to intp3 pins an on-chip noise eliminator uses analog delay to eliminate noise. consequently, if a signal having a constant level is input for longer than a specified time to these pins, it is detected as a valid edge. such edge detection occurs after the specified amount of time. (b) elimination of noise from intp4 to intp6, adtrg, and rtptrg pins a digital noise eliminator is provided on chip. this circuit uses digital sampling. a pin?s input level is detected using a sampling clock (f xx ), and noise elimination is performed for the intp4, intp5, adtrg, and rtptrg pins if the same level is not detected three times consecutively. the noise-elimination width can be changed for the intp6 pin (see 5.3.8 (3) noise elimination of intp6 pin ). chapter 14 port function user?s manual u13850ej4v0um 377 cautions 1. if the input pulse width is 2 or 3 clock, whether it will be detected as a valid edge or eliminated as noise is undermined. 2. to ensure correct detection of pulses as pulses, constant-level input is required for 3 clocks or more. 3. if noise is occurring in synchronization with the sampling clock, it may not be recognized as noise. in such cases, attach a filter to the input pins to eliminate the noise. 4. noise elimination is not performed when these pins are used as an ordinary input port. (3) control registers (a) port 0 mode register (pm0) pm0 can be read/written in 8-/1-bit units. figure 14-2. port 0 mode register (pm0) after reset: ffh r/w address: fffff020h 76543210 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 0 (pu0) pu0 can be read/written in 8-/1-bit units. figure 14-3. pull-up resistor option register 0 (pu0) after reset: 00h r/w address: fffff080h 76543210 pu0 pu07 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu0n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect chapter 14 port function user?s manual u13850ej4v0um 378 (c) rising edge specification register 0 (egp0) egp0 can be read/written in 8-/1-bit units. figure 14-4. rising edge specification register 0 (egp0) after reset: 00h r/w address: fffff0c0h <7> <6> <5> <4> <3> <2> <1> <0> egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n control of rising edge detection (n = 0 to 7) 0 interrupt request signal does not occur at rising edge 1 interrupt request signal occurs at rising edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins (d) falling edge specification register 0 (egn0) egn0 can be read/written in 8-/1-bit units. figure 14-5. falling edge specification register 0 (egn0) after reset: 00h r/w address: fffff0c2h <7> <6> <5> <4> <3> <2> <1> <0> egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n control of falling edge detection (n = 0 to 7) 0 interrupt request signal does not occur at falling edge 1 interrupt request signal occurs at falling edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins chapter 14 port function user?s manual u13850ej4v0um 379 (4) block diagram (port 0) figure 14-6. block diagram of p00 to p07 p-ch wr pm wr port rd wr pu v dd p00/nmi p01/intp0 p02/intp1 p03/intp2 p04/intp3 p05/intp4/adtrg p06/intp5/rtptrg p07/intp6 selector pu0n pu0 output latch (p0n) pm0n pm0 internal bus remarks 1. pu0: pull-up resistor option register 0 pm0: port 0 mode register rd: port 0 read signal wr: port 0 write signal 2. n = 0 to 7 chapter 14 port function user?s manual u13850ej4v0um 380 14.2.2 port 1 port 1 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). bits 0, 1, 2, 4, and 5 are selectable as normal outputs or n-ch open-drain outputs. figure 14-7. port 1 (p1) after reset: 00h r/w address: fffff002h 76543210 p1 0 0 p15 p14 p13 p12 p11 p10 p1n control of output data (in output mode) (n = 0 to 5) 0 outputs 0 1 outputs 1 remark in input mode: when the p1 register is read, the pin levels at that time are read. writing to p1 writes the values to that register. this does not affect the input pins. in output mode: when the p1 register is read, the p1 register?s values are read. writing to p1 writes the values to that register, and those values are immediately output. port 1 includes the following alternate functions. sda0 and scl0 pins are available only in the pd70303xay and 70f303way. table 14-3. port 1 alternate function pins pin name alternate function i/o pull note remark port 1 p10 si0/sda0 i/o yes selectable as n-ch open-drain output p11 so0 p12 sck0/scl0 p13 si1/rxd0 ? p14 so1/txd0 selectable as n-ch open-drain output p15 sck1/asck0 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 381 (1) function of p1 pins port 1 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 1 mode register (pm1). in output mode, the values set to each bit are output to the port 1 register (p1). the port 1 function register (pf1) can be used to specify whether p10 to p12, p14, and p15 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading the p1 register. also, the p1 register (output latch) values can be read by reading the p1 register while in output mode. a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 1 (pu1). clear the p1 and pm1 registers to 0 when using alternate-function pins as outputs. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 1 mode register (pm1) pm1 can be read/written in 8-/1-bit units. figure 14-8. port 1 mode register (pm1) after reset: 3fh r/w address: fffff022h 76543210 pm1 0 0 pm15 pm14 pm13 pm12 pm11 pm10 pm1n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode (b) pull-up resistor option register 1 (pu1) pu1 can be read/written in 8-/1-bit units. figure 14-9. pull-up resistor option register 1 (pu1) after reset: 00h r/w address: fffff082h 76543210 pu1 0 0 pu15 pu14 pu13 pu12 pu11 pu10 pu1n control of on-chip pull-up resistor connection (n = 0 to 5) 0 do not connect 1 connect chapter 14 port function user?s manual u13850ej4v0um 382 (c) port 1 function register (pf1) pf1 can be read/written in 8-/1-bit units. figure 14-10. port 1 function register (pf1) after reset: 00h r/w address: fffff0a2h 76543210 pf1 0 0 pf15 pf14 0 note pf12 pf11 pf10 pf1n control of normal output/n-ch open-drain output (n = 0 to 2, 4, 5) 0 normal output 1 n-ch open-drain output note bit 3 is fixed as a normal output. (3) block diagram (port 1) figure 14-11. block diagram of p10 to p12, p14, and p15 p-ch wr pm wr pf wr port rd wr pu v dd v dd selector pf1n pf1 pm1n pm1 pu1n pu1 p-ch n-ch internal bus output latch (p1n) alternate function p10/si0/sda0 note p11/so0 p12/sck0/scl0 note p14/so1/txd0 p15/sck1/asck0 note the sda0, scl0 pins apply only to the pd70303xay and 70f303way. remarks 1. pu1: pull-up resistor option register 1 pf1: port 1 function register pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal 2. n = 0 to 2, 4, 5 chapter 14 port function user?s manual u13850ej4v0um 383 figure 14-12. block diagram of p13 p-ch wr pm wr port rd wr pu v dd selector output latch (p13) pm13 pm1 pu13 pu1 internal bus alternate function p13/si1/rxd0 remark pu1: pull-up resistor option register 1 pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal chapter 14 port function user?s manual u13850ej4v0um 384 14.2.3 port 2 port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). p20, p21, p22, p24 and p25 are selectable as normal outputs or n-ch open-drain outputs. when p26 and p27 are used as ti2 and ti3 pins, noise is eliminated from these pins by a digital noise eliminator. figure 14-13. port 2 (p2) after reset: 00h r/w address: fffff004h 76543210 p2 p27 p26 p25 p24 p23 p22 p21 p20 p2n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when the p2 register is read, the pin levels at that time are read. writing to p2 writes the values to that register. this does not affect the input pins. in output mode: when the p2 register is read, the p2 register?s values are read. writing to p2 writes the values to that register, and those values are immediately output. port 2 includes the following alternate functions. sda1 and scl1 are available only in the pd70303xay and 70f303way. table 14-4. port 2 alternate function pins pin name alternate function i/o pull note remark port 2 p20 si2/sda1 p21 so2 p22 sck2/scl1 selectable as n-ch open-drain output p23 si3/rxd1 ? p24 so3/txd1 p25 sck3/asck1 selectable as n-ch open-drain output p26 ti2/to2 p27 ti3/to3 i/o yes digital noise elimination note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 385 (1) function of p2 pins port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 2 mode register (pm2). in output mode, the values set to each bit are output to the port 2 register (p2). the port 2 function register (pf2) can be used to specify whether p20, p21, p22, p24 and p25 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading the p2 register. also, the p2 register (output latch) values can be read by reading the p2 register while in output mode. a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 2 (pu2). when using the alternate function as ti2 and ti3 pins, noise elimination is provided by a digital noise eliminator (same as digital noise eliminator for port 0). clear the p2 and pm2 registers to 0 when using alternate-function pins as outputs. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 2 mode register (pm2) pm2 can be read/written in 8-/1-bit units. figure 14-14. port 2 mode register (pm2) after reset: ffh r/w address: fffff024h 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 386 (b) pull-up resistor option register 2 (pu2) pu2 can be read/written in 8-/1-bit units. figure 14-15. pull-up resistor option register 2 (pu2) after reset: 00h r/w address: fffff084h 76543210 pu2 pu27 pu26 pu25 pu24 pu23 pu22 pu21 pu20 pu2n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect (c) port 2 function register (pf2) pf2 can be read/written in 8-/1-bit units. figure 14-16. port 2 function register (pf2) after reset: 00h r/w address: fffff0a4h 76543210 pf2 0 0 pf25 pf24 0 pf22 pf21 pf20 pf2n control of normal output/n-ch open-drain output (n = 0 to 2, 4, 5) 0 normal output 1 n-ch open-drain output chapter 14 port function user?s manual u13850ej4v0um 387 (3) block diagram (port 2) figure 14-17. block diagram of p20 to p22, p24, and p25 p-ch wr pm wr pf wr port rd wr pu v dd v dd selector pf2n pf2 pm2n pm2 pu2n pu2 p-ch n-ch internal bus output latch (p2n) alternate function p20/si2/sda1 note p21/so2 p22/sck2/scl1 note p24/so3/txd1 p25/sck3/asck1 note the sda1, scl1 pins apply only to the pd70303xay and 70f303way. remarks 1. pu2: pull-up resistor option register 2 pf2: port 2 function register pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 0 to 2, 4, 5 chapter 14 port function user?s manual u13850ej4v0um 388 figure 14-18. block diagram of p23, p26, and p27 p-ch wr pm wr port rd wr pu v dd selector output latch (p13) pm13 pm1 pu13 pu1 internal bus alternate function p13/si1/rxd0 remarks 1. pu2: pull-up resistor option register 2 pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 3 , 6, or 7 chapter 14 port function user?s manual u13850ej4v0um 389 14.2.4 port 3 port 3 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). either a normal output or n-ch open-drain out can be selected for p33 and p34. when using p36 and p37 as the ti4 and ti5 pins, noise is eliminated by the digital noise eliminator. figure 14-19. port 3 (p3) after reset: 00h r/w address: fffff006h 76543210 p3 p37 p36 p35 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when the p3 register is read, the pin levels at that time are read. writing to p3 writes the values to that register. this does not affect the input pins. in output mode: when the p3 register is read, the p3 register?s values are read. writing to p3 writes the values to that register, and those values are immediately output. port 3 includes the following alternate functions. table 14-5. port 3 alternate function pins pin name alternate function i/o pull note remark p30 ti00 p31 ti01 p32 ti10/si4 ? p33 ti11/so4 p34 to0/a13/sck4 selectable as n-ch open-drain output. p35 to1/a14 ? p36 ti4/to4/a15 port 3 p37 ti5/to5 i/o yes digital noise elimination note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 390 (1) function of p3 pins port 3 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 3 mode register (pm3). in output mode, the values set to each bit are output to the port 3 register (p3). the port 3 function register (pf3) can be used to specify whether p33 and p34 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading the p3 register. also, the p3 register (output latch) values can be read by reading the p3 register while in output mode. a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 3 (pu3). when using the alternate function as ti4 and ti5 pins, noise elimination is provided by a digital noise eliminator (same as digital noise eliminator for port 0). when using the alternate function as a13 to a15 pins, set the pin functions via the memory address output mode register (mam). at this time, be sure to set the pm3 registers (pm34, pm35, pm36) and the p3 registers (p34, p35, p36) to 0. clear the p3 and pm3 registers to 0 when using alternate-function pins as outputs. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 3 mode register (pm3) pm3 can be read/written in 8-/1-bit units. figure 14-20. port 3 mode register (pm3) after reset: ffh r/w address: fffff026h 76543210 pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 3 (pu3) pu3 can be read/written in 8-/1-bit units. figure 14-21. pull-up resistor option register 3 (pu3) after reset: 00h r/w address: fffff086h 76543210 pu3 pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu3n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect chapter 14 port function user?s manual u13850ej4v0um 391 (c) port 3 function register (pf3) pf3 can be read/written in 8-/1-bit units. figure 14-22. port 3 function register (pf3) after reset: 00h r/w address: fffff0a6h 76543210 pf3 0 0 0 pf34 pf33 0 0 0 pf3n control of normal output/n-ch open-drain output (n = 3, 4) 0 normal output 1 n-ch open-drain output (3) block diagram (port 3) figure 14-23. block diagram of p30 to p32 and p35 to p37 p-ch wr pm wr port rd wr pu v dd selector output latch (p3n) pm3n pm3 pu3n pu3 internal bus alternate function p30/ti00 p31/ti01 p32/ti10/si4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 remarks 1. pu3: pull-up resistor option register 3 pm3: port 3 mode register rd: port 3 read signal wr: port 3 write signal 2. n = 0 to 2, 5 to 7 chapter 14 port function user?s manual u13850ej4v0um 392 figure 14-24. block diagram of p33 and p34 p-ch wr pm wr pf wr port rd wr pu v dd v dd selector pf3n pf3 pm3n pm3 pu3n pu3 p-ch n-ch internal bus output latch (p3n) alternate function p33/ti11/so4 p34/to0/a13/sck4 remarks 1. pu3: pull-up resistor option register 3 rf3: port 3 function register pm3: port 3 mode register rd: port 3 read signal wr: port 3 write signal 2. n = 3, 4 chapter 14 port function user?s manual u13850ej4v0um 393 14.2.5 ports 4 and 5 ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. figure 14-25. ports 4 and 5 (p4 and p5) after reset: 00h r/w address: fffff008h, fffff00ah 76543210 pn pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 pnx control of output data (in output mode) (n = 4, 5, x = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when the p4 and p5 registers are read, the pin levels at that time are read. writing to p4 and p5 writes the values to those registers. this does not affect the input pins. in output mode: when the p4 and p5 registers are read, their values are read. writing to p4 and p5 writes the values to those registers, and those values are immediately output. ports 4 and 5 include the following alternate functions. table 14-6. alternate function pins of ports 4 and 5 pin name alternate function i/o pull note remark port 4 p40 ad0 i/o no ? p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 ad7 port 5 p50 ad8 i/o no ? p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 ad15 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 394 (1) functions of p4 and p5 pins ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 4 mode register (pm4) the and port 5 mode register (pm5). in output mode, the values set to each bit are output to the port 4 and 5 registers (p4 and p5). when using these ports in input mode, the pin statuses can be read by reading the p4 and p5 registers. also, the p4 and p5 register (output latch) values can be read by reading the p4 and p5 registers while in output mode. a software pull-up function is not implemented. when using the alternate function as ad0 to ad15, set the pin functions via the memory expansion register (mm). this does not affect the pm4 and pm5 registers. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 4 mode register and port 5 mode register (pm4 and pm5) pm4 and pm5 can be read/written in 1-bit or 8-bit units. figure 14-26. port 4 mode register, port 5 mode register (pm4, pm5) after reset: ff h r/w address: fffff028h, fffff02ah 76543210 pmn pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 (n = 4, 5) pmnx control of i/o mode (n = 4, 5, x = 0 to 7) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 395 (3) block diagram (ports 4 and 5) figure 14-27. block diagram of p40 to p47 and p50 to p57 wr pm wr port rd selector output latch (mn) pmmn pmm internal bus pmn/adx remarks 1. pmm: port m mode register rd: port m read signal wr: port m write signal 2. m = 4, 5 n = 0 to 7 x = 0 to 15 chapter 14 port function user?s manual u13850ej4v0um 396 14.2.6 port 6 port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. figure 14-28. port 6 (p6) after reset: 00h r/w address: fffff00ch 76543210 p6 0 0 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 5) 0 outputs 0 1 outputs 1 remark in input mode: when the p6 register is read, the pin levels at that time are read. writing to p6 writes the values to that register. this does not affect the input pins. in output mode: when the p6 register is read, the p6 register?s values are read. writing to p6 writes the values to that register, and those values are immediately output. port 6 includes the following alternate functions. table 14-7. port 6 alternate function pins pin name alternate function i/o pull note remark port 6 p60 a16 i/o no ? p61 a17 p62 a18 p63 a19 p64 a20 p65 a21 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 397 (1) function of p6 pins port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 6 mode register (pm6). in output mode, the values set to each bit are output to the port 6 register (p6). when using this port in input mode, the pin statuses can be read by reading the p6 register. also, the p6 register (output latch) values can be read by reading the p6 register while in output mode. a software pull-up function is not implemented. when using the alternate function as a16 to a21, set the pin functions via the memory expansion register (mm). this does not affect the pm6 register. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 6 mode register (pm6) pm6 can be read/written in 8-/1-bit units. figure 14-29. port 6 mode register (pm6) after reset: 3fh r/w address: fffff02ch 76543210 pm6 0 0 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 398 (3) block diagram (port 6) figure 14-30. block diagram p60 to p65 wr pm wr port rd selector output latch (p6n) pm6n pm6 internal bus p6n/ax remarks 1. pm6: port 6 mode register rd: port 6 read signal wr: port 6 write signal 2. n = 0 to 5 x = 16 to 21 chapter 14 port function user?s manual u13850ej4v0um 399 14.2.7 ports 7 and 8 port 7 is an 8-bit input port and port 8 is a 4-bit input port. both ports are read-only and are accessible in 8-/1-bit units. figure 14-31. ports 7 and 8 (p7 and p8) after reset: undefined r address: fffff00eh 76543210 p7 p77 p76 p75 p74 p73 p72 p71 p70 p7n pin level (n = 0 to 7) 0/1 read pin level of bit n after reset: undefined r address: fffff010h 76543210 p8 0 0 0 0 p83 p82 p81 p80 p8n pin level (n = 0 to 3) 0/1 read pin level of bit n ports 7 and 8 include the following alternate functions. table 14-8. alternate function pins of ports 7 and 8 pin name alternate function i/o pull note remark port 7 p70 ani0 input no ? p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 port 8 p80 ani8 input no ? p81 ani9 p82 ani10 p83 ani11 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 400 (1) functions of p7 and p8 pins port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. the pin statuses can be read by reading the port 7 and 8 registers (p7 and p8). data cannot be written to p7 or p8. a software pull-up function is not implemented. values read from pins specified as analog inputs are undefined values. do not read values from p7 or p8 during a/d conversion. (2) block diagram (ports 7 and 8) figure 14-32. block diagram of p70 to p77 and p80 to p83 pmn/anix rd internal bus remarks 1. rd: port 7, port 8 read signals 2. m = 7, 8 n = 0 to 7 (m = 7), 0 to 3 (m = 8) x = 0 to 7 (m = 7), 8 to 11 (m = 8) chapter 14 port function user?s manual u13850ej4v0um 401 14.2.8 port 9 port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. figure 14-33. port 9 (p9) after reset: 00h r/w address: fffff012h 76543210 p9 0 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 6) 0 outputs 0 1 outputs 1 remark in input mode: when the p9 register is read, the pin levels at that time are read. writing to p9 writes the values to that register. this does not affect the input pins. in output mode: when the p9 register is read, the p9 register?s values are read. writing to p9 writes the values to that register, and those values are immediately output. port 9 includes the following alternate functions. table 14-9. port 9 alternate function pins pin name alternate function i/o pull note remark p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak port 9 p96 hldrq i/o no ? note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 402 (1) function of p9 pins port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 9 mode register (pm9). in output mode, the values set to each bit are output to the port 9 register (p9). when using this port in input mode, the pin statuses can be read by reading the p9 register. also, the p9 register (output latch) values can be read by reading the p9 register while in output mode. a software pull-up function is not implemented. when using the p9 for control signals in expansion mode, set the pin functions via the memory expansion mode register (mm). when a reset is input, the settings are initialized to input mode. (2) control register (a) port 9 mode register (pm9) pm9 can be read/written in 1-bit or 8-bit units. figure 14-34. port 9 mode register (pm9) after reset: 7fh r/w address: fffff032h 76543210 pm9 0 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 6) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 403 (3) block diagram (port 9) figure 14-35. block diagram of p90 to p96 wr pm wr port rd selector output latch (p9n) pm9n pm9 internal bus p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq remarks 1. pm9: port 9 mode register rd: port 9 read signal wr: port 9 write signal 2. n = 0 to 6 chapter 14 port function user?s manual u13850ej4v0um 404 14.2.9 port 10 port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). the pins in this port are selectable as normal outputs or n-ch open-drain outputs. when using p100 to p107 as kr0 to kr7 pins, noise is eliminated by the analog noise eliminator. figure 14-36. port 10 (p10) after reset: 00h r/w address: fffff014h 76543210 p10 p107 p106 p105 p104 p103 p102 p101 p100 p10n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when the p10 register is read, the pin levels at that time are read. writing to p10 writes the values to that register. this does not affect the input pins. in output mode: when the p10 register is read, the p10 register?s values are read. writing to p10 writes the values to that register, and those values are immediately output. port 10 includes the following alternate functions. ierx and ietx pins are valid only for the v850/sb2. table 14-10. port 10 alternate function pins pin name alternate function i/o pull note remark port 10 p100 rtp0/a5/kr0 i/o yes selectable as n-ch open-drain outputs p101 rtp1/a6/kr1 analog noise elimination p102 rtp2/a7/kr2 p103 rtp3/a8/kr3 p104 rtp4/a9/kr4/ierx p105 rtp5/a10/kr5/ietx p106 rtp6/a11/kr6 p107 rtp7/a12/kr7 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 405 (1) function of p10 pins port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 10 mode register (pm10). in output mode, the values set to each bit are output to the port 10 register (p10). the port 10 function register (pf10) can be used to specify whether outputs are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading the p10 register. also, the p10 register (output latch) values can be read by reading the p10 register while in output mode. a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 10 (pu10). when using the alternate function as a5 to a12 pins, see the pin functions via the memory address output mode register (mam). at this time, be sure to set p10 and pm10 to 0. when used as kr0 to kr7 pins, noise is eliminated by the analog noise eliminator. clear the p10 and pm10 registers to 0 when using alternate-function pins as outputs. the ored result of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 10 mode register (pm10) pm10 can be read/written in 1-bit or 8-bit units. figure 14-37. port 10 mode register (pm10) after reset: ffh r/w address: fffff034h 76543210 pm10 pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 pm10n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 406 (b) pull-up resistor option register 10 (pu10) pu10 can be read/written in 8-/1-bit units. figure 14-38. pull-up resistor option register 10 (pu10) after reset: 00h r/w address: fffff094h 76543210 pu10 pu107 pu106 pu105 pu104 pu103 pu102 pu101 pu100 pu10n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect (c) port 10 function register (pf10) pf10 can be read/written in 8-/1-bit units. figure 14-39. port 10 function register (pf10) after reset: 00h r/w address: fffff0b4h 76543210 pf10 pf107 pf106 pf105 pf104 pf103 pf102 pf101 pf100 pf10n control of normal output/n-ch open-drain output (n = 0 to 7) 0 normal output 1 n-ch open-drain output chapter 14 port function user?s manual u13850ej4v0um 407 (3) block diagram (port 10) figure 14-40. block diagram of p100 to p107 p-ch wr pm wr pf wr port rd wr pu v dd v dd selector pf10n pf10 pm10n pm10 pu10n pu10 p-ch n-ch internal bus output latch (p10n) alternate function p100/rtp0/a5/kr0 p101/rtp1/a6/kr1 p102/rtp2/a7/kr2 p103/rtp3/a8/kr3 p104/rtp4/a9/kr4/ierx note p105/rtp5/a10/kr5/ietx note p106/rtp6/a11/kr6 p107/rtp7/a12/kr7 note the ierx, ietx pins apply only to the v850/sb2. remarks 1. pu10: pull-up resistor option register 10 rf10: port 10 function register pm10: port 10 mode register rd: port 10 read signal wr: port 10 write signal 2. n = 0 to 7 chapter 14 port function user?s manual u13850ej4v0um 408 14.2.10 port 11 port 11 is a 4-bit port. a pull-up resistor can be connected to bits 0 to 3 in 1-bit units (software pull-up function). p11 can be read/written in 8-/1-bit units. the on/off of wait function can be switched with a port alternate-function control register (pac). caution when using the wait function, set bc dd to the same potential as ev dd . figure 14-41. port 11 (p11) after reset: 00h r/w address: fffff016h 76543210 p11 0 0 0 undefined p113 p112 p111 p110 p11n control of output data (in output mode) (n = 0 to 3) 0 outputs 0 1 outputs 1 remark in input mode: when the p11 register is read, the pin levels at that time are read. writing to p11 writes the values to that register. this does not affect the input pins. in output mode: when the p11 register is read, the p11 register?s values are read. writing to p11 writes the values to that register, and those values are immediately output. port 11 includes the following alternate functions. table 14-11. port 11 alternate function pins pin name alternate function i/o pull note remark port 11 p110 a1/wait i/o yes ? p111 a2 p112 a3 p113 a4 note software pull-up function chapter 14 port function user?s manual u13850ej4v0um 409 (1) function of p11 pins port 11 is a 4-bit (total) port for which i/o settings can be controlled in 1-bit units. in output mode, the values set to each bit (bit 0 to bit 3) are output to the port register (p11). when using this port in input mode, the pin statuses can be read by reading the p11 register. also, the p11 register (output latch) values can be read by reading the p11 register while in output mode (bit 0 to bit 3 only). a pull-up resistor can be connected in 1-bit units for p110 to p113 when specified via pull-up resistor option register 11 (pu11). the on/off of wait function can be switched with a port-alternate function control register (pac). when using the alternate function as a1 to a4 pins, set the pin functions via the memory address output mode register (mam). at this time, be sure to clear p11 and pm11 to 0. when a reset is input, the settings are initialized to input mode. caution a wait function generated by the wait pin cannot be used while a separate bus is being used. however, a programmable wait is possible. (2) control register (a) port 11 mode register (pm11) pm11 can be read/written in 1-bit or 8-bit units. figure 14-42. port 11 mode register (pm11) after reset: 1fh r/w address: fffff036h 76543210 pm11 0 0 0 1 pm113 pm112 pm111 pm110 pm11n control of i/o mode (n = 0 to 3) 0 output mode 1 input mode chapter 14 port function user?s manual u13850ej4v0um 410 (b) pull-up resistor option register 11 (pu11) pu11 can be read/written in 8-/1-bit units. figure 14-43. pull-up resistor option register 11 (pu11) after reset: 00h r/w address: fffff096h 76543210 pu11 0 0 0 0 pu113 pu112 pu111 pu110 pu11n control of on-chip pull-up resistor connection (n = 0 to 3) 0 do not connect 1 connect (c) port alternate-function control register (pac) pac can be read/written in 8-/1-bit units. figure 14-44. port alternate-function control register (pac) after reset: 00h r/w address: fffff040h 7654321<0> pac 0000000wac p120 control of output data (in output mode) 0 wait function off 1 wait function on chapter 14 port function user?s manual u13850ej4v0um 411 (3) block diagram (port 11) figure 14-45. block diagram of p110 to p113 p-ch wr pm wr port rd wr pu v dd selector pu11n pu11 output latch (p11n) pm11n pm11 internal bus p110/a1/wait p111/a2 p112/a3 p113/a4 remarks 1. pu11: pull-up resistor option register 11 pm11: port 11 mode register rd: port 11 read signal wr: port 11 write signal 2. n = 0 to 3 chapter 14 port function user?s manual u13850ej4v0um 412 14.3 setting when port pin is used for alternate function when a port pin is used for an alternate function, set the port n mode register (pm0 to pm6 and pm9 to pm11) and output latch as shown in table 14-12 below. table 14-12. setting when port pin is used for alternate function (1/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p00 nmi input pm00 = 1 setting not needed for p00 ? p01 intp0 input pm01 = 1 setting not needed for p01 ? p02 intp1 input pm02 = 1 setting not needed for p02 ? p03 intp2 input pm03 = 1 setting not needed for p03 ? p04 intp3 input pm04 = 1 setting not needed for p04 ? intp4 input p05 adtrg input pm05 = 1 setting not needed for p05 ? intp5 input p06 rtptrg input pm06 = 1 setting not needed for p06 ? p07 intp6 input pm07 = 1 setting not needed for p07 ? si0 input pm10 = 1 setting not needed for p10 p10 sda0 note i/o pm10 = 0 p10 = 0 ? p11 so0 output pm11 = 0 p11 = 0 ? input pm12 = 1 setting not needed for p12 sck0 output p12 scl0 note i/o pm12 = 0 p12 = 0 ? si1 input p13 rxd0 input pm13 = 1 setting not needed for p13 ? so1 output p14 txd0 output pm14 = 0 p14 = 0 ? input pm15 = 1 setting not needed for p15 sck1 output pm15 = 0 p12 = 0 p15 asck0 input pm15 = 1 setting not needed for p15 ? note provided for the pd70303xay and 70f303way only. chapter 14 port function user?s manual u13850ej4v0um 413 table 14-12. setting when port pin is used for alternate function (2/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) si2 input pm20 = 1 setting not needed for p20 p20 sda1 note i/o pm20 = 0 p20 = 0 ? p21 so2 output pm21 = 0 p21 = 0 ? input pm22 = 1 setting not needed for p22 sck2 output p22 scl1 note i/o pm22 = 0 p22 = 0 ? si3 input p23 rxd1 input pm23 = 1 setting not needed for p23 ? so3 output p24 txd1 output pm24 = 0 p24 = 0 ? input pm25 = 1 setting not needed for p25 sck3 output pm25 = 0 p25 = 0 p25 asck1 input pm25 = 1 setting not needed for p25 ? ti2 input pm26 = 1 setting not needed for p26 p26 to2 output pm26 = 0 p26 = 0 ? ti3 input pm27 = 1 setting not needed for p27 p27 to3 output pm27 = 0 p27 = 0 ? p30 ti00 input pm30 = 1 setting not needed for p30 ? p31 ti01 input pm31 = 1 setting not needed for p31 ? ti10 input p32 si4 input pm32 = 1 setting not needed for p32 ? ti11 input pm33 = 1 setting not needed for p33 p33 so4 output pm33 = 0 p33 = 0 ? to0 output ? a13 output pm34 = 0 p34 = 0 refer to figure 3-22 (mam) input pm34 = 1 setting not needed for p34 p34 sck4 output pm34 = 0 p34 = 0 ? note provided for the pd70303xay and 70f303way only. chapter 14 port function user?s manual u13850ej4v0um 414 table 14-12. setting when port pin is used for alternate function (3/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) to1 output ? p35 a14 output pm35 = 0 p35 = 0 refer to figure 3-22 (mam) ti4 input pm36 = 1 setting not needed for p36 to4 output ? p36 a15 output pm36 = 0 p36 = 0 refer to figure 3-22 (mam) ti5 input pm37 = 1 setting not needed for p37 p37 to5 output pm37 = 0 p37 = 0 ? p40 to p47 ad0 to ad7 i/o setting not needed for pm40 to pm47 setting not needed for p40 to p47 refer to figure 3-21 (mm) p50 to p57 ad8 to ad15 i/o setting not needed for pm50 to pm57 setting not needed for p50 to p57 refer to figure 3-21 (mm) p60 to p65 a16 to a21 output setting not needed for pm60 to pm65 setting not needed for p60 to p65 refer to figure 3-21 (mm) p70 to p77 ani0 to ani7 input none setting not needed for p70 to p77 ? p80 to p83 ani8 to ani11 input none setting not needed for p80 to p83 ? lben output p90 wrl output setting not needed for pm90 setting not needed for p90 refer to figure 3-21 (mm) p91 uben output setting not needed for pm91 setting not needed for p91 refer to figure 3-21 (mm) r/w output p92 wrh output setting not needed for pm92 setting not needed for p92 refer to figure 3-21 (mm) dstb output p93 rd output setting not needed for pm93 setting not needed for p93 refer to figure 3-21 (mm) p94 astb output setting not needed for pm94 setting not needed for p94 refer to figure 3-21 (mm) p95 hldak output setting not needed for pm95 p95 = 1 refer to figure 3-21 (mm) p96 hldrq input setting not needed for pm96 p96 = 1 refer to figure 3-21 (mm) chapter 14 port function user?s manual u13850ej4v0um 415 table 14-12. setting when port pin is used for alternate function (4/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) rtp0 to rtp3 output ? a5 to a8 output pm100 to pm103 = 0 p 100 to p103 = 0 refer to figure 3-22 (mam) p100 to p103 kr0 to kr3 input pm 100 to pm103 = 1 setting not needed for p100 to p103 ? rtp4 output ? a9 output pm104 = 0 p 104 = 0 refer to figure 3-22 (mam) kr4 input ? p104 ierx note input pm104 = 1 setting not needed for p104 ? rtp5 output ? a10 output pm105 = 0 p 105 = 0 refer to figure 3-22 (mam) kr5 input pm 105 = 1 setting not needed for p105 ? p105 ietx note output pm105 = 0 p 105 = 0 ? rtp6, rtp7 output ? a11, a12 output pm106, pm107 = 0 p 106, p107 = 0 refer to figure 3-22 (mam) p106, p107 kr6, kr7 input pm 106, pm107 = 1 setting not needed for p106 and p107 ? a1 output pm110 = 0 p110 = 0 refer to figure 3-22 (mam) p110 wait input pm110 = 1 setting not needed for p110 wac = 1 (pac) p111 to p113 a2 to a4 output pm 111 to pm113 = 0 p111 to p113 = 0 refer to figure 3-22 (mam) note only for the v850/sb2. cautions 1. when changing the output level of port 0 by setting the port 0?s port function output mode, the interrupt request flag will be set because port 0 also has an alternate function as external interrupt request input. therefore, be sure to set a corresponding interrupt mask flag to 1 before using the output mode. 2. when using the i 2 c bus mode, be sure to specify n-ch open-drain output for the sda0/p10, scl0/p12, sda1/p20, and scl1/p22 pins by setting the port n function register (pfn) (n = 1, 2). remark pmnx bit of pmn register and pnx bit of pn register n: 0 (x = 0 to 7) n: 1 (x = 0 to 5) n: 2 (x = 0 to 7) n: 3 (x = 0 to 7) n: 4 (x = 0 to 7) n: 5 (x = 0 to 7) n: 6 (x = 0 to 5) n: 7 (x = 0 to 7) n: 8 (x = 0 to 3) n: 9 (x = 0 to 6) n: 10 (x = 0 to 7) n: 11 (x = 0 to 3) user?s manual u13850ej4v0um 416 chapter 15 reset function 15.1 general when a low-level input occurs at the reset pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. in addition, oscillation of the main clock is stopped during the reset period, although oscillation of the sub clock continues. when the input at the reset pin changes from low level to high level, the reset status is canceled and the cpu resumes program execution. the contents of the various registers should be initialized within the program as necessary. an on-chip noise eliminator uses analog delay to prevent noise-related malfunction of the reset pin. 15.2 pin operations during the system reset period, high impedance is set at almost all pins (all pins except for reset, x2, xt2, regc, av ref , v dd , v ss , av dd , av ss , bv dd , bv ss , ev dd , ev ss , and v pp /ic). accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor for each pin. if such a resistor is not attached, high impedance will be set for these pins, which could damage the data in memory devices. likewise, make sure the pins are handled so as to prevent such effects at the signal outputs by on- chip peripheral i/o functions and output ports. figure 15-1. system reset timing analog delay eliminated as noise hi-z x1 analog delay 20.2 ms (@ 20 mhz operation) reset internal system reset signal reset is acknowledged reset is canceled oscillation stabilization time analog delay user?s manual u13850ej4v0um 417 chapter 16 regulator 16.1 outline the v850/sb1 and v850/sb2 incorporate a regulator to realize a 5 v single power supply, low power consumption, and to reduce noise. this regulator supplies a voltage obtained by stepping down v dd power supply voltage to oscillation blocks and on-chip logic circuits (excluding the a/d converter and output buffers). the regulator output voltage is set to 3.3 v (v850/sb1) or 3.0 v (v850/sb2). refer to 2.4 i/o circuit types, i/o buffer power supply and connection of unused pins for the power supply corresponding to each pin. figure 16-1. regulator a/d converter 4.5 v to 5.5 v av dd main/sub oscillators on-chip digital circuit 3.3 v: v850/sb1 3.0 v: v850/sb2 regulator v dd bv dd ev dd flash memory 3.0 v to 5.5 v 3.0 v to 5.5 v bi-directional level shifter ev dd- system i/o buffer bv dd- system i/o buffer v pp regc 16.2 operation the regulators of the v850/sb1 and v850/sb2 operate in every mode (stop, idle, halt). for stabilization of regulator outputs, connect an electrolytic capacitor of about 1 f to the regc pin. user?s manual u13850ej4v0um 418 chapter 17 rom correction function 17.1 general the rom correction function provided in the v850/sb1 and v850/sb2 is a function that replaces part of a program in the mask rom with a program in the internal ram. first, the instruction of the address where the program replacement should start is replaced with the jmp r0 instruction and the program is instructed to jump to 00000000h. the correction request register (corrq) is then checked. at this time, if the corrqn flag is set to 1, program control shifts to the internal ram after jumping to the internal rom area by an instruction such as a jump instruction. instruction bugs found in the mask rom can be avoided, and program flow can be changed by using the rom correction function. up to four correction addresses can be specified. cautions 1. the rom correction function cannot be used for the data in the internal rom; it can only be used for instruction codes. if rom correction is carried out on data, that data will replace the instruction code of the jmp r0 instruction. 2. rom correction for the instructions that access the registers corcn, corrq, or corad0 to corad3 is prohibited. figure 17-1. block diagram of rom correction rom (1 mb area) instruction address bus s q r correction address register n (coradn) comparator correction control register (corcnn bit) jmp r0 instruction generation instruction replacement instruction data bus correction request register (corrqn bit) 0 clear instruction remark n = 0 to 3 chapter 17 rom correction function user?s manual u13850ej4v0um 419 17.2 rom correction peripheral i/o registers 17.2.1 correction control register (corcn) corcn controls whether or not the instruction of the correction address is replaced with the jmp r0 instruction when the correction address matches the fetch address (n = 0 to 3). whether match detection by a comparator is enabled or disabled can be set for each channel. corcn can be set by a 1-bit or 8-bit memory manipulation instruction. figure 17-2. correction control register (corcn) after reset: 00h r/w address: fffff36ch 7654<3><2><1><0> corcn 0 0 0 0 coren3 coren2 coren1 coren0 corenn coradn register and fetch address match detection control 0 match detection disabled (not detected) 1 match detection enabled (detected) remark n = 0 to 3 chapter 17 rom correction function user?s manual u13850ej4v0um 420 17.2.2 correction request register (corrq) corrq saves the channel in which rom correction occurred. the jmp r0 instruction makes the program jump to 00000000h after the correction address matches the fetch address. at this time, the program can judge the following cases by reading corrq. ? reset input: corrq = 00h ? rom correction generation: corrqn bit = 1 (n = 0 to 3) ? branch to 00000000h by user program: corrq = 00h figure 17-3. correction request register (corrq) after reset: 00h r/w address: fffff36eh 7654<3><2><1><0> corrq 0 0 0 0 corrq3 corrq2 corrq1 corrq0 corrqn channel n rom correction request flag 0 no rom correction request occurred. 1 rom correction request occurred. remark n = 0 to 3 chapter 17 rom correction function user?s manual u13850ej4v0um 421 17.2.3 correction address registers 0 to 3 (corad0 to corad3) coradn sets the start address of an instruction to be corrected (correction address) in the rom. up to four points of the program can be corrected at once since the v850/sb1 and v850/sb2 have four correction address registers (coradn) (n = 0 to 3). since the rom capacity varies depending on the product, set the correction address within following ranges. pd703031a, 703031ay, 703034a, 703034ay (128 kb): 00000000h to 0001fffeh pd703033a, 703033ay, 703035a, 703035ay (256 kb): 00000000h to 0003fffeh pd703030a, 703030ay, 703036a, 703036ay (384 kb): 00000000h to 0005fffeh pd703032a, 703032ay, 703037a, 703037ay (512 kb): 00000000h to 0007fffeh bits 0 and 20 to 31 should be fixed to 0. figure 17-4. correction address registers 0 to 3 (corad0 to corad3) after reset: 00000000h r/w address: corad0: fffff370h corad2: fffff378h corad1: fffff374h corad3: fffff37ch 31 20 19 1 0 coradn fixed to 0 correction address 0 (n = 0 to 3) chapter 17 rom correction function user?s manual u13850ej4v0um 422 figure 17-5. rom correction operation and program flow start (reset vector) correction address? corenn = 1? corrqn = 0? yes no data for rom correction setting is loaded from an external memory into the internal ram to initialize rom correction function. if there is a correction code, it is loaded in the internal ram. microcontroller initialization clears corrqn flag. jmp channel n correct code address executes internal rom program executes correction program code jumps to internal rom yes no yes no corrqn flag set jmp r0 the address of the internal ram that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal rom. : executed by a program stored in the internal rom : executed by a program stored in the internal ram : executed by the rom correction function caution check the rom correction generation from the vector table with a high interrupt level when executing rom correction during a vector interrupt routine. if an interrupt conflicts with rom correction, processing is branched to an interrupt vector, where, if rom correction is being re-executed, corrqn is set (1) again and multiple corrqn flags are set (1). the channel for which rom correction is to be executed is determined by the interrupt level. remark n = 0 to 3 user?s manual u13850ej4v0um 423 chapter 18 flash memory the following products are the flash memory versions of the v850/sb1 and v850/sb2. caution the flash memory version and mask rom version differ in noise immunity and noise radiation. if replacing a flash memory version with a mask rom version when changing from of experimental production to mass production, make a thorough evaluation by using the cs model (not es model) of the mask rom version. (1) v850/sb1 pd70f3033a, 70f3033ay: 256 kb flash memory versions pd70f3032a, 70f3032ay: 512 kb flash memory versions (2) v850/sb2 pd70f3035a, 70f3035ay: 256 kb flash memory versions pd70f3037a, 70f3037ay: 512 kb flash memory versions in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock, the same as in the mask rom version. writing to flash memory can be performed with memory mounted on the target system (on board). the dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and the applications using a flash memory. ? software can be altered after the v850/sb1 or v850/sb2 is solder-mounted on the target system. ? small scale production of various models is made easier by differentiating software. ? data adjustment in starting mass production is made easier. 18.1 features ? 4-byte/1-clock access (in instruction fetch access) ? all area one-shot erase/area unit erase ? communication via serial interface with the dedicated flash programmer ? erase/write voltage: v pp = 7.8 v ? on-board programming ? flash memory programming in area (128 kb) units by self-writing 18.1.1 erasing unit the erasing unit differs depending on the product. (1) v850/sb1 ( pd70f3033a, 70f3033ay), v850/sb2 ( pd70f3035a, 70f3035ay) the erasing units for 256 kb flash memory versions are shown below. (a) all area one-shot erase the area of xx000000h to xx03ffffh can be erased in one shot. the erasing time is 4.0 s. chapter 18 flash memory user?s manual u13850ej4v0um 424 (b) area erase erasure can be performed in area units (there are two 128 kb unit areas). the erasing time is 2.0 s for each area. area 0: the area of xx000000h to xx01ffffh (128 kb) is erased area 1: the area of xx020000h to xx03ffffh (128 kb) is erased (2) v850/sb1 ( pd70f3032a, 70f3032ay), v850/sb2 ( pd70f3037a, 70f3037ay) the erasing units for 512 kb flash memory versions are shown below. (a) all area one-shot erase the area of xx000000h to xx07ffffh can be erased in one shot. the erasing time is 8.0 s. (b) area erase erasure can be performed in area units (there are four 128 kb unit areas). the erasing time is 2.0 s for each area. area 0: the area of xx000000h to xx01ffffh (128 kb) is erased area 1: the area of xx020000h to xx03ffffh (128 kb) is erased area 2: the area of xx040000h to xx05ffffh (128 kb) is erased area 3: the area of xx060000h to xx07ffffh (128 kb) is erased 18.1.2 write/read time the write/read time is shown below. write time: 50 s/byte read time: 50 ns (cycle time) 18.2 writing with flash programmer writing can be performed either on-board or off-board with the dedicated flash programmer. (1) on-board programming the contents of the flash memory are rewritten after the v850/sb1 or v850/sb2 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to a flash memory are performed by the dedicated program adapter (fa series), etc., before mounting the v850/sb1 or v850/sb2 on the target system. remark fa series is a product of naito densei machida mfg. co., ltd. chapter 18 flash memory user?s manual u13850ej4v0um 425 18.3 programming environment the following shows the environment required for writing programs to the flash memory of the v850/sb1 and v850/sb2. figure 18-1. environment required for writing programs to flash memory rs-232c host machine v850/sb1, v850/sb2 dedicated flash programmer v ss v pp v dd reset uart/csi a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used for the interface between the dedicated flash programmer and the v850/sb1 or v850/sb2 to perform writing, erasing, etc. a dedicated program adapter (fa series) required for off-board writing. 18.4 communication system the communication between the dedicated flash programmer and the v850/sb1 or v850/sb2 is performed by serial communication using uart0 or csi0 of the v850/sb1, v850/sb2 . (1) uart0 transfer rate: 4800 to 76800 bps figure 18-2. communication with dedicated flash programmer (uart0) v850/sb1, v850/sb2 reset v ss v dd v pp dedicated flash programmer txd0 rxd0 v pp v dd gnd reset rxd txd chapter 18 flash memory user?s manual u13850ej4v0um 426 (2) csi0 serial clock: up to 1 mhz (msb first) figure 18-3. communication with dedicated flash programmer (csi0) v850/sb1, v850/sb2 reset v ss v dd v pp dedicated flash programmer so0 si0 v pp v dd gnd reset si so sck0 sck (3) csi0 + + + + hs serial clock: up to 1 mhz (msb first) figure 18-4. communication with dedicated flash programmer (csi0 + + + + hs) v850/sb1, v850/sb2 reset v ss v dd v pp dedicated flash programmer so0 si0 v pp v dd gnd reset si so sck0 sck p15 hs the dedicated flash programmer outputs the transfer clock, and the v850/sb1 and v850/sb2 operate as slaves. when the pg-fp3 is used as the dedicated flash programmer, it generates the following signals to the v850/sb1 or v850/sb2 . for details, refer to the pg-fp3 manual. chapter 18 flash memory user?s manual u13850ej4v0um 427 table 18-1. signal generation of dedicated flash programmer (pg-fp3) pg-fp3 v850/sb1, v850/sb2 connection handling signal name i/o pin function pin name csi0 uart0 csi0 + hs v pp output writing voltage v pp v dd i/o v dd voltage generation/ voltage monitoring v dd gnd ? ground v ss clk note output clock output to v850/sb1, v850/sb2 x1 reset output reset signal reset si/rxd input receive signal so0/txd0 so/txd output transmit signal si0/rxd0 sck output transfer clock sck0 hs input handshake signal of csi0 + hs p15 note supply clocks on the target board. remark : always connected { : does not need to be connected, if generated on the target board : does not need to be connected chapter 18 flash memory user?s manual u13850ej4v0um 428 18.5 pin connection when performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. also, install a function on-board to switch from the normal operation mode to the flash memory programming mode. when switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset. therefore, all the ports enter the output high-impedance status, so that pin handling is required when the external device does not acknowledge the output high-impedance status. 18.5.1 v pp pin in the normal operation mode, 0 v is input to the v pp pin. in the flash memory programming mode, a 7.8 v write voltage is supplied to the v pp pin. the following shows an example of the connection of the v pp pin. figure 18-5. v pp pin connection example v pp dedicated flash programmer connection pin pull-down resistor ( r vpp ) v850/sb1, v850/sb2 18.5.2 serial interface pin the following shows the pins used by each serial interface. table 18-2. pins used in serial interfaces serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, p15 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to conflict of signals and malfunction of other devices, etc. chapter 18 flash memory user?s manual u13850ej4v0um 429 (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 18-6. conflict of signals (serial interface input pin) v850/sb1, v850/sb2 other device output pin conflict of signals input pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. dedicated flash p ro g rammer connection p ins chapter 18 flash memory user?s manual u13850ej4v0um 430 (2) malfunction of other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. figure 18-7. malfunction of other device v850/sb1, v850/sb2 pin in the flash memory programming mode, if the signal the v850/sb1 or v850/sb2 outputs affects the other device, isolate the signal on the other device side. other device in p ut p in dedicated flash programmer connection pin v850/sb1, v850/sb2 pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin chapter 18 flash memory user?s manual u13850ej4v0um 431 18.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the reset pin that is connected to the reset signal generator on-board, conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 18-8. conflict of signals (reset pin) reset v850/sb1, v850/sb2 reset signal generator output pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. dedicated flash programmer connection pin 18.5.4 port pins (including nmi) when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer enter the output high-impedance status. if problems such as disabling output high- impedance status should occur in the external devices connected to the port, connect them to v dd or v ss via resistors. 18.5.5 other signal pins connect x1, x2, xt2, and av ref to the same status as that in the normal operation mode. 18.5.6 power supply supply the power supply as follows: v dd = ev dd supply the power supply (av dd , av ss , bv dd , bv ss ) the same as when in normal operation mode. chapter 18 flash memory user?s manual u13850ej4v0um 432 18.6 programming method 18.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 18-9. procedure for manipulating flash memory supplies reset pulse switch to flash memory programming mode select communication system manipulate flash memory end? no yes end start chapter 18 flash memory user?s manual u13850ej4v0um 433 18.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash programmer, set the v850/sb1 or v850/sb2 in the flash memory programming mode. when switching modes, set the v pp pin before releasing reset. when performing on-board writing, change modes using a jumper, etc. figure 18-10. flash memory programming mode v pp reset flash memory programming mode 7.8 v 3 v 0 v 12 ? n v pp operation mode 0 v normal operation mode 7.8 v flash memory programming mode chapter 18 flash memory user?s manual u13850ej4v0um 434 18.6.3 selection of communication mode in the v850/sb1 and v850/sb2, the communication mode is selected by inputting pulses (16 pulses max.) to the v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 18-3. list of communication modes v pp pulse communication mode remarks 0 csi0 v850/sb1 and v850/sb2 perform slave operation, msb first 3csi0 + hs v850/sb1 and v850/sb2 perform slave operation, msb first 8 uart0 communication rate: 9600 bps (at reset), lsb first others rfu setting prohibited caution when uart is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the v pp pulse. 18.6.4 communication command the v850/sb1 and v850/sb2 communicate with the dedicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850/sb1 or v850/sb2 is called a ?command?. the response signal sent from the v850/sb1 or v850/sb2 to the dedicated flash programmer is called a ?response command?. figure 18-11. communication command v850/sb1, v850/sb2 command dedicated flash programmer response command chapter 18 flash memory user?s manual u13850ej4v0um 435 the following shows the commands for flash memory control of the v850/sb1 and v850/sb2. all of these commands are issued from the dedicated flash programmer, and the v850/sb1 and v850/sb2 perform the various processing corresponding to the commands. table 18-4. flash memory control command category command name function verify one-short verify command compares the contents of the entire memory and the input data. erase one-shot erase command erases the contents of the entire memory. write back command writes back the erased contents. blank check one-shot blank check command checks the erase state of the entire memory. data write high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes a verify check. continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. system setting and control status read out command acquires the status of operations. oscillating frequency setting command sets the oscillation frequency. erasing time setting command sets the erasing time of one-shot erase. writing time setting command sets the writing time of data write. write back time setting command sets the write back time. baud rate setting command sets the baud rate when using uart. silicon signature command reads outs the silicon signature information. reset command escapes from each state. the v850/sb1 and v850/sb2 send back response commands to the commands issued from the dedicated flash programmer. the following shows the response commands the v850/sb1 and v850/sb2 send out. table 18-5. response command response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. 18.6.5 resources used the resources used in the flash memory programming mode are all the ffe000h to ffe7ffh area of the internal ram and all the registers. the ffe800h to ffefffh area of the internal ram retains data as long as the power is on. the registers that are initialized by reset are changed to the default value. user?s manual u13850ej4v0um 436 chapter 19 iebus controller (v850/sb2) iebus (inter equipment bus) is a small-scale digital data transfer system that transfers data between units. to implement iebus with the v850/sb2, an external iebus driver and receiver are necessary because they are not provided. the internal iebus controller of the v850/sb2 is of negative logic. 19.1 iebus controller function 19.1.1 communication protocol of iebus the communication protocol of the iebus is as follows: (1) multi-task mode all the units connected to the iebus can transfer data to the other units. (2) broadcasting communication function communication between one unit and plural units can be performed as follows: ? group-unit broadcasting communication: broadcasting communication to group units ? all-unit broadcasting communication: broadcasting communication to all units. (3) effective transfer rate the effective transfer rate is in mode 1 (the v850/sb2 does not support modes 0 and 2 for the effective transfer rate). ? mode 1: approx. 17 kbps caution different modes must not be mixed on one iebus. (4) communication mode data transfer is executed in half-duplex asynchronous communication mode. (5) access control: csma/cd (carrier sense multiple access with collision detection) the priority of the iebus is as follows: <1> broadcasting communication takes precedence over individual communication (communication from one unit to another). <2> the lower master address takes precedence. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 437 (6) communication scale the communication scale of iebus is as follows: ? number of units: 50 max. ? cable length: 150 m max. (when twisted pair cable is used) caution the communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the iebus driver/receiver and iebus. 19.1.2 determination of bus mastership (arbitration) an operation to occupy the bus is performed when a unit connected to the iebus controls the other units. this operation is called arbitration. when two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus. because only one unit is granted the bus mastership as a result of arbitration, the priority conditions of the bus are predetermined as follows: caution the bus mastership is released if communication is aborted. (1) priority by communication type broadcasting communication (communication from one unit to plural units) takes precedence over normal communication (communication from one unit to another). (2) priority by master address if the communication type is the same, communication with the lower master address takes precedence. a master address consists of 12 bits, with unit 000h having the highest priority and unit fffh having the lowest priority. 19.1.3 communication mode although the iebus has three communication modes each having a different transfer rate, the v850/sb2 supports only communication mode 1. the transfer rate and the maximum number of transfer bytes in one communication frame in communication mode 1 are as shown in table 19-1. table 19-1. transfer rate and maximum number of transfer bytes in communication mode 1 communication mode maximum number of transfer bytes (bytes/frame) effective transfer rate (kbps) note 1 32 approx. 17 note the effective transfer rate when the maximum number of transfer bytes is transmitted. select the communication mode (mode 1) for each unit connected to the iebus before starting communication. if the communication mode of the master unit and that of the partner unit (slave unit) are not the same, communication is not correctly executed. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 438 19.1.4 communication address with the iebus, each unit is assigned a specific 12-bit address. this communication address consists of the following identification numbers: ? higher 4 bits: group number (number to identify the group to which each unit belongs) ? lower 8 bits: unit number (number to identify each unit in a group) 19.1.5 broadcasting communication normally, transmission or reception is performed between the master unit and its partner slave unit on a one-to- one basis. during broadcasting communication, however, two or more slave units exist and the master unit executes transmission to these slave units. because plural slave units exist, the slave units do not return an acknowledge signal during communication. whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit (for this bit, refer to 19.1.6 (2) broadcasting bit ). broadcasting communication is classified into two types: group-unit broadcasting communication and all-unit broadcasting communication. group-unit broadcasting and all-unit broadcasting are identified by the value of the slave address (for the slave address, refer to 19.1.6 (4) slave address field ). (1) group-unit broadcasting communication broadcasting communication is performed to the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) all-unit broadcasting communication broadcasting communication is performed to all the units, regardless of the value of the group number. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 439 19.1.6 transfer format of iebus figure 19-1 shows the transfer signal format of the iebus. figure 19-1. iebus transfer signal format header master address field slave address field control field telegraph length field data field start bit broad- casting bit master address bit p frame format slave address bit pa control bit pa tele- graph length bit pa data bit pa data bit pa remarks 1. p: parity bit, a: ack/nack bit 2. the master station ignores the acknowledge bit during broadcasting communication. (1) start bit the start bit is a signal that informs the other units of the start of data transfer. the unit that is to start data transfer outputs a high-level signal (start bit) from the ietx pin for a specific time, and then starts outputting the broadcasting bit. if another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. when the output of the start bit by the other unit is complete, the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit. the units other than the one that has started communication detect this start bit, and enter the reception status. (2) broadcasting bit this bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcasting communication) as the other party of communication. when the broadcasting bit is 0, it indicates broadcasting communication; when it is 1, individual communication is indicated. broadcasting communication is classified into two types: group-unit communication and all-unit communication. these communication types are identified by the value of the slave address (for the slave address, refer to 19.1.6 (4) slave address field ). because two or more slave units exist in the case of broadcasting communication, the acknowledge bit in each field subsequent to the master address field is not returned. if two or more units start transmitting a communication frame at the same time, broadcasting communication takes precedence over individual communication, and wins in arbitration. if one station occupies the bus as the master, the value set to the broadcasting request bit (allrq) of the iebus control register (bcr) is output. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 440 (3) master address field the master address field is output by the master to inform a slave of the master?s address. the configuration of the master address field is as shown in figure 19-2. if two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration. the master address field compares the data it outputs with the data on the bus each time it has output one bit. if the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. as a result, the master stops transmission and enters the reception status. because the iebus is configured of wired and, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. after a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. if one unit occupies the bus as the master, the address set by the iebus unit address register (uar) is output. figure 19-2. master address field master address field master address (12 bits) msb lsb parity chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 441 (4) slave address field the master outputs the address of the unit with which it is to communicate. figure 19-3 shows the configuration of the slave address field. a parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. when the master has detected the acknowledge signal, it starts outputting the control field. during broadcasting communication, however, the master does not detect the acknowledge bit but starts outputting the control field. the slave unit outputs the acknowledge signal if its slave address coincides and if the slave detects that the parities of both the master address and slave address are even. the slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. at this time, the master unit is in the standby (monitor) status, and communication ends. during broadcasting communication, the slave address is used to identify group-unit broadcasting or all-unit broadcasting, as follows: if slave address is fffh: all-unit broadcasting communication if slave address is other than fffh: group-unit broadcasting communication remark the group no. during group-unit broadcasting communication is the value of the higher 4 bits of the slave address. if one unit occupies the bus as the master, the address set by the slave address register (sar) is output. figure 19-3. slave address field slave address field unit no. msb lsb ack parity slave address (12 bits) group no. (5) control field the master outputs the operation it requires the slave to perform, by using this field. the configuration of the control field is as shown in figure 19-4. if the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. if the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. the master unit starts outputting the telegraph field after confirming the acknowledge signal. if the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. during broadcasting communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. table 19-2 shows the contents of the control bits. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 442 table 19-2. contents of control bits bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 reads slave status 0 0 0 1 undefined 0 0 1 0 undefined 0011 reads data and locks note 2 0100 reads lock address (lower 8 bits) note 3 0101 reads lock address (higher 4 bits) note 3 0110 reads slave status and unlocks note 2 0 1 1 1 reads data 1 0 0 0 undefined 1 0 0 1 undefined 1010 writes command and locks note 2 1011 writes data and locks note 2 1 1 0 0 undefined 1 1 0 1 undefined 1 1 1 0 writes command 1 1 1 1 writes data notes 1. the telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (msb). if bit 3 is ?1?: transfer from master unit to slave unit if bit 3 is ?0?: transfer from slave unit to master unit 2. this is a control bit that specifies locking or unlocking (refer to 19.1.7 (4) locking and unlocking ). 3. the lock address is transferred in 1-byte (8-bit) units and is configured as follows: msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 443 if the control bit received from the master unit is not as shown in table 19-3, the unit locked by the master unit rejects acknowledging the control bit, and does not output the acknowledge bit. table 19-3. control field for locked slave unit bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 reads slave status 0 1 0 0 reads lock address (lower 8 bits) 0 0 0 1 reads lock address (higher 4 bits) moreover, units for which lock is not set by the master unit reject acknowledgement and do not output an acknowledge bit when the control data shown in table 19-4 is acknowledged. table 19-4. control field for unlocked slave unit bit 3 bit 2 bit 1 bit 0 function 0 1 0 0 lock address read (lower 8 bits) 0 1 0 1 lock address read (higher 4 bits) if one unit occupies the bus as the master, the value set to the iebus control register (cdr) is output. figure 19-4. control field msb lsb ack parity control bit (4 bits) control field chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 444 table 19-5. acknowledge signal output condition of control field (a) if received control data is ah, bh, eh, or fh received control data communication target (slvrq) slave specification = 1 no specification = 0 lock status (lock) lock = 1 unlock = 0 master unit identification (match with par) lock request unit = 1 other = 0 slave transmission enable (enslvtx) slave reception enable (enslvrx) ah bh eh fh 0 don?t care 1 11 don?t care 1 { other than above (b) if received control data is 0h, 3h, 4h, 5h, 6h, or 7h received control data communication target (slvrq) slave specification = 1 no specification = 0 lock status (lock) lock = 1 unlock = 0 master unit identification (match with par) lock request unit = 1 other = 0 slave transmission enable (enslvtx) slave reception enable (enslvrx) 0h 3h 4h 5h 6h 7h 0 { { 0 1 { { { { don?t care { { { don?t care { { { { 1 1 1 1 don?t care { { { { { { other than above caution if the received control data is other than the data shown in table 19-5, (ack is not returned) is unconditionally assumed. remarks 1. { : ack is returned. : ack is not returned. 2. enslvtx: bit 4 of the iebus unit control register (bcr) enslvrx: bit 3 of the iebus unit control register (bcr) lock: bit 2 of the iebus unit status register (usr) slvrq: bit 6 of the iebus unit status register (usr) par: iebus partner address register chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 445 (6) telegraph length field this field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. the configuration of the telegraph length field is as shown in figure 19-5. table 19-6 shows the relationship between the telegraph length bit and the number of transmit data. figure 19-5. telegraph length field msb lsb telegraph length field telegraph length bit (8 bits) parity ack table 19-6. contents of telegraph length bit telegraph length bit (hex) number of transmit data bytes 01h 02h | ffh 00h 1 byte 2 bytes | 255 bytes 256 bytes the operation of the telegraph length field differs depending on whether the master transmits data (when control bit 3 is 1) or receives data (when control bit 3 is 0). (a) when master transmits data the telegraph length bit and parity bit are output by the master unit and the synchronization signals of bits are output by the master unit. when the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. during broadcasting communication, however, the slave unit does not output the acknowledge signal. if the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. at this time, the master unit also returns to the standby status, and communication ends. (b) when master receives data the telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. if the master unit detects that the parity bit is even, it outputs the acknowledge signal. if the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby status. at this time, the slave unit also returns to the standby status, and communication ends. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 446 (7) data field this is data output by the transmission side. the master unit transmits or receives data to or from a slave unit by using the data field. the configuration of the data field is as shown below. figure 19-6. data field data field (number specified by telegraph length field) msb lsb one data ack parity control bit (8 bits) ack parity following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. use broadcasting communication only for when the master unit transmits data. at this time, the acknowledge bit is ignored. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 447 the operation differs as follows depending on whether the master transmits or receives data. (a) when master transmits data when the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. if the parity is even and the receive data is not stored in the iebus data register (dr) when the slave unit has received the data bit and parity bit, the slave unit outputs an acknowledge signal. if the parity is odd or if the receive data is stored in the iebus data register (dr), the slave unit rejects receiving the data, and does not output the acknowledge signal. if the slave unit does not output the acknowledge signal, the master unit transmits the same data again. this operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. if the data has continuation and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. during broadcasting communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. if the parity is odd or the dr register is storing receive data after the slave unit has received the data bit and parity bit during broadcasting communication, the slave unit judges that reception has not been performed correctly, and stops reception. (b) when master receives data when the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. the slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. the master unit reads the data and parity bits output by the slave unit, and checks the parity. if the parity is odd, or if the dr register is storing a receive data, the master unit rejects accepting the data, and does not output the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. if the parity is even and the dr register is not storing a receive data, the master unit accepts the data and returns the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. caution do not operate master reception in broadcasting communication, because the slave unit cannot be defined and data transfer cannot be performed correctly. (8) parity bit the parity bit is used to check to see if the transmit data has no error. the parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. the parity is an even parity. if the number of bits in data that are ?1? is odd, the parity bit is ?1?. if the number of bits in the data that are ?1? is even, the parity bit is ?0?. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 448 (9) acknowledge bit during normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. ? end of slave address field ? end of control field ? end of telegraph length field ? end of data field the definition of the acknowledge bit is as follows: ? 0: indicates that the transmit data is recognized (ack). ? 1: indicates that the transmit data is not recognized (nack). during broadcasting communication, however, the contents of the acknowledge bit are ignored. (a) last acknowledge bit of slave field the last acknowledge bit of the slave field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the master address bit or slave address bit is incorrect ? if a timing error (error in bit format) occurs ? if a slave unit does not exist (b) last acknowledge bit of control field the last acknowledge bit of the control field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the control bit is incorrect ? if control bit 3 is ?1? (write operation) when the slave reception enable flag (enslvrx) is not set (1) note ? if the control bit indicates reading of data (3h or 7h) when the slave transmission enable flag (enslvtx) is not set (1) note ? if a unit other than that has set locking requests 3h, 6h, 7h, ah, bh, eh, or fh of the control bit when locking is set ? if the control bit indicates reading of lock addresses (4h, 5h) even when locking is not set ? if a timing error occurs ? if the control bit is undefined note refer to 19.3.2 (1) iebus control register (bcr) . cautions 1. even when the slave transmission enable flag (enslvtx) is not set (1), ack is always returned if slave status request control data is received. 2. even when slave reception enable flag (enslvrx) is not set (1), nack is always returned by the acknowledge bit in the control field if data/command writing control data is acknowledged. slave reception can be disabled (communication stopped) by enslvrx flag only in the case of independent communication. in the case of broadcasting communication, communication is maintained and the data request interrupt (intie1) or iebus end interrupt (intie2) is generated. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 449 (c) last acknowledge bit of telegraph length field the last acknowledge bit of the telegraph length field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the telegraph length bit is incorrect ? if a timing error occurs (d) last acknowledge bit of data field the last acknowledge bit of the data field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the data bit is incorrect note ? if a timing error occurs after the preceeding acknowledge bit has been transmitted ? if the receive data is stored in the iebus data register (dr) and no more data can be received note note in this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. for broadcasting communication, the transmission side does not execute transmission again, a communication error occurs on the reception side and reception stops. 19.1.7 transfer data (1) slave status the master unit can learn why the slave unit did not return the acknowledge bit (ack) by reading the slave status. the slave status is determined according to the result of the last communication the slave unit has executed. all the slave units can supply information on the slave status. the configuration of the slave status is shown below. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 450 figure 19-7. bit configuration of slave status msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 note 1 meaning 0 transmit data is not written in iebus data register (dr) 1 transmit data is written in iebus data register (dr) bit 1 note 2 meaning 0 receive data is not stored in iebus data register (dr) 1 receive data is stored in iebus data register (dr) bit 2 meaning 0 unit is not locked 1 unit is locked bit 3 meaning 0 fixed to 0 bit 4 note 3 meaning 0 slave transmission is stopped 1 slave transmission is ready bit 5 meaning 0 fixed to 0 bit 7 bit 6 meaning 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 not used indicates the highest mode supported by unit note 4 . notes 1. after reset: bit 0 is set to 1. 2. the receive buffer size is 1 byte. 3. when the v850/sb2 serves as a slave unit, this bit corresponds to the status indicated by bit 4 (enslvtx) of the iebus control register (bcr). 4. when the v850/sb2 serves as a slave unit, bits 7 and 6 are fixed to ?0? and ?1? (mode 1), respectively. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 451 (2) lock address when the lock address is read (control bit: 4h or 5h), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. figure 19-8. configuration of lock address msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb (3) data if the control bit indicates reading of data (3h or 7h), the data in the data buffer of the slave unit is read by the master unit. if the control bit indicates writing of data (bh or fh), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) locking and unlocking the lock function is used when a message is transferred in two or more communication frames. the unit that is locked does not receive data from units other than the one that has locked the unit (does not receive broadcasting communication). a unit is locked or unlocked as follows: (a) locking if the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ack = 0) by the control bit that specifies locking (3h, ah, or bh), the slave unit is locked by the master unit. at this time, the bit (bit 2) in the byte indicating the slave status is set to ?1?. (b) unlocking after transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3h, ah, or bh), or the control bit that has specified unlocking (6h), the slave unit is unlocked by the master unit. at this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to ?0?. locking or unlocking is not performed during broadcasting communication. locking and unlocking conditions are shown below. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 452 (c) lock setting conditions broadcasting communication individual communication control data communication end frame end communication end frame end 3h, 6h note cannot be locked lock set ah, bh cannot be locked cannot be locked cannot be locked lock set 0h, 4h, 5h, eh, fh cannot be locked cannot be locked cannot be locked cannot be locked (d) unlock release conditions (while locked) broadcasting communication from lock request unit individual communication from lock request unit control data communication end frame end communication end frame end 3h, 6h note unlocked remains locked ah, bh unlocked unlocked unlocked remains locked 0h, 4h, 5h, eh, fh remains locked remains locked remains locked remains locked note the frame end of control data 6h (slave status read/unlock) occurs when the parity in the data field is odd, and when the acknowledge signal from the iebus unit is repeated up to the maximum number of transfer bytes without being output. 19.1.8 bit format the format of the bits constituting the communication frame of the iebus is shown below. figure 19-9. bit format of iebus logic ?1? logic ?0? preparation period synchronization period data period stop period preparation period: first low-level (logic ?1?) period synchronization period: next high-level (logic ?0?) period data period: period indicating value of bit stop period: last low-level (logic ?1?) period the synchronization period and data period are almost equal to each other in length. the iebus synchronizes each bit. the specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. the master and slave units monitor whether each period (preparation period, synchronization period, data period, and stop period) is output for specified time while they are in communication. if a period is not output for the specified time, the master and slave units report a timing error, immediately terminate communication and enter the standby status. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 453 19.2 iebus controller configuration the block diagram of the iebus controller is shown below. figure 19-10. iebus controller block diagram bcr(8 ) uar ( 12 ) sar ( 12 ) par ( 12 ) cdr ( 8) dlr ( 8) dr ( 8 ) usr(8 ) isr ( 8 ) ssr(8 ) scr(8 ) ccr(8 ) 81212 8 8 8 8 12 8 8 8 888 888 88 8 nf rx tx mpx mpx 12-bit latch comparator contention detection ack generation parity generation error detection tx/rx interrupt controller interrupt control block int request ? ? ? ? ? ? ? cpu interface block internal registers (handler, dma transfer) iebus interface block clk bit processing block field processing block internal bus r/w psr (8 bits) 8 5 8 12 12 12 internal bus 8 12 (1) hardware configuration and function the iebus mainly consists of the following six internal blocks. ? cpu interface block ? interrupt control block ? internal registers ? bit processing block ? field processing block ? iebus interface block chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 454 (a) cpu interface block this is a control block that interfaces between the cpu (v850/sb2) and iebus. (b) interrupt control block this control block transfers interrupt request signals from iebus to the cpu. (c) internal registers these registers set data to the control registers and fields that control iebus (for the internal registers, refer to 19.3 internal registers of iebus controller ). (d) bit processing block this block generates and disassembles bit timing, and mainly consists of a bit sequence rom, 8-bit preset timer, and comparator. (e) field processing block this block generates each field in the communication frame, and mainly consists of a field sequence rom, 4-bit down counter, and comparator. (f) iebus interface block this is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, collision detector, parity detector, parity generator, and ack/nack generator. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 455 19.3 internal registers of iebus controller 19.3.1 internal register list table 19-7. internal registers of iebus controller bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff3e0h iebus control register bcr ? ? 00h fffff3e2h iebus unit address register uar ? ? fffff3e4h iebus slave address register sar r/w ?? fffff3e6h iebus partner address register par r ? ? 0000h fffff3e8h iebus control data register cdr ? ? fffff3eah iebus telegraph length register dlr ? ? 01h fffff3ech iebus data register dr r/w ? ? fffff3eeh iebus unit status register usr r ? ? fffff3f0h iebus interrupt status register isr r/w ? ? 00h fffff3f2h iebus slave status register ssr ? ? 41h fffff3f4h iebus communication success counter scr ? ? 01h fffff3f6h iebus transmit counter ccr r ? ? 20h fffff3f8h iebus clock selection register ieclk r/w ? ? 00h chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 456 19.3.2 internal registers the internal registers incorporated in the iebus controller are described below. (1) iebus control register (bcr) figure 19-11. iebus control register (bcr) after reset: 00h rw address: fffff3e0h <7> <6> <5> <4> <3> 2 1 0 bcr eniebus mstrq allrq enslvtx enslvrx 0 0 0 eniebus communication enable flag 0 iebus unit stopped 1 iebus unit active mstrq master request flag 0 iebus unit not requested as master 1 iebus unit requested as master allrq broadcast request flag 0 individual communication requested 1 broadcasting communication requested enslvtx slave transmission enable flag 0 slave transmission disabled 1 slave transmission enabled enslvrx slave reception enable flag 0 slave reception disabled 1 slave reception enabled cautions 1. while the iebus is operating as the master, writing to the bcr register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. master requests cannot therefore be multiplexed. however, if the iebus is specified as a slave while a master request is being held pending, the bcr can be written to at the end of communication to clear the communication end/frame end flag. this is also the case when communication has been forcibly stopped (eniebus flag = 0). 2. if a bit manipulation instruction for the bcr register conflicts with a hardware reset of the mstrq flag, the bcr register may not operate normally. the following countermeasures are recommended in this case. ? ? ? ? because the hardware reset is instigated in the acknowledgement period of the slave address field, be sure to observe caution 1 of (b) master request flag (mstrq) below. ? ? ? ? be sure to observe the caution above regarding writing to the bcr register. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 457 (a) communication enable flag (eniebus)...bit 7 chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 458 (d) slave transmission enable flag (enslvtx)...bit 4 chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 459 (2) iebus unit address register (uar) this register sets the unit address of an iebus unit. this register must be always set before starting communication. sets the unit address (12 bits) to bits 11 to 0. figure 19-12. iebus unit address register (uar) format 15 0 14 0 13 0 12 0 uar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e2h after reset 0000h r/w r/w (3) iebus slave address register (sar) during master request, the value of this register is reflected in the value of the transmit data in the slave address field. this register must be always set before starting communication. sets the slave address (12 bits) to bits 11 to 0. figure 19-13. iebus slave address register (sar) format 15 0 14 0 13 0 12 0 sar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e4h after reset 0000h r/w r/w chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 460 (4) iebus partner address register (par) (a) when slave unit the value of the receive data in the master address field (address of the master unit) is written to this register. if a request ?4h? to read the lock address (lower 8 bits) is received from the master, the cpu must read the value of this register, and write it to the lower 8 bits iebus data register (dr). if a request ?5h? to read the lock address (higher 4 bits) is received from the master, the cpu must read the value of this register and write the data of the higher 4 bits to dr. sets the partner address (12 bits) to bits 11 to 0. figure 19-14. iebus partner address register (par) format 15 0 14 0 13 0 12 0 par 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e6h after reset 0000h r/w r (5) iebus control data register (cdr) (a) when master unit the data of the lower 4 bits is reflected in the data transmitted in the control field. during master request, this register must be set in advance before starting communication. (b) when slave unit the data received in the control field is written to the lower 4 bits. when the status transmission flag (status) of the iebus interrupt status register (isr) is set, an interrupt (intie2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of cdr. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 461 figure 19-15. iebus control data register (cdr) format after reset: 01h r/w address: fffff3e8h 76543210 cdr0000modselcl2selcl1selcl0 mod selcl2 selcl1 selcl0 function 0 0 0 0 reads slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 reads data and locks 0 1 0 0 reads lock address (lower 8 bits) 0 1 0 1 reads lock address (lower 4 bits) 0 1 1 0 reads slave status and unlocks 0 1 1 1 reads data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 writes command and locks 1 0 1 1 writes data and locks 1 1 0 0 undefined 1 1 0 1 undefined 1 1 1 0 writes command 1 1 1 1 writes data cautions 1. because the slave unit must judge whether the received data is a ?command? or ?data?, it must read the value of this register after completing communication. 2. if the master unit sets an undefined value, nack is returned from the slave unit, and communication is aborted. during broadcasting communication, however, the master unit continues communication without recognizing ack/nack; therefore, make sure not to set an undefined value to this register during broadcasting communication. 3. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, the telegraph length register (dlr) is fixed to ?01h?. therefore, when a re-request of the master follows, the appointed telegraph length must be set to dlr. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 462 (c) slave status return operation when the iebus receives a request to transfer from master to slave status or a lock address request (control data: 0h, 6h), whether ack in the control field is returned or not depends on the status of the iebus unit. (1) if 0h or 6h control data was received in the unlocked state ack returned (2) if 4h or 5h control data was received in the unlocked state ack not returned (3) if 0h, 4h, 5h or 6h control data was received in the locked state from the unit that sent the lock request ack returned (4) if 0h, 4h, or 5h control data was received in the locked state from other than the unit that sent the lock request ack returned (5) if 6h control data was received in the locked state from other than the unit that sent the lock request ack not returned in all of the above cases, the acknowledgement of a slave status or lock request will cause the statusf flag (bit 4 of the isr register) to be set and the status interrupt (intie2) to be generated. the generation timing is at the end of the control field parity bit (at the start of the ack bit). however, if ack is not returned, a nack error is generated after the ack bit, and communication is terminated. figure 19-16. interrupt generation timing (for (1), (3), and (4)) intie2 flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing control field telegraph length field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) telegraph length bits (8 bits) chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 463 figure 19-17. interrupt generation timing (for (2) and (5)) intie2 flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing error generated by detection of nack control field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) terminated by communication error because in (4) and (5) the communication was from other than the unit that sent the lock request while the iebus was in the locked state, the start or communication complete interrupt (intie2) is not generated, even if the iebus unit is the communication target. the statusf flag (bit 4 of the isr register) is set and the status interrupt (intie2) generated, however, if a slave status or lock address request is acknowledged. note that even if the same control data is received while the iebus is in the locked state, the interrupt generation timing for intie2 differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. figure 19-18. timing of intie2 interrupt generation in locked state (for (4) and (5)) intie2 iebus sequence status interrupt start master address (12 + p) broad- casting slave address (12 + p + a) control (4 + p + a) telegraph length note (8 + p + a) data note (8 + p + a) note the telegraph length and data modes are not set in the case of (5) because ack is not returned. remark p: parity bit, a: ack/nack bit chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 464 figure 19-19. timing of intie2 interrupt generation in locked state (for (3)) intie2 iebus sequence status interrupt start master address (12 + p) broad- casting slave address (12 + p + a) control (4 + p + a) telegraph length (8 + p + a) communication complete interrupt data (8 + p + a) start interrupt remark p: parity bit, a: ack/nack bit (6) iebus telegraph length register (dlr) (a) when transmission unit ... master transmission, slave transmission the data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. this register must be set in advance before transmission. (b) when reception unit ... master reception, slave reception the receive data in the telegraph length field transmitted from the transmission unit is written to this register. remark the iebus telegraph length register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 465 figure 19-20. iebus telegraph length register (dlr) format after reset: 01h r/w address: fffff3eah 76543210 dlr bit 76543210 setting value remaining number of communication data bytes 00000001 01h 1 byte 00000010 02h 2 bytes :::::::: : : 00100000 20h 32 bytes :::::::: : : 11111111 ffh 255 bytes 00000000 00h 256 bytes cautions 1. if the master issues a request ?0h, 4h, 5h, or 6h? to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to ?01h? by hardware; therefore, the cpu does not have to set this register. 2. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, dlr is fixed to ?01h?. therefore, if a re-request of the master follows, the appointed telegraph length must be set to dlr. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 466 (7) iebus data register (dr) the iebus data register (dr) sets the communication data. sets the communication data (8 bits) to bits 7 to 0. remark the iebus data register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. (a) when transmission unit the data (1 byte) written to the iebus data register (dr) is stored to the iebus interface shift register of the iebus. it is then output from the most significant bit, and an interrupt (intie1) is issued to the cpu each time 1 byte has been transmitted. if nack is received after 1-byte data has been transferred during individual transfer, data is not transferred from dr to the shift register, and the same data is retransmitted. at this time, intie1 is not generated. intie1 is issued when the iebus interface shift register stores the iebus data register value. however, when the last byte and 32nd byte (the last byte of 1 communication frame) is stored in the shift register, intie1 is not issued. (b) when reception unit one byte of the data received by the shift register of the iebus interface block is stored to this register. each time 1 byte has been correctly received, an interrupt (intie1) is issued. when transmit/receive data is transferred to and from the iebus data register, using dma can reduce the cpu processing load. figure 19-21. iebus data register (dr) format after reset: 00h r/w address: fffff3ech 76543210 dr cautions 1. if the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (intie2) occurs, stopping transmission. 2. when the iebus is a receiving unit, if the reading of the data is too late for the next data reception timing, the unit will enter the overrun state. at this time, during individual communication reception, nack will be returned at the acknowledge bit of the data field, and the master unit will be requested to retransmit the data. if an overrun error occurs during broadcasting communication, the communication error interrupt (intie2) is generated. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 467 (8) iebus unit status register (usr) figure 19-22. iebus unit status register (usr) after reset: 00h r address: fffff3eeh 7 <6> <5> <4> <3> <2> 1 0 usr 0 slvrq arbit alltrns ack lock 0 0 slvrq slave request flag 0 no request from master to slave 1 request from master to slave arbit arbitration result flag 0 arbitration win 1 arbitration loss alltrns broadcasting communication flag 0 individual communication status 1 broadcasting communication status ack ack transmission flag 0 nack transmitted 1 ack transmitted lock lock status flag 0 unit unlocked 1 unit locked (a) slave request flag (slvrq)...bit 6 a flag indicating whether there has been a slave request from the master. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 468 (b) arbitration result flag (arbit)...bit 5 a flag that indicates the result of arbitration. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 469 (e) lock status flag (lock)...bit 2 a flag that indicates whether the unit is locked. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 470 (9) iebus interrupt status register (isr) this register indicates the status when iebus issues an interrupt. the isr is read to generate an interrupt, after which the specified interrupt processing is carried out. reset the isr register after reading it. until it is reset, the intie2 interrupt signal is not generated (nor held pending). to reset the isr register, reset each flag, satisfying the reset conditions in table 19-8. table 19-8. reset conditions of flags in isr register flag name reset condition processing example ieerr, startf, statusf byte write operation of isr register. any value can be written. isr = 00h, etc. endtrns, endfram set mstrq, enslvtx, or enslvrx flag. bcr register = 88h or enslvtx = 1, etc. caution even if 0 is written to the endtrns or endfram flag by accessing the isr register, these flags are not reset. reset them as described above. remark mstrq: bit 6 of the iebus control register (bcr) enslvtx: bit 4 of the iebus control register (bcr) enslvrx: bit 3 of the iebus control register (bcr) chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 471 figure 19-24. iebus interrupt status register (isr) after reset: 00h r/w address: fffff3f0h 7 <6> <5> <4> <3> <2> 1 0 isr 0 ieerr startf statusf endtrns endfram 0 0 ieerr communication error flag (during communication) 0 no communication error 1 communication error startf start interrupt flag 0 start interrupt does not occur 1 start interrupt occurs statusf status transmission flag (slave) 0 no slave status/lock address (higher 4 bits, lower 8 bits) transmission request 1 slave status/lock address (higher 4 bits, lower 8 bits) transmission request endtrns communication end flag 0 communication does not end after the number of bytes set in the telegraph length field have been transferred 1 communication ends after the number of bytes set in the telegraph length field have been transferred endfram frame end flag 0 the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) does not end 1 the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) ends caution each of ieerr, startf, statusf, endtrns, and endfram are generation triggers for the interrupt request signal (intie2) (see figure 19-29). because of this, if any one of these interrupt triggers have been set, no new interrupt will be generated by a subsequent trigger. clear the flag of the interrupt source by the interrupt processing program, before the next interrupt occurs. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 472 (a) communication error flag (ieerr)...bit 6 a flag that indicates the detection of an error during communication. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 473 (f) communication error triggers ? timing error occurrence conditions: occurs if the high/low level width of the communication bit has shifted from the prescribed value. remark: the respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer. an interrupt is generated when a timing error occurs. ? parity error occurrence conditions: occurs if the generated parity and the received parity in each field do not match when iebus is a receiving unit. remark: during individual communication, an interrupt is generated if a parity error occurs in a field other than the data field. during broadcasting communication, an interrupt is generated even if a parity error occurs in the data field. restriction: if there is a slave request that has lost in arbitration to a broadcast request, no interrupt is generated, even if a parity error occurs. ? nack reception error occurrence conditions: this error occurs when nack is received during the ack period in each of the slave address, control, and telegraph length fields during individual communication, regardless of whether the unit is the master or a slave unit. a nack reception error only occurs in individual communication. ack and nack are not discriminated in broadcasting communication. remark: an interrupt is generated if nack is received in a field other than the data field. ? underrun occurrence conditions: occurs during data transmission if there was insufficient time to write the next transmit data to the iebus data register (dr) before ack reception. remark: an interrupt is generated if an underrun occurs. ? overrun occurrence conditions: the data interrupt request (intie1) that stores each byte of data in the iebus data register (dr), and the dr register is read by dma or software. an overrun error occurs if this reading processing is late and its timing becomes that of the next data reception. remark: in individual communication reception, an acknowledgement is not returned in the ack period of this data, resulting in the retransmission of the data by the transmit unit. consequently, the iebus transfer counter (ccr) is decremented, whereas the iebus communication success counter (scr) is not. in broadcasting communication reception, reception is stopped by the occurrence of a communication error (intie2), at which time the dr register is not updated. the statrx flag (bit 1 of the ssr register) also remains set (1) without generating intie1. the overrun state is released at the timing of the next data reception following the reading of dr. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 474 (g) overrun error - supplementary details (i) when the frame ends in the overrun state during individual communication reception if the dr register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (intie2) is generated. the overrun state is maintained until the dr register is read after the end of the frame. (ii) if the next reception is started in the case of (i) above, or if the next reception is started without the dr register being read after the final data has been received, regardless of whether the communication is broadcasting or individual even if communication to the iebus unit starts in the overrun state, the cause of the overrun, nack, is not returned in the ack period of the slave address, control, or telegraph length field (the dr register is not updated). if the next communication is not to the iebus unit, the dr register is not updated until it is read. because the iebus unit is not a communication target, the data interrupt (intie1) and communication error interrupt (intie2) are not generated. (iii) if the next transmission occurs in the overrun state the data to be transmitted next in the overrun state can be no more than 2 bytes long. because the data request interrupt (intie1) is not generated, the transmit data cannot be set, resulting in an underrun error. therefore, clear the overrun status before starting transmission. (iv) overrun state release the overrun state can only be released by reading the dr register or by a system reset. therefore, be sure to read dr in a communication error interrupt processing program. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 475 (10)iebus slave status register (ssr) this register indicates the communication status of the slave unit. after receiving a slave status transmission request from the master, the cpu reads this register, and writes a slave status to the iebus data register (dr) to transmit the slave status. at this time, the telegraph length is automatically set to ?01h? that setting of the iebus telegraph length register (dlr) is not required (because it is preset by hardware). bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to ?01h? (mode 1). figure 19-25. iebus slave status register (ssr) format after reset: 41h r address: fffff3f2h 7 6 5 <4> 3 <2> <1> <0> ssr 0 1 0 statslv 0 statlock statrx stattx statslv slave transmission status flag 0 slave transmission stops 1 slave transmission enabled statlock lock status flag 0 unlock status 1 lock status statrx dr receive status 0 receiving data not stored in dr 1 receiving data stored in dr stattx dr transmit status 0 transmission data not stored in dr 1 transmission data stored in dr (a) slave transmission status flag (statslv)...bit 4 reflects the contents of slave transmission enable flag. (b) lock status flag (statlock)...bit 2 reflects the contents of locked flag. (c) dr reception status (statrx)...bit 1 this flag indicates the dr reception state. (d) dr transmission status (stattx)...bit 0 this flag indicates the dr transmission state. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 476 (11)iebus success count register (scr) the iebus success count register (scr) indicates the number of remaining communication bytes. this register reads the count value of the counter that decrements the value set by the telegraph length register by ack in the data field. when the count value has reached ?00h?, the communication end flag (endtrns) of the iebus interrupt status register (isr) is set. figure 19-26. iebus success count register (scr) format after reset: 01h r address: fffff3f4h 76543210 scr bit 76543210 setting value remaining number of communication data bytes 00000001 01h 1 byte 00000010 02h 2 bytes :::::::: : : 00100000 20h 32 bytes :::::::: : : 11111111 ffh 255 bytes 00000000 00h 0 byte ( end of communication) or 256 bytes note note the actual hard counter consists of 9 bits. when ?00h? is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. therefore, either the communication end flag is used, or if ?00h? is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 477 (12)iebus communication count register (ccr) the iebus communication count register (ccr) indicates the number of remaining bytes in the communication byte number specified in the communication mode. bits 7 to 0 of the iebus communication count register (ccr) indicate the number of transfer bytes. this register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1. whereas scr (iebus communication success counter) is decremented during normal communication (ack), ccr is decremented when 1 byte has been communicated, regardless of whether ack or nack.w hen the c ount value has reached ?00h?, the frame end flag (endfram) is set. the maximum number of transfer bytes of the preset value of mode 1 per frame is 20h (32 bytes). figure 19-27. iebus communication count register (ccr) format after reset: 20h r address: fffff3f6h 76543210 ccr (13)iebus clock selection register (ieclk) this register selects the clock of iebus. the main clock frequencies that can be used are shown below. main clock frequencies other than the following cannot be used. ? 6.0 mhz/6.291 mhz ? 12.0 mhz/12.582 mhz figure 19-28. iebus clock selection register (ieclk) format after reset: 00h r/w address: fffff3f8h 76543210 ieclk00000 0 0iecs iecs iebus clock selection 0@ f xx = 6.0 mhz or f xx = 6.291 mhz 1@ f xx = 12.0 mhz or f xx = 12.582 mhz chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 478 19.4 interrupt operations of iebus controller 19.4.1 interrupt control block interrupt request signal <1> communication error ieerr <2> start interrupt startf <3> status communication statusf <4> end of communication endtrns <5> end of frame endfram <6> transmit data write request stattx <7> receive data read request statrx 1 through 5 of the above interrupt requests are assigned to the interrupt status register (isr). for details, refer to table 19-9 interrupt source list . the configuration of the interrupt control block is illustrated below. figure 19-29. configuration of interrupt control block ieerr startf statusf endtrns endfram stattx statrx iebus macro interrupt control block v850/sb2 cpu intie1 intie2 cautions 1. or output of statrx and stattx is treated as a dma transfer start signal (intie1). 2. or output of ieerr, startf, statusf, endtrns, and endfram is treated as a vector interrupt request signal (intie2) for v850/sb2. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 479 19.4.2 interrupt source list the interrupt request signals of the internal iebus controller in the v850/sb2 can be classified into vector interrupts and dma transfer interrupts. these interrupt request signals can be specified through software manipulation. the interrupt sources are listed below. table 19-9. interrupt source list condition of generation interrupt source unit field cpu processing after generation of interrupt remark timing error master/slave all fields other than data (individual) parity error reception all fields (broadcasting) nack reception reception (transmission) other than data (individual) underrun error transmission data communication error overrun error reception data (broadcasting) undo communication processing communication error is or output of timing error, parity error, nack reception, underrun error, and overrun error master slave/address slave request judgment contention judgment (if loses, remaster processing) communication preparation processing interrupt always occurs if loses in contention during master request start interrupt slave slave/address slave request judgment communication preparation processing generated only during slave request status transmission slave control refer to transmission processing example such as slave status. interrupt occurs regardless of slave transmission enable flag interrupt occurs if nack is returned in the control field. transmission data dma transfer end processing end of communication reception data dma transfer end processing receive data processing set if scr is cleared to 0 transmission data retransmission preparation processing end of frame reception data re-reception preparation processing set if ccr is cleared to 0 transmit data write transmission data reading of transmit data note . set after transfer transmission data to internal shift register this does not occur when the last data is transferred. receive data read reception data reading of received data note set after normal data reception note if dma transfer or software manipulation is not executed. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 480 19.4.3 communication error source processing list the following table shows the occurrence conditions of the communication errors (timing error, nack reception error, overrun error, underrun error, and parity error), error processing by the internal iebus controller, and examples of processing by software. table 19-10. communication error source processing list (1/2) timing error unit status reception transmission occurrence condition if bit specification timing is not correct occurrence condition location of occurrence other than data field data field other than data field data field hardware processing ? reception stops. ? intie2 occurs ? to start bit waiting status remark communication between other units does not end. ? transmission stops. ? intie2 occurs ? to start bit waiting status broadcasting communication software processing ? error processing (such as retransmission request) ? error processing (such as retransmission request hardware processing ? reception stops. ? intie2 occurs ? nack is returned. ? to start bit waiting status ? transmission stops. ? intie2 occurs ? to start bit waiting status individual communication software processing ? error processing (such as retransmission request) ? error processing (such as retransmission request nack reception error unit status reception transmission occurrence condition unit nack transmission unit nack transmission occurrence condition location of occurrence other than data field data field other than data field data field nack reception of data of 32nd byte hardware processing ????? broadcasting communication software processing ????? hardware processing ? reception stops. ? intie2 occurs. ? to start bit waiting status ? intie2 does not occur. ?data retransmitted by other unit is received. ? reception stops. ? intie2 occurs. ? to start bit waiting status ? intie2 does not occur. ? retrans- mission processing ?intie2 occurs note . ? to start bit waiting status individual communication software processing ? error processing (such as retransmission request) ? ?error processing (such as retransmission request) ? ?error processing (such as retransmission request) note both isr.6 (ieerr) and isr.2 (endfram) are set to 1. to reset them, satisfy the conditions in table 19-8. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 481 table 19-10. communication error source processing list (2/2) overrun error underrun error unit status reception transmission occurrence condition dr cannot be read in time before the next data is received. dr cannot be written in time before the next data is transmitted. occurrence condition location of occurrence other than data field data field other than data field data field hardware processing ? ? reception stops. ? intie2 occurs. ? to start bit waiting status remarks 1. communication between other units does not end. 2. data cannot be received until the overrun status is cleared. ? ? transmission stops. ? intie2 occurs. ? to start bit waiting status broadcasting communication software processing ? ? dr is read and overrun status is cleared. ? error processing (such as retransmission request) ? ? error processing (such as retransmission request) hardware processing ? ? intie2 does not occur. ? nack is returned. ? data is retransmitted from other unit. remark data cannot be received until overrun status is cleared. ? ? transmission stops. ? intie2 occurs. ? to start bit waiting status individual communication software processing ? ? dr is read and overrun status is cleared. ? error processing (such as retransmission request) ? ? error processing (such as retransmission request) parity error unit status reception transmission occurrence condition received data and received parity do not match. ? occurrence condition location of occurrence other than data field data field other than data field data field hardware processing ? reception stops. ? intie2 occurs. ? to start bit waiting status remark communication between other units does not end. ?? broadcasting communication software processing ? error processing (such as retransmission) ?? hardware processing ? reception stops. ? intie2 occurs. ? to start bit waiting status ? reception does not stop. ? intie2 does not occur. ? nack is returned. ? data retransmitted by other unit is received. ?? individual communication software processing ? error processing (such as retransmission request) ??? chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 482 19.5 interrupt generation timing and main cpu processing 19.5.1 master transmission initial preparation processing: sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. communication start processing: sets the bus control register (enables communication, master request, and slave reception). figure 19-30. master transmission start broad- casting m address p s address p a control p a telegraph length p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> approx. 624 s (mode 1) approx. 390 s (mode 1) <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave reception processing (see 19.5.1 (1) slave reception processing ) judgment of contention result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame re-communication processing (see 19.5.1 (3) recommunication processing ) remarks 1. : interrupt (intie1) occurrence (see 19.5.1 (2) interrupt (intie1) occurrence ) the transmit data of the second byte and those that follow are written to the iebus data register (dr) by dma transfer. at this time, the data transfer direction is ram (memory) sfr (peripheral) 2. : an interrupt (intie1) does not occur. 3. n = final number of data bytes chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 483 (1) slave reception processing if a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from ram (memory) ? sfr (peripheral) to sfr (peripheral) ? ram (memory) until the first data is received. the maximum pending period of this data transfer direction changing processing is about 1040 s in communication mode 1. (2) interrupt (intie1) occurrence if nack is received from the slave in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication ends midway. (3) recommunication processing the vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 484 19.5.2 master reception before performing master reception, it is necessary to notify the slave of slave transmission units. therefore, more than two communication frames are necessary for master reception. the slave unit prepares the transmit data, set (1) the slave transmission enable flag (enslvtx), and waits. initial preparation processing: sets a unit address, slave address, and control data. communication start processing: sets the bus control register (enables communication and master request). figure 19-31. master reception approx. 1014 s (mode 1) start broad- casting m address p s address p a control a p telegraph length a p data 1 approx. 390 s (mode 1) data 1 p a data 2 p a data n ? 1 p a data n p a < 2 > < 1 > <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave processing judgment of collision result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 19.5.2 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 19.5.2 (1) interrupt (intie1) occurrence ) the receive data stored to the iebus data register (dr) is read by dma transfer. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 485 (1) interrupt (intie1) occurrence if nack is transmitted (hardware processing) in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted from the slave. if the receive data is not read in time until the next data is received, the hardware automatically transmits nack. (2) frame end processing the vector interrupt processing in <2> judges whether the data has been correctly received within one frame. if the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 486 19.5.3 slave transmission initial preparation processing: sets a unit address, telegraph length, and the first byte of the transmit data. communication start processing: sets the bus control register (enables communication, slave transmission, and slave reception). figure 19-32. slave transmission start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> pa approx. 390 s (mode 1) approx. 624 s (mode 1) broad- casting telegraph length <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 19.5.3 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 19.5.3 (1) interrupt (intie1) occurrence ). the transmit data of the second byte and those that follow are written to the iebus data register (dr) by dma transfer. at this time, the data transfer direction is ram (memory) sfr (peripheral). 2. : an interrupt (intie1) does not occur. 3. : interrupt (intie2) occurrence an interrupt occurs only when 0h, 4h, 5h, or 6h is received in the control field in the slave status (for the slave status response operation during locked, refer to 19.3.2 (5) iebus control data register (cdr) ). 4. n = final number of data bytes chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 487 (1) interrupt (intie1) occurrence if nack is received from the master in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended. (2) frame end processing the vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the continuation of the data must be transmitted. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 488 19.5.4 slave reception initial preparation processing: sets a unit address. communication start processing: sets the bus control register (enables communication, disables slave transmission, and enables slave reception). figure 19-33. slave reception start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> pa <2> approx. 390 s (mode 1) approx. 1014 s (mode 1) broad- casting telegraph length <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 19.5.4 (2) frame end processing ). remarks 1. : interrupt (intie1) occurrence (see 19.5.4 (1) interrupt (intie1) occurrence ). the receive data stored to the iebus data register (dr) is read by dma transfer. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 489 (1) interrupt (intie1) occurrence if nack is transmitted in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted from the master. if the receive data is not read in time until the next data is received, nack is automatically transmitted. (2) frame end processing the vector interrupt processing in <2> judges whether the data has been correctly received within one frame. chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 490 19.5.5 interval of occurrence of interrupt for iebus control each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. therefore, the cpu must control the iebus control block, taking the shortest time of this interrupt into consideration. the locations at which the following interrupts may occur are indicated by in the field where it may occur. does not mean that the interrupt occurs at each of the points indicated by . if an error interrupt (timing error, parity error, or ack error) occurs, the iebus internal circuit is initialized. as a result, the following interrupt does not occur in that communication frame. (1) master transmission figure 19-34. master transmission (interval of interrupt occurrence) start bit t t1 t broad- casting master address t t2 p slave address t pa at t t3 control p a a t4 tat telegraph length p a data p a communication starts communication start interrupt pa data data a p data tt t4 end of communication end of frame u u t5 a remarks 1. t: timing error a: ack error u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 93 s communication starts ? communication start interrupt t2 approx. 1282 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s transmission data request interrupt interval t5 approx. 375 s chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 491 (2) master reception figure 19-35. master reception (interval of interrupt occurrence) pa pa pa pa pa p a data data data p t1 t communication starts start bit broad- casting master address slave address control telegraph length data tt a end of communication end of frame communication start interrupt tt t t t at t4 t4 t5 t2 a p t a t3 remarks 1. t: timing error p: parity error a: ack error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 93 s communication starts ? communication start interrupt t2 approx. 1282 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s receive data read interval t5 approx. 375 s chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 492 (3) slave transmission figure 19-36. slave transmission (interval of interrupt occurrence) pa pa pa pa pa pa p t1 t tt u u tt t p p t t tt at t5 t4 t3 t6 t7 t7 t2 a p a communication starts end of communication end of frame communication start interrupt status request data data data start bit broad- casting master address slave address control data telegraph length remarks 1. t: timing error p: parity error a: ack error u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 96 s communication starts ? communication start interrupt t2 approx. 1192 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? status request t4 approx. 225 s transmission data request interrupt interval t5 approx. 375 s status request ? timing error t6 approx. 15 s status request ? end of communication t7 approx. 787 s chapter 19 iebus controller (v850/sb2) user?s manual u13850ej4v0um 493 (4) slave reception figure 19-37. slave reception (interval of interrupt occurrence) pa pa pa pa pa p a p t1 t tt tt t p p tt at t4 t4 t5 t2 p a pt a t3 p o a p o p start bit data data data end of communication end of frame communication start interrupt communication starts broad- casting master address slave address control data telegraph length remarks 1. t: timing error p: parity error a: ack error o: overrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 96 s communication starts ? communication start interrupt t2 approx. 1192 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s receive data read interval t5 approx. 375 s user?s manual u13850ej4v0um 494 appendix a register index (1/7) symbol name unit page adcr a/d conversion result register adc 346 adcrh a/d conversion result register h adc 346 adic interrupt control register intc 139 to 141 adm1 a/d converter mode register 1 adc 348 adm2 a/d converter mode register 2 adc 350 ads analog input channel specification register adc 350 asim0 asynchronous serial interface mode register 0 uart 315 asim1 asynchronous serial interface mode register 1 uart 315 asis0 asynchronous serial interface status register 0 uart 316 asis1 asynchronous serial interface status register 1 uart 316 bcc bus cycle control register bcu 112 bcr iebus control register iebus 456 brgc0 baud rate generator control register 0 brg 317 brgc1 baud rate generator control register 1 brg 317 brgck4 baud rate generator output clock selection register 4 brg 338 brgcn4 baud rate generator source clock selection register 4 brg 337 brgmc00 baud rate generator mode control register 00 brg 318 brgmc01 baud rate generator mode control register 01 brg 318 brgmc10 baud rate generator mode control register 10 brg 318 brgmc11 baud rate generator mode control register 11 brg 318 ccr iebus communication count register iebus 477 cdr iebus control data register iebus 461 corad0 correction address register 0 cpu 421 corad1 correction address register 1 cpu 421 corad2 correction address register 2 cpu 421 corad3 correction address register 3 cpu 421 corcn correction control register cpu 419 corrq correction request register cpu 420 cr00 capture/compare register 00 rpu 177 cr01 capture/compare register 01 rpu 178 cr10 capture/compare register 10 rpu 177 cr11 capture/compare register 11 rpu 178 cr20 8-bit compare register 2 rpu 211 cr23 16-bit compare register 23 (when connected to tm2,tm3 cascade) rpu 227 cr30 8-bit compare register 3 rpu 211 appendix a register index user?s manual u13850ej4v0um 495 (2/7) symbol name unit page cr40 8-bit compare register 4 rpu 211 cr45 16-bit compare register 45 (when connected to tm4,tm5 cascade) rpu 227 cr50 8-bit compare register 5 rpu 211 cr60 8-bit compare register 6 rpu 211 cr67 16-bit compare register 67 (when connected to tm6,tm7 cascade) rpu 227 cr70 8-bit compare register 7 rpu 211 crc0 capture/compare control register 0 rpu 181 crc1 capture/compare control register 1 rpu 181 csib4 variable-length serial setting register 4 csi 336 csic0 interrupt control register intc 139 to 141 csic1 interrupt control register intc 139 to 141 csic2 interrupt control register intc 139 to 141 csic3 interrupt control register intc 139 to 141 csic4 interrupt control register intc 139 to 141 csim0 serial operation mode register 0 csi 247 csim1 serial operation mode register 1 csi 247 csim2 serial operation mode register 2 csi 247 csim3 serial operation mode register 3 csi 247 csim4 variable-length serial control register 4 csi 335 csis0 serial clock selection register 0 csi 248 csis1 serial clock selection register 1 csi 248 csis2 serial clock selection register 2 csi 248 csis3 serial clock selection register 3 csi 248 dbc0 dma byte counter register 0 dmac 366 dbc1 dma byte counter register 1 dmac 366 dbc2 dma byte counter register 2 dmac 366 dbc3 dma byte counter register 3 dmac 366 dbc4 dma byte counter register 4 dmac 366 dbc5 dma byte counter register 5 dmac 366 dchc0 dma channel control register 0 dmac 367 dchc1 dma channel control register 1 dmac 367 dchc2 dma channel control register 2 dmac 367 dchc3 dma channel control register 3 dmac 367 dchc4 dma channel control register 4 dmac 367 dchc5 dma channel control register 5 dmac 367 dioa0 dma peripheral i/o address register 0 dmac 360 dioa1 dma peripheral i/o address register 1 dmac 360 dioa2 dma peripheral i/o address register 2 dmac 360 appendix a register index user?s manual u13850ej4v0um 496 (3/7) symbol name unit page dioa3 dma peripheral i/o address register 3 dmac 360 dioa4 dma peripheral i/o address register 4 dmac 360 dioa5 dma peripheral i/o address register 5 dmac 360 dlr iebus telegraph length register iebus 465 dmaic0 interrupt control register intc 139 to 141 dmaic1 interrupt control register intc 139 to 141 dmaic2 interrupt control register intc 139 to 141 dmaic3 interrupt control register intc 139 to 141 dmaic4 interrupt control register intc 139 to 141 dmaic5 interrupt control register intc 139 to 141 dmas dma start factor expansion register dmac 366 dr iebus data register iebus 466 dra0 dma internal ram address register 0 dmac 361 dra1 dma internal ram address register 1 dmac 361 dra2 dma internal ram address register 2 dmac 361 dra3 dma internal ram address register 3 dmac 361 dra4 dma internal ram address register 4 dmac 361 dra5 dma internal ram address register 5 dmac 361 dwc data wait control register bcu 111 ecr interrupt source register cpu 76 egn0 falling edge specification register 0 intc 132, 378 egp0 rising edge specification register 0 intc 132, 378 eipc status saving register during interrupt cpu 76 eipsw status saving register during interrupt cpu 76 fepc status saving registers for nmi cpu 76 fepsw status saving registers for nmi cpu 76 iebic1 interrupt control register iebus 139 to 141 iebic2 interrupt control register iebus 139 to 141 ieclk iebus clock selection register iebus 477 iic0 iic shift register 0 i 2 c 268 iic1 iic shift register 1 i 2 c 268 iicc0 iic control register 0 i 2 c 257 iicc1 iic control register 1 i 2 c 257 iicce0 iic clock expansion register 0 i 2 c 266 iicce1 iic clock expansion register 1 i 2 c 266 iiccl0 iic clock selection register 0 i 2 c 265 iiccl1 iic clock selection register 1 i 2 c 265 iicic1 interrupt control register i 2 c 139 to 141 appendix a register index user?s manual u13850ej4v0um 497 (4/7) symbol name unit page iics0 iic status register 0 i 2 c 262 iics1 iic status register 1 i 2 c 262 iicx0 iic function expansion register 0 i 2 c 266 iicx1 iic function expansion register 1 i 2 c 266 ispr in-service priority register intc 142 isr iebus interrupt status register iebus 470 kric interrupt control register kr 139 to 141 krm key return mode register kr 156 mam memory address output mode register port 92 mm memory expansion mode register port 91 ncc noise elimination control register intc 144 osts oscillation stabilization time selection register wdt 163, 238 p0 port 0 port 375 p1 port 1 port 380 p2 port 2 port 384 p3 port 3 port 389 p4 port 4 port 393 p5 port 5 port 393 p6 port 6 port 396 p7 port 7 port 399 p8 port 8 port 399 p9 port 9 port 401 p10 port 10 port 404 p11 port 11 port 408 pac port alternate function control register port 410 par iebus partner address register iebus 460 pcc processor clock control register cg 160 pf1 port 1 function register port 382 pf2 port 2 function register port 386 pf3 port 3 function register port 391 pf10 port 10 function register port 406 pic0 interrupt control register intc 139 to 141 pic1 interrupt control register intc 139 to 141 pic2 interrupt control register intc 139 to 141 pic3 interrupt control register intc 139 to 141 pic4 interrupt control register inyc 139 to 141 pic5 interrupt control register intc 139 to 141 pic6 interrupt control register intc 139 to 141 appendix a register index user?s manual u13850ej4v0um 498 (5/7) symbol name unit page pm0 port 0 mode register port 377 pm1 port 1 mode register port 381 pm2 port 2 mode register port 385 pm3 port 3 mode register port 390 pm4 port 4 mode register port 394 pm5 port 5 mode register port 394 pm6 port 6 mode register port 397 pm9 port 9 mode register port 402 pm10 port 10 mode register port 405 pm11 port 11 mode register port 409 prcmd command register cg 105 prm00 prescaler mode register 00 rpu 183 prm01 prescaler mode register 01 rpu 183 prm10 prescaler mode register 10 rpu 185 prm11 prescaler mode register 11 rpu 185 psc power save control register cg 162 psw program status word cpu 77 pu0 pull-up resistor option register 0 port 377 pu1 pull-up resistor option register 1 port 381 pu2 pull-up resistor option register 2 port 386 pu3 pull-up resistor option register 3 port 390 pu10 pull-up resistor option register 10 port 406 pu11 pull-up resistor option register 11 port 410 rtbh real time output buffer register h rpu 370 rtbl real time output buffer register l rpu 370 rtpc real time output port control register rpu 372 rtpm real time output port mode register rpu 371 rx0 receive shift register 0 uart 313 rx1 receive shift register 1 uart 313 rxb0 receive buffer register 0 uart 313 rxb1 receive buffer register 1 uart 313 sar iebus slave address register iebus 459 scr iebus success count register iebus 476 seric0 interrupt control register intc 139 to 141 seric1 interrupt control register intc 139 to 141 sio0 serial i/o shift register 0 csi 245 sio1 serial i/o shift register 1 csi 245 sio2 serial i/o shift register 2 csi 245 appendix a register index user?s manual u13850ej4v0um 499 (6/7) symbol name unit page sio3 serial i/o shift register 3 csi 245 sio4 variable length serial i/o shift register 4 csi 333 ssr iebus slave status register iebus 475 stic0 interrupt control register intc 139 to 141 stic1 interrupt control register intc 139 to 141 sva0 slave address register 0 i 2 c 268 sva1 slave address register 1 i 2 c 268 syc system control register cg 107 sys system status register cg 105 tcl20 timer clock selection register 20 rpu 212 tcl21 timer clock selection register 21 rpu 212 tcl30 timer clock selection register 30 rpu 212 tcl31 timer clock selection register 31 rpu 212 tcl40 timer clock selection register 40 rpu 212 tcl41 timer clock selection register 41 rpu 212 tcl50 timer clock selection register 50 rpu 212 tcl51 timer clock selection register 51 rpu 212 tcl60 timer clock selection register 60 rpu 212 tcl61 timer clock selection register 61 rpu 212 tcl70 timer clock selection register 70 rpu 212 tcl71 timer clock selection register 71 rpu 212 tm0 16-bit timer register 0 rpu 176 tm1 16-bit timer register 1 rpu 176 tm2 8-bit counter 2 rpu 211 tm23 16-bit counter 23 (when connected to tm2,tm3 cascade) rpu 227 tm3 8-bit counter 3 rpu 211 tm4 8-bit counter 4 rpu 211 tm45 16-bit counter 45 (when connected to tm4,tm5 cascade) rpu 227 tm5 8-bit counter 5 rpu 211 tm6 8-bit counter 6 rpu 211 tm67 16-bit counter 67 (when connected to tm6,tm7 cascade) rpu 227 tm7 8-bit counter 7 rpu 211 tmc0 16-bit timer mode control register 0 rpu 179 tmc1 16-bit timer mode control register 1 rpu 179 tmc2 8-bit timer mode control register 2 rpu 216 tmc3 8-bit timer mode control register 3 rpu 216 tmc4 8-bit timer mode control register 4 rpu 216 tmc5 8-bit timer mode control register 5 rpu 216 appendix a register index user?s manual u13850ej4v0um 500 (7/7) symbol name unit page tmc6 8-bit timer mode control register 6 rpu 216 tmc7 8-bit timer mode control register 7 rpu 216 tmic00 interrupt control register intc 139 to 141 tmic01 interrupt control register intc 139 to 141 tmic10 interrupt control register intc 139 to 141 tmic11 interrupt control register intc 139 to 141 tmic2 interrupt control register intc 139 to 141 tmic3 interrupt control register intc 139 to 141 tmic4 interrupt control register intc 139 to 141 tmic5 interrupt control register intc 139 to 141 tmic6 interrupt control register intc 139 to 141 tmic7 interrupt control register intc 139 to 141 toc0 16-bit timer output control register 0 rpu 182 toc1 16-bit timer output control register 1 rpu 182 txs0 transmit shift register 0 uart 313 txs1 transmit shift register 1 uart 313 uar iebus unit address register iebus 459 usr iebus unit status register iebus 467 wdcs watchdog timer clock selection register wdt 239 wdtic interrupt control register intc 139 to 141 wdtm watchdog timer mode register wdt 143, 240 wtncs watch timer clock selection register wt 233 wtnic interrupt control register intc 139 to 141 wtniic interrupt control register intc 139 to 141 wtnm watch timer mode control register wt 232 user?s manual u13850ej4v0um 501 appendix b instruction set list ? how to read instruction set list cy instruction group mnemonic this column shows instruction groups. instructions are divided into each instruction group and described. this column shows instruction mnemonics. this column shows instruction operands (refer to table b-1 ). this column shows instruction codes (opcode) in binary format. 32-bit instructions are displayed in 2 lines (refer to table b-2 ). this column shows instruction operations (refer to table b-3 ). this column shows flag statuses (refer to table b-4 ). operand op code operation flag ov s z sat table b-1. symbols in operand description symbol description reg1 general-purpose register (r0 to r31): used as source register reg2 general-purpose register (r0 to r31): mainly used as destination register ep element pointer (r30) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement regid system register number vector 5-bit data that specifies trap vector number (00h to 1fh) cccc 4-bit data that indicates c ondition code appendix b instruction set list user?s manual u13850ej4v0um 502 table b-2. symbols used for op code symbol description r 1-bit data of code that specifies reg1 or regid r 1-bit data of code that specifies reg2 d 1-bit data of displacement i 1-bit data of immediate data cccc 4-bit data that indicates c ondition code bbb 3-bit data that specifies bit number table b-3. symbols used for operation description symbol description assignment gr[ ] genera-purpose register sr[ ] system register zero-extend (n) zero-extends n to word length. sign-extend (n) sign-extends n to word length. load-memory (a,b) reads data of size b from address a. store-memory (a,b,c) writes data b of size c to address a. load-memory-bit (a,b) reads bit b from address a. store-memory-bit (a,b,c) writes c to bit b of address a saturated (n) performs saturated processing of n. (n is 2?s complements). result of calculation of n: if n is n 7fffffffh as result of calculation, 7fffffffh. if n is n 80000000h as result of calculation, 80000000h. result reflects result to a flag. byte byte (8 bits) halfword half-word (16 bits) word word (32 bits) + add ? subtract || bit concatenation multiply divide and logical product or logical sum xor exclusive logical sum not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift appendix b instruction set list user?s manual u13850ej4v0um 503 table b-4. symbols used for flag operation symbol description (blank) not affected 0 cleared to 0 set of cleared according to result r previously saved value is restored table b-5. condition codes condition name (cond) condition code ( cccc) c onditional expression description v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ( (s xor ov) or z) = 1 less than or equal signed gt 1111 ( (s xor ov) or z) = 0 greater than signed appendix b instruction set list user?s manual u13850ej4v0um 504 instruction set list (1/4) flag instruction group mnemonic operand op code operation cy ov s z sat sld.b disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) gr [reg2] sign-extend (load-memory (adr, byte)) sld.h disp8 [ep], reg2 rrrrr1000ddddddd ( note 1 ) adr ep + zero-extend (disp8) gr [reg2] sign-extend (load-memory (adr, halfword)) sld.w disp8 [ep], reg2 rrrrr1010dddddd0 ( note 2 ) adr ep + zero-extend (disp8) gr [reg2] load-memory (adr, word) ld.b disp16 [reg1], reg2 rrrrr111000rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, byte)) ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 ( note 3 ) adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, halfword)) ld.w disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 ( note 3 ) adr gr [reg1] + sign-extend (disp16) gr [reg2] load-memory (adr, word)) sst.b reg2, disp7 [ep] rrrrr0111ddddddd adr ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) sst.h reg2, disp8 [ep] rrrrr1001ddddddd ( note 1 ) adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) sst.w reg2, disp8 [ep] rrrrr1010dddddd1 ( note 2 ) adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) st.b reg2, disp16 [reg1] rrrrr111010rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 ( note 3 ) adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) load/store st.w reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 ( note 3 ) adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) mov reg1, reg2 rrrrr000000rrrrr gr [reg2] gr [reg1] mov imm5, reg2 rrrrr010000iiiii gr [reg2] sign-extend (imm5) movhi imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + (imm16 || 0 16 ) arithmetic operation movea imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) notes 1. ddddddd is the higher 7 bits of disp8. 2. dddddd is the higher 6 bits of disp8. 3. ddddddddddddddd is the higher 15 bits of disp16. appendix b instruction set list user?s manual u13850ej4v0um 505 instruction set list (2/4) flag instruction group mnemonic operand op code operation cy ov s z sat add reg1, reg2 rrrrr001110rrrrr gr [reg2] gr [reg2] + gr [reg1] add imm5, reg2 rrrrr010010iiiii gr [reg2] gr [reg2] + sign-extend (imm5) addi imm16, reg1, reg2 rrrrr110000rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) sub reg1, reg2 rrrrr001101rrrrr gr [reg2] gr [reg2] ? gr [reg1] subr reg1, reg2 rrrrr001100rrrrr gr [reg2] gr [reg1] ? gr [reg2] mulh reg1,reg2 rrrrr000111rrrrr gr [reg2] gr [reg2] note gr [reg1] note (signed multiplication) mulh imm5, reg2 rrrrr010111iiiii gr [reg2] gr [reg2] note sign-extend (imm5) (signed multiplication) mulhi imm16, reg1, reg2 rrrrr110111rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] note imm16 (signed multiplication) divh reg1, reg2 rrrrr000010rrrrr gr [reg2] gr [reg2] gr [reg2] note (signed division) cmp reg1, reg2 rrrrr001111rrrrr result gr [reg2] ? gr [reg1] cmp imm5, reg2 rrrrr010011iiiii result gr [reg2] ? sign-extend (imm5) arithmetic operation setf cccc, reg2 rrrrr 1111110 cccc 0000000000000000 if conditions are satisfied then gr [reg2] 00000001h else gr [reg2] 00000000h satadd reg1, reg2 rrrrr000110rrrrr gr [reg2] saturated (gr [reg2] + gr [reg1]) satadd imm5, reg2 rrrrr010001iiiii gr [reg2] saturated (gr [reg2] + sign- extend (imm5)) satsub reg1, reg2 rrrrr000101rrrrr gr [reg2] saturated (gr [reg2] ? gr [reg1]) satsubi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii gr [reg2] saturated (gr [reg1] ? sign- extend (imm16)) saturated operation satsubr reg1, reg2 rrrrr000100rrrrr gr [reg2] saturated (gr [reg1] ? gr [reg2]) tst reg1, reg2 rrrrr001011rrrrr result gr [reg2] and gr [reg1] 0 or reg1, reg2 rrrrr001000rrrrr gr [reg2] gr [reg2] or gr [reg1] 0 ori imm16, reg1, reg2 rrrrr110100rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] or zero-extend (imm16) 0 and reg1, reg2 rrrrr001010rrrrr gr [reg2] gr [reg2] and gr [reg1] 0 logic operation andi imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] and zero-extend (imm16) 00 note only the lower half-word data is valid. appendix b instruction set list user?s manual u13850ej4v0um 506 instruction set list (3/4) flag instruction group mnemonic operand op code operation cy ov s z sat xor reg1, reg2 rrrrr001001rrrrr gr [reg2] gr [reg2] xor gr [reg1] 0 xori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] xor zero-extend (imm16) 0 not reg1, reg2 rrrrr000001rrrrr gr [reg2] not (gr [reg1]) 0 shl reg1, reg2 rrrrr111111rrrrr 0000000011000000 gr [reg2] gr [reg2] logically shift left by gr [reg1]) 0 shl imm5, reg2 rrrrr010110iiiii gr [reg2] gr [reg2] logically shift left by zero-extend (imm5) 0 shr reg1, reg2 rrrrr1111111 cccc 0000000010000000 gr [reg2] gr [reg2] logically shift right by gr [reg1] 0 shr imm5, reg2 rrrrr010100iiiii gr [reg2] gr [reg2] logically shift right by zero-extend (imm5) 0 sar reg1, reg2 rrrrr111111rrrrr 0000000010100000 gr [reg2] gr [reg2] arithmetically shift right by gr [reg1] 0 logic operation sar imm5, reg2 rrrrr010101iiiii gr [reg2] gr [reg2] arithmetically shift right by zero-extend (imm5) 0 jmp [reg1] 00000000011rrrrr pc gr [reg1] jr disp22 0000011110dddddd ddddddddddddddd0 ( note 1 ) pc pc + sign-extend (disp22) jarl disp22, reg2 rrrrr11110dddddd ddddddddddddddd0 ( note 1 ) gr [reg2] pc + 4 pc pc + sign-extend (disp22) jump bcond disp9 ddddd1011ddd cccc ( note 2 ) if conditions are satisfied then pc pc + sign-extend (disp9) set1 bit#3, disp16 [reg1] 00bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3) store memory-bit (adr, bit#3, 1) clr1 bit#3, disp16 [reg1] 10bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store memory-bit (adr, bit#3, 0) not1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) bit manipulate tst1 bit#3, disp16 [reg1] 11bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) notes 1. ddddddddddddddddddddd is the higher 21 bits of dip22. 2. dddddddd is the higher 8 bits of disp9. appendix b instruction set list user?s manual u13850ej4v0um 507 instruction set list (4/4) flag instruction group mnemonic operand op code operation cy ov s z sa t regid = eipc, fepc regid = eipsw, fepsw ldsr reg2, regid rrrrr111111rrrrr 0000000000100000 ( note ) sr [regid] gr [reg2] regid = psw stsr regid, reg2 rrrrr111111rrrrr 0000000001000000 gr [reg2] sr [regid] trap vector 00000111111iiiii 0000000100000000 eipc pc + 4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (vector = 00h to 0fh) 00000050h (vector = 10h to 1fh) reti 0000011111100000 0000000101000000 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw rrrrr halt 0000011111100000 0000000100100000 stops di 0000011111100000 0000000101100000 psw.id 1 (maskable interrupt disabled) ei 1000011111100000 0000000101100000 psw.id 0 (maskable interrupt enabled) special nop 0000000000000000 uses 1 clock cycle without doing anything note the op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table. therefore, the meaning of register specification for mnemonic description and op code is different from that of the other instructions. rrr = regid specification rrrrr = reg2 specification user?s manual u13850ej4v0um 508 appendix c index [number] 16-bit compare register 23 -------------------------------227 16-bit compare register 45 -------------------------------227 16-bit compare register 67 -------------------------------227 16-bit counter 23 -------------------------------------------227 16-bit counter 45 -------------------------------------------227 16-bit counter 67 -------------------------------------------227 16-bit timer ---------------------------------------------------174 16-bit timer mode control registers 0, 1 --------------179 16-bit timer output control registers 0, 1 -------------182 16-bit timer registers 0, 1 ---------------------------------176 3-wire serial i/o ---------------------------------------------244 3-wire variable-length serial i/o ------------------------332 8-bit compare registers 2 to 7----------------------------211 8-bit counters 2 to 7 ----------------------------------------211 8-bit timer -----------------------------------------------------209 8-bit timer mode control registers 2 to 7 --------------216 [a] a/d conversion result register --------------------------346 a/d conversion result register h -----------------------346 a/d converter ------------------------------------------------344 a/d converter mode register 1 --------------------------348 a/d converter mode register 2 --------------------------350 a1 to a4 -------------------------------------------------------- 67 a13 to a15 ---------------------------------------------------- 62 a16 to a21 ---------------------------------------------------- 64 a5 to a12 ------------------------------------------------------ 66 access clock -------------------------------------------------107 ad0 to ad7 --------------------------------------------------- 63 ad8 to ad15 -------------------------------------------------- 63 adcr ----------------------------------------------------------346 adcrh -------------------------------------------------------346 address match detection method ----------------------295 address space ----------------------------------------------- 79 adic ------------------------------------------------- 139 to 141 adm1 ----------------------------------------------------------348 adm2 ----------------------------------------------------------350 ads ------------------------------------------------------------350 adtrg --------------------------------------------------------- 59 analog input channel specification register ---------350 ani0 to ani11 ------------------------------------------------ 64 arbitration ----------------------------------------------------296 asck0 --------------------------------------------------------- 60 asck1 --------------------------------------------------------- 61 asim0, asim1 ---------------------------------------------- 315 asis0, asis1 ----------------------------------------------- 316 astb ------------------------------------------------------------65 asynchronous serial interface -------------------------- 312 asynchronous serial interface mode registers 0, 1 ------------------------------------------------ 315 asynchronous serial interface status registers 0, 1 ------------------------------------------------ 316 av dd -------------------------------------------------------------67 av ref ------------------------------------------------------------67 av ss -------------------------------------------------------------67 [b] baud rate generator control registers 0, 1 ----------- 317 baud rate generator mode control registers n0, n1 --------------------------------------------- 318 baud rate generator source clock selection register 4 ----------------------------------------------------- 337 baud rate generator output clock selection register 4 ----------------------------------------------------- 338 bcc ----------------------------------------------------------- 112 bcr ----------------------------------------------------------- 456 bcu --------------------------------------------------------38, 48 brgc0, brgc1 ------------------------------------------- 317 brgck4 ----------------------------------------------------- 338 brgcn4 ----------------------------------------------------- 337 brgmcn0, brgmcn1 ----------------------------------- 318 bus control function --------------------------------------- 106 bus control pin ---------------------------------------------- 106 bus control unit ------------------------------------------38, 48 bus cycle control register -------------------------------- 112 bus hold function ------------------------------------------ 114 bus priority --------------------------------------------------- 122 bus timing ---------------------------------------------------- 115 bus width ----------------------------------------------------- 108 bv dd -------------------------------------------------------------67 bv ss -------------------------------------------------------------68 byte access ------------------------------------------------- 108 [c] capture/compare control registers 0, 1 -------------- 181 capture/compare register n0 --------------------------- 177 capture/compare register n1 --------------------------- 178 ccr ----------------------------------------------------------- 477 appendix c index user?s manual u13850ej4v0um 509 cdr ----------------------------------------------------------- 460 cg ----------------------------------------------------------38, 48 clkout --------------------------------------------------------67 clock generation function -------------------------------- 158 clock generator (cg) ----------------------------------38, 48 clock output function ------------------------------------- 160 command register ----------------------------------------- 104 communication command ------------------------------- 434 communication reservation ----------------------------- 299 communication system ---------------------------------- 425 corad0 to corad3 ------------------------------------ 421 corcn ------------------------------------------------------- 419 correction address registers 0 to 3 ------------------- 421 correction control register ------------------------------- 419 correction request register ------------------------------ 420 corrq ------------------------------------------------------- 420 cpu --------------------------------------------------------38, 48 cpu address space -----------------------------------------79 cpu register set ----------------------------------------------74 cr20 to cr70 ---------------------------------------------- 211 cr23, cr45, cr67 --------------------------------------- 227 crc0, crc1 ------------------------------------------------ 181 crn0 ---------------------------------------------------------- 177 crn1 ---------------------------------------------------------- 178 csi0 to csi3 ------------------------------------------------ 244 csi4 ----------------------------------------------------------- 332 csib4 --------------------------------------------------------- 336 csic0 to csic4 -----------------------------------139 to 141 csim0 to csim3 ------------------------------------------- 247 csim4 --------------------------------------------------------- 335 csis0 to csis3 -------------------------------------------- 248 [d] data wait control register -------------------------------- 110 dbc0 to dbc5 --------------------------------------------- 366 dchc0 to dchc5 ----------------------------------------- 367 dioa0 to dioa5 ------------------------------------------- 360 dlr ------------------------------------------------------------ 465 dma function ----------------------------------------------- 360 dma byte count registers 0 to 5 ----------------------- 366 dma channel control registers 0 to 5 ----------------- 367 dma internal ram address registers 0 to 5 -------- 361 dma peripheral i/o address registers 0 to 5 ------- 360 dmaic0 to dmaic5 ------------------------------139 to 141 dma start factor expansion register ------------------ 366 dmas --------------------------------------------------------- 366 dr ------------------------------------------------------------- 466 dra0 to dra5 --------------------------------------------- 361 dstb ----------------------------------------------------------- 65 dwc ---------------------------------------------------------- 110 [e] ecr ------------------------------------------------------------- 76 egn0 ---------------------------------------------------142, 378 egp0 ---------------------------------------------------142, 378 eipc ------------------------------------------------------------ 76 eipsw --------------------------------------------------------- 76 error detection --------------------------------------------- 295 ev dd ------------------------------------------------------------ 68 ev ss ------------------------------------------------------------- 68 exception trap ---------------------------------------------- 148 extension code --------------------------------------------- 295 external expansion mode --------------------------------- 98 external memory -------------------------------------------- 89 external wait function ------------------------------------- 111 [f] falling edge specification register 0 ------------132, 378 fepc ----------------------------------------------------------- 76 fepsw -------------------------------------------------------- 76 flash memory ---------------------------------------------- 423 flash memory control ------------------------------------ 432 flash memory programming mode -------------- 78, 433 [g] general-purpose register ---------------------------------- 75 [h] halfword access ------------------------------------------- 108 halt mode ------------------------------------------------- 165 handling of unused pins ----------------------------------- 69 hardware start --------------------------------------------- 344 hldak --------------------------------------------------------- 65 hldrq --------------------------------------------------------- 65 [i] i 2 c bus ------------------------------------------------------- 252 i 2 c bus mode ----------------------------------------------- 252 i 2 c interrupt request -------------------------------------- 276 ic ---------------------------------------------------------------- 68 idle mode ---------------------------------------------------- 68 idle state insertion function ----------------------------- 112 iebic1 ----------------------------------------------- 139 to 141 iebic2 ----------------------------------------------- 139 to 141 iebus clock selection register -------------------------- 477 iebus communication count register ----------------- 477 appendix c index user?s manual u13850ej4v0um 510 iebus control data register ------------------------------460 iebus control register -------------------------------------456 iebus controller ---------------------------------------------436 iebus data register ----------------------------------------466 iebus interrupt status register --------------------------470 iebus partner address register -------------------------460 iebus slave address register ----------------------------460 iebus slave status register ------------------------------475 iebus success count register ---------------------------476 iebus telegraph length register -------------------------465 iebus unit address register ------------------------------460 iebus unit status register --------------------------------467 ieclk ---------------------------------------------------------477 ierx ------------------------------------------------------------ 66 ietx ------------------------------------------------------------ 66 iic clock expansion registers 0, 1 ----------------------266 iic clock selection registers 0, 1 -----------------------265 iic control registers 0, 1 ----------------------------------267 iic function expansion registers 0, 1 ------------------266 iic shift registers 0, 1 --------------------------------------- 68 iic status registers 0, 1 -----------------------------------262 iic0, iic1 -----------------------------------------------------268 iicc0, iicc1 -------------------------------------------------257 iicce0, iicce1 ---------------------------------------------266 iiccl0, iiccl1 ----------------------------------------------265 iicic1 ------------------------------------------------ 139 to 141 iics0, iics1 -------------------------------------------------262 iicx0, iicx1 -------------------------------------------------266 illegal op code -----------------------------------------------148 image ----------------------------------------------------------- 80 in-service priority register --------------------------------142 intc ------------------------------------------------------- 38, 48 internal ram area ------------------------------------------- 86 internal rom area ------------------------------------------ 83 interrupt control register ----------------------------------139 interrupt controller -------------------------------------- 38, 48 interrupt request signal generator ---------------------256 interrupt source register ----------------------------------- 76 interrupt status saving register -------------------------- 76 interrupt/exception processing function --------------124 interval timer mode ----------------------------------------237 intp0 to intp6 ---------------------------------------------- 59 ispr -----------------------------------------------------------142 isr -------------------------------------------------------------470 [k] key interrupt function --------------------------------------156 key return mode register ---------------------------------156 kr0 to kr7 ----------------------------------------------------66 kric -------------------------------------------------139 to 141 krm ----------------------------------------------------------- 156 [l] lben ------------------------------------------------------------64 low power consumption mode ------------------------- 356 [m] main system clock oscillator ---------------------------- 158 mam -------------------------------------------------------------92 maskable interrupt ----------------------------------------- 133 memory address output mode register -----------------93 memory block function ----------------------------------- 109 memory boundary operation condition --------------- 123 memory expansion mode register -----------------------92 memory map --------------------------------------------------82 mm ---------------------------------------------------------------91 multiple interrupt ------------------------------------------- 151 [n] ncc ----------------------------------------------------------- 144 nmi --------------------------------------------------------------59 nmi status saving register ---------------------------------76 noise elimination control register ---------------------- 144 non-maskable interrupt ---------------------------------- 127 normal operation mode ------------------------------------78 [o] off-board programming ---------------------------------- 424 on-board programming ---------------------------------- 424 on-chip peripheral i/o area -------------------------------88 operation mode ----------------------------------------------78 oscillation stabilization time ---------------------------- 172 oscillation stabilization time selection register 163, 238 osts --------------------------------------------------- 163, 238 [p] p0 -------------------------------------------------------------- 375 p00 to p07 -----------------------------------------------------59 p1 -------------------------------------------------------------- 380 p10 ------------------------------------------------------------ 404 p10 to p15 -----------------------------------------------------60 p100 to p107 -------------------------------------------------66 p11 ------------------------------------------------------------ 408 p110 to p113 -------------------------------------------------66 p2 -------------------------------------------------------------- 384 p20 to p27 -----------------------------------------------------61 appendix c index user?s manual u13850ej4v0um 511 p3 -------------------------------------------------------------- 389 p30 to p37 -----------------------------------------------------62 p4 -------------------------------------------------------------- 393 p40 to p47 -----------------------------------------------------62 p5 -------------------------------------------------------------- 393 p50 to p57 -----------------------------------------------------63 p6 -------------------------------------------------------------- 396 p60 to p65 -----------------------------------------------------63 p7 -------------------------------------------------------------- 399 p70 to p77 -----------------------------------------------------64 p8 -------------------------------------------------------------- 399 p80 to p83 -----------------------------------------------------64 p9 -------------------------------------------------------------- 401 p90 to p96 -----------------------------------------------------64 pac ----------------------------------------------------------- 410 par ----------------------------------------------------------- 460 pcc ----------------------------------------------------------- 160 peripheral i/o registers -------------------------------------95 pf1 ------------------------------------------------------------ 382 pf10 ---------------------------------------------------------- 406 pf2 ------------------------------------------------------------ 386 pf3 ------------------------------------------------------------ 391 pic0 to pic6 ---------------------------------------139 to 141 pin function ----------------------------------------------------51 pin i/o buffer power supply -------------------------------69 pin i/o circuit type -------------------------------------------69 pm0 ------------------------------------------------------------ 377 pm1 ------------------------------------------------------------ 381 pm10 ---------------------------------------------------------- 405 pm11 ---------------------------------------------------------- 409 pm2 ------------------------------------------------------------ 385 pm3 ------------------------------------------------------------ 390 pm4 ------------------------------------------------------------ 394 pm5 ------------------------------------------------------------ 394 pm6 ------------------------------------------------------------ 397 pm9 ------------------------------------------------------------ 402 port ---------------------------------------------------------40, 50 port 0 ---------------------------------------------------------- 375 port 0 mode register -------------------------------------- 377 port 1 ---------------------------------------------------------- 380 port 1 function register ----------------------------------- 382 port 1 mode register -------------------------------------- 381 port 10 -------------------------------------------------------- 404 port 10 function register ---------------------------------- 406 port 10 mode register ------------------------------------- 405 port 11 -------------------------------------------------------- 408 port 11 mode register ------------------------------------- 409 port 2 ---------------------------------------------------------- 384 port 2 function register ----------------------------------- 386 port 2 mode register -------------------------------------- 385 port 3 --------------------------------------------------------- 389 port 3 function register ----------------------------------- 391 port 3 mode register -------------------------------------- 390 port 4 --------------------------------------------------------- 393 port 4 mode register -------------------------------------- 394 port 5 --------------------------------------------------------- 393 port 5 mode register -------------------------------------- 394 port 6 --------------------------------------------------------- 396 port 6 mode register -------------------------------------- 397 port 7 --------------------------------------------------------- 399 port 8 --------------------------------------------------------- 399 port 9 --------------------------------------------------------- 401 port 9 mode register -------------------------------------- 402 port alternate function control register --------------- 411 power save control register ----------------------------- 162 power save function -------------------------------------- 164 prcmd ------------------------------------------------------ 105 prescaler mode register 0n ----------------------------- 183 prescaler mode register 1n ----------------------------- 185 priority control ---------------------------------------------- 151 prm0n ------------------------------------------------------- 183 prm1n ------------------------------------------------------- 185 processor clock control register ----------------------- 160 program counter --------------------------------------------- 75 program register set ---------------------------------------- 75 program status word --------------------------------------- 77 programmable wait function ---------------------------- 110 programming environment ------------------------------ 425 programming method ------------------------------------ 432 psc ----------------------------------------------------------- 162 psw ------------------------------------------------------------ 76 pu0 ----------------------------------------------------------- 377 pu1 ----------------------------------------------------------- 381 pu10 ---------------------------------------------------------- 406 pu11 ---------------------------------------------------------- 410 pu2 ----------------------------------------------------------- 386 pu3 ----------------------------------------------------------- 390 pull-up resistor option register 0 ----------------------- 377 pull-up resistor option register 1 ----------------------- 381 pull-up resistor option register 10 --------------------- 406 pull-up resistor option register 11 --------------------- 410 pull-up resistor option register 2 ----------------------- 386 pull-up resistor option register 3 ----------------------- 390 [r] r/w ------------------------------------------------------------- 65 appendix c index user?s manual u13850ej4v0um 512 ram ------------------------------------------------------- 38, 48 rd --------------------------------------------------------------- 65 real-time output buffer register h ---------------------370 real-time output buffer register l ----------------------370 real-time output function --------------------------------369 real-time output port control register -----------------372 real-time output port mode register -------------------371 receive buffer registers 0, 1 ----------------------------313 receive shift registers 0, 1 ------------------------------313 recommended use of address space ----------------- 94 regc ---------------------------------------------------------- 67 regulator -----------------------------------------------------417 reset --------------------------------------------------------- 67 reset function -----------------------------------------------416 rising edge specification register 0 ------------132, 378 rom -------------------------------------------------------- 38,48 rom correction function ----------------------------------418 rtbh ----------------------------------------------------------370 rtbl ----------------------------------------------------------370 rto ------------------------------------------------------------369 rtp -------------------------------------------------------- 39, 49 rtp0 to rtp7 ------------------------------------------------ 66 rtpc ----------------------------------------------------------372 rtpm ----------------------------------------------------------371 rtptrg ------------------------------------------------------- 59 rx0, rx1 -----------------------------------------------------313 rxb0, rxb1 -------------------------------------------------313 rxd0 ----------------------------------------------------------- 60 rxd1 ----------------------------------------------------------- 61 [s] sar ------------------------------------------------------------459 sck0, sck1 -------------------------------------------------- 60 sck2, sck3 -------------------------------------------------- 61 sck4 ----------------------------------------------------------- 62 scl0 ------------------------------------------------------------ 60 scl1 ------------------------------------------------------------ 61 scr ------------------------------------------------------------476 sda0 ----------------------------------------------------------- 60 sda1 ----------------------------------------------------------- 61 serial clock counter ----------------------------------------255 serial clock selection registers 0 to 3 -----------------248 serial i/o shift registers 0 to 3 --------------------------245 serial interface function ----------------------------------244 serial operation mode registers 0 to 3 ----------------247 seric0, seric1 --------------------------------- 139 to 141 si0, si1 -------------------------------------------------------- 60 si2, si3 -------------------------------------------------------- 61 si4 ---------------------------------------------------------------62 single-chip mode --------------------------------------------78 sio0 to sio3 ------------------------------------------------ 245 sio4 ----------------------------------------------------------- 333 slave address registers 0, 1 ---------------------------- 268 so latch ------------------------------------------------------ 255 so0, so1 ------------------------------------------------------60 so2, so3 ------------------------------------------------------61 so4 --------------------------------------------------------------62 software exception ---------------------------------------- 146 software start ----------------------------------------------- 344 software stop mode ------------------------------------ 170 specific register -------------------------------------------- 103 ssr ----------------------------------------------------------- 475 standby function ------------------------------------------- 331 start condition ---------------------------------------------- 270 stic0, stic1 --------------------------------------139 to 141 stop condition ---------------------------------------------- 273 subsystem clock oscillator ------------------------------ 158 successive approximation register -------------------- 345 sva0, sva1 ------------------------------------------------- 268 syc ------------------------------------------------------------ 107 sys ------------------------------------------------------------ 105 system control register ----------------------------------- 107 system register set ------------------------------------------76 system status register ------------------------------------ 105 [t] tcl20 to tcl70 ------------------------------------------- 213 tcl21 to tcl71 ------------------------------------------- 213 ti00, ti01, ti10, ti11, ti4, ti5 ---------------------------62 ti2, ti3 ---------------------------------------------------------61 timer clock selection registers 20 to 70 ------------- 213 timer clock selection registers 21 to 71 ------------- 213 timer/counter function ------------------------------------ 174 tm0, tm1 --------------------------------------------- 174, 176 tm2 to tm7 ------------------------------------------- 209, 211 tm23, tm45, tm67 --------------------------------------- 227 tmc0, tmc1 ------------------------------------------------ 179 tmc2 to tmc7 --------------------------------------------- 216 tmic00 ----------------------------------------------139 to 141 tmic01 ----------------------------------------------139 to 141 tmic10 ----------------------------------------------139 to 141 tmic11 ----------------------------------------------139 to 141 tmic2 to tmic7 -----------------------------------139 to 141 to0, to1, to4, to5 ---------------------------------------62 to2, to3 ------------------------------------------------------61 toc0, toc1 ------------------------------------------------ 182 appendix c index user?s manual u13850ej4v0um 513 transfer completion interrupt request ---------------- 360 transmit shift registers 0, 1 ----------------------------- 313 txd0 ------------------------------------------------------------60 txd1 ------------------------------------------------------------61 txs0, txs1 ------------------------------------------------- 313 [u] uar ----------------------------------------------------------- 459 uart0, uart1 -------------------------------------------- 312 uben -----------------------------------------------------------65 usr ----------------------------------------------------------- 467 [v] v850/sb1 ------------------------------------------------------31 v850/sb2 ------------------------------------------------------41 variable-length serial control register 4 -------------- 335 variable-length serial i/o shift register 4 ------------- 333 variable-length serial setting register 4 -------------- 336 v dd ---------------------------------------------------------------68 v pp ---------------------------------------------------------------68 v ss ---------------------------------------------------------------68 [w] wait ------------------------------------------------------------67 wait function ------------------------------------------------ 110 wake-up controller ---------------------------------------- 255 wake-up function ------------------------------------------ 298 watch timer clock selection register ----------------- 233 watch timer function ------------------------------------- 230 watch timer mode control register -------------------- 232 watchdog timer clock selection register ------------ 239 watchdog timer function -------------------------------- 236 watchdog timer mode ----------------------------------- 237 watchdog timer mode register -------------------143, 240 wdcs -------------------------------------------------------- 239 wdtic ---------------------------------------------- 139 to 141 wdtm --------------------------------------------------143, 240 word access ------------------------------------------------ 108 wrap-around of cpu address space ------------------ 81 wrh ------------------------------------------------------------ 66 writing with flash programmer ------------------------- 424 wrl ------------------------------------------------------------ 65 wtncs ------------------------------------------------------ 233 wtnic ---------------------------------------------- 139 to 141 wtniic --------------------------------------------- 139 to 141 wtnm -------------------------------------------------------- 232 [x] x1 ---------------------------------------------------------------- 67 x2 ---------------------------------------------------------------- 67 xt1 -------------------------------------------------------------- 67 xt2 -------------------------------------------------------------- 67 user?s manual u13850ej4v0um 514 [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we?ve taken, you may encounter problems in the documentation. please complete this form whenever you?d like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 taiwan nec electronics taiwan ltd. fax: +886-2-2719-5951 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 01.2 name company from: tel. fax facsimile message |
Price & Availability of UPD703036AYGF-XXX-3BA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |