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hb56d473ej series 4,194,304-word 72-bit high density dynamic ram module ade-203-725a (z) rev. 1.0 feb. 27, 1997 description the hb56d473ej belongs to 8 byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 4 and 8 byte processor applications. the hb56d473ej is a 4m 72 dynamic ram module, mounted 16 pieces of 16-mbit dram (hm5117400) sealed in soj package and 8 pieces of 4-mbit dram (hm514100) sealed in soj package, 1 pieces of 16- bit bicmos line driver (74abt16244) sealed in tssop package and 1 pieces of 20-bit bicmos line driver (74abt16827) sealed in tssop package. an outline of the hb56d473ej is 168-pin socket type package (dual lead out). therefore, the hb56d473ej makes high density mounting possible without surface mount technology. the hb56d473ej provides common data inputs and outputs. decoupling capacitors are mounted on the module board. features 168-pin socket type package (dual lead out) ? outline: 133.35 mm (length) 25.40 mm (height) 9.00 mm (thickness) ? lead pitch: 1.27 mm single 5 v ( 5%) supply high speed ? access time: t rac = 60/70 ns (max) t cac = 20/25 ns (max) low power dissipation ? active mode: 12.5/11.3 w (max) ? standby mode (ttl): 588 mw (max) (cmos): 462 mw (max) buffered input except ras and dq 4 byte interleave enabled, dual address input (a0/b0) jedec standard outline buffered 8-byte dimm fast page mode capability 2,048 refresh cycles: 32 ms
hb56d473ej series 2 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh ttl compatible ordering information type no. access time package contact pad hb56d473ej-6 HB56D473EJ-7 60 ns 70 ns 168-pin dual lead out socket type gold pin arrangement 1 pin 85 pin 10 pin 94 pin 11 pin 95 pin 40 pin 124 pin 41 pin 125 pin 84 pin 168 pin front side back side
hb56d473ej series 3 pin arrangement pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe2 86 dq36 128 nc 3 dq1 45 re2 87 dq37 129 nc 4 dq2 46 ce4 88 dq38 130 ce5 5 dq3 47 ce6 89 dq39 131 ce7 6v cc 48 we2 90 v cc 132 pde 7 dq4 49 v cc 91 dq40 133 v cc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 v cc 101 dq49 143 v cc 18 v cc 60 dq24 102 v cc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 v ss 65 dq25 107 v ss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 v cc 68 v ss 110 v cc 152 v ss 27 we0 69 dq28 111 nc 153 dq64 28 ce0 70 dq29 112 ce1 154 dq65 29 ce2 71 dq30 113 ce3 155 dq66 30 re0 72 dq31 114 nc 156 dq67 31 oe0 73 v cc 115 nc 157 v cc 32 v ss 74 dq32 116 v ss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70
hb56d473ej series 4 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 nc 164 pd4 39 nc 81 pd5 123 nc 165 pd6 40 v cc 82 pd7 124 v cc 166 pd8 41 nc 83 id0 (nc) 125 nc 167 id1 (v ss ) 42 nc 84 v cc 126 b0 168 v cc pin description pin name function a0 to a10, b0 address input row address : a0 to a10, b0 column address : a0 to a10, b0 refresh address (d0 to d15) : a0 to10, b0 refresh address (m0 to m7) : a0 to a9, b0 dq0 to dq71 data-in/data-out re0 , re2 row address strobe ( ras ) ce0 to ce7 column address strobe ( cas ) we0 , we2 read/write enable oe0 , oe2 output enable v cc power supply v ss ground pd1 to pd8 presence detect id0, id1 id bit pde presence detect enable nc no connection
hb56d473ej series 5 presence detect pin assignment pde = low pde = high pin name pin no. 60 ns 70 ns all pd1 79 1 1 high-z pd2 163 1 1 high-z pd3 80 0 0 high-z pd4 164 1 1 high-z pd5 81 0 0 high-z pd6 165 1 0 high-z pd7 82 1 1 high-z pd8 166 1 1 high-z note: 1: high level (driver output) 0: low level (driver output)
hb56d473ej series 6 block diagram v cc dq0 dq1 dq2 dq3 i/o i/o i/o i/o cas ras d0 we oe dq4 dq5 dq6 dq7 i/o i/o i/o i/o cas ras d1 we oe dq9 dq10 dq11 dq12 i/o i/o i/o i/o cas ras we oe dq13 dq14 dq15 dq16 i/o i/o i/o i/o cas ras we oe dq18 dq19 dq20 dq21 i/o i/o i/o i/o cas ras d4 we oe dq22 dq23 dq24 dq25 i/o i/o i/o i/o cas ras d5 we oe dq27 dq28 dq29 dq30 i/o i/o i/o i/o cas ras d6 we oe dq31 dq32 dq33 dq34 i/o i/o i/o i/o cas ras d7 we oe re0 oe0 we0 ce0 dq36 dq37 dq38 dq39 i/o i/o i/o i/o cas ras d8 we oe dq40 dq41 dq42 dq43 i/o i/o i/o i/o cas ras d9 we oe dq45 dq46 dq47 dq48 i/o i/o i/o i/o cas ras d10 we oe dq49 dq50 dq51 dq52 i/o i/o i/o i/o cas ras d11 we oe dq54 dq55 dq56 dq57 i/o i/o i/o i/o cas ras d12 we oe dq58 dq59 dq60 dq61 i/o i/o i/o i/o cas ras d13 we oe dq63 dq64 dq65 dq66 i/o i/o i/o i/o cas ras d14 we oe dq67 dq68 dq69 dq70 i/o i/o i/o i/o cas ras d15 we oe re2 oe2 we2 ce4 d0 to d15, m0 to m7, 74abt16244, 74abt16827 v ss b0 a0 d0 to d15, m0 to m7 d0 to d15, m0 to m7, 74abt16244, 74abt16827 d8 to d15, m4 to m7 d0 to d7, m0 to m3 v cc v cc v ss v cc v ss pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 note : d0 to d15 : hm5117400 m0 to m7 : hm514100 : 74abt16244, 74abt16827 0.22 f 26 pcs m ce1 ce2 ce3 ce5 ce6 ce7 pd1 to pd8 dq44 dq8 dq53 dq17 dq62 dq26 dq71 dq35 din/dout cas ras m4 we din/dout cas ras m0 we din/dout cas ras m5 we din/dout cas ras m1 we din/dout cas ras m6 we din/dout cas ras m2 we din/dout cas ras m7 we din/dout cas ras m3 we a1 to a10 d2 d3 v cc v ss v cc v ss v cc
hb56d473ej series 7 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t ?.5 to +7.0 v supply voltage relative to v ss v cc ?.5 to +7.0 v short circuit output current iout 50 ma power dissipation pt 25 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c recommended dc operating conditions (ta = 0 to 70 c) parameter symbol min typ max unit note supply voltage v ss 000 v v cc 4.75 5.0 5.25 v 1 input high voltage v ih 2.4 5.5 v 1 input low voltage v il ?.5 0.8 v 1 note: 1. all voltage referred to v ss .
hb56d473ej series 8 dc characteristics (ta = 0 to 70 c, v cc = 5 v 5%, v ss = 0 v) 60 ns 70 ns parameter symbol min max min max unit test conditions notes operating current i cc1 2384 2144 ma t rc = min 1, 2 standby current i cc2 112 112 ma ttl interface ras , cas = v ih dout = high-z 88 88 ma cmos interface ras , cas 3 v cc ?0.2 v dout = high-z ras -only refresh current i cc3 2384 2144 ma t rc = min 2 standby current i cc5 184 184 ma ras = v ih , cas = v il dout = enable 1 cas -before- ras refresh current i cc6 2384 2144 ma t rc = min fast page mode current i cc7 2224 1984 ma t pc = min 1, 3 input leakage current i li ?0 10 ?0 10 m a 0 v vin 5.5 v output leakage current i lo ?0 10 ?0 10 m a 0 v vout 5.5 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = ? ma output low voltage v ol 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected, i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . capacitance (ta = 25 c, v cc = 5 v 5%) parameter symbol typ max unit notes input capacitance (address) c i1 ?0pf1 input capacitance ( cas , we , oe )c i2 ?0pf1 input capacitance ( ras )c i3 ?9pf1 i/o capacitance (dq0 to dq7, dq9 to dq16, dq18 to dq25, dq27 to dq34, dq36 to dq43, dq45 to dq52, dq54 to dq61, dq63 to dq70) c i/o1 20 pf 1, 2 i/o capacitance (dq8, dq17, dq26, dq35, dq44, dq53, dq62, dq71) c i/o2 25 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
hb56d473ej series 9 ac characteristics (ta = 0 to 70 c, v cc = 5 v 5%, v ss = 0 v) *1, *2 test conditions input rise and fall times: 5 ns input timing reference levels: 0.8 v, 2.4 v output timing reference levels: 0.4 v, 2.4 v output load: 2 ttl gate + c l (100 pf) (including scope and jig) read, write and refresh cycles (common parameters) 60 ns 70 ns parameter symbol min max min max unit notes random read or write cycle time t rc 110 130 ns ras precharge time t rp 40 50 ns cas precharge time t cp 10 10 ns ras pulse width t ras 60 10000 70 10000 ns cas pulse width t cas 15 10000 20 10000 ns row address setup time t asr 55ns row address hold time t rah 10 10 ns column address setup time t asc 00ns column address hold time t cah 15 15 ns ras to cas delay time t rcd 20 40 20 45 ns 3 ras to column address delay time t rad 15 25 15 30 ns 4 ras hold time t rsh 20 25 ns cas hold time t csh 60 70 ns cas to ras precharge time t crp 15 15 ns oe to din delay time t oed 20 25 ns 5, 18 oe delay time from din t dzo 0 0 ns 6, 18 cas delay time from din t dzc 00ns6 transition time (rise and fall) t t 3 50 3 50 ns 7 refresh period (2,048 cycles) t ref 32 32 ms
hb56d473ej series 10 read cycle 60 ns 70 ns parameter symbol min max min max unit notes access time from ras t rac 60 70 ns 8, 9 access time from cas t cac 20 25 ns 9, 10, 17 access time from address t aa 35 40 ns 9, 11, 17 access time from oe t oea 20 25 ns 9, 18 read command setup time t rcs 00ns read command hold time to cas t rch 00ns12 read command hold time to ras t rrh 55ns12 column address to ras lead time t ral 35 40 ns column address to cas lead time t cal 30 35 ns cas to output in low-z t clz 22ns output data hold time t oh 33ns output data hold time from oe t oho 33ns18 output buffer turn-off time t off 20 25 ns 13 output buffer turn-off to oe t oez 20 25 ns 13, 18 cas to din delay time t cdd 20 25 ns 5 write cycle 60 ns 70 ns parameter symbol min max min max unit notes write command setup time t wcs 00ns14 write command hold time t wch 15 15 ns write command pulse width t wp 10 10 ns data-in setup time t ds 00ns15 data-in hold time t dh 20 20 ns 15
hb56d473ej series 11 refresh cycle 60 ns 70 ns parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 15 15 ns cas hold time (cbr refresh cycle) t chr 10 10 ns we setup time (cbr refresh cycle) t wrp 55ns we hold time (cbr refresh cycle) t wrh 10 10 ns ras precharge to cas hold time t rpc 10 10 ns
hb56d473ej series 12 fast page mode cycle 60 ns 70 ns parameter symbol min max min max unit notes fast page mode cycle time t pc 40 45 ns fast page mode ras pulse width t rasp 100000 100000 ns 16 access time from cas precharge t cpa 40 45 ns 9, 17 ras hold time from cas precharge t cprh 40 45 ns notes: 1. ac measurements assume t t = 5 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh cycle or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 2ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs is not restrictive operating parameters. it is included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 15. these parameters are referred to cas leading edge in early write cycle. 16. t rasp defines ras pulse width in fast page mode cycles. 17. access time is determined by the longest among t aa , t cac or t cpa . 18. parity bit of this item must not use (dq8, dq17, dq26, dq35, dq44, dq53, dq62, dq71). 19. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hb56d473ej series 13 timing waveforms * 19 read cycle ras address we dout oe din t rc t ras t rp t csh t crp t rcd t rsh t cas t t t rad t ral t cal t asc t cah t asr row column t rah t rcs t rch t rrh t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas
hb56d473ej series 14 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t wp t ds t dh din t wcs wcs (min) high-z* t cas
hb56d473ej series 15 ras -only refresh cycle ras address dout high-z row t off t asr t rah t crp t t t ras t rc t rp t rpc t crp cas
hb56d473ej series 16 cas -before- ras refresh cycle ras cas we address dout high-z t off t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
hb56d473ej series 17 fast page mode read cycle we din oe dout address ras t rasp t cprh t rp t t t csh t rcd t cas t cp t cas t pc t rsh t cp t cas t crp t ral t cal t cah asc t t asc t t cal t cal t asc t t rad t asr t rah tt rch t rch tt t rrh t rch t cdd high-z t dzc t cdd t dzc t cdd t dzc high-z high-z t dzo t oed t oed t dzo tt oed t oh t aa t oh t aa t oh t cpa t cpa t rac t aa t oea t oea t oea t oho t oho t oho t cac t clz t oez t off t cac t clz t oez t off t cac t clz t oez t off dout n dout 2 dout 1 row column 1 column 2 column n cah cah rcs rcs rcs dzo cas
hb56d473ej series 18 fast page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas t wp t wp t wp
hb56d473ej series 19 physical outline unit: mm/inch 6.35 0.250 3.175 0.125 6.35 0.250 1.00 0.039 detail c detail b detail a 0.25 max 2.54 min 0.010 max 0.100 min 3.125 0.125 3.125 0.125 0.123 0.005 0.123 0.005 1.27 0.050 3.00 133.35 0.118 5.250 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.150 1.450 a b c 1 84 front side back side 1.27 0.10 4.00 min 0.157 min 0.050 0.004 9.00 max 0.354 max 85 4.00 0.157 17.78 0.700 25.40 1.000 168 2 ? f 3.00 2 ? f 0.118 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 2.00 0.10 0.079 0.004 3.175 0.125 component area (front) component area (back)
hb56d473ej series 20 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071
hb56d473ej series 21 revision record rev. date contents of modification drawn by approved by 1.0 feb. 27, 1997 initial issue

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