View BT458LPJ165_2258416.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet l45801 rev. n september 2, 1999 bt457/bt458 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac the bt457 and bt458 are pin- and software-compatible ramdacs designed specifically for high-performance, high-resolution color graphics. the architecture enables a display of 1280 x 1024 bit-mapped color graphics (up to 8 bits per pixel plus up to 2 bits of overlay information). this minimizes the use of costly ecl interfacing, because most of the high-speed (pixel clock) logic is contained on-chip. the multiple pixel ports and internal multiplexing enable ttl-compatible interface (up to 32 mhz) to the frame buffer, while maintaining the 165 mhz video data rates required for sophisticated color graphics. the bt457 is a single-channel version of the bt458 and has a 256 x 8 color lookup table with a single 8-bit video d/a converter. it includes a pll output to enable subpixel synchronization of multiple bt457s. on-chip features include programmable blink rates, bit plane masking and blinking, color overlay capability, and a dual-port color palette ram. functional block diagram clock* clock vaa gnd fsadjust vref ld* p[7:0] (a-e) ol[1,0] (a-e) sync* blank* clock 40 10 40 10 40 10 8 2 8 2 4(8) 4(8) 4(8) comp ior (n/c) iog (iout) iob (pll) 4(8) 8 d[7:0] ce* r/w co c1 load control mux control blink control latch latch mux read mask blink mask 256 x 12 (24) color palette 4 x 12 (24) overlay bus control addr reg r g b 457-8_001 distinguishing features ? 165, 135, 125, 110, 80 mhz operation 4:1 or 5:1 input mux 256-word dual-port color palette four dual-port overlay registers rs-343a-compatible outputs bit plane read and blink masks standard mpu interface 84-pin plcc or pga package +5 v cmos monolithic construction applications high-resolution color graphics cae/cad/cam image processing video reconstruction
l45801 rev. n conexant information provided by conexant systems, inc. (conexant) is believed to be accurate and reliable. however, no responsibility i s assumed by conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent rights of conexant other than for circuitry embodied in conexan t products. conexant reserves the right to change circuitry at any time without notice. this document is subject to change withou t notice. conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a conexant product can reasonably be expected to result in personal injury or death. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting f rom such improper use or sale. the trademarks ?conexant? and the conexant symbol are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. ? 1999 conexant systems, inc. printed in u.s.a. all rights reserved reader response: conexant strives to produce quality documentation, and welcomes your feedback. please send comments and suggestions to conexant.tech.pubs@conexant.com . for technical questions, contact your local conexant sales office or field applications engineer. ordering information model number ram dacs speed package ambient temperature range bt458lg165 256 x 24 triple 8-bit 165 mhz 84-pin ceramic pga 0 to + 70 c bt458kg135 256 x 24 triple 8-bit 135 mhz 84-pin ceramic pga 0 to + 70 c bt458kg125 256 x 24 triple 8-bit 125 mhz 84-pin ceramic pga 0 to + 70 c bt458kg110 256 x 24 triple 8-bit 110 mhz 84-pin ceramic pga 0 to + 70 c bt458kg80 256 x 24 triple 8-bit 80 mhz 84-pin ceramic pga 0 to + 70 c BT458LPJ165 256 x 24 triple 8-bit 165 mhz 84-pin plastic j-lead 0 to + 70 c bt458lpj135 256 x 24 triple 8-bit 135 mhz 84-pin plastic j-lead 0 to + 70 c bt458lpj125 256 x 24 triple 8-bit 125 mhz 84-pin plastic j-lead 0 to + 70 c bt458lpj110 256 x 24 triple 8-bit 110 mhz 84-pin plastic j-lead 0 to + 70 c bt458lpj80 256 x 24 triple 8-bit 80 mhz 84-pin plastic j-lead 0 to + 70 c bt457kg135 256 x 8 single 8-bit 135 mhz 84-pin ceramic pga 0 to + 70 c bt457kg125 256 x 8 single 8-bit 125 mhz 84-pin ceramic pga 0 to + 70 c bt457kg110 256 x 8 single 8-bit 110 mhz 84-pin ceramic pga 0 to + 70 c bt457kg80 256 x 8 single 8-bit 80 mhz 84-pin ceramic pga 0 to + 70 c bt457kpj135 256 x 8 single 8-bit 135 mhz 84-pin plastic j-lead 0 to + 70 c bt457kpj125 256 x 8 single 8-bit 125 mhz 84-pin plastic j-lead 0 to + 70 c bt457kpj110 256 x 8 single 8-bit 110 mhz 84-pin plastic j-lead 0 to + 70 c bt457kpj80 256 x 8 single 8-bit 80 mhz 84-pin plastic j-lead 0 to + 70 c
l45801 rev. n conexant iii table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 mpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 6 2.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 read mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 blink mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 bt458 test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.5 bt457 control/test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 3.0 pc board layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pc board considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 power and ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 device decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.5 comp decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.6 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.7 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.8 analog output protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 4.0 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 clock interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 using multiple devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 bt457 nonvideo applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
table of contents bt457/bt458 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac iv conexant l45801 rev. n 4.4 initializing the bt458 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 initializing the bt457 (monochrome) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6 initializing the bt457 (color) 24-bit mpu data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.7 initializing the bt457 (color) 8-bit mpu data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 5.0 parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
bt457/bt458 list of figures 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac l45801 rev. n conexant v list of figures figure 1-1. bt457/bt458 84-pin j-lead package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 figure 1-2. bt457/bt458 84-pin pga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 figure 1-3. video input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 figure 1-4. composite video output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 figure 3-1. sample layout showing power and ground plane isolation gaps . . . . . . . . . . . . . . . . . . . 3-2 figure 3-2. typical connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 figure 4-1. generating the bt458 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 figure 4-2. generating the bt457 signals (monochrome application). . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-3. generating the bt457 clock signals (color application) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 5-1. video input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-2. mpu read/write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-3. 84-pin plastic j-lead (plcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 figure 5-4. 84-pin ceramic pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
list of figures bt457/bt458 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac vi conexant l45801 rev. n
bt457/bt458 list of tables 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac l45801 rev. n conexant vii list of tables table 1-1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 table 1-2. pin labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 table 1-3. address register (addr) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 table 1-4. palette and overlay select truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 table 1-5. video output truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 table 2-1. command registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 table 2-2. bt458 test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-3. bt457 control test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 3-1. typical parts list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 table 5-1. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -1 table 5-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-3. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-4. ac characteristics for 165 mhz and 135 mhz devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-5. ac characteristics for 125 mhz and 110 mhz devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 table 5-6. ac characteristics for 80 mhz device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 table 5-7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
list of tables bt457/bt458 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac viii conexant l45801 rev. n
l45801 rev. n conexant 1-1 1 1.0 circuit description 1.1 pin descriptions the bt457/bt458 is available in both 84-pin plastic leaded chip carrier (plcc) and ceramic pga packages, as illustrated in figures 1-1 and 1-2 . table 1-1 provides pin descriptions. table 1-2 gives pin labels for the pga package. figure 1-1. bt457/bt458 84-pin j-lead package pin bt458 bt457 28 29 30 ior iog iob n/c iout pll p4e p5a p5b p5c p5d p5e p6a p6b p6c p6d p6e p7a p7b p7c p7d p7e vaa gnd vaa gnd vref 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 p2a p1e p1d p1c p1b p1a p0e p0d p0c p0b p0a ol1e ol1d ol1c ol1b ol1a ol0e ol0d ol0c ol0b ol0a 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d[0] d[7] d[6] d[5] d[4] d[3] d[2] d[1] ce* gnd gnd vaa c0 c1 r/w vaa (n/c)|or (iout)iog (pll)iob fsadjust comp 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 p2b p2d p2c p2e p3a p3e p3d p3c p3b gnd vaa vaa clock clock ld* blank* sync* p4a p4d p4c p4b 457-8_002
1.0 circuit description bt457/bt458 1.1 pin descriptions 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1-2 conexant l45801 rev. n figure 1-2. bt457/bt458 84-pin pga package pin bt458 bt457 a10 a11 b9 iog iob ior iout pll n/c bt457/458 (top view) 12 11 10 9 8 7 6 5 4 3 2 1 a b cde fg h j kl m a b c d e f g h j k l m (bottom view) alignment marker (on top) 12 11 10 9 8 7 6 5 4 3 2 1 comp gnd vaa p7d p7b p6e p6c p6b p5e p5c p5b p4b iob gnd vaa p7e p7c p7a p6d p6a p5d p5a p4c p4a iog fsadj vref p4d p4b sync* vaa ior blk* ld* c1 r/w clk* clk vaa co vaa vaa gnd gnd p3e gnd ce* d[7] p3c p3d d[6] d[5] p3a p3b d[4] d[2] d[0] p2a p2c p2e d[3] d[1] ol0b ol0e ol1b ol1e p0b p0d p1a p1d p1e p2d ol0a ol0c ol0d ol1a ol1c ol1d p0a p0c p0e p1b p1c p2b comp gnd vaa p7d p7b p6e p6c p6b p5e p5c p5b p4e iob gnd vaa p7e p7c p7a p6d p6a p5d p5a p4c p4a iog p4d p4b sync* vaa ior blk* ld* c1 r/w clk* clk vaa co vaa vaa gnd gnd p3e gnd ce* d7 p3c p3d d[6] d[5] p3a p3b d[4] d[2] d[0] p2a p2c p2e d[3] d[1] ol0b ol0e ol1b ol1e p0b p0d p1a p1d p1e p2d ol0a ol0c ol0d ol1a ol1c ol1d p0a p0c p0e p1b p1c p2b vref fsadj 457-8_003
bt457/bt458 1.0 circuit description 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1.2 pin descriptions l45801 rev. n conexant 1-3 1.2 pin descriptions table 1-1. pin descriptions (1 of 2) pin name description blank* composite blank control input (ttl compatible). a logical 0 drives the analog outputs to the blanking level, as specified in table 1-5 . blank* is latched on the rising edge of ld*. when blank* is a logical 0, the pixel and overlay inputs are ignored. sync* composite sync control input (ttl compatible). a logical 0 on this input switches off a 40 ire current source on the iog output (see figure 1-4 ). sync* does not override any other control or data input, as illustrated in table 1-5 ; therefore, it should be asserted only during the blanking interval. it is latched on the rising edge of ld*. if sync information is not generated on the iog output, this pin should be connected to gnd. ld* load control input (ttl compatible). the p[7:0] {a ? e}, ol[1,0] {a ? e}, blank*, and sync* inputs are latched on the rising edge of ld*. while ld* is either one fourth or one fifth the clock rate, it can be phase independent of the clock and clock* inputs. ld* can have any duty cycle within the limits specified in the ac characteristics section. p[7:0] {a ? e} pixel select inputs (ttl compatible). these inputs are used to specify, on a pixel basis, which of the 256 entries in the color palette ram is used to provide color information. either 4 or 5 consecutive pixels (up to 8 bits per pixel) are input through this port. they are latched on the rising edge of ld*. unused inputs should be connected to gnd. the {a} pixel is output first, followed by the {b} pixel, then the {c} pixel, etc., until all 4 or 5 pixels have been output, at which point the cycle repeats. ol[1,0] {a ? e} overlay select inputs (ttl compatible). these control inputs are latched on the rising edge of ld*. in conjunction with bit 6 of the command register, they specify which palette is to be used for color information, as follows: when accessing the overlay palette, the p[7:0] {a ? e} inputs are ignored. overlay information bits (up to 2 bits per pixel) for either 4 or 5 consecutive pixels are input through this port. unused inputs should be connected to gnd. ior, iog, iob, iout red, green, and blue video current outputs. these high-impedance current sources can directly drive a doubly terminated 75 ? coaxial cable (see figure 3-2 ). the bt457 outputs iout rather than ior, iog, and iob. ol1 ol0 cr6 = 1 cr6 = 0 0 0 color palette ram overlay color 0 0 1 overlay color 1 overlay color 1 1 0 overlay color 2 overlay color 2 1 1 overlay color 3 overlay color 3
1.0 circuit description bt457/bt458 1.2 pin descriptions 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1-4 conexant l45801 rev. n pll phase lock loop current output ? bt457 only. this high-impedance current source is used to enable multiple bt457s to be synchronized with subpixel resolution when used with an external pll. a logical 1 on the blank* input results in no current being output onto this pin, while a logical 0 results in the following current being output: pll (ma) = 3,227 * vref (v) / rset ( ? ) if subpixel synchronization of multiple devices is not required, this output should be connected to gnd (either directly or through a resistor up to 150 ? ). comp compensation pin. this pin provides compensation for the internal reference amplifier. a 0.1 f ceramic capacitor must be connected between this pin and vaa ( figure 3-2 ). connecting the capacitor to vaa rather than to gnd provides the highest possible power supply noise rejection. the comp capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and to maximize the capacitor's self-resonant frequency to be greater than the ld* frequency. the pc board layout considerations section contains critical layout criteria. fsadjust full-scale adjust control. a resistor (rset) connected between this pin and gnd controls the magnitude of the full-scale video signal ( figure 3-1 ). the ire relationships in figure 1-4 are maintained, regardless of the full-scale output current. the relationship between rset and the full-scale output current on iog (or iout for the bt457) is as follows: rset ( ? ) = 11,294 * vref (v) / iog (ma) the full-scale output current on ior and iob (for the bt458) for a given rset is as follows: ior, iob (ma) = 8,067 * vref (v) / rset ( ? ) vref voltage reference input. an external voltage reference circuit, such as that illustrated in figure 3-2 , must supply this input with a 1.235 v (typical) reference. the use of a resistor network to generate the reference is not recommended, because any low-frequency power supply noise on vref is directly coupled onto the analog outputs. a 0.1 f ceramic capacitor is used to decouple this input to vaa, as shown in figure 3-2 . if vaa is excessively noisy, better performance can be obtained by decoupling vref to gnd. the decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. refer to the pc board layout considerations section for critical layout criteria. clock, clock* clock inputs. these differential clock inputs are driven by ecl logic configured for single-supply (+5 v) operation. the clock rate is typically the pixel clock rate of the system. refer to the pc board layout considerations section for critical layout criteria. ce* chip enable control input (ttl compatible). this input must be a logical 0 to enable data to be written to or read from the device. during write operations, data is internally latched on the rising edge of ce*. glitches should be avoided on this edge-triggered input. r/w read/write control input (ttl compatible). to write data to the device, both ce* and r/w must be a logical 0. to read data from the device, ce* must be a logical 0 and r/w must be a logical 1. r/w is latched on the falling edge of ce*. c[1,0] command control inputs (ttl compatible). c0 and c1 specify the type of read or write operation being performed, as presented in table 1-3 . they are latched on the falling edge of ce*. d[7:0] data bus (ttl compatible). data transfers into and out of the device over this 8-bit bidirectional data bus. d0 is the least significant bit. vaa analog power. all vaa pins must be connected together on the same pcb plane to prevent latchup. refer to the pc board layout considerations section for critical layout criteria. gnd analog ground. all gnd pins must be connected together on the same pcb plane to prevent latchup. refer to the pc board layout considerations section for critical layout criteria. table 1-1. pin descriptions (2 of 2) pin name description
bt457/bt458 1.0 circuit description 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1.2 pin descriptions l45801 rev. n conexant 1-5 table 1-2. pin labels pin number pin label pin number pin label pin number pin label l9 blank* k11 p5a c12 vaa m10 sync* l12 p5b c11 vaa m9 ld* k12 p5c a9 vaa l8 clock* j11 p5d l7 vaa m8 clock j12 p5e m7 vaa a7 vaa g1 p0a h11 p6a g2 p0b h12 p6b b12 gnd h1 p0c g12 p6c b11 gnd h2 p0d g11 p6d m6 gnd j1 p0e f12 p6e b6 gnd a6 gnd j2 p1a f11 p7a k1 p1b e12 p7b a12 comp l1 p1c e11 p7c b10 fs adjust k2 p1d d12 p7d c10 vref l2 p1e d11 p7e a5 ce* k3 p2a a1 ol0a b8 r/w m1 p2b c2 ol0b a8 c1 l3 p2c b1 ol0c b7 c0 m2 p2d c1 ol0d m3 p2e d2 ol0e c3 d[0] b2 d[1] l4 p3a d1 ol1a b3 d[2] m4 p3b e2 ol1b a2 d[3] l5 p3c e1 ol1c a3 d[4] m5 p3d f1 ol1d b4 d[5] l6 p3e f2 ol1e a4 d[6] b5 d[7] m11 p4a a10 iog(iout) l10 p4b a11 iob (pll) l11 p4c b9 ior (n/c) k10 p4d m12 p4e note(s): bt457 pin names are in parentheses.
1.0 circuit description bt457/bt458 1.3 mpu interface 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1-6 conexant l45801 rev. n 1.3 mpu interface as illustrated in the functional block diagram on the cover page, the bt457/458 supports a standard mpu bus interface, allowing the mpu direct access to the internal control registers and color/overlay palettes. the dual-port color palette ram and dual-port overlay registers allow color updating, without contention, with the display refresh process. as presented in table 1-3 , the c0 and c1 control inputs, in conjunction with the internal address register, specify which control register, color palette ram entry, or overlay register is accessed by the mpu. the 8-bit address register (addr[7:0]) is used to address the internal ram and registers, eliminating the requirement for external address multiplexers. addr0 corresponds to d[0] and is the least significant bit. bt458 reading/writing color data to write color data, the mpu loads the address register with the address of the color palette ram location or overlay register to be modified. the mpu performs three successive write cycles (red, green, and blue), using c0 and c1 to select either the color palette ram or overlay registers. during the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. the address register then increments to the next location, which the mpu can modify by writing another sequence of red, green, and blue data. to read color data, the mpu loads the address register with the address of the color palette ram location or overlay register to be read. the mpu performs three successive read cycles (red, green, and blue), using c0 and c1 to select either the color palette ram or overlay registers. following the blue read cycle, the address register increments to the next location, which the mpu can read by reading another sequence of red, green, and blue data. table 1-3. address register (addr) operation addr[7:0] c1 c0 addressed by mpu $xx 0 0 address register $00 ? $ff 0 1 color palette ram $00 1 1 overlay color 0 $01 1 1 overlay color 1 $02 1 1 overlay color 2 $03 1 1 overlay color 3 $04 1 0 read mask register $05 1 0 blink mask register $06 1 0 command register $07 1 0 control/test register
bt457/bt458 1.0 circuit description 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1.3 mpu interface l45801 rev. n conexant 1-7 when accessing the color palette ram, the address register resets to $00 after a blue read or write cycle to location $ff. when accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register three. to keep track of the red, green, and blue read/write cycles, the address register has two additional bits that count modulo three. they are reset to 0 when the mpu reads or writes to the address register. the mpu does not have access to these bits. the other 8 bits of the address register (addr[7:0]) are accessible to the mpu. bt457 reading/writing color data (normal mode) to write color data, the mpu loads the address register with the address of the color palette ram location or overlay register to be modified. the mpu performs a color write cycle, using c0 and c1 to select either the color palette ram or the overlay registers. the address register then increments to the next location, which the mpu can modify by writing another color. reading color data is similar to writing it, except the mpu executes read cycles. this mode is useful if a 24-bit data bus is available, because 24 bits of color information (8 bits each of red, green, and blue) can be read or written to three bt457s in a single mpu cycle. in this application, the ce* inputs of all three bt457s are connected together. if only an 8-bit data bus is available, the ce* inputs must be individually selected during the appropriate color write cycle (red ce* during red write cycle, blue ce* during blue write cycle, and green ce* during green write cycle). when accessing the color palette ram, the address register resets to $00 after a read or write cycle to location $ff. when accessing the overlay registers, the address register increments to $04 following a read or write cycle to overlay register three. bt457 reading/writing color data (rgb mode) to write color data, the mpu loads the address register with the address of the color palette ram location or overlay register to be modified. the mpu performs three successive write cycles (8 bits each of red, green, and blue), using c0 and c1 to select either the color palette ram or the overlay registers. after the blue write cycle, the address register then increments to the next location, which the mpu can modify by writing another sequence of red, green, and blue data. reading color data is similar to writing it, except the mpu executes read cycles. this mode is useful if only an 8-bit data bus is available. each bt457 is programmed to be a red, green, or blue ramdac and responds only to the assigned color read or write cycle. in this application, the bt457s share a common 8-bit data bus. the ce* inputs of all three bt457s must be asserted simultaneously only during color read/write cycles and address register write cycles. when accessing the color palette ram, the address register resets to $00 after a blue read or write cycle to location $ff. when accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register three. to keep track of the red, green, and blue read/write cycles, the address register has two additional bits that count modulo three. they are reset to 0 when the mpu reads or writes to the address register. the mpu does not have access to these bits. the other 8 bits of the address register (addr[7:0]) are accessible to the mpu.
1.0 circuit description bt457/bt458 1.3 mpu interface 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1-8 conexant l45801 rev. n additional information although the color palette ram and overlay registers are dual-ported, if the pixel and overlay data are addressing the same palette entry being written to by the mpu during the write cycle, one or more of the pixels on the display screen can be disturbed. a maximum of one pixel is disturbed if the write data from the mpu is valid during the entire chip enable time. the control registers are also accessed through the address register in conjunction with the c0 and c1 inputs, as specified in table 1-3 . all control registers can be written to or read by the mpu at any time. the address register does not increment following read or write cycles to the control registers, facilitating read-modify-write operations. if an invalid address loads into the address register, data written to the device is ignored, and invalid data is read by the mpu. frame buffer interface to enable pixel data to be transferred from the frame buffer at ttl data rates, the bt457/458 incorporates internal latches and multiplexers. as illustrated in figure 1-3 , on the rising edge of ld*, sync and blank information, color (up to 8 bits per pixel), and overlay (up to 2 bits per pixel) information, for either 4 or 5 consecutive pixels, are latched into the device. with this configuration, the sync and blank timing is recognized only with 4- or 5-pixel resolution. typically, the ld* signal is used to clock external circuitry to generate basic video timing. each clock cycle, the bt457/458 outputs color information based on the {a} inputs, followed by the {b} inputs, then the {c} inputs, etc., until all 4 or 5 pixels have been output, at which point the cycle repeats. the overlay inputs can have pixel timing, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis. on the other hand, they can be controlled by external character or cursor generation logic. to simplify the frame buffer interface timing, ld* can be phase shifted in any amount relative to clock. this enables the ld* signal to be derived by externally dividing clock by 4 or 5 independent of the propagation delays of the ld* generation logic. as a result, the pixel and overlay data are latched on the rising edge of ld*, independent of the clock phase. figure 1-3. video input/output timing clock data ior, iog, iob (iout ? bt457) p[7:0] (a ? e), ol[1,0] (a ? e), sync*, blank* ld* 457-8_014
bt457/bt458 1.0 circuit description 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1.3 mpu interface l45801 rev. n conexant 1-9 internal logic maintains an internal load signal synchronous to clock and is guaranteed to follow the ld* signal by at least one, but not more than four, clock cycles. this load signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. if 4:1 multiplexing is specified, only one rising edge of ld* should occur every four clock cycles. if 5:1 multiplexing is specified, only one rising edge of ld* should occur every five clock cycles. otherwise, the internal load generation circuitry assumes it is not locked onto the ld* signal and continuously attempts to resynchronize itself to ld*. color selection each clock cycle, 8 bits of color information (p7:0) and 2 bits of overlay information (ol1,0) for each pixel are processed by the read mask, blink mask, and command registers. through the control registers, individual bit planes can be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. to ensure blinking does not cause a color change to occur during the active display time (i.e., in the middle of the screen), the bt457/458 monitors the blank* input to determine vertical retrace intervals. a vertical retrace interval is recognized by determining that blank* has been a logical 0 for at least 256 ld* cycles. the processed pixel data is then used to select which color palette entry or overlay register is to provide color information. p[0] is the lsb when addressing the color palette ram. table 1-4 is the truth table used for color selection. video generation every clock cycle, the selected color information, from the color palette rams or overlay registers, is presented to the d/a converters. the sync* and blank* inputs are pipelined to maintain synchronization with the pixel data. they add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as described in figure 1-4 . varying output current from each d/a converter produces a corresponding voltage level, used to drive the color crt monitor. only the green output (iog) on the bt458 contains sync information. table 1-5 details how the sync* and blank* inputs modify the output levels. the d/a converters on the bt457 and bt458 use a segmented architecture in which bit currents are routed to either the current output or gnd by a sophisticated decoding scheme. this architecture eliminates the need for table 1-4. palette and overlay select truth table cr[6] ol[1] ol[0] p[7:0] addressed by frame 1 0 0 $00 color palette entry $00 1 0 0 $01 color palette entry $01 :::: : 1 0 0 $ff color palette entry $ff 0 0 0 $xx overlay color 0 x 0 1 $xx overlay color 1 x 1 0 $xx overlay color 2 x 1 1 $xx overlay color 3
1.0 circuit description bt457/bt458 1.3 mpu interface 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 1-10 conexant l45801 rev. n precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. an on-chip operational amplifier stabilizes the d/a converter?s full-scale output current against temperature and power supply variations. figure 1-4. composite video output waveforms no sync sync ma v ma v 19.05 1.44 0.00 0.714 0.054 0.000 26.67 9.05 7.62 0.00 1.000 0.340 0.286 0.000 92.5 ire 7.5 ire 40 ire white level black level blank level sync level 457-8_004 table 1-5. video output truth table description iog (iout) (ma) ior, iob (ma) sync* blank* dac input data white 26.67 19.5 1 1 $ff data data + 9.05 data + 1.44 1 1 data data - sync data + 1.44 data + 1.44 0 1 data black 9.05 1.44 1 1 $00 black-sync 1.44 1.44 0 1 $00 black 7.62 0 1 0 $xx sync 0 0 0 0 $xx note(s): typical with full-scale iog = 26.67 ma. rset = 523 ? and vref = 1.235 v.
l45801 rev. n conexant 2-1 2 2.0 registers 2.1 internal 2.1.1 command register the command register can be written or read by the mpu at any time and is not initialized. for proper operation, it must be initialized by the user after power-up. cr0 corresponds to data bus bit d[0]. table 2-1. command registers (1 of 2) function description cr7 multiplex select this bit specifies whether 4:1 or 5:1 multiplexing is to be used for the pixel and overlay inputs. if 4:1 is specified, the {e} pixel and {e} overlay inputs are ignored and should be connected to gnd, and the ld* input should be one fourth the clock rate. if 5:1 is specified, all of the pixel and overlay inputs are used, and the ld* input should be one fifth the clock rate. the pipeline delay of the bt457/458 can be reset to a fixed eight clock cycles. in this instance, each time the input multiplexing is changed, the bt457/458 must again be reset to a fixed pipeline delay. (0) (1) 4:1 multiplexing 5:1 multiplexing cr6 ram enable when the overlay select bits are 00, this bit specifies whether to use the color palette ram or overlay color 0 to provide color information. (0) (1) use overlay color 0 use color palette ram cr5,4 blink rate selection these 2 bits control the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. the numbers in parentheses specify the duty cycle (percent on/off). (00) (01) (10) (11) 16 on, 48 off (25/75) 16 on, 16 off (50/50) 32 on, 32 off (50/50) 64 on, 64 off (50/50) cr3 ol1 blink enable if a logical 1, this bit forces the ol1 {a ? e} inputs to toggle between a logical 0 and the input value at the selected blink rate prior to palette section. a value of logical 0 does not affect the value of the ol1 {a ? e} inputs. in order for overlay 1 bit plane to blink, bit cr1 must be set to a logical 1.
2.0 registers bt457/bt458 2.1 internal 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 2-2 conexant l45801 rev. n cr2 ol0 blink enable if a logical 1, this bit forces the ol0 {a ? e} inputs to toggle between a logical 0 and the input value at the selected blink rate prior to palette selection. a value of the logical 0 does not affect the value of the ol0 {a ? e} inputs. in order for overlay 0 bit plane to blink, bit cr0 must be set to a logical 1. cr1 ol1 display enable if a logical 0, this bit forces the ol1 {a ? e} inputs to a logical 0 prior to selecting the palettes. a value of a logical 1 does not affect the value of the ol1 {a ? e} inputs. (0) (1) disable enable cr0 ol0 display enable if a logical 0, this bit forces the ol0 {a ? e} inputs to a logical 0 prior to selecting the palettes. a value of a logical 1 does not affect the value of the ol0 {a ? e} inputs. (0) (1) disable enable table 2-1. command registers (2 of 2) function description
bt457/bt458 2.0 registers 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 2.2 read mask register l45801 rev. n conexant 2-3 2.2 read mask register the read mask register enables (logical 1) or disables (logical 0) a bit plane from addressing the color palette ram. d[0] corresponds to bit plane 0 (p0 {a ? e}), and d[7] corresponds to bit plane 7 (p7 {a ? e}). each register bit is logically anded with the corresponding bit plane input. this register can be written to or read by the mpu at any time and is not initialized. for proper operation, it must be initialized by the user after power-up. 2.3 blink mask register the blink mask register enables (logical 1) or disables (logical 0) a bit plane from blinking at the blink rate and duty cycle specified by the command register. d[0] corresponds to bit plane 0 (p0 {a ? e}), and d[7] corresponds to bit plane 7 (p7 {a ? e}). in order for a bit plane to blink, the corresponding bit in the read mask register must be a logical 1. this register can be written to or read by the mpu at any time and is not initialized. for proper operation, it must be initialized by the user after power-up. 2.4 bt458 test register the test register provides diagnostic capability by enabling the mpu to read the d/a converters inputs. it can be written to or read by the mpu at any time and is not initialized. for proper operation, it must be initialized by the user after power-up. when writing to the register, the upper 4 bits (d[7:4]) are ignored. the contents of the test register are defined as follows: to use the test register, the host mpu writes to it, setting only one of the red, green, or blue enable bits. these bits specify which four bits of color information the mpu wishes to read (r[3:0], g[3:0], b[3:0], r[7:4], g[7:4], or b[7:4]). when the mpu reads the test register, the four bits of color information from the dac table 2-2. bt458 test register d[7:4] color information d[3] low (logical 1) or high (logical 0) nibble d[2] blue enable d[1] green enable d[0] red enable
2.0 registers bt457/bt458 2.4 bt458 test register 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 2-4 conexant l45801 rev. n inputs are contained in the upper four bits, and the lower four bits contain the red, green, blue, and low or high nibble enable information previously written. either the clock must be slowed down to the mpu cycle time, or the same pixel and overlay data must be presented to the device during the entire mpu read cycle. for example, to read the upper four bits of red color information being presented to the d/a converters, the mpu writes to the test register, setting only the red enable bit. the mpu then reads the test register, keeping the pixel data stable, which results in d[7:4] containing r[7:4] color bits and d[3:0] containing red, green, blue, and low or high nibble enable information, as illustrated below: d[7] r7 d[6] r6 d[5] r5 d[4] r4 d[3] 0 d[2] 0 d[1] 0 d[0] 1
bt457/bt458 2.0 registers 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 2.5 bt457 control/test register l45801 rev. n conexant 2-5 2.5 bt457 control/test register the control/test register provides diagnostic capability by enabling the mpu to read the d/a converter inputs. it can be written to or read by the mpu at any time and is not initialized. for proper operation, it must be initialized by the user after power-up. when writing to the register, the upper four bits (d[7:4]) are ignored. the contents of the test register are defined as follows: to use the control/test register, the mpu writes to it, specifying the low or high nibble of color information. when the mpu reads the register, the four bits of color information from the dac inputs are contained in the upper four bits, and the lower four bits contain whatever was previously written to the register. either the clock must be slowed down to the mpu cycle time, or the same pixel and overlay data must be presented to the device during the entire mpu read cycle. the red, green, and blue enable bits specify the mode in which color data is written to and read from, the bt457. if all three enable bits are logical 0s, each write cycle to the color palette ram or overlay registers loads 8 bits of color data. during each read cycle of the color palette ram or overlay registers, 8 bits of color data are output onto the data bus. if a 24-bit data bus is available, three bt457s can be accessed simultaneously. if any of the red, green, or blue enable bits is a logical 1, the bt457 assumes the mpu is reading and writing color information using red-green-blue cycles, such as are used in the bt458. setting the appropriate enable bit configures the bt457 to output or input color data only for the color read/write cycle corresponding to the enabled color. thus, if the green enable bit is a logical 1, and a red-green-blue write cycle occurred, the bt457 would input data only during the green write cycle. if a red-green-blue read cycle occurred, the bt457 would output data only during the green read cycle. ce* must be a logical 0 during each of the red-green-blue cycles. only one of the enable bits must be a logical 1. this mode of operation is useful when only an 8-bit data bus is available and the software drivers are written for rgb operation. table 2-3. bt457 control test register d[7:4] color information d[3] low (logical 1) or high (logical 0) nibble d[2] blue channel enable d[1] green channel enable d[0] red channel enable
2.0 registers bt457/bt458 2.5 bt457 control/test register 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 2-6 conexant l45801 rev. n
l45801 rev. n conexant 3-1 3 3.0 pc board layout considerations 3.1 pc board considerations the bt457 and bt458 layouts should be optimized for lowest noise on their power and ground lines by shielding the digital inputs and providing good decoupling. the trace length between groups of vaa and gnd pins should be as short as possible to minimize inductive ringing. a well-designed power distribution network is critical to eliminate digital switching noise. the ground plane must provide a low-impedance return path for the digital circuits. a pc board with a minimum of six layers is recommended. the ground layer is used as a shield to isolate noise from the analog traces with layer 1 (top) the analog traces, layer two the ground plane, layer three the analog power plane, and the remaining layers used for digital traces and digital power supplies. the optimum layout enables the bt457 and bt458 to be located as close as possible to the power supply connector and the video output connector.
3.0 pc board layout considerations bt457/bt458 3.2 power and ground planes 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3-2 conexant l45801 rev. n 3.2 power and ground planes power and ground planes need isolation gaps to minimize digital switching noise effects on the analog signals and components. these gaps need to be at least 1/8-inch wide. they are placed so that digital currents cannot flow through a peninsula that contains the analog components, signals, and video connector. figure 3-1 illustrates a sample layout. figure 3-1. sample layout showing power and ground plane isolation gaps edge of pcb digital area ramdac analog area digital area 457-8_005
bt457/bt458 3.0 pc board layout considerations 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3.3 device decoupling l45801 rev. n conexant 3-3 3.3 device decoupling for optimum performance, all capacitors should be located as close as possible to the device, using the shortest possible leads (consistent with reliable operation) to reduce the lead inductance. chip capacitors are recommended for minimum lead inductance. radial lead ceramic capacitors can be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. values chosen have self-resonance above the pixel clock. 3.4 power supply decoupling the best power supply decoupling performance is obtained by providing a 0.1 f ceramic capacitor in parallel with a 0.01 f chip capacitor to decouple each group of vaa pins to gnd. the capacitors should be placed as close as possible to the device vaa and gnd pins. the 10 f capacitor illustrated in figure 3-2 is for low-frequency power supply ripple; the 0.1 f and 0.01 f capacitors are for high-frequency power supply noise rejection. the decoupling capacitors should be connected at the vaa and gnd pins, using short, wide traces. when using a linear regulator, the power-up sequence must be verified to prevent latchup. a linear regulator is recommended to filter the analog power supply if the power supply noise is greater than 200 mv. this is especially important when using a switching power supply and the switching frequency is close to the raster scan frequency. note: about 10 percent of power supply hum and ripple noise less than 1 mhz will couple onto the analog outputs.
3.0 pc board layout considerations bt457/bt458 3.4 power supply decoupling 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3-4 conexant l45801 rev. n figure 3-2. typical connection diagram comp vaa vref gnd fs adjust (n/c) ior (out) iog (pll) iob bt457/458 c8 analog power plane c2 ? c4 c5 ? c7 r4 c9 z1 + c10 c1 +5 v (vcc) rset r1 r2 r3 (1) (1) to video connector vaa p p p p dac output 1n4148/9 1n4148/9 to monitor ground (power supply connector) 457-8_006 note(s): (1) not used with bt457. 2. bt457 pin names are in parentheses. each pair of device vaa and gnd pins must be separately decoupled with 0.1 f and 0.01 f capacitors
bt457/bt458 3.0 pc board layout considerations 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3.4 power supply decoupling l45801 rev. n conexant 3-5 table 3-1. typical parts list location description? vendor part number c1 ? c4, c8, c9 0.1 f ceramic capacitor erie rpe112z5u104m50v c5 ? c7 0.01 f ceramic chip capacitor avx 12102t103qa1018 c10 10 f tantalum capacitor mallory csr13g106km l1 ferrite bead fair-rite 2743001111 r1, r2, r3 75 ? 1% metal film resistor dale cmf-55c r4 1000 ? 1% metal film resistor dale cmf-55c rset 523 ? 1% metal film resistor dale cmf-55c z1 1.2 v voltage reference national semiconductor lm385z-1.2 note(s): the vendor numbers above are listed only as a guide. substitution of devices with similar characteristics does not affect the performance of the bt457/458. r3 is not used with bt457 (see section 4.0, application information ).
3.0 pc board layout considerations bt457/bt458 3.5 comp decoupling 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3-6 conexant l45801 rev. n 3.5 comp decoupling the comp pin must be decoupled to vaa, typically with a 0.1 f ceramic capacitor. low-frequency supply noise requires a larger value. the comp capacitor must be as close as physically possible to the comp and vaa pins. a surface-mount ceramic chip capacitor is preferred for minimal lead inductance, which degrades the noise rejection of the circuit. short, wide traces also reduce lead inductance. if the display has a ghosting problem, additional capacitance connected in parallel with the comp capacitor can help. 3.6 digital signal interconnect digital inputs to the bt457 and bt458 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power and output signals. most noise on the analog outputs is caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. the digital edge rates should be no faster than necessary, because feedthrough noise is proportional to the digital edge rates. lower speed applications benefit from using lower speed logic (3 ? 5 ns edge rates) to reduce data-related noise on the analog outputs. transmission lines mismatch if the lines do not match the source and destination impedance. this degrades signal fidelity if the line length reflection time is greater than one fourth the signal edge time. line termination or line length reduction is the solution. for example, logic edge rates of 2 ns require line lengths of less than four inches without using termination. ringing can be reduced by damping the line with a series resistor (30 ? 300 ? ). radiation of digital signals can also be picked up by the analog circuitry. this is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through pc board capacitance by routing the signals 90 degrees to any analog signals. the clock driver and all other digital devices on the circuit board must be adequately decoupled to prevent the noise generated by digital devices from coupling into the analog circuitry.
bt457/bt458 3.0 pc board layout considerations 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3.7 analog signal interconnect l45801 rev. n conexant 3-7 3.7 analog signal interconnect the bt457 and bt458 should be located as close as possible to the output connectors. this minimizes noise pickup and reflections caused by impedance mismatch. analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. to maximize the high-frequency power supply rejection, the video output signals should not overlay the analog power plane. for maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. analog output video edges exceeding the crt monitor bandwidth can be reflected, producing cable-length dependent ghosts. simple pulse filters can reduce high-frequency energy, reducing emi and noise. the filter impedance must match the line impedance. 3.8 analog output protection the bt457 and bt458 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from ? hot-switching ? ac-coupled monitors. the diode protection circuit illustrated in figure 3-2 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. the 1n4148/9 are low-capacitance, fast-switching diodes, which are available in multiple-device packages (fsa250x or fsa270x) or surface-mountable pairs (bav99 or mmbd7001).
3.0 pc board layout considerations bt457/bt458 3.8 analog output protection 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 3-8 conexant l45801 rev. n
l45801 rev. n conexant 4-1 4 4.0 application information 4.1 clock interfacing because of the high clock rates at which the bt457 and bt458 can operate, they will accept differential clock signals (clock and clock*). these clock inputs are generated by ecl logic operating at +5 v. the clock and clock* inputs require termination resistors (220 ? to gnd) that should be located as close as possible to the clock driver. a 150 ? chip resistor connected between the ramdac ? s clock and clock* pins is also required to ensure proper termination. it should be located as close as possible to the ramdac. figure 4-1 illustrates the location. figure 4-1. generating the bt458 clock signals +5v 14 monitor products 970e 7 220 330 +5v 220 220 150 0.1 1k vaa clock clock* lda vref clock clock* lda* vref bt438 bt458 457-8_007
4.0 application information bt457/bt458 4.1 clock interfacing 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4-2 conexant l45801 rev. n applications of 165 mhz require robust ecl clock signals with strong pulldown ( ? 20 ma at voh) and double termination for clock trace lengths greater than 2 inches. the clock and clock* inputs must be differential signals and greater than 0.6 v peak to peak because of the noise margins of the cmos process. the bt457/458 will not function if it uses a single-ended clock with clock* connected to ground. typically, ld* is generated by dividing clock by 4 or 5 (depending on whether 4:1 or 5:1 multiplexing was specified) and translating the result to ttl levels. as ld* can be phase shifted relative to clock, propagation delays need not be considered when the ld* signal is derived. ld* can be used as the shift clock for the video drams and to generate the fundamental video timing of the system (e.g., sync* and blank*). it is recommended that the bt438 or bt439 clock generator chips be used to generate the clock and load signals. both support the 4:1 and 5:1 input multiplexing of the bt457/458, and set the pipeline delay of the bt457 and bt458 to eight clock cycles. figure 4-1 and figure 4-2 illustrate use of the bt438 with the bt457/458. when a single bt457 is used, the pll output is ignored and should be connected to gnd (either directly or through a resistor up to 150 ? ). setting the pipeline delay (bt457 and bt458) the pipeline delay of the bt457/458, although fixed after a power-up condition, can be anywhere from six to ten clock cycles. the bt457/458 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. the bt438 and bt439 clock generator chips support this mode of operation when they are used with the bt457/458. to reset the bt457/458, it should be powered up with ld*, clock, and clock* running. the clock and clock* signals should be stopped with clock high and clock* low for at least three rising edges of ld*. the device can be held with clock and clock* stopped for an unlimited time. figure 4-2. generating the bt457 signals (monochrome application) +5v 14 monitor products 970e 7 220 330 +5v 220 220 150 0.1 1k vaa clock clock* lda vref clock clock* lda* vref bt438 bt457 457-8_008
bt457/bt458 4.0 application information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4.1 clock interfacing l45801 rev. n conexant 4-3 clock and clock* should be restarted so that the first edge of the signals is as close as possible to the rising edge of ld*. (the falling edge of clock leads the rising edge of ld* by no more than 1 clock cycle or follows the rising edge of ld* by no more than 1.5 clock cycles). when the clocks are restarted, the minimum clock pulse width must not be violated. when the bt457/458 is reset to an eight-clock-cycle pipeline delay, the blink counter circuitry is not reset. therefore, if multiple bt457/458s are used in parallel, the on-chip blink counters cannot be synchronized. in this instance, the blink mask register should be $00, and the overlay blink enable bits should be logical 0s. software can control blinking through the read mask register and overlay display enable bits. in standard operation, the bt457/458 must be reset only following a power-up or reset condition. under these circumstances the on-chip blink circuitry can be used. bt457 color display applications for color display applications in which up to four bt457s are used, it is recommended that the bt439 clock generator chip be used to generate the clock and load signals. it supports the 4:1 and 5:1 input multiplexing of the bt457, synchronizes the clock and load signals to subpixel resolution, and sets the pipeline delay of the bt457 to eight clock cycles. the bt439 can also be used to interface the bt457 to a ttl clock. figure 4-3 illustrates use of the bt439 with the bt457.
4.0 application information bt457/bt458 4.1 clock interfacing 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4-4 conexant l45801 rev. n subpixel synchronization is supported by the pll output. essentially, pll provides a signal to indicate the amount of analog output delay of the bt457 relative to clock. the bt439 compares the phase of the pll signals generated by up to four bt457s, and adjusts the phase of each of the clock and clock* signals to the bt457s to minimize the pll phase difference. there should be minimal layout skew in the clock and pll trace paths to ensure proper clock alignment. if subpixel synchronization of multiple bt457s is not necessary, the bt438 clock generator chip can be used rather than the bt439. in this instance, the clock, clock*, and ld* inputs of up to four bt457s are connected together and driven by a single bt438 (daisy chain with single balanced termination for <100 mhz or through a 10h116 buffer for >100 mhz). the vref inputs of the bt457s must still have a 0.1 f bypass capacitor to vaa. the pll outputs would not be used and should be connected to gnd (either directly or through a resistor up to 150 ? ). figure 4-3. generating the bt457 clock signals (color application) 7 +5v 14 monitor products 970e 220 330 +5v +5v +5v 2.2k 430 2n3904 to bt439 70 from bt457 220 150 pll0 clock 0 clock 0* pll1 clock1 clock1* pll2 clock 2 clock2* ld vref bt439 bt457 #1 bt457 #2 bt457 #3 pll clock clock* pll clock clock* pll clock clock* ld* vref ld* vref q1 r1 r2 r1 r1 r1 r1 r1 r2 r2 r2 q1 q1 q1 r1 vaa vaa vaa 457-8_009
bt457/bt458 4.0 application information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4.2 using multiple devices l45801 rev. n conexant 4-5 4.2 using multiple devices when multiple ramdacs are used, each ramdac should have its own power plane ferrite bead. in addition, a single voltage reference can drive multiple devices; however, isolation resistors are recommended to reduce color channel crosstalk. higher performance can be obtained if each ramdac has its own voltage reference. this can further reduce the amount of color channel crosstalk and color palette interaction. each ramdac must still have its own rset resistor, analog output termination resistors, power supply bypass capacitors, comp capacitor, and vref capacitor. 4.3 bt457 nonvideo applications the bt457 can be used in nonvideo applications by disabling the video-specific control signals. sync* should be a logical 0, and blank* should be a logical 1. the relationship between rset and the full-scale output current (iout) in this configuration is as follows: rset ( ? ) = 7,457 * vref (v) / iout (ma) with the dac data inputs at $00, there is a dc offset current (imin) defined as follows: imin (ma) = 610 * vref (v) / rset ( ? ) therefore, the total full-scale output current is iout + imin.
4.0 application information bt457/bt458 4.4 initializing the bt458 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4-6 conexant l45801 rev. n 4.4 initializing the bt458 following a power-on sequence, the bt458 must be initialized. if the clock/ld* sequence is controlled to reset the pipeline delay of the bt458 to a fixed pipeline delay of eight clock cycles, this initialization sequence must be performed after the reset sequence. the command register must also be reinitialized when the multiplex selection changes (e.g., from 4:1 to 5:1 input multiplexing). this sequence configures the bt458 as follows: 4:1 multiplexed operation no overlays no blinking control register initialization c1,c0 write $04 to address register 00 write $ff to read mask register 10 write $05 to address register 00 write $00 to blink mask register 10 write $06 to address register 00 write $40 to command register 10 write $07 to address register 00 write $00 to test register 10 color palette ram initialization write $00 to address register 00 write red data to ram (location $00)] 01 write green data to ram (location $00) 01 write blue data to ram (location $00) 01 write red data to ram (location $01) 01 write green data to ram (location $01) 01 write blue data to ram (location $01) 01 :: write red data to ram (location $ff) 01 write green data to ram (location $ff) 01 write blue data to ram (location $ff) 01 overlay color palette initialization write $00 to address register 00 write red data to overlay (location $00) 11 write green data to overlay (location $00) 11 write blue data to overlay (location $00) 11 write red data to overlay (location $01) 11
bt457/bt458 4.0 application information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4.4 initializing the bt458 l45801 rev. n conexant 4-7 write green data to overlay (location $01) 11 write blue data to overlay (location $01) 11 :: write red data to overlay (location $03) 11 write green data to overlay (location $03) 11 write blue data to overlay (location $03) 11
4.0 application information bt457/bt458 4.5 initializing the bt457 (monochrome) 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4-8 conexant l45801 rev. n 4.5 initializing the bt457 (monochrome) following a power-on sequence, the bt457 must be initialized. if the clock/ld* sequence is controlled to reset the pipeline delay of the bt457 to a fixed pipeline delay of eight clock cycles, this initialization sequence must be performed after the reset sequence. the command register must also be reinitialized when the multiplex selection changes (e.g., from 4:1 to 5:1 input multiplexing). this sequence configures the bt457 as follows: 4:1 multiplexed operation no overlays no blinking color data written/read every cycle control register initialization c1,c0 write $04 to address register 00 write $ff to read mask register 10 write $05 to address register 00 write $00 to blink mask register 10 write $06 to address register 00 write $40 to command register 10 write $07 to address register 00 write $00 to test register 10 color palette ram initialization write $00 to address register 00 write data to ram (location $00) 01 write data to ram (location $01) 01 :: write data to ram (location $ff) 01 overlay color palette initialization write $00 to address register 00 write data to overlay (location $00) 11 write data to overlay (location $01) 11 :: write data to overlay (location $03) 11
bt457/bt458 4.0 application information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 4.6 initializing the bt457 (color) 24-bit mpu l45801 rev. n conexant 4-9 4.6 initializing the bt457 (color) 24-bit mpu data bus in this example, three bt457s are used in parallel to generate true color. a 24-bit mpu data bus is available to access all three bt457s in parallel. the operation and initialization are the same as the monochrome application of the bt457. 4.7 initializing the bt457 (color) 8-bit mpu data bus in this example, three bt457s are used in parallel to generate true color. an 8-bit mpu data bus is available to access the bt457s. while accessing the command, read mask, blink mask, and control/test and address registers, each bt457 must be accessed individually. while accessing the color palette ram or overlay registers, all three bt457s are accessed simultaneously. following a power-on sequence, the bt457s must be initialized. if the clock/ld* sequence is controlled to reset the pipeline delay of the bt457s to a fixed pipeline delay of eight clock cycles, this initialization sequence must be performed after the reset sequence. the command register must also be reinitialized when the multiplex selection changes (e.g., from 4:1 to 5:1 input multiplexing). this sequence configures the bt457s as follows: 4:1 multiplexed operation no overlays no blinking each bt457 initialized as a red, green, or blue device control register initialization c1,c0 red bt457 write $04 to address register 00 write $ff to read mask register 10 write $05 to address register 00 write $00 to blink mask register 10 write $06 to address register 00 write $40 to command register 10 write $07 to address register 00 write $00 to test register 10
4.0 application information bt457/bt458 4.7 initializing the bt457 (color) 8-bit mpu data bus 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette 4-10 conexant l45801 rev. n green bt457 write $04 to address register 00 write $ff to read mask register 10 write $05 to address register 00 write $00 to blink mask register 10 write $06 to address register 00 write $40 to command register 10 write $07 to address register 00 write $02 to test register 10 blue bt457 write $04 to address register 00 write $ff to read mask register 10 write $05 to address register 00 write $00 to blink mask register 10 write $06 to address register 00 write $40 to command register 10 write $07 to address register 00 write $04 to test register 10 color palette ram initialization write $00 to all three address registers 00 write red data to ram (location $00) 01 write green data to ram (location $00) 01 write blue data to ram (location $00) 01 write red data to ram (location $01) 01 write green data to ram (location $01) 01 write blue data to ram (location $01) 01 :: write red data to ram (location $ff) 01 write green data to ram (location $ff) 01 write blue data to ram (location $ff) 01 overlay color palette initialization write $00 to all three address registers 00 write red data to overlay (location $00) 11 write green data to overlay (location $00) 11 write blue data to overlay (location $00) 11 write red data to overlay (location $01) 11 write green data to overlay (location $01) 11 write blue data to overlay (location $01) 11 :: write red data to overlay (location $03) 11 write green data to overlay (location $03) 11 write blue data to overlay (location $03) 11
l45801 rev. n conexant 5-1 5 5.0 parametric information 5.1 dc electrical parameters table 5-1. recommended operating conditions parameter symbol min typ max units power supply vaa 4.75 5.00 5.25 v ambient operating temperature ta 0 ? +70 c output load rl ? 37.5 ? ? reference voltage vref 1.20 1.235 1.26 v fs adjust resistor rset ? 523 ? ?
5.0 parametric information bt457/bt458 5.1 dc electrical parameters 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-2 conexant l45801 rev. n table 5-2. absolute maximum ratings parameter symbol min typ max units vaa (measured to gnd) ??? 7.0 v voltage on any signal pin (1) ? gnd ? 0.5 ? vaa +0.5 v analog output short-circuit duration to any power supply or common isc ? indefinite ?? ambient operating temperature ta ???? storage temperature ts ? 55 ? +125 c junction temperature tj ? 65 ? +150 c ceramic package ??? +175 c plastic package ??? +150 c soldering temperature (5 seconds, 1/4 ? from pin) tsol ?? 260 c vapor phase soldering (1 minute) tvsol ?? 220 c note(s): (1) this device uses high-impedance cmos devices on all signal pins. it should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v can induce destructive latchup. 2. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.1 dc electrical parameters l45801 rev. n conexant 5-3 table 5-3. dc characteristics (1 of 2) parameter symbol min typ max units analog outputs ?? ? ? ? resolution (each dac) ? 8 (4) 8 (4) 8 (4) bits accuracy (each dac) ?? ? ? ? integral linearity error il ?? 1 (1/8) lsb differential linearity error dl ?? 1 (1/16) lsb gray-scale error ?? ? 5 %gray scale monotonicity ?? guaranteed ?? coding ?? ? ? binary digital inputs (except clock, clock*) ?? ? ? ? input high voltage vih 2.0 ? vaa + 0.5 v input low voltage vil gnd ? 0.5 ? 0.8 v input high current (vin = 4.0 v) iih ?? 1a input low current (vin = 0.4 v) iil ?? ? 1a input capacitance (f = 1 mhz, vin = 2.4 v) cin ? 410pf clock inputs (clock, clock*) ?? ? ? ? differential input voltage vin 0.6 ? 6v input high current (vin = 4.0 v) ikih ?? 1a input low current (vin = 0.4 v) iikil ?? ? 1a input capacitance (f = 1 mhz, vin = 4.0 v) ckin ? 410pf digital outputs d[7:0] ?? ? ? ? output high voltage (ioh = ? 800 a) voh 2.4 ?? v output low voltage (iol = 6.4 ma) vol ?? 0.4 v 3-state current ioz ?? 10 a output capacitance cdout ? 10 ? pf analog outputs ?? ? ? ? output current ?? ? ? ? white level relative to blank ? 17.69 19.05 20.40 ma white level relative black ? 16.74 17.62 18.50 ma black level relative to blank ? 0.95 1.44 1.90 ma blank level on ior, iob ? 0 5 50 a blank level on iog or iout ? 6.29 7.62 8.96 ma sync level on iog or iout ? 0 5 50 a lsb size ?? ? ? ?
5.0 parametric information bt457/bt458 5.1 dc electrical parameters 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-4 conexant l45801 rev. n bt457, bt458 ?? 69.1 ? a da0-to-dac matching (1) ?? 25 % output compliance voc ? 0.5 ? +1.2 v output impedance raout ? 50 ? k ? output capacitance (f = 1 mhz, iout = 0 ma) caout ? 13 20 pf voltage reference input current iref ? 10 ? a power supply rejection ratio (comp = 0.1 f, f = 1 khz) psrr ? 0.5 ? % / % ? vaa note(s): (1) does not apply to the bt457. 2. test conditions (unless otherwise specified): ? recommended operating conditions ? with rset = 523 ? and vref = 1.235 v. as the parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. table 5-3. dc characteristics (2 of 2) parameter symbol min typ max units
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.2 ac electrical parameters l45801 rev. n conexant 5-5 5.2 ac electrical parameters table 5-4. ac characteristics for 165 mhz and 135 mhz devices (1 of 2) 165 mhz devices 135 mhz devices parameter symbol min typ max min typ max units clock rate fmax ?? 165 ?? 135 mhz ld* rate ldmax ?? 41.25 ?? 33.75 mhz r/w, c0, c1 setup time 1 0 ?? 0 ?? ns r/w, c0, c1 hold time 2 15 ?? 15 ?? ns ce* low tiime 3 50 ?? 50 ?? ns ce* high time 4 25 ?? 25 ?? ns ce* asserted to data bus driven 5 7 ?? 7 ?? ns ce* asserted to data valid 6 ?? 75 ?? 75 ns ce* negated to data bus 3-stated 7 ?? 15 ?? 15 ns write data setup time 8 35 ?? 35 ?? ns write data hold time 9 3 ?? 3 ?? ns pixel and control setup time 10 3 ?? 3 ?? ns pixel and control hold time 11 2 ?? 2 ?? ns clock cycle time 12 6.06 ?? 7.4 ?? ns clock pulse width high time 13 2.6 ?? 3 ?? ns clock pulse width low time 14 2.6 ?? 3 ?? ns ld* cycle time 15 24.24 ?? 29.63 ?? ns ld* pulse width high time 16 10 ?? 12 ?? ns ld* pulse width low time 17 10 ?? 12 ?? ns analog output delay 18 ? 12 ?? 12 ? ns analog output rise/fall time 19 ? 2 ?? 2 ? ns analog output settling time 20 ?? 8 ?? 8ns clock and data feedthrough (1) ?? 35 ?? 35 ? pv ? sec glitch impulse (1) ?? 50 ?? 50 ? pv ? sec analog output skew (2) ?? 02 ? 02ns pipeline delay ? 6 ? 10 ??? clocks
5.0 parametric information bt457/bt458 5.2 ac electrical parameters 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-6 conexant l45801 rev. n vaa supply current (3) iaa ?????? ? bt458 ?? 310 370 ? 235 340 ma bt457 ?? n/a n/a ? 207 257 ma note(s): (1) clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the digital inputs. for this test, the ttl digital inputs have a 1 k ? resistor to gnd and are driven by 74hc logic. settling time does not include clock and data feedthrough. glitch impulse includes clock and data feedthrough, and ? 3 db test bandwidth = 2x clock rate. (2) does not apply to the bt457. (3) at fmax. iaa (typ) at vaa = 5.0 v and ta = 20 c. iaa (max) at vaa = 5.25 v and ta = 0 c. 4. test conditions (unless otherwise specified): "recommended operating conditions" with rset = 523 ? and vref = 1.235 v. ttl input values are 0 ? 3 v with input rise/fall times 4 ns, measured between the 10% and 90% points. ecl input values are vaa ? 0.8 to vaa ? 1.8 v with input rise/fall times 2 ns, measured between the 20% and 80% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf and d[7:0] output load 75 pf. see timing notes in figure 5-1 . as the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. table 5-4. ac characteristics for 165 mhz and 135 mhz devices (2 of 2) 165 mhz devices 135 mhz devices parameter symbol min typ max min typ max units
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.2 ac electrical parameters l45801 rev. n conexant 5-7 table 5-5. ac characteristics for 125 mhz and 110 mhz devices (1 of 2) 125 mhz devices 110 mhz devices parameter symbol min typ max min typ max units clock rate fmax ?? 125 ?? 110 mhz ld* rate ldmax ?? 31.25 ?? 27.5 mhz r/w, c0, c1 setup time 1 0 ?? 0 ?? ns r/w, c0, c1 hold time 2 15 ?? 15 ?? ns ce* low time 3 50 ?? 50 ?? ns ce* high time 4 25 ?? 25 ?? ns ce* asserted to data bus driven 5 7 ?? 7 ?? ns ce* asserted to data valid 6 ?? 75 ?? 75 ns ce* negated to data bus 3-stated 7 ?? 15 ?? 15 ns write data setup time 8 35 ?? 35 ?? ns write data hold time 9 3 ?? 3 ?? ns pixel and control setup time 10 3 ?? 3 ?? ns pixel and control hold time 11 2 ?? 2 ?? ns clock cycle time 12 8 ?? 9.09 ?? ns clock pulse width high time 13 3.2 ?? 4 ?? ns clock pulse width low time 14 3.2 ?? 4 ?? ns ld* cycle time 15 3.2 ?? 36.36 ?? ns ld* pulse width high time 16 13 ?? 15 ?? ns ld* pulse width low time 17 13 ?? 15 ?? ns analog output delay 18 ? 12 ?? 12 ? ns analog output rise/fall time 19 ? 2 ?? 2 ? ns analog output settling time 20 ?? 8 ?? 8ns clock and data feedthrough (1) ?? 35 ?? 35 ? pv ? sec glitch impulse (1) ?? 50 ?? 50 ? pv ? sec analog output skew (2) ?? 02 ? 02ns pipeline delay ? 6 ? 10 6 ? 10 clocks
5.0 parametric information bt457/bt458 5.2 ac electrical parameters 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-8 conexant l45801 rev. n vaa supply current (3) iaa ?????? ? bt458 ?? 225 330 ? 210 315 ma bt457 ?? 200 250 ? 190 240 ma note(s): (1) clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the digital inputs. for this test, the ttl digital inputs have a 1 k ? resistor to gnd and are driven by 74hc logic. settling time does not include clock and data feedthrough. glitch impulse includes clock and data feedthrough, and ? 3 db test bandwidth = 2x clock rate. (2) does not apply to the bt457. (3) at fmax. iaa (typ) at vaa = 5.0 v and ta = 20 c. iaa (max) at vaa = 5.25 v and ta = 0 c. 4. test conditions (unless otherwise specified): "recommended operating conditions" with rset = 523 ? and vref = 1.235 v. ttl input values are 0 ? 3 v with input rise/fall times 4 ns, measured between the 10% and 90% points. ecl input values are vaa ? 0.8 to vaa ? 1.8 v with input rise/fall times 2 ns, measured between the 20% and 80% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf and d[7:0] output load 75 pf. see timing notes in figure 5-1 . as the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. table 5-5. ac characteristics for 125 mhz and 110 mhz devices (2 of 2) 125 mhz devices 110 mhz devices parameter symbol min typ max min typ max units
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.2 ac electrical parameters l45801 rev. n conexant 5-9 table 5-6. ac characteristics for 80 mhz device (1 of 2) 80 mhz devices parameter symbol min typ max units clock rate fmax ?? 80 mhz ld* rate ldmax ?? 20 mhz r/w, c0, c1 setup time 1 0 ?? ns r/w, c0, c1 hold time 2 15 ?? ns ce* low time 3 50 ?? ns ce* high time 4 25 ?? ns ce* asserted to data bus driven 5 7 ?? ns ce* asserted to data valid 6 ?? 75 ns ce* negated to data bus 3-stated 7 ?? 15 ns write data setup time 8 35 ?? ns write data hold time 9 3 ?? ns pixel and control setup time 10 4 ?? ns pixel and control hold time 11 2 ?? ns clock cycle time 12 12.5 ?? ns clock pulse width high time 13 5 ?? ns clock pulse width low time 14 5 ?? ns ld* cycle time 15 50 ?? ns ld* pulse width high time 16 20 ?? ns ld* pulse width low time 17 20 ?? ns analog output delay 18 ? 12 ? ns analog output rise/fall time 19 ? 2 ? ns analog output settling time 20 ?? 8ns clock and data feedthrough (1) ?? 35 ? pv ? sec glitch impulse (1) ?? 50 ? pv ? sec analog output skew (2) ?? 02 ns pipeline delay ? 6 ? 10 clocks
5.0 parametric information bt457/bt458 5.2 ac electrical parameters 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-10 conexant l45801 rev. n vaa supply current (3) iaa ??? ? bt458 ?? 200 285 ma bt457 ?? 170 220 ma note(s): (1) clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the digital inputs. for this test, the ttl digital inputs have a 1 k ? resistor to gnd and are driven by 74hc logic. settling time does not include clock and data feedthrough. glitch impulse includes clock and data feedthrough, and ? 3 db test bandwidth = 2x clock rate. (2) does not apply to the bt457. (3) at fmax. iaa (typ) at vaa = 5.0 v and ta = 20 c. iaa (max) at vaa = 5.25 v and ta = 0 c. 4. test conditions (unless otherwise specified): "recommended operating conditions" with rset = 523 ? and vref = 1.235 v. ttl input values are 0 ? 3 v with input rise/fall times 4 ns, measured between the 10% and 90% points. ecl input values are vaa ? 0.8 to vaa ? 1.8 v with input rise/fall times 2 ns, measured between the 20% and 80% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf and d[7:0] output load 75 pf. see timing notes in figure 5-1 . as the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. table 5-6. ac characteristics for 80 mhz device (2 of 2) 80 mhz devices parameter symbol min typ max units
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.3 timing waveforms l45801 rev. n conexant 5-11 5.3 timing waveforms figure 5-1. video input/output timing 15 16 17 10 11 20 19 14 12 13 clock ior, iog, iob (iout ? bt457) p[7:0]{a ? e}, ol[1.0]{a ? e}, sync*, blank* ld* 457-8_010 note(s): 1. output delay time is measured from the 50% point of the rising clock edge to the 50% point of full-scale transition. 2. output settling time is measured from the 50% point of full-scale transition to the output settling within 1 lsb for the bt457/458. 3. output rise/fall time is measured between the 10% and 90% points of full-scale transition.
5.0 parametric information bt457/bt458 5.3 timing waveforms 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-12 conexant l45801 rev. n figure 5-2. mpu read/write timing 1 2 3 4 6 5 7 8 9 r/w, co, c1 ce* d[7:0](read) d[7:0](write) valid data out (rw = 1) data in (rw = 0) 457-8_011
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.4 package drawing l45801 rev. n conexant 5-13 5.4 package drawing figure 5-3. 84-pin plastic j-lead (plcc) a 1 detail "a" .020 min. .026 .032 .013 .021 .025/.045 r. a d 2 e 2 d 2 e 2 see detail "a" .042 .056 d 3 e 3 .056 bsc. d d 1 .042 .048 x 45 o e 1 e inches millimeters s y m b o l min. nom. max. min. nom. max. a d e a 1 e 1 d 1 d 2 e 2 e 3 d 3 .165 .090 1.185 1.150 .545 1.185 1.150 .545 1.000 ref. 1.000 ref. .200 .130 1.195 1.158 .565 1.195 1.158 .565 4.20 2.29 30.10 29.21 13.84 25.40 ref. 30.10 29.21 13.84 5.08 3.30 30.35 29.41 14.35 30.35 29.41 14.35 25.40 ref. 457-8_012 note(s): 1. dimensions are in inches [millimeters]. 2. tolerances are: .xxx 0.005 [0.127]. 3. plcc packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.
5.0 parametric information bt457/bt458 5.4 package drawing 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-14 conexant l45801 rev. n figure 5-4. 84-pin ceramic pga 0.050 typ [1.27] 1.1000 typ [27.94] 0.100 [2.54] typ 0.075 [1.91] 1.215 sq [30.86] 0.045 [1.143] 0.024 [0.609] 0.050 [1.27] detail a 4 pl pin no. 1 identifier 0.150 ? 0.170 [3.81 ? 4.318] 0.018 [0.457] dia no. 1 index see detail a 457-8_013 note(s): 1. dimensions are in inches [millimeters]. 2. tolerances are: .xxx 0.005 [0.127]. 3. pins are intended for insertion in hole rows on 0.100" [2.54] centers.
bt457/bt458 5.0 parametric information 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5.5 revision history l45801 rev. n conexant 5-15 5.5 revision history table 5-7. revision history datasheet revision change from previous revision i expanded pc board layout considerations section. changed ac parameter "ce* asserted to data bus driven" from 10 ns to 7 ns minimum. j changed ac parameter "vaa supply current (max)" for the bt457: 80 mhz changed from 190 ma to 220 ma, 110 mhz changed from 210 ma to 240 ma, and 125 mhz changed from 220 ma to 250 ma. k changed speed grade from 170 mhz to 165 mhz. changed pll feedback circuitry. consolidated bt458 power specifications. changed ac characteristics clock, load cycle, and pulse width times. changed typical analog output delay times. l added 135 mhz speed grade. m revised pcb layout section. n bt451 obsolete.
5.0 parametric information bt457/bt458 5.5 revision history 125 mhz/135 mhz/165 mhz monolithic cmos 256 color palette ramdac 5-16 conexant l45801 rev. n

further information literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u . s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 1) 41 44 36 50 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0 . 0 sa l es offi ces

▲Up To Search▲

Price & Availability of BT458LPJ165

	To Download BT458LPJ165 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .