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doc . ver s i on : 3 tota l p ag es : 4 3 da te : 20 0 6/ 0 6/ 25 note: the content of the specifications is subject to change. ? 2006 au optronics all rights reserved, model name: a025dl02 v5 product specifications 2.5 color ltps tft-lcd module < >preliminary specifications < > final specifications www..net
record of revision version revise date p a g e content 0 20 0 6/ 0 3/ 9 f ir s t dr aft 1 20 0 6/ 0 6/ 21 7~8, 16~17 up d at e ac t im in g a nd s er ia l c o ntr o l i nt er f ac e 2 20 0 6/ 0 6/ 22 30 up d at e o ut l in e dr a wi n g 5 update pin assignment 6~7 update electrical characteristics 8~13 update ac timing 23 update register vblk 3 20 0 6/ 0 6/ 25 34~43 update application notes www..net
version: 3 page: 2 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. contents a. physical specifications ......................... ................................................... ......................... 4 b. electrical specifications ....................... ................................................... .......................... 5 1. pin assignment ................................................... ................................................... .....................5 a. tft-lcd panel driving section ................... ................................................... .......................5 2. absolute maximum ratings ................................................... ................................................... .6 3. electrical characteristics ................................................... ................................................... .....7 a. recommended operating conditions (gnd=agnd=0v) .. ..................................................7 b. electrical characteristics (gnd = agnd = 0v).... ................................................... ...........7 c. recommended capacitance values of external capac itor ............................................... .....8 d. backlight driving conditions.................... ................................................... ...........................8 4. ac timing ................................................... ................................................... ..............................9 a. ups051 (24mhz) timing conditions (refer to fig. 1, fig. 2) ......................................... .....9 b. ups051 (20mhz) timing conditions (refer to fig. 1, fig. 2) ......................................... .....9 c. ups052 (320 mode/ntsc/24.535mhz) timing specific ations (refer to fig. 3, fig. 4) ...13 d. ups052 (320 mode/pal/24.375mhz) timing specifica tions (refer to fig. 3, fig. 4)......13 e. ups052 (360 mode/ntsc/27mhz) timing specificatio ns (refer to fig. 3, fig. 4) ..........13 f. ups052 (360 mode/pal/27mhz) timing specification s (refer to fig. 3, fig. 4)..............14 g. ccir656 timing chart............................ ................................................... ..........................17 h. ccir656 decoding................................ ................................................... ...........................17 i. ccir656 to rgb conversion ....................... ................................................... .....................17 5. serial control interface ................................................... ................................................... .....19 a. timing condition (refer to fig. 7) .............. ................................................... ......................19 b. serial setting map.............................. ................................................... ...............................19 c. description of serial control operations ........ ................................................... ................20 d. description of serial control data.............. ................................................... .......................21 c. optical specifications (note 1, note 2, note 3). ................................................... .......... 29 d. reliability test items .......................... ................................................... ........................... 31 e. outline dimension............................... ................................................... .......................... 32 f. packing form.................................... ................................................... .............................. 33 g. application notes............................... ................................................... ........................... 34 www..net
version: 3 page: 3 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 1. input data timing ................................................... ................................................... ...............34 2. typical application circuit ................................................... ................................................... .36 3. power on/off sequence ................................................... ..................................................3 8 www..net
version: 3 page: 4 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. a. physical specifications no. item specification remark 1 display resolution (dot) 960 (w) x 240 (h) 2 active area (mm) 50.4 x 37.8 3 screen size (inch) 2.5? (diagonal) 4 dot pitch (mm) 0.0525 x 0.1575 5 color configuration r. g. b. delta 6 overall dimension (mm) 60.73 x 45.07 x 2.58 7 weight (g) 17 8 panel surface treatment hard coating (3h) www..net
version: 3 page: 5 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. b. electrical specifications 1. pin assignment a. tft-lcd panel driving section pin no. symbol i/o description remark 1 vcom i common voltage 2 cs i serial command enable signal note 1 3 sda i serial command data input note 1 4 scl i serial command clock input note 1 5 hsync i horizontal sync input 6 vsync i vertical sync input 7 dclk i input data clock 8 d7 i data input; msb 9 d6 i data input 10 d5 i data input 11 d4 i data input 12 d3 i data input 13 d2 i data input 14 d1 i data input 15 d0 i data input; lsb 16 drv o vled boost transistor driving signal 17 vled p led power: anode 18 fb i / p led power: cathode 19 avdd c power setting capacitor 20 agnd p ground for analog circuit 21 gnd p ground for digital circuit 22 vcci p power supply for digital interface 23 vdc p power supply for dc-dc circuit 24 v1 c power setting capacitor 25 v2 c power setting capacitor 26 v3 c power setting capacitor 27 v4 c power setting capacitor www..net
version: 3 page: 6 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 28 v5 c power setting capacitor 29 v6 c power setting capacitor 30 v7 c power setting capacitor 31 v8 c power setting capacitor 32 v9 c power setting capacitor 33 v10 c power setting capacitor 34 frp o vcom driving signal note 2 35 vgl c power setting capacitor 36 vgh c power setting capacitor 37 vcoml c power setting capacitor for vcom 38 vcomh c power setting capacitor for vcom 39 vcom i common voltage i: input; o: output; p: power; c: capacitor note 1: 3-wire serial control interface is operatio nal after v cci power on reset, but execution of programmed commands is synchronized at front edge o f next vsync pulse. note 2: frp is the output of vcom driver. it is the same phase and amplitude with common electrode driving signal (vcom). the vcom amplitude and dc level setting can be adjusted through serial control. 2. absolute maximum ratings item symbol condition min. max. unit remark power voltage v dc gnd = 0 -0.5 5 v power voltage v cci gnd = 0 -0.5 5 v operating temperature topa 0 60 ambient temperature storage temperature tstg -25 80 ambient temperature pin 1 pin 39 www..net
version: 3 page: 7 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 3. electrical characteristics a. recommended operating conditions (gnd=agnd=0v) item symbol min. typ. max. unit remark v dc 3.0 3.3 3.6 v note 1 power supply v cci 1.7 3.3 3.6 v note 2 h level v ih 0.8* v cci - v cci v input signal voltage l level v il gnd - 0.2* v cci v note 1: a build-in power on reset circuit for v dc and v cci is provided within the integrated lcd driver ic. the lcd module is in power save mode in default, an d a standby releasing is required after v cci power on through serial control. please refer to th e register stb setting for detail. note 2: the power supply of digital interface, v cci , is for the 1.8v digital interface requirement in the future. these digital signals are dclk, hsync, vsyn c, d7~d0, cs, sda and scl. if the digital interface is in the level of 3.3v, please s hort the power pin v dc and v cci to 3.3v. in other words, no matter the voltage level of v cci is 1.8v or 3.3v, the voltage level of v dc needs to be kept 3.3v. b. electrical characteristics (gnd = agnd = 0v) parameter symbol condition min. typ. max. unit remark 18.5 note 1 i dc v dc =3.3v 22.5 m a note 2 20 note 1,3 input current for v dc i dc(standby) v dc =3.3v 20 ua note 2,3 24 note 1 i cci v cci =3.3v 45 u a note 2 10 note 1,3 input current for v cci i cci(standby) v cci =3.3v 10 ua note 2,3 v gh v dc =3.3v 11.5 v note 4 dc-dc voltage v gl v dc =3.3v -5.3 v note 4 v cac 5.0 5.6 6.4 vp-p ac component, note 5 vcom voltage v cdc 1.75 2.4 3.5 v dc component, note 6 note 1: test condition: 8colorbar+grayscale pattern , ups051 mode, dclk=24mhz, frame rate: 60hz, other registers are default setting note 2: test condition: 8colorbar+grayscale pattern , ups052 320x240 mode, dclk = 24mhz, other registers are default setting note 3:in standby mode, digital signals dclk, hsync , vsync, d7~d0, cs, sda and scl are stopped. note 4: v gh and v gl are output voltages of integrated lcd driver ic. note 5: the brightness of lcd panel could be adjust ed by the adjustment of the ac component of vcom. www..net
version: 3 page: 8 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. note 6: v cdc could be adjusted, so as to minimize flicker and m aximum contrast on each module. c. recommended capacitance values of external capac itor the recommended capacitance values of the external capacitor are shown below. these values should be finally determined only after performing sufficient evaluation on the module. pin name recommended value of capacitors ( f) withstanding voltage (v) avdd 4.7 to 10 16 vgh 4.7 to 10 16 vgl 4.7 to 10 16 vcomh 4.7 to 10 16 vcoml 4.7 to 10 16 v1, v2 2.2 to 10 16 v3, v4 2.2 to 10 16 v5, v6 2.2 to 10 16 v7, v8 2.2 to 10 16 v9, v10 2.2 to 10 16 d. backlight driving conditions parameter symbol min. typ. max. unit remark led current 20 ma led voltage v l 11.4 v note note: for 3 leds, vled = 3.6*3+0.6 = 11.4v. www..net
version: 3 page: 9 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 4. ac timing a. ups051 (24mhz) timing conditions (refer to fig. 1, fig. 2) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 22.93 24.535 27.19 mhz period t h 1560 1560 1728 dclk display period t hdisp 960 dclk blanking t hblk 66 241 255 dclk front porch t hfp 345 359 dclk hsync pulse width t hsw 1 1 t hblk -1 dclk note 1 15.2 16.6 20 ms period t v 245 262.5 265 t h display period t vdisp 240 t h blanking t vblk 3 21 31 t h vsync pulse width t vsw 1 1 t vblk ?1 dclk note 2 data set-up time t ds 12 ns data hold time t dh 12 ns vsync-to-hsync set-up time t vhs 1 dclk (*) when t h = 68us, t v = 245t h note 1: ups051 horizontal blanking time (t hblk ) is adjustable by setting register hblk; requireme nt of minimum blanking time and minimum front porch time must be satisfied. note 2: ups051 vertical blanking time (t vblk ) is adjustable by setting register vblk. ups051 ac cepts both interlace and non-interlace vertical input timing. b. ups051 (20mhz) timing conditions (refer to fig. 1, fig. 2) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 19.43 20.00 22.93 mhz period t h 1322 1360 1560 dclk display period t hdisp 960 dclk blanking t hblk 66 241 255 dclk front porch t hfp 123 159 534 dclk hsync pulse width t hsw 1 1 t hblk -1 dclk note 1,2 15.2 16.6 20 ms period t v 245 245 265 t h display period t vdisp 240 t h blanking t vblk 3 4 24 t h vsync pulse width t vsw 1 1 t vblk ?1 dclk note 3 data set-up time t ds 12 ns data hold time t dh 12 ns www..net
version: 3 page: 10 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. vsync-to-hsync set-up time t vhs 1 dclk note 1: if the dclk number of 1 hsync period is les s than 1560, please set series command r133 = 29h & r134 = aeh & r136 = 2bh & r137 = 8ch & r138 = 0bh . note 2: ups051 horizontal blanking time (t hblk ) is adjustable by setting register hblk; requireme nt of minimum blanking time and minimum front porch time must be satisfied. note 3: ups051 vertical blanking time (t vblk ) is adjustable by setting register vblk. ups051 ac cepts both interlace and non-interlace vertical input timing. www..net
version: 3 page: 11 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 2 invalid data invalid data 959 960 1 t hdisp t hblk t hsw hsync dclk data t h t dclk t dh t ds t hfp fig. 1 ups051 input horizontal signal www..net
version: 3 page: 12 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. line 240 line 2 t vdisp line 1 invalid data invalid data t vblk t vsw vsync hsync data t v odd field line 2 t vdisp line 1 invalid data invalid data t vblk t vsw vsync hsync data t v line 240 even field 0.5 t h fig. 2 ups051 input vertical signal www..net
version: 3 page: 13 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. c. ups052 (320 mode/ntsc/24.535mhz) timing specific ations (refer to fig. 3, fig. 4) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 24 24.535 27 mhz period t h 1560 t dclk display period t hdisp 1280 t dclk blanking t hblk 241 t dclk hsync pulse width t hsw 1 t dclk t v 15.2 16.6 20 ms period t v 262.5 t h display period t vdisp 240 t h blanking t vblk 21 t h vsync pulse width t vsw 1 t dclk d. ups052 (320 mode/pal/24.375mhz) timing specifica tions (refer to fig. 3, fig. 4) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 24 24.375 27 mhz period t h 1560 t dclk display period t hdisp 1280 t dclk blanking t hblk 241 t dclk hsync pulse width t hsw 1 t dclk t v 15.2 16.6 20 ms period t v 312.5 t h display period t vdisp 288 t h blanking t vbp 24 t h vsync pulse width t vsw 1 t dclk e. ups052 (360 mode/ntsc/27mhz) timing specificatio ns (refer to fig. 3, fig. 4) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 24 27 28 mhz period t h 1716 t dclk display period t hdisp 1440 t dclk blanking t hblk 241 t dclk hsync pulse width t hsw 1 t dclk t v 15.2 16.6 20 ms period t v 262.5 t h display period t vdisp 240 t h blanking t vblk 21 t h vsync pulse width t vsw 1 t dclk www..net
version: 3 page: 14 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. f. ups052 (360 mode/pal/27mhz) timing specification s (refer to fig. 3, fig. 4) parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 24 27 28 mhz period t h 1728 t dclk display period t hdisp 1440 t dclk blanking t hblk 241 t dclk hsync pulse width t hsw 1 t dclk t v 15.2 16.6 20 ms period t v 312.5 t h display period t vdisp 288 t h blanking t vbp 24 t h vsync pulse width t vsw 1 t dclk www..net
version: 3 page: 15 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. b1 g1 r1 b0 r0 g0 invalid data invalid data(*) t hdisp t hblk t hsw hsync dclk data t h :dummy vsync t vsw t ds t dh * please send 00h as blanking data. fig. 3 ups052 input horizontal signal www..net
version: 3 page: 16 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. line n line 2 t vdisp line 1 invalid data invalid data t vblk t vsw vsync hsync data t v odd field line 2 t vdisp line 1 invalid data invalid data t vblk t vsw vsync hsync data t v line n even field 0.5 t h fig. 4 ups052 input vertical signal www..net
version: 3 page: 17 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. g. ccir656 timing chart fig. 5: ccir656 data input format h. ccir656 decoding ff 00 00 xy signals are involved with hsync,vsync a nd field xy encode following bits: f=field select v=indicate vertical blanking h=1 if eav else 0 for sav p3-p0=protection bits p3=v h p2=f h p1=f v p0=f v h represents the exclusive-or function. control is provided through ?end of video? (eav) an d ?start of video? (sav) timing references. horizontal blanking section consists of repeating p attern 80 10 80 10 xy d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) 1 f v h p3 p2 p1 p0 i. ccir656 to rgb conversion r=y +1.371*(cr-128) g=y -0.698(cr-128)-0.336(cb-128) b=y +1.732(cb-128) where y:16~235 cr:16~240 cb:16~240 in ccir656 mode , please set series command r3=2eh & r13=4bh for the better contrast . d[7..0] dclk (27mhz) ffh 00h 00h xy (sav) cb0 y0 cr0 y1 cb 718 y718 cr 718 y719 ffh 00h 00h invalid data invalid data xy (eav) 720 ccir valid data www..net
version: 3 page: 18 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. csync timing chart fig. 6: csync data input format item min typ max hysnc width 20 clk 4.7us 6us equivalent pulse width 20 clk 2.35us 3us serrated pulse width (inside vsync) 20 clk 4.7us 6us vsync width 2.3h ntsc:3h pal:2.5h 10h vsync hsync vertical sync equivalent equivalent odd field even field vertical sync equivalent equivalent vsync hsync odd field even field ntsc mode pal mode www..net
version: 3 page: 19 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 5. serial control interface a. timing condition (refer to fig. 7) parameter symbol min. typ. max. unit. remark serial load input setup time t s0 100 ns serial load input hold time t h0 100 ns serial data input setup time t s1 100 ns serial data input hold time t h1 100 ns t w1l 200 ns scl pulse width t w1h 200 ns cs pulse width t w2 600 ns b. serial setting map register address register data (default setting) no s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 r0 0 0 0 0 0 0 0 0 vcom_ac (011) r1 0 0 0 0 0 0 0 1 flk (0) vcom_dc (18h) r3 0 0 0 0 0 0 1 1 brightness(40h) r4 0 0 0 0 0 1 0 0 yuv (0) sel (00) ntsc/pal (10) vdir (1) hdir (1) r5 0 0 0 0 0 1 0 1 drv_ freq (0) grb (1) pwm_duty(10) shdb2 (1) shdb1 (1) stb (0) r6 0 0 0 0 0 1 1 0 led_curren t (00) vblk (15h) r7 0 0 0 0 0 1 1 1 hblk (1eh) r8 0 0 0 0 1 0 0 0 bl_drv (00) r12 0 0 0 0 1 1 0 0 pair(00) csync (1) cbcr (0) vdpol (1) hdpol (1) dclkpol (0) r13 0 0 0 0 1 1 0 1 contrast(40h) r14 0 0 0 0 1 1 1 0 sub-contrast_r(40h) r15 0 0 0 0 1 1 1 1 sub-brightness_r(40h) r16 0 0 0 1 0 0 0 0 sub-contrast_b(40h) r17 0 0 0 1 0 0 0 1 sub-brightness_b(40h) r18 0 0 0 1 0 0 1 0 gamma_vr2(8h) gamma_vr1(8h) r19 0 0 0 1 0 0 1 1 gamma_vr4(8h) gamma_vr3(8h) r133 1 0 0 0 0 1 0 1 reserved register for ic test mode r134 1 0 0 0 0 1 1 0 reserved register for ic test mode r136 1 0 0 0 1 0 0 0 reserved register for ic test mode r137 1 0 0 0 1 0 0 1 reserved register for ic test mode r138 1 0 0 0 1 0 1 0 reserved register for ic test mode : reserved, please set to '0' www..net
version: 3 page: 20 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. s12 s11 s10 s9 s8 s7 s15 s14 s13 s3 s2 s1 s0 s6 s5 s4 s15 s14 t w1h t w1l t w2 t h0 t s1 t s0 t h1 cs scl sda 50% 50% c. description of serial control operations each serial command consists of 16 bits of data wh ich is loaded one bit a time at the rising edge of serial clock scl command loading operation starts from the falling edge of cs and is completed at the next rising edge the serial control block is operational after powe r on reset, but commands are established by the vsync signal. if command is transferred multiple ti mes for the same register, the last command before the vsync signal is valid. please refer to f ig. 8. if less than 16 bits of scl are input while cs is low, the transferred data is ignored. if 16 bits or more of scl are input while cs is lo w, the first 16 bits of transferred data before the rising edge of cs pulse are valid data. serial block operates with the scl clock and seria l data can be accepted in the power save mode fig. 7 serial control timing www..net
version: 3 page: 21 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. command1 for r0 command2 for r0 command3 for r1 command4 for r2 command5 for r5 command6 for r7 vsync cs established commands: command 2 command 3 command 4 fig. 8 illustration of serial command operation d. description of serial control data vcom_ac: common voltage ac level selection; 3 bit s etting, 0.2v / lsb (deviation 4%) (msb ? lsb) vcom ac level unit 000 5.0 001 5.2 010 5.4 011 5.6 (default) 100 5.8 101 6.0 110 6.2 111 6.4 v frp vcom_ac 1 vcom_ac 2 www..net
version: 3 page: 22 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. vcom_dc: common voltage dc level selection; 6 bit s etting, 27.8mv / lsb (msb ? lsb) vcom ac level unit 00h 1.75 18h 2.4(default) 3fh 3.5 v vcom_dc gnd frp flk: flicker pattern output flk function 0 normal operation (default) 1 flicker patttern output black 50% grey l1 l240 h (depends on resolution) brightness: rgb bright level setting; 8-bit setting (msb-lsb) function 00h dark 40h center (default) ffh bright hdir: horizontal scan direction setting hdir function 0 right-to-left scan 1 left-to-right scan (default) www..net
version: 3 page: 23 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. vdir: vertical scan direction setting vdir function 0 down-to-up scan 1 up-to-down scan (default) ntsc/pal: ntsc or pal mode selection (for ups052 in put timing) (msb-lsb) function 00 pal mode 01 ntsc mode 1x auto-detection mode (default) sel: input data timing format selection; please ref er to ac timing section for detail specifications (msb-lsb) input timing format 00 ups051 (default) 01 ups052: 320x240 1x ups052: 360x240 yuv: yuv (ccir656) or rgb input selection yuv function 0 rgb input ( default) 1 ccir656 input(*) when this command is sent to asic,it will be execut ed immediately. when csync = ? 0 ? , csync input from hsync pin,if yuv= ? 1 ? & csync=?0? ,yuv is the input signal. (*)for ccir656 input interface, sel has to be set a s ? 11 ? stb: standby ( power saving ) mode setting stb function 0 standby mode (default) 1 normal operation shdb1: shut-down for back light power converter shdb1 function 0 the black power converter is off 1 the black power converter is controlled by build- in on/off sequence (default) shdb2: shut-down for vgh/vgl charge pump shdb function 0 the vgh/vgl charge pump is off 1 the vgh/vgl charge pump is controlled by build-in on/off sequence (default) www..net
version: 3 page: 24 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. pwm_duty: pwm duty cycle selection for back light p ower converter (msb-lsb) function(pwm duty cycle) 00 50% 01 60% 10 65%(default) 11 70% grb: register reset setting grb function 0 reset all registers to default values 1 normal operation (default) drv_freq: drv signal frequency setting mode drv_freq=?0? (default) drv_freq=?1? ups051 960x240 dclk/64 dclk/32 ups052 dclk/64 dclk/32 vblk: vertical blanking setting for ups051, ups052 and ccir656 ; 5-bit setting, 1 line/lsb for ups051and ups052 ntsc mode ; 5-bit setting, 1 l ine/lsb (msb-lsb) v-blanking t vblk unit 03h (min) 3 15h (typ.) 21 (default) 1fh (max) 31 line for ccir656 ntsc mode ; 5-bit setting, 1 line/lsb (msb-lsb) v-blanking t vblk unit 03h (min) 3 16h (typ.) 22 1fh (max) 31 line under ccir656 pal mode ; vertical blanking+3, as the following table ; 5-bit setting, 1 line/lsb (msb-lsb) v-blanking t vblk unit 03h (min) 6 15h (typ.) 24 1fh (max) 34 line note:v-blanking must be adjusted based on the input data. led_current: adjust led current dc-dc feedback voltage (msb-lsb) function 00 0.6 v(default, 20ma) 01 0.75v (25ma) 10 0.45v (15ma) 11 0.3v (10ma) www..net
version: 3 page: 25 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. hblk: horizontal blanking setting for ups051; 8-bit setting, 1 dclk/lsb (msb-lsb) h-blanking t hblk unit 00h 0 1eh 30 (default) ffh 255 dclk bl_drv: backlight driving capability setting d7 d6 bl_drv capability 0 0 normal capability (default) 0 1 2 times the normal capability 1 0 4 times the normal capability 1 1 8 times the normal capability note: for better efficiency, the setting drv_freq=? 1? and bl_drv=?11? are recommended. dclkpol: dclk polarity selection dclkpol function 0 positive polarity ( default) 1 negative polarity hdpol: hsync polarity selection hdpol function 0 positive polarity 1 negative polarity ( default) vdpol: vsync polarity selection vdpol function 0 positive polarity 1 negative polarity ( default) d1 d2 d3 d4 vsync hsync dclk data hdpol=1, vdpol=1, clkpol=0 d1 d2 d3 d4 vsync hsync dclk data hdpol=0, vdpol=0, clkpol=1 www..net
version: 3 page: 26 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. cbcr: cbcr: cb & cr exchange position csync: separate sync or csync input selection csync function 0 csync input 1 separate sync input ( default) when csync = ? 0 ? , csync input from hsync pin if yuv= ? 1 ? & csync=?0? ,yuv is the input signal(vsync needs t o pull high) gamma_vr1, gamma_vr2 , gamma_vr3 , gamma_vr4 : resi stor range 8k(0000)~23k(1111) (msb-lsb) function 0000 8k 1000 16k (default) 1111 23k 1, vgma1, vgma2, vgma3 are generated within driver ic and adjustable throu gh serial register setting 2. vr1, vr2, vr3, vr4 are adjustable through 4 bit registers cb0 y0 cr0 y1 cb2 y2 cr2 y3 cbcr=?0? cbcr=?1? cr0 y0 cb0 y1 cr2 y2 cb2 y3 vgma3 vgma4 vgma2 vgma1 4 bit register vgma0 level 23 level 53 level 101 level 0 level 127 vgma0 vr1 vr2 vr3 vr4 vgma4 4 bit register 4 bit register 4 bit register www..net
version: 3 page: 27 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 3. when frp=l (positive polarity) vgma0=3.7v, vgma4 = 0v 4. when frp=h (negative polarity) vgma0=0v, vg ma4 = 3.7v contrast: rgb contrast level setting, the gain chan ges (1/64)/bit (msb-lsb) function 00h 0 40h 1 (default) ffh 3.984 sub-contrast: rb sub-contrast level setting, the g ain changes (1/256) / bit (msb-lsb) function 00h 0.75 40h 1 (default) 7fh 1.246 sub-brightness: rb sub-bright level setting, settin g accuracy: 1 step / bit (msb-lsb) function 00h dark ( -64 ) 40h center (0) (default) 7fh bright ( +63 ) pair: pair : vertical start time setting for odd/ev en frame ups051 / ups052 ntsc / ups052 pal (*) ccir656 ntsc/pal (**) (*)the typical value of vblk of ups052 pal (24 h) is different than ups051/ups052 ntsc (21h). (**) the typical value of vblk of ccir656 pal (24 h ) is different than ccir656 ntsc (22h). note: v-blanking must be adjusted based on the inpu t data. vblk pair(1:0) odd / even unit x 0 21/21(default) x 1 21/20 h vblk pair(1:0) odd / even unit 0 0 22/22 0 1 22/23 1 0 23/22 1 1 23/23 h www..net
version: 3 page: 28 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. this table is based on vblk=21. 523 284 524 285 even 261 22 261 22 odd end start end start line pair=1 pair=0 field 262 1 2 21 22 23 264 265 284 285 286 263 525 21 21 vsync hsync www..net
version: 3 page: 29 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 50cm | ------------------------------ - | 90 c. optical specifications (note 1, note 2, note 3) item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 - - 15 20 25 30 ms ms note 4 contrast ratio cr at optimized viewing angle 200 300 - note 5,6 viewing angle top bottom left right cr R 10 35 60 45 45 45 70 55 55 - - - - deg. note 7 brightness y l =0 350 400 - cd/m 2 note 8 x =0 0.28 0.33 0.38 white chromaticity y =0 0.30 0.35 0.40 luminance uniformity 60 % note 9 note 1. ambient temperature =25 . and backlight current i l =20 ma note 2. to be measured in the dark room. note 3. to be measured on the center area of panel with a field angle of 1 by topcon luminance meter bm-7, after 10 minutes operation, distance: 500 50mm. note 4. definition of response time: the output signals of photo detector are measured when the input signals are changed from ?b lack? to ?white?(falling time) and from ?white? to ?black?(rising time), respectively. the response time is defined as the time interval b etween the 10% and 90% of amplitudes. refer to figure as below. s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% www..net
version: 3 page: 30 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. note 5. definition of contrast ratio: contrast ratio is calculated with the following for mula. photo detector output when lcd is at ?white? state photo detector output when lcd is at ?black? state note 6. white vi=v i50 1.5v black vi=v i50 2.0v ? ? means that the analog input signal swings in phas e with com signal. ? ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmissio n of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: . note 8. measured at the center area of the panel w hen all the input terminals of lcd panel are electrically opened contrast ratio (cr)= 1.5v 2.0v com white vi black vi v i50 1.5v 2.0v www..net
version: 3 page: 31 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. d. reliability test items no. test items conditions remark 1 high temperature storage ta= 80 240hrs 2 low temperature storage ta= -25 240hrs 3 high temperature operation ta= 60 240hrs 4 low temperature operation ta= 0 240hrs 5 high temperature and high humidity ta= 60 . 90% rh 240hrs operation 6 heat shock -25 ~80 /50 cycle 2hrs/cycle non-operation 7 electrostatic discharge 200v,200pf(0 ), once for each terminal non-operation frequency range : 10~55hz stoke : 1.5mm sweep : 10~55hz~10hz 2 hours for each direction of x,y,z 8 vibration (6 hours for total) non-operation jis c7021, a-10 condition a 9 mechanical shock 100g . 6ms, x, y, z 3 times for each direction non-operation jis c7021, a-7 condition c 10 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ?6db/octave from 200~500hz iec 68-34 11 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces note: ta: ambient temperature. www..net
e. outline dimension www..net
f. packing form www..net
version: 3 page: 34 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. g. application notes this ltps tft lcd module is designed for digital st ill camera application. a cog type lcd driver ic is integrated within this module, makes it much easier to design and cost-effective. the main features of integrated driver are: accepting digital serial r, g, b 8-bit signal, few er adjustment, fewer design effort, and lower power consumption compared to other analog ltps solution. integrated timing controller for ups051 and ups052 input timing formats. for ups052 input timing, the input signal is always the same for different p anel resolution. integrated led power converter controller, dc-dc c harge pump, and vcom driver. a design requires less peripheral components and reduces the total sy stem cost. 1. input data timing two kinds of input timing format are supported: ups 051 and ups052. in ups051 input format, the conversion of image data to display dots is control ed by the user. in ups052 input format, the mapping of incoming data to display dots is take cared by buil t in scaling function of driver ic. for ups051 timing, the module accpet one dot video data at the rising edge of dclk, and display them one dot by one dot. therefore the input data timing is different according to different panel resoluti ons and scan directions. refer to the ac timing of ups051 part, you can use the typ. value for a typical case, or y ou can use the min. value to lower down the power consumption and emi. because of delta color filter arrangement, the rgb data sequence for even and odd lines are different based on scan direction. for the definition of even and odd lines, see the below figure. even even odd invalid data vsync 1 2 3 4 240 data up to down left to right odd even invalid data invalid data invalid data odd odd even down to up left to right even odd invalid data invalid data odd odd even even odd invalid data invalid data up to down right to left even even odd down to up right to left odd even invalid data invalid data fig 9. ups051 even and odd lines definition www..net
version: 3 page: 35 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. for the rgb sequence, see the below figure. dclk 1 invalid data 2 3 data g b r g b r g b b r g b r g b r r g odd line even line h shift direction = left to right g r b g r b g r b g r b g r b g b r even line odd line h shift direction = right to left, fig. 10 ups051 input rgb sequence for 960x240 resol ution for the color filter arrangement, see the below fig ure right to left left to right r g b r b g r g b up to down r g b r b g r g b ???? up to down ??? r g b r b g r b g down to up left to right r g b r b g r b g down to up right to left ???? ??? fig. 11 color filter arrangement for 960x240 resolu tion for ups052 timing, there are two input rgb data mod es to choose from: 320xrgb and 360xrgb. input data is processed and mapped to display dots by int egrated driver ic according to panel resolution and scan direction settings. ups052 input format saves the e ffort of data scaling for users and keeps a consist ent interface for different display resolutions, in the cost of higher input data rate and less image proc essing elasticity. an additional ntsc/pal auto-detection function is p rovided for ups052 input format. when the function is active, the hsync and vsync inputs are monitored. i f there are more than 288 hsync in a vsync period, it is detected as the pal mode (288 active lines). on the other hand, if there are less than 288 hsync in a www..net
version: 3 page: 36 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. vsync period, it is asserted as the ntsc mode (240 active lines). please refer to the serial control s etting for more details. for vertical input timing, both ups051 and ups052 a ccept odd / even field switching or single field on ly input. for detail timing spec., please refer to fig 2 and fig 4. 2. typical application circuit 2-1. internal led booster circuit the integrated driver ic provides build-in led boos ter controller, dc-dc charge pump, and vcom driver. see the below figure for the application circuit. vdc v3 v4 v5 v6 v7 v8 v9 v10 v1 v2 vgl vgh avdd vcoml vcomh drv vled fb vcomh vcoml drv vgh vgl fb avdd v1 vdc v2 v3 v4 v5 v6 v7 v8 v9 v10 vled cs dclk sda hsync scl vsync d7 d6 d3 d2 d4 d0 d5 d1 vcci agnd agnd gnd gnd gnd agnd vcom gnd dgnd dgnd dgnd dgnd dgnd frp vcom led con1 con-39pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 l2 bead c7 10uf c8 1nf l1 33uh c2 10uf q1 fmmt618 2 1 3 r1 5.5k l3 bead c4 4.7uf c5 4.7uf c1 4.7uf c3 4.7uf c13 2.2uf c10 2.2uf c11 2.2uf c12 2.2uf c6 4.7uf led led c9 2.2uf r2 30 sb07 d1 power supply vdc (typical 3.3v) and vcci (typical 3 .3v) are required to provide driver ic power and generate all necessary voltages for lcd related cir cuits. according to the above figure, the l1, q1, d1,and c 7 together form the led boost converter. the converter with 0.6v feedback (fb) and r2 provide a constant 20ma current for led backlight unit. the b oost converter switching signal drv is generated base on divided frequency of dclk. therefore the dclk inpu t is required for led driver operation, and the absent o f dclk signal during normal operation will set the driver ic into standby mode. a low esr capacitor for c7 is re commended in order to reduce voltage ripple of vled . the build-in led boost controller is default active, an d it is able to be turned off by setting the regist er shdb1 to low. the positive (vgh) and negtive (vgl) power supplies for lcd are generated through build-in dc-dc charge pump circuit, an elegant design with only ei ght passive power-setting capacitors are required. the led booster circuit may cause the wave like phe nomenon, in order to reduce the phenomenon ,agnd and dgnd (system gnd) and led boos ter circuit gnd must be separated. fig.12 typical application circuit www..net
version: 3 page: 37 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. if user wants higher dc-dc charge pump efficiency o r to fine-tune the led current , using external led driver circuit is an alternative choice. the charge pump frequency is about 7~8khz, which ca n be heard by human. to prevent this signal from being amplified by microphone or other audio r ecoder, c9~c13 are suggested to be kept as far away as possible from these devices. 2-2. external led driver circuit see the below figure for the application circuit. vdc vdc vcomh d2 scl d5 dclk cs sda vcoml d7 drv vgh hsync vsync d1 d3 vgl d4 d6 fb avdd d0 v1 vdc vcci v2 v3 v4 v5 v6 v7 v8 v9 v10 v3 v4 v5 v6 v7 v8 v9 v10 v1 v2 vgl vgh avdd vcoml vcomh vled vled vled bl_on agnd vcom agnd agnd gnd frp vcom gnd dgnd dgnd dgnd dgnd gnd dgnd gnd gnd l1 33uh u1 zxld1100 1 2 3 4 5 6 lx gnd fb en vsense vin l3 bead c6 10uf c3 10uf c12 4.7uf c1 4.7uf c2 4.7uf c4 4.7uf c7 4.7uf c11 4.7uf c10 4.7uf c8 4.7uf led c5 4.7uf r1 5 sb07 d1 c9 4.7uf led con2 con-39pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 led l2 bead power supply vdc (typical 3.3v) and vcci (typical 3 .3v) are required to provide driver ic power and generate all necessary voltages for lcd related cir cuits. according to the above, the led driver(zxld1100) an d r1(5 ohm) with 0.1v feedback (fb) can provide a constant 20ma current for led backlight unit. to co ntrol the back light on/off timing, user should cre ate a control signal bl_on (please refer to the zxld1100 date she et). the charge pump frequency is about 7~8khz, which ca n be heard by human. to prevent this signal from being amplified by microphone or other audio r ecoder, c8~c12 are suggested to be kept as far away as possible from these devices. fig.13 external led driver circuit www..net
version: 3 page: 38 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 3. power on/off sequence the register setting of standby mode disabling / en abling is used to control the build-in power on / o ff sequence. 3-1 power on (global reset and standby disabling) after vdc/vcci power on reset, vsync/hsync/dclk/dat a can be input, and serial control interface is also operational. to ensure that panel can be light ed on successfully, the first step is setting globa l reset (register #5 ?16(hex)?) as the timing in fig. 14. t hen the lcd driver is in default standby mode after vdc/vcci power-on, and setting register #5 bit #0 t o high (stb=1) to disable the standby mode is requi red for normal operation. when the standby mode is disa bled, a build-in power on sequence is started. the driver ic analog power avdd is turned on first, and then t he lcd positive and negative power supplies vgh/vgl are pumped, and followed by the led power vled. sin ce we recommend using external led driver, the bl_on signal (see fig.13) should be provided at thi s time. please refer to fig.14 and fig. 18 for the detail timing of power on/off sequence, especially the glo bal reset timing in fig. 18. 3-2 power off (standby enabling) when the register #5 bit #0 is set to low (stb = 0) to enable standby mode, a build-in power off seque nce is started. please refer to fig.14 for the detail timi ng. no serial command programming is allowed right after standby mode is enabled, for a time period of minim um 5 fields (1 field: ntsc=16.6msec / pal = 20msec) . 3-3 clock stop reset the dclk signal is required for normal operation. w hen the dclk is stopped for more than 5.6 sec (or dclk frequency <140k hz) during normal operation, t he driver ic will be reset and operated in standby mode. this dclk stop reset does not affect the seri al interface settings. www..net
version: 3 page: 39 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. 4 fields pre -setting > 50 msec invalid invalid sel,ntsc/pal 1 fields 1 fields hi - z normal w hite hi - z w hite 2 fields 2 fields vdc/ vcc i vsync stb (serial command) vg h vcom / ltps control signals dac_out bl on serial command user input lcd driver output avdd < 2 msec hsync/dclk/ data invalid valid data valid data 1 fields > = 0 msec vg l 1 fields fig.14 power on / off sequence www..net
version: 3 page: 40 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. power on power off vcc min: 0 msec d6h input serial setting register r5 set standby dclk / hsync / vsync / data input min: 5 fields) (1 field: ntsc=16.6ms / pal=20ms) dclk / hsync / vsync / data input vcc min: 50 msec max: 2 msec input register r8 c0h r4 0bh set ups051 input mode set backlight driving capability f1h the hblk is the typical value. r7 16h r5 r5 d7h release standby fig.15 recommend serial command settings for ups051 www..net
version: 3 page: 41 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. dclk / hsync / vsync / data input vcc min: 50 msec max: 2 msec input register r4 1bh set ups052 320x240 input set backlight driving capability power on power off vcc min: 0 msec d6h input serial setting register r5 set standby dclk / hsync / vsync / data input min: 5 fields) (1 field: ntsc=16.6ms / pal=20ms) c0h r8 16h r5 release standby d7h r5 fig.16 recommend serial command settings for ups052 320x240 www..net
version: 3 page: 42 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. dclk / hsync / vsync / data input vcc min: 50 msec max: 2 msec input register r4 7bh set ccir656 input mode power on power off vcc min: 0 msec d6h input serial setting register r5 set standby dclk / hsync / vsync / data input min: 5 fields) (1 field: ntsc=16.6ms / pal=20ms) 16h r6 16h r5 set brightness 2eh r3 the vblk setting depends on the input source release standby d7h r5 set contrast 4bh r13 set backlight driving capability c0h r8 fig.17 recommend serial command settings for ccir65 6 www..net
version: 3 page: 43 / 43 all rights strictly reserved. any portion of this p aper shall not be reproduced, copied, or transformed to any other forms without permission f rom au optronics corp. power on stabilized dclk / hsync / vsync / data input vcc min: 50 msec max: 2 msec input register setting other registers other commands 16h r5 set global reset vsync hsync global reset other command register setting stablized dclk / hsync / vsync > 32 hsync period legal interval of global reset fig.18 valid timing of global reset www..net

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