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1 features ee programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and 2,097,152 x 1-bit serial memories designed to store configuration programs for altera flex ? and apex fpgas (device selection guide included) available as a 3.3v (-10%) to 5.0v (+10%) version in-system programmable (isp) via 2-wire bus simple interface to sram fpgas compatible with atmel at6000, at40k and at94k devices, altera flex ? , apex ? devices, lucent orca ? fpgas, xilinx xc3000 ? , xc4000 ? ,xc5200 ? ,spartan ? ,virtex ? fpgas, motorola mpa1000 fpgas cascadable read-back to support additional configurations or higher-density arrays very low-power cmos eeprom process programmable reset polarity available 8-lead pdip, 20-lead plcc and 32-lead tqfp packages (pin compatible across product family) emulation of atmel?s at24cxxx serial eeproms low-power standby mode high-reliability ? endurance: 100,000 write cycles ? data retention: 90 years for industrial parts (at 85 c) and 190 years for commercial parts (at 70 c) description the at17a series fpga configuration eeproms (configurators) provide an easy-to- use, cost-effective configuration memory for field programmable gate arrays. the at17a series device is packaged in the 8-lead pdip (1) , 20-lead plcc and 32-lead tqfp, see table 1. the at17a series configurator uses a simple serial-access proce- dure to configure one or more fpga devices. the user can select the polarity of the reset function by programming four eeprom bytes. these devices also support a write-protection mechanism within its programming mode. note: 1. the 8-lead lap and soic packages for the at17lv65a/128a/256a do not have an a label. however, the 8-lead packages are pin compatible with the 8-lead package of altera?s eeproms, refer to the at17lv65/128/256/512/010/002/040 datasheet available on the atmel web site for more information. the at17a series configurators can be programmed with industry-standard program- mers, atmel?s atdh2200e programming kit or atmel?s atdh2225 isp cable. table 1 . at17a series packages package at17lv65a/ at17lv128a/ at17lv256a at17lv512a at17lv010a at17lv002a 8-lead pdip ye s ye s ye s ? 20-lead plcc yes yes yes yes 32-lead tqfp ??yesyes 44-lead plcc ???? fpga configuration eeprom memory at17lv65a at17lv128a at17lv256a at17lv512a at17lv010a at17lv002a 3.3v to 5v system support rev. 2322c?cnfg?06/02
2 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 pin configuration 8-lead pdip 20-lead plcc 32-lead tqfp notes: 1. this pin is only available on at17lv65a/128a/256a devices. 2. this pin is only available on at17lv512a/010a/002a devices. 3. this pin is only available on at17lv010a/002a devices. 1 2 3 4 8 7 6 5 data dclk (wp (1) )reset/oe ncs vcc ser_en (a2) ncasc gnd 4 5 6 7 8 18 17 16 15 14 dclk wp1 (2) nc (wp (1) ) nc reset/oe ser_en nc nc nc (ready (2) ) nc 3 2 1 20 19 9 10 11 12 13 ncs gnd nc (a2) ncasc nc nc data nc vcc nc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc dclk nc (wp1 (3) )nc nc nc reset/oe nc nc ser_en nc nc ready nc nc nc 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc ncs nc gnd nc nc (a2) ncasc nc nc data nc nc nc vcc nc nc
3 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 block diagram notes: 1. this pin is only available on at17lv65a/128a/256a devices. 2. this pin is only available on at17lv512a/010a/002a devices. power on reset ser_en wp1 (2) ready (2) dclk ncs ncasc reset/oe (wp (1) ) oscillator (3) oscillator controll
4 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 device description the control signals for the configuration eeprom (ncs, reset/oe and dclk) inter- face directly with the fpga device control signals. all fpga devices can control the entire configuration process and retrieve data from the configuration eeprom without requiring an external controller. the configuration eeprom?s reset/oe and ncs pins control the tri-state buffer on the data output pin and enable the address counter and the oscillator. when reset/oe is driven low, the configuration eeprom resets its address c ounter and tri- states its data pin. the ncs pin also controls the output of the at17a series configura- tor. if ncs is held high after the reset/oe pulse, the counter is disabled and the data output pin is tri-stated. when ncs is driven subsequently low, the counter and the data output pin are enabled. when reset/oe is driven low again, the address counter is reset and the data output pin is tri-stated, regardless of the state of the ncs. when the configurator has driven out all of its data and ncasc is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. this is the default setting for the device. since almost all fpgas use reset low and oe high, this document will describe reset /oe.
5 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 data three-state data output for configuration. open-collector bi-directional pin for programming. dclk clock output or clock input. rising edges on dclk increment the internal address counter and present the next bit of data to the data pin. the counter is incremented only if the reset/oe input is held high, the ncs input is held low, and all configuration data has not been transferred to the target device (otherwise, as the master device, the dclk pin drives low). wp1 write protect (1). this pin is used to protect portions of memory during program- ming, and it is disabled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. this pin is only available on at17lv512a/010a/002a devices. reset/oe output enable (active high) and reset (active low) when ser_en is high. a low logic level resets the address counter. a high logic level (with ncs low) enables data and permits the address counter to count. in the mode, if this pin is low (reset), the internal oscillator becomes inactive and dclk drives low. the logic polarity of this input is programmable and must be programmed active high (reset active low) by the user during programming for altera applications. wp write protect (wp) input (when ncs is low) during programming only (ser_en low). when wp is low, the entire memory can be written. when wp is enabled (high), the lowest block of the memory cannot be written. this pin is only available on at17lv65a/128a/256a devices. pin description name i/o at17lv65a/ at17lv128a/ at17lv256a at17lv512a/ at17lv010a at17lv002a 20 plcc 8 pdip 20 plcc 32 tqfp 20 plcc 32 tqfp datai/o2 1 231231 dclki424242 wp1i??5454 reset/oe i 83 8787 wp i ? ? ? ? ncsi9 4 910910 gnd 10 5 10121012 ncasc o 12 6 12151215 a2 i ready o ? ? 15 20 15 20 ser_en i18 7 18231823 v cc 20 8 20272027
6 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 ncs chip select input (active low). a low input (with oe high) allows dclk to increment the address counter and enables data to drive out. if the at17a series is reset with ncs low, the device initializes as the first (and master) device in a daisy-chain. if the at17a series is reset with ncs high, the device initializes as a subsequent at17a series device in the chain. gnd ground pin. a 0.2 f decoupling capacitor between v cc and gnd is recommended. ncasc cascade select output (active low). this output goes low when the address counter has reached its maximum value. in a daisy-chain of at17a series devices, the ncasc pin of one device is usually connected to the ncs input pin of the next device in the chain, which permits dclk from the master configurator to clock data from a subse- quent at17a series device in the chain. a2 device selection input, a2. this is used to enable (or select) the device during program- ming (i.e., when ser_en is low). a2 has an internal pull-down resistor. ready open collector reset state indicator. driven low during power-on reset cycle, released when power-up is complete. (recommended 4.7 k ? pull-up on this pin if used). ser_en serial enable must be held high during fpga loading operations. bringing ser_en low enables the 2-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . v cc +3.3v (-10%) to 5.0v (+10%) power supply pin. at17lv(a) devices with date codes of 0902 and later are tested to an extended voltage range. these parts can now be used in both 3.3v (-10%) to 5.0v (+10%) applications and replace the at17c(a) 5v-only devices.
7 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configura- tion program. the program is loaded either automatically upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the configuration program from an external memory. the at17a serial configuration eeprom has been designed for compatibility with the master serial mode. this document discusses the altera flex fpga device interfaces control of configuration most connections between the fpga device and the at17a serial eeprom are simple and self-explanatory. the data output of the at17a series configurator drives din of the fpga devices. the master fpga dclk output or external clock source drives the dclk input of the at17a series configurator. the ncasc output of any at17a series configurator drives the ncs input of the next configurator in a cascaded chain of eeproms. ser_en must be connected to v cc (except during isp). cascading serial configuration eeproms for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configu- ration memories, cascaded configurators provide additional memory. after the last bit from the first configurator is read, the next clock signal to the configura- tor asserts its ncasc output low and disables its data line driver. the second configurator recognizes the low level on its ncs input and enables its data output. after configuration is complete, the address counters of all cascaded configurators are reset if the reset/oe on each configurator is driven to a low level. if the address counters are not to be reset upon completion, then the r eset/oe input canbetiedtoahighlevel. at17a series reset polarity the at17a series configurator allows the user to program the polarity of the reset/oe pin as either reset/oe or reset /oe. this feature is supported by industry-standard programmer algorithms. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be programmed by the 2-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated inside the chip. standby mode the at17lv65a/128a/256a enters a low-power standby mode whenever ncs is asserted high. in this mode, the configurator consumes less than 50 a of current at 3.3v (100 a for the at17lv512a/010a/002a). the output remains in a high-imped- ance state regardless of the state of the reset/oe input.
8 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 absolute maximum ratings* operating temperature .................................. -55 cto+125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 cto+150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +7.0v maximum soldering temp. (10 sec. @ 1/16 in.) ............. 260 c esd (r zap =1.5k,c zap = 100 pf)................................. 2000v operating conditions symbol description at17lv65a/ at17lv128a/ at17lv256a/ at17lv512a/ at17lv010a at17lv002a units minmaxminmax v cc commercial supply voltage relative to gnd -0 cto+70 c 3.0 5.5 3.15 5.5 v industrial supply voltage relative to gnd -40 cto+85 c 3.0 5.5 3.15 5.5 v military supply voltage relative to gnd -55 cto+125 c 3.0 5.5 3.15 5.5 v dc characteristics symbol description at1 7lv65 a/ at17lv128a/ at17lv256a at17lv512a/ at17lv010a at17lv002a units min max min max min max v ih high-level input voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il low-level input voltage 0 0.8 0 0.8 0 0.8 v v oh high-level output voltage (i oh =-2.5ma) commercial 2.4 2.4 2.4 v v ol low-level output voltage (i ol =+3ma) 0.4 0.4 0.4 v v oh high-level output voltage (i oh =-2ma) industrial 2.4 2.4 2.4 v v ol low-level output voltage (i ol =+3ma) 0.4 0.4 0.4 v v oh high-level output voltage (i oh =-2ma) military 2.4 2.4 2.4 v v ol low-level output voltage (i ol =+2.5ma) 0.4 0.4 0.4 v i cca supply current, active mode 5 5 5 ma i l input or output leakage current (v in =v cc or gnd) -10 10 -10 10 -10 10 a i ccs supply current, standby mode commercial 50 100 100 a industrial/ military 100 100 100 a
9 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 ac characteristics ac characteristics when cascading ncs reset/oe dclk data t sce t lc t hc t oe t ce t cac t oh t hoe t hce t sce t df t oh reset/oe ncs dclk data ncasl t cdf t ock last bit t oce t ooe t oce first bit
10 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 notes: 1. preliminary specifications for military operating range only. 2. ac test lead = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. ac characteristics symbol description at17lv65a/ at17lv128a/ at17lv256a at17lv512a/ at17lv010a at17lv002a units min max min max min max t oe (2) reset/oe to data delay commercial 50 50 50 ns military (1) 55 55 55 ns t ce (2) ncstodatadelay commercial 60 55 55 ns military (1) 60 60 60 ns t cac (2) dclktodatadelay commercial 75 60 60 ns military (1) 80 65 65 ns t oh data hold from ncs, oe, or dclk commercial 0 0 0 ns military (1) 000ns t df (3) ncs or oe to data float delay commercial 55 50 50 ns military (1) 55 50 50 ns t lc dclk low time commercial 25 20 20 ns military (1) 25 20 20 ns t hc dclk high time commercial 25 20 20 ns military (1) 25 20 20 ns t sce ncs setup time to dclk (to guarantee proper counting) commercial 35 20 20 ns military (1) 50 25 25 ns t hce ncsholdtimefromdclk (to guarantee proper counting) commercial 0 0 0 ns military (1) 000ns t hoe oe low time (guarantees counter is reset) commercial 25 20 20 ns military (1) 25 20 20 ns f max maximum input clock frequency commercial 10 15 15 mhz military (1) 10 10 10 mhz t lc dclk low time master mode commercial 30 300 30 300 ns military (1) 30 300 30 300 ns t hc dclk high time master mode commercial 30 300 30 300 ns military (1) 30 300 30 300 ns v rdy ready pin open collector voltage commercial 1.2 2.4 1.2 2.4 v military (1) 1.2 2.4 1.2 2.4 v
11 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 notes: 1. preliminary specifications for military operating range only. 2. ac test lead = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. ac characteristics when cascading symbol description at17lv65a/ at17lv128a/ at17lv256a at17lv512a/ at17lv010a at17lv002a units min max min max min max t cdf (3) dclk to data float delay commercial 60 50 50 ns industrial/ military (1) 60 50 50 ns t ock (2) dclk to ncasc delay commercial 55 50 50 ns industrial/ military (1) 60 55 55 ns t oce (2) ncs to ncasc delay commercial 55 35 35 ns industrial/ military (1) 60 40 40 ns t ooe (2) reset/oe to ncasc delay commercial 40 35 35 ns industrial/ military (1) 45 35 35 ns f max maximum input clock frequency commercial 8 12.5 12 ns industrial/ military (1) 81010ns
12 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 notes: 1. for more information refer to the ?thermal characteristics of atmel?s packages?, available on the atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. 2. airflow = 0 ft/min. thermal resistance coefficients (1) package type at17lv65a/ at17lv128a/ at17lv256a at17lv512a/ at17lv010a at17lv002a 8p3 plastic dual inline package (pdip) jc [ c/w] 37 ja [ c/w] (2) 107 20j plastic leaded chip carrier (plcc) jc [ c/w] 35 35 35 ja [ c/w] (2) 90 90 90 32a thin plastic quad flat package (tqfp) jc [ c/w] ja [ c/w] (2) 44j plastic leaded chip carrier (plcc) jc [ c/w] ? ? 15 ja [ c/w] (2) ??50
13 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 figure 1. ordering code (1) note: 1. the 8-lead lap and soic packages for the at17lv65a/128a/256a do not have an a label. however, the 8-lead packages are pin compatible with the 8-lead package of altera?s eeproms, refer to the at17lv65/128/256/512/010/002/040 datasheet available on the atmel web site for more information. package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 20j 20-lead, plastic j-leaded chip carrier (plcc) 32a 32-lead, thin (1.0 mm) plastic quad flat package carrier (tqfp) voltag e size (bits) special pinouts package temperature 65 = 65k a = altera c = commercial 128 = 128k blank = xilinx/atmel/ =8p3 i = industrial 256 = 256k 512 = 512k = 20j 010 = 1m = 32a 002 = 2m at17lv65a-10pc p j a 3.3v nominal to 5v nominal other
14 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 notes: 1. currently, there are two types of low-density configurators. the new version will be identified by a ?b? after the datacode. the ?b? version is fully backward-compatible with the original devices so existing customers will not be affected. the new parts no longer require a mux for isp. see programming specification for more details. 2. use 64-kbit density parts to replace altera epc1064. 3. use 256-kbit density parts to replace altera epc1213. 4. use 512-kbit density parts to replace altera epc1441. 5. use 1-mbit density parts to replace altera epc1 6. use 2-mbit density parts to replace altera epc2. atmel at17lv002a devices do not support jtag programming; atmel at17lv002a devices use a 2-wire serial interface for in-system programming. ordering information (1) memory size ordering code package operation range 64-kbit (2) at17lv65a-10jc 20j commercial (0 cto70 c) at17lv65a-10ji 20j industrial (-40 cto85 c) 128-kbit at17lv128a-10jc 20j commercial (0 cto70 c) at17lv128a-10ji 20j industrial (-40 cto85 c) 256-kbit (3) at17lv256a-10jc 20j commercial (0 cto70 c) at17lv256a-10ji 20j industrial (-40 cto85 c) 512-kbit (4) at17lv512a-10pc at17lv512a-10jc 8p3 20j commercial (0 cto70 c) at17lv512a-10pi at17lv512a-10ji 8p3 20j industrial (-40 cto85 c) 1-mbit (5) at17lv010a-10pc at17lv010a-10jc AT17LV010A-10QC 8p3 20j 32a commercial (0 cto70 c) at17lv010a-10pi at17lv010a-10ji at17lv010a-10qi 8p3 20j 32a industrial (-40 cto85 c) 2-mbit (6) at17lv002a-10jc at17lv002a-10qc 20j 32a commercial (0 cto70 c) at17lv002a-10ji at17lv002a-10qi 20j 32a industrial (-40 cto85 c)
15 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 packaging information 8p3?pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
16 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 20j?plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
17 at17lv65a/128a/256a/512a/002a 2322c?cnfg?06/02 32a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 atmel programmable sli hotline (408) 436-4119 atmel programmable sli e-mail configurator@atmel.com faq available on web site e-mail literature@atmel.com web site http://www.atmel.com 2322c?cnfg?06/02 xm atmel ? is the registered trademark of atmel. flex ? is the trademark of altera corporation; orca ? is the trademark of lucent technologies, inc.; spartan ? and virtex ? are the registered trademarks of xilinx, inc.; xc3000 ? ,xc4000 ? and xc5200 ? are the trademarks of xilinx, inc.; apex ? is the trademark of mips technologies; other terms and product names may be the trademarks of others.

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