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revisions ltr description date ( yr -mo -da ) approved a add device types 04, 05, and 06. modify boilerplate to include rad hard requirements. editorial changes throughout. 96-03-13 monica l. poelking b add device types 07, 08, and 09. update boilerplate. editorial changes throughout. ? tvn 98-08-27 monica l. poelking c in table i, change i in limits; add footnote to i ddq ; add t c in power-up master reset timing section; add footnote to v os and v dis . correct the jtag timing waveforms. change footnote 3 / in table iii. ? tvn 99-04-28 monica l. poelking d add device types 10 and 11. editorial changes throughout. - tvn 00-06-27 monica l. poelking e add notes to memory write and memory read waveforms. editorial changes throughout. ? tvn 01-03-13 thomas m. hess f correct dimension l for case outline y in figure 1. also, correct footnote 1 / for radiation exposure connections in figure 6. ? tvn 01-07-27 thomas m. hess rev b b b d sheet 35 36 37 38 rev d d b b b f d d b d b e e c b f b b b b sheet 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 rev f d d d f d d d d d d d d d rev status of sheets sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pmic n/a prepared by thomas m. hess checked by thomas m. hess defense supply center columbus columbus, ohio 43216 http://www.dscc.dla.mil approved by monica l. poelking drawing approval date 95-03-31 microcircuit, digital, cmos, serial microcoded multi -mode intelligent terminal and transceiver, silicon size a cage code 67268 5962 -94663 standard microcircuit this drawing is available for use by all departments and agencies of the department of defense amsc n/a revision level f sheet 1 of 38 dscc form 2233 apr 97 5962 -e538-01 distribution statement a . approved for public release; distribution is unlimited.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 2 dscc form 2234 apr 97 1. scope 1.1 scope . this drawing documents two product assurance class levels consisting of high reliability (device classes q and m) and space application (device class v). a choice of case outlines and lead finishes are available and are reflected in the part or identifying number (pin). when available, a choice of radiation hardness assurance (rha) levels are reflected in the pin. 1.2 pin . the pin is as shown in the following example: 5962 h 94663 01 v x x federal rha device device case lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) \ / (see 1.2.3) \/ drawing number 1.2.1 rha designator . device classes q and v rha marked devices meet the mil-prf-38535 specified rha levels and are marked with the appropriate rha designator. device class m rha marked devices meet the mil-prf-38535, appendix a specified rha levels and are marked with the appropriate rha designator. a dash ( -) indicates a non -rha device . 1.2.2 device type(s) . the device type(s) identify the circuit function as follows: device type generic number circuit function 01 69151 -lx15 serial microcoded multi -mode intelligent terminal with 15 -volt transceiver 02 69151 -dx serial microcoded multi -mode intelligent terminal with 5 -volt transceiver 03 69151 -lx12 serial microcoded multi -mode intelligent terminal with 12 -volt transceiver 04 69151 -lxe15 enhanced serial microcoded multi -mode intelligent terminal with 15 -volt transceiver radiat ion hardened 05 69151 -dxe enhanced serial microcoded multi -mode intelligent terminal with 5 -volt transceiver radiation hardened 06 69151 -lxe12 enhanced serial microcoded multi -mode intelligent terminal with 12 -volt transceiver 07 69151 -lxe15 enhanced s erial microcoded multi -mode intelligent terminal with 15 -volt transceiver 08 69151 -dxe enhanced serial microcoded multi -mode intelligent terminal with 5 -volt transceiver 09 69151 -lxe12 enhanced serial microcoded multi -mode intelligent terminal with 1 2 -volt transceiver 10 69151 -lxe15 enhanced serial microcoded multi -mode intelligent terminal with 15 -volt transceiver radiation hardened 11 69151 -dxe enhanced serial microcoded multi -mode intelligent terminal with 5 -volt transceiver radiation hardened
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 3 dscc form 2234 apr 97 1.2.3 device class designator . the device class designator is a single letter identifying the product assurance level as follows: device class device requirements documentation m vendor self -certification to the requirements for mil-std-883 complia nt, non -jan class level b microcircuits in accordance with mil-prf-38535, appendix a q or v certification and qualification to mil-prf-38535 1.2.4 case outline(s) . the case outline(s) are as designated in mil-std-1835 and as follows: outline letter descriptive designator terminals package style x see figure 1 100 pin grid array 1 / y see figure 1 100 leaded chip carrier with nonconductive tier bar 1.2.5 lead finish . the lead finish is as specified in mil-prf-38535 for device classes q and v or mil-prf-38535, appendix a for device class m. 1.3 absolute maximum ratings . 2 / storage temperature range (t stg ) ................................ ................................ .... -65 c to +150 c operating case temperature range (t c ) ................................ ............................ -55 c to +125 c transceiver supply voltage (v ee ): device types 01, 03, 04, 0 6, 07, 09, 10 ................................ ......................... -22 v dc transceiver supply voltage range (v cc ): device types 02, 05, 08, 11 ................................ ................................ .......... -0.3 v dc to +7.0 v dc logic supply voltage range (v dd ) ................................ ................................ ....... -0.3 v dc to +7.0 v dc input voltage range (v dr ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... 42 v p,l-l device types 02, 05, 08, 11 ................................ ................................ .......... 10 v p,l-l maximum power dissipation (p d ) ................................ ................................ ....... 5 w logic voltage on any pin range (v i/o ) ................................ ................................ . -0.3 v dc to v dd + 0.3 v dc logic latch-up immunity (i lu ) ................................ ................................ ............. 150 ma logic input current (i i ) ................................ ................................ ...................... 10 ma output current (i o ): device types 01 , 03, 04, 06, 07, 09, 10 ................................ ......................... 190 ma device types 02, 05, 08, 11 ................................ ................................ .......... 1000 ma maximum junction temperature (t j ) ................................ ................................ . +150 c receiver common mode input voltage range (v ic ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... -11 v dc to +11 v dc device types 02, 05, 08, 1 1 ................................ ................................ .......... -5 v dc to +5 v dc lead temperature (soldering, 5 seconds) ................................ ........................... +300 c thermal resistance junction-to-case ( q jc ): 3 / cases x and y ................................ ................................ ............................. 7 c/w 1 / this package contains 96 terminals on the bottom and 4 terminals on top of the packag e, see figure 1. 2 / stress outside the listed absolute maximum rating may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods affect device reliability. 3 / per mil-std-883, method 1012.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 4 dscc form 2234 apr 97 1.4 recommended operating conditions . transceiver supply voltage range (v cc ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... +4.75 v dc to +5.5 v dc device type 02 ................................ ................................ .............................. +4.75 v dc to +5.25 v dc device types 05, 08, 11 ................................ ................................ ................ +4.5 v dc to +5.5 v dc logic supply voltage range (v dd ) ................................ ................................ ...... +4.5 v dc to +5.5 v dc transceiver supply voltage range (v ee ): device types 01, 04, 07, 10 ................................ ................................ .......... -15 v dc device types 03, 06, 09 ................................ ................................ ................ -12 v dc receiver differential voltage (v dr ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... 40 v p-p device types 02, 05, 08, 11 ................................ ................................ .......... 8.0 v p-p logic dc input voltage range (v in ) ................................ ................................ ...... 0 v d c to v dd receiver common mode input voltage (v ic ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... 10 v dc device types 02, 05, 08, 11 ................................ ................................ .......... 5.0 v dc driver peak output current (i o ): device types 01, 03, 04, 06, 07, 09, 10 ................................ ......................... 180 ma device types 02, 05, 08, 11 ................................ ................................ .......... 700 ma serial data rate range (s d ) ................................ ................................ ............... 0 to 1 mhz clock duty cycle (d c ) ................................ ................................ ....................... 50 5% case operating temperature range (t c ) ................................ ............................ -55 c to +125 c operating frequency (f in ) ................................ ................................ ................. 24 mhz 0.01% radiation features: total dose device type 04, 10 ................................ ................................ .................. 100k rads (si) d evice type 05 ................................ ................................ ........................ 1m rads (si) device type 11 ................................ ................................ ........................ 300k rads (si) single event phenomenon (sep) effective linear energy threshold, no upsets ................................ ............................ 1 / neutron fluence (tm 1017) ................................ ................................ ........... 1 / 1.5 digital logic testing for device classes q and v . fault coverage measurement of manufacturing logic tests (mil -std -883, test method 5012) ................................ ................ 95.12 percent 2. applicable documents 2.1 government specification, standards, and handbooks . the following specification, standards, and handbooks form a part of this drawing to the extent specified herein. unless otherwise specified, the issues of these documents are those listed in the issue of the department of defense index of specifications and standards (dodiss) and supplement thereto, cited in the solicitation. 1 / values will be added when they become available. rad hard devices have not yet been tested for neutron or sep.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level f sheet 5 dscc form 2234 apr 97 specification department of defense mil-prf-38535 - integrated circuits, manufacturing, general specification for . standards department of defense mil -std -883 - test methods standard microcircuits. mil-std-1835 - interface standard electronic component case outlines. handbooks department of defense mil-hdbk-103 - list of standard microcircuit drawings. mil -hdb k -780 - standard microcircuit drawings. (unless otherwise indicated, copies of the specification, standards, and handbooks are available from the standardization document order desk, 700 robbins avenue, building 4d, philadelphia, pa 19111-5094.) 2.2 non -government publications . the following document(s) form a part of this document to the extent specified herein. unless otherwise specified, the issues of the documents which are dod adopted are those listed in the issue of the dodiss cited in the solicitation. unless otherwise specified, the issues of documents not listed in the dodiss are the issues of the documents cited in the solicitation. institute of electrical and electronics engineers (ieee) ieee standard 1149.1 - ieee standard test access port and boundary scan architecture. (applications for copies should be addressed to the institute of electrical and electronics engineers, 445 hoes lane, piscataway, nj 08854-4150.) (non-government standards and other publications are normally availab le from the organizations that prepare or distribute the documents. these documents may also be available in or through libraries or other informational services.) 2.3 order of precedence . in the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. requirements 3.1 item requirements . the individual item requirements for device classes q and v shall be in accordance with mil-prf-38535 and as specified herein or as modified in the device manufacturer's quality management (qm) plan. the modification in the qm plan shall not affect the form, fit, or function as described herein. the individual item requirements for device class m shall be in accordance with mil-prf-38535, appendix a for non-jan class level b devices and as specified herein. 3.2 design, construction, and physical dimensions . the design, construction, and physical dimensions shall be as specified in mil-prf-38535 and herein for device classes q and v or mil-prf-38535, appendix a and herein for device class m.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 6 dscc form 2234 apr 97 3.2.1 case outlines . the case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 terminal connections . the terminal connections shall be as specified on figure 2. 3.2.3 block diagram . the block diagram shall be as specified on figure 3. 3.2.4 boundary scan instruction codes . the boundary scan instruction codes shall be as specified on figure 4. 3.2.5 timing waveforms . the timing waveforms shall be as specified on figure 5. 3.2.6 radiation exposure connections . the radiation exposure connections shall be as specified on figure 6. 3.3 electrical performance characteristics and postirradiation parameter limits . unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table ia and shall apply over the full case operating temperature range. 3.4 electrical test requirements . the electrical test requirements shall be the subgroups specified in table iia. the electrical tests for each subgroup are defined in table ia. 3.5 marking . the part shall be marked with the pin listed in 1.2 herein. in addition, the manufacturer's pin may also be marked as listed in mil-hdbk-103. for packages where marking of the entire smd pin number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. for rha product using this option, the rha designator shall still be marked. marking for device classes q and v shall be in accordance with mil-prf-38535. marking for device class m shall be in accordance with mil-prf-38535, appendix a. 3.5.1 certification/compliance mark . the certification mark for device classes q and v shall be a "qml" or "q" as required in mil-prf-38535. the compliance mark for device class m shall be a "c" as required in mil-prf-38535, appendix a. 3.6 certificate of compliance . for device classes q and v, a certificate of compliance shall be required from a qml -38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). for device class m, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in mil-hdbk-103 (see 6.6.2 herein). the certificate of compliance submitted to dscc -va prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes q and v, the requirements of mil -prf -38535 and herein or for device class m, the requirements of mil-prf-38535, appendix a and herein. 3.7 certificate of conformance . a certificate of conformance as required for device classes q and v in mil-prf-38535 or for device class m in mil-prf-38535, appendix a shall be provided with each lot of microcircuits delivered to this drawing. 3.8 notification of change for device class m . for device class m, notification to dscc -va of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in mil-prf-38535, appendix a. 3.9 verification and review for device class m . for device class m, dscc, dscc's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. offshore documentation shall be made available onshore at the option of the reviewer. 3.10 microcircuit group assignment for device class m . device class m devices covered by this drawing shall be in microcircuit group number h (see mil-prf-38535, appendix a). 3.11 ieee 1149.1 compliance . these devices shall be compliant to ieee 1149.1.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 7 dscc form 2234 apr 97 table ia. electrical performance characteristics . limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit low level input voltage v il1 all 1, 2, 3 0.8 01, 02 03, 04 05, 06 10, 11 1, 2, 3 0.8 low level input voltage, tck only v il2 07, 08 09 1, 2, 3 0.7 v high level input voltage v ih all 1, 2, 3 2.2 v low level input voltage 2 / v ilc all 1, 2, 3 0.3v dd v high level input voltage 2 / v ihc all 1, 2, 3 0.7v d d v i ol = 4.0 ma 0.4 low level output voltage v ol output loads i ol = 1.0 m a 3 / all 1, 2, 3 0.05 v i oh = 4.0 ma 2.4 high level output voltage v oh output loads i oh = 1.0 m a 3 / all 1, 2, 3 v dd -0.05 v ttl driven inputs v in = v dd or v ss -10 +10 v in = v dd all 1, 2, 3 -10 +10 01, 02, 03, 04, 05, 06 10, 11 -900 -150 input leakage current i in inputs with pull -up resistors v in = v ss 07, 08, 09 1, 2, 3 -167 -27 m a three -state output leakage current, ttl loaded outputs, single -drive buffer i oz v o = v dd or v ss all 1, 2, 3 -10 +10 m a short -circuit output current, output loads i os 4 / 5 / v dd = 5.5 v, v o = 0 v v dd = 5.5 v, v o = v dd all 1, 2, 3 -100 +100 ma input capacitance c in all 4 45 output capacitance c out all 4 45 bi-directional capacitance 6 / c io f = 1 mhz at 0 v see 4.4.1c all 4 45 pf standby operating current i dds f = 24 mhz all 1, 2, 3 40 ma see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 8 dscc form 2234 apr 97 table ia. electrical performance characteristics - continu ed. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit 1, 3 35 m a f = 0 mhz 01 ? 10 2 1 ma 1, 3 35 m a pre-irradiation level r 11 2 1 ma 1, 3 35 m a quiescent current 7 / 8 / i ddq pre-irradiation level f 11 2 5 ma 0% duty cycle (non -transmitting) 140 50% duty cycle (f = 1 mhz) 9 / 140 v ee = -12 v v cc = 5 v 100% duty cycle (f = 1 mhz) 9 / 03, 06 09 140 0% duty cycle (non -transmitting) 140 50% duty cycle (f = 1 mhz) 10 / 140 v ee = -15 v v cc = 5 v 100% duty cycle (f = 1 mhz) 10 / 01, 04 07, 10 1, 2, 3 140 0% duty cycle (non -transmitting) 55 25% duty cycle 10 / 250 50% duty cycle (f = 1 mhz) 10 / 410 87.5% duty cycle (f = 1 mhz) 10 / 02, 05 08, 11 650 v cc supply current i cc v cc = 5 v 100% duty cycle (f = 500 khz) 02 1, 2, 3 855 ma 0% duty cycle (non -transmitting) 80 50% duty cycle (f = 1 mhz) ) 9 / 180 v ee = -12 v v cc = 5 v 100% duty cycle (f = 1 mhz) ) 9 / 03, 06 09 270 0% duty cycle (non -transmitting) 80 50% duty cycle (f = 1 mhz) ) 10 / 180 i ee supply current i ee v ee = -15 v v cc = 5 v 100% duty cycle (f = 1 mhz) ) 10 / 01, 04 07, 10 1, 2, 3 270 ma see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 9 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit functional tests see 4.4.1b all 7, 8 register write timing address setup time 9 / t a all 9, 10, 11 0 data setup time 9 / t b all 9, 10, 11 10 data hold time 9 / t c all 9, 10, 11 8 address hold time 9 / t d all 9, 10, 11 8 cs to cs - 9 / t e all 9, 10, 11 105 access delay 9 / 11 / 12 / t f all 9, 10, 11 85 rd/ wr assertion to cs assertion 10 / t g all 9, 10, 11 0 cs negation to rd/ wr negation 10 / t h all 9, 10, 11 0 cs assertion to output enable 9 / t i all 9, 10, 11 0 40 cs negation to output three -state 10 / t j v cc = minimum see figure 5 all 9, 10, 11 5 35 ns register read timing address setup time 9 / t a all 9, 10, 11 0 cs assertion to output enable data valid 9 / t b all 9, 10, 11 95 cs negation to output disabled 10 / t c all 9, 10, 11 5 35 address hold time 9 / t d all 9, 10, 11 0 cs assertion to output enable data invalid 9 / t e all 9, 10, 11 0 40 access delay 9 / 11 / 12 / t f all 9, 10, 11 45 cs to cs - 9 / t g v cc = minimum see figure 5 all 9, 10, 11 105 ns memory write timing 01 ? 06 10, 11 9, 10, 11 0 18 address propagation delay t a 07, 08 09 9, 10, 11 0 21 address valid to rcs , rwr assertion 9 / t b v cc = minimum see figure 5 all 9, 10, 11 15 35 ns see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 10 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit memory write timing ? continued dtack setup time 9 / t c all 9, 10, 11 10 rcs and rwr hold time 9 / 13 / t d all 9, 10, 11 20 50 data propagation delay 9 / t e all 9, 10, 11 20 60 address hold time 9 / t g all 9, 10, 11 10 30 dtack hold time 9 / t h all 9, 10, 11 10 01 ? 06 10, 11 9, 10, 11 34 rwr and rcs pulse width ( dtack tied to ground) t i 07, 08 09 9, 10, 11 32 rwr and rcs - to dmack - 10 / t j all 9, 10, 11 15 125 data hold time 10 / t k v cc = minimum see figure 5 all 9, 10, 11 10 40 ns memory read timing 01 ? 06 10, 11 9, 10, 11 0 18 address propagation delay t a 07, 08 09 9, 10, 11 0 21 address valid to rcs , rrd assertion 9 / t b all 9, 10, 11 15 35 dtack setup time 9 / t c all 9, 10, 11 10 rcs and rrd hold time 9 / 13 / t d all 9, 10, 11 20 50 01 - 06 9, 10, 11 12 07, 08 09 9, 10, 11 10 data setup delay 9 / t e 10, 11 9, 10, 11 14 01 ? 06 10, 11 9, 10, 11 0 data hold delay t f 07, 08 09 9, 10, 11 2 address hold time 9 / t g v cc = minimum see figure 5 all 9, 10, 11 10 30 ns see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 11 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit memory read timing - continued dtack hold time t h all 9, 10, 11 10 01 ? 06 10, 11 9, 10, 11 34 rrd and rcs pulse width ( dtack tied to ground) t i 07, 08 09 9, 10, 11 32 rrd and rcs - to dmack - 10 / t j v cc = minimum see figure 5 all 9, 10, 11 15 45 ns dma timing teract assertion to dmar assertion 10 / t a v cc = minimum see figure 5 all 9, 10, 11 5 01, 02 03 9, 10, 11 7 bus controller 04 - 11 9, 10, 11 16 remote terminal all 9, 10, 11 7 remote terminal with monitor all 9, 10, 11 7 dmar assertion to dmack negation 10 / t b monitor all 9, 10, 11 7 m s 01 ? 06 10, 11 9, 10, 11 0 30 dmag assertion to dmack assertion 10 / t c 07, 08 09 9, 10, 11 5 30 dmag assertion to dmar negation 10 / t d all 9, 10, 11 0 35 01 ? 06 10, 11 9, 10, 11 0 5 dmack assertion to address bus active t e 07, 08 09 9, 10, 11 -5 5 dmack assertion to dmag negation 9 / t f all 9, 10, 11 10 dmack negation to dmar assertion 10 / t g all 9, 10, 11 500 ns see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 12 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit dma timing - continued 01 ? 06 10, 11 0 5 dmack assertion to ram control active (negated) t h 07, 08 09 9, 10, 11 -5 5 dmack negation to address three -state 10 / t i all 9, 10, 11 5 dmack negation to ram control disabled 10 / t j v cc = minimum see figure 5 all 9, 10, 11 5 ns power -up master reset timing mrst pulse width 10 / t a all 9, 10, 11 500 ns mrst negation to romen assertion 10 / t b all 9, 10, 11 5 m s mrst negation to ready assertion 10 / t c all 9, 10, 11 10 m s dmack negation to romen negation 10 / t d v cc = minimum see figure 5 all 9, 10, 11 500 ns jtag timing tck frequency all 9, 10, 11 1 mhz tck period t a all 9, 10, 11 1000 tck high time t b all 9, 10, 11 1/2t a tck low time t c all 9, 10, 11 1/2t a tck rise time t d all 9, 10, 11 5 tck fall time t e all 9, 10, 11 5 tdi, tms setup time t f all 9, 10, 11 250 tdi, tms hold time t g all 9, 10, 11 250 tdo valid delay t h see figure 5 all 9, 10, 11 250 ns receiver electrical characteristics differential (receiver) input impedance 10/ r iz v cc = minimum, see figure 5 input f = 1 mhz (no transformer in circuit) 01, 03 04, 06 07, 09 10 1, 2, 3 15 k w 01, 03 04, 06 07, 09 10 1, 2, 3 -10 +10 common mode input voltage 10 / v ic v cc = minimum, see figure 5 direct -coupled stub, input 1.2 v pp , 200 ns rise/fall time 25 ns, f = 1 mhz 02, 05 08, 11 1, 2, 3 -5 +5 v see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 13 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit receiver electrical characteristics - continued common mode rejection ratio 10/ cmrr v cc = minimum, see figure 5 all 1, 2, 3 pass/fail 14 / n/a v cc = minimum, see figure 5 transformer -coupled stub, input at f = 1 mhz, rise/fall time 200 ns (receiver output 0 ? 1 transition) 10 / all 1, 2, 3 0.20 input threshold voltage (no response) v th1 v cc = minimum, see figure 5 direct -coupled stub, input at f = 1 mhz, rise/fall time 200 ns (receiver output 0 ? 1 transition) all 1, 2, 3 0.28 v pp,l-l v cc = minimum, see figure 5 transformer -coupled stub, input at f = 1 mhz, rise/fall time 200 ns (receiver output 0 ? 1 transition) 10 / all 1, 2, 3 0.86 14.0 input threshold voltage (response) v th2 v cc = minimum, see figure 5 direct -coupled stub, input at f = 1 mhz, rise/fall time 200 ns (receiver output 0 ? 1transition) all 1, 2, 3 1.20 20.0 10 / v pp,l-l differential input voltage level v idr v cc = minimum, see figure 5 02 1, 2, 3 8.0 v p-p transmitter electrical characteristics v cc = minimum, see figure 5 transformer -cou pled stub, point a, input f = 1 mhz, r l = 70 w 10/ all 1, 2, 3 18 27 v cc = minimum, see figure 5 direct -coupled stub, point a, input f = 1 mhz, r l = 35 w all 1, 2, 3 6.0 9 output voltage swing v o v cc = minimum, see figure 5 point a, input f = 1 mhz, r l = 35 w 10/ all 1, 2, 3 6.0 20 v pp,l-l v cc = minimum, see figure 5 transformer -coupled stub, point a, input f = dc to 10 mhz, r l = 70 w all 1, 2, 3 14 output noise voltage differential 10 / v ns v cc = minimum, see figure 5 direct -coupled stub, point a, input f = dc to 10 mhz, r l = 35 w all 1, 2, 3 5 mv - rms l-l see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 14 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit transmitter electrical characteristics - continued v cc = minimum transformer -coupled stub, point a, r l = 70 w , measurement taken 2.5 m s after end of transmission 10 / all 1, 2, 3 -250 +250 output symmetry 15 / v os v cc = minimum direct -coupled stub, point a, r l = 35 w , measurement taken 2.5 m s after end of transmission 16 / all 1, 2, 3 -90 +90 mv pp,l-l 01 03 ? 11 1, 2, 3 -900 +900 mv peak,l-l v cc = minimum, see figure 5 transformer -coupled stub, point a, r l = 70 w 10 / 02 1, 2, 3 -2.0 +2.0 v peak,l-l 01 03 ? 11 1, 2, 3 -300 +300 mv peak,l-l output voltage distortion (overshoot or ring) v dis v cc = minimum, see figure 5 direct -coupled stub, point a, r l = 35 w 16 / 02 1, 2, 3 -1.0 +1.0 v peak,l-l v cc = minimum, see figure 5 transformer -coupled stub, point a, input f = 75 khz to 1 mhz, (power on or power off, non- transmitting, r l removed from circuit) all 1, 2, 3 1 terminal input impedance 10 / t iz v cc = minimum, see figure 5 direct -coupled stub, point a, input f = 75 khz to 1 mhz, (power on or power off, non- transmitting, r l removed from circuit) all 1, 2, 3 2 k w ac electrical characteristics transmitter output rise/fall time t r , t f v cc = minimum, see figure 5 input f = 1 mhz 50% duty cycle: direct -coupled, r l = 35 w , output at 10% through 90% points txout, txout all 9, 10, 11 100 300 zero crossing distortion t rzcd v cc = minimum, see figure 5 direct -coupled stuff, input f = 1 mhz, 3 v pp (skew input 150 ns), rise/fall time 200 ns all 9, 10, 11 -150 +150 ns see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 15 dscc form 2234 apr 97 table ia. electrical performance characteristics - continued. limits test symbol test conditions 1 / -55 c t c +125 c 4.5 v v dd 5.5 v unless otherwise specified device type group a subgroups min max unit ac electrical characteristics - continued zero crossing stability t tzcs v cc = minimum, see figure 5 input txin and txin should create transmitter output zero crossings at 500 ns, 1000 ns, 1500 ns, and 2000 ns. these zero crossings should not deviate more than 25 ns all 9, 10, 11 -25 +25 ns 1 / device type 04 supplied to this drawing will meet all levels m, d, p, l, r of irradiation. device ty pe 05 supplied to this drawing will meet all levels m, d, p, l, r, f, g, and h of irradiation. however, these devices are only tested at the 'r' and 'h' level, respectively. device type 10 supplied to this drawing will meet level r of irradiation and will only be tested at level r. device type 11 supplied to this drawing will meet levels r and f of irradiation and will only be tested at level supplied. pre and post irradiation values are identical unless otherwise specified in table ia. when performing post irradiation electrical measurements for any rha level, t a = +25 c. all testing to be performed using worst case test conditions unless otherwise specified. gnd may not vary from 0 v by more than 50 mv. unless otherwise specified, v cc = 5.0 v 5% for device type 02; v cc = 5.0 v 10% for device types 05, 08, and 11; v cc = 5.0 v +10%, -5% and v ee = -12.0 v or -15.0 v 5% for device types 01, 03, 04, 06, 07, 09, and 10. 2 / 24 mhz input only. 3 / the worst case test condition is when iol and ioh = 4.0 ma. 4 / supplied as a design limit but not guaranteed or tested. 5 / not more than one output may be shorted at a time for maximum duration of one second. 6 / for all pins except cha, cha , chb, chb . 7 / all inputs tied to v dd . 8 / post irradiation limit is 1.0 ma. device type 11 post irradiation limit is 1.0 ma level r of irradiation and 5.0 ma level f of irradiation. 9 / for device types 07, 08, and 09, this parameter is guaranteed, but not tested. 10 / guaranteed by char acterization but not tested. 11 / read cycle followed by a read cycle - minimum 45 ns. read cycle followed by a write cycle - minimum 45 ns. write cycle followed by a read cycle - minimum 85 ns. write cycle followed by a write cycle - minimum 85 ns. 12 / minimum pulse width from latter rising edge of rd/ wr or cs to first falling edge. 13 / pulse width duration is measured with respect to the device recognizing dtack assertion. 14 / pass/fail criteria per the test method described in mil-std-1553, appendix a. rt validation test plan, section 5.1.2.2, common mode rejection. 15 / test in accordance with the method described in mil -std -1553b output symmetry, section 4.5.2.1.1.4. 16 / tested on dei vce types 07, 08, and 09 only.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 16 dscc form 2234 apr 97 table ib. sep test limits . 1 / 2 / 3 / v dd = 4.5 v device type t a = temperature 10 c 4 / effective let no upsets [mev/(mg/cm 2 )] maximum device cross section let = 120 ( m m 2 ) bias for latch -up test v dd = 5.5 v no latch -up let = 4 / 04, 05 10, 11 +25 c 5 / 5 / 5 / 1 / devices that contain cross -coupled resistance must be tested at the maximum rated t a . 2 / for sep test conditions, see 4.4.4.5 herein. 3 / technology characterization and model verification supplem ented by in -line data may be used in lieu of end -of -line testing. test plan must be approved by trb and qualifying activity. 4 / worst case temperature t a = +125 c. 5 / values will be added when they become available. these devices have not yet been test ed for sep.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 17 dscc form 2234 apr 97 case x figure 1. case outlines .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 18 dscc form 2234 apr 97 case x symbol millimeters inches min max min max a 6.85 8.00 .270 .315 a1 2.54 3.17 .100 .125 b 0.40 0.50 .016 .020 d 32.89 33.66 1.295 1.325 d1 29.21 bsc 1.150 bsc e 26.54 27.30 1.045 1.075 e 1.27 bsc .050 bsc l 4.37 4.77 .172 .188 note: the us government preferred system of measurement is the metric si system. however, this item was originally designed using inch -pound units of measurements. in the event of conflict between the metric and inch -pound units, the inch -pound units shall take precedence. figure 1. case outlines - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 19 dscc form 2234 apr 97 case y figure 1. case outlines - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level f sheet 20 dscc form 2234 apr 97 case y symbol millimeters inches min max min max a 2.66 .105 a1 2.28 3.30 .090 .130 b 0.152 0.254 .006 .010 c 0.1270 0.1905 .0050 .0075 d/e 65.532 2.580 d1 33.91 34.67 1.335 1.365 d2/e2 15.24 bsc .600 bsc e1 24.64 25.40 .970 1.000 e 0.635 bsc .025 bsc l 8.89 .350 note: the us government pre ferred system of measurement is the metric si system. however, this item was originally designed using inch -pound units of measurements. in the event of conflict between the metric and inch -pound units, the inch -pound units shall take precedence. figure 1. case outlines - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 21 dscc form 2234 apr 97 device type all case outline x terminal number terminal symbol terminal number terminal symbol terminal number terminal symbol terminal number terminal symbol a2 a15 c2 a12 t1 a3 v1 v ss a4 a14 c4 v dd t3 a4 v3 rrd a6 a13 c6 a8 t5 v dd v5 d14 a8 romen c8 v ss t7 a6 v7 dtack a10 cs c10 dmag t9 24 mhz v9 d13 a12 msel0 c12 yf_ int t11 v ss v11 d15 a14 tck c14 tms t13 lock v13 d9 a16 tdi c16 a/ b std t15 ready v15 d10 a18 tdo c18 chb t17 gnd v17 d8 a20 rta2 c20 gnd t19 v cc v19 d1 a22 rta0 c22 chb t21 v ee 1 / v21 d2 a24 gnd c24 v cc t23 v ee 1 / v23 d0 b1 v dd d1 a9 u2 a1 w2 a5 b3 a11 d3 a7 u4 v dd w4 rwr b5 a10 d5 v ss u6 a2 w6 a0 b7 dmack d7 v dd u8 v ss w8 tclk b9 autoen d9 msg_ int u10 d12 w10 v dd b11 rd/ wr d11 v ss u12 d11 w12 rcs b13 msel1 d13 dmar u14 ssysf w14 d5 b15 trst d15 mrst u16 teract w16 d6 b17 rta4 d17 gnd u18 cha w18 d7 b19 rta3 d19 v cc u20 gnd w20 d4 b21 rta1 d21 v ee 1 / u22 cha w22 d3 b23 rtpty d23 v ee 1 / u24 v cc w24 gnd terminal located on top of package cp1 v ddq cp2 v ssq cp3 v dd cp4 v ss 1 / device types 01, 03, 04, 06, 07, 09, a nd 10 only. for device types 02, 05, 08, and 11, this is a n/c (no connection). figure 2. terminal connections .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 22 dscc form 2234 apr 97 device type all case outline y terminal number terminal symbol terminal number terminal symbol terminal number terminal symbol terminal number terminal symbol 1 dmack 26 a15 51 tdi 76 v dd 2 dmag 27 v ee 1 / 52 tdo 77 v ss 3 dmar 28 v ee 1 / 53 trst 78 romen 4 dtack 29 gnd 54 rtpty 79 autoen 5 v ss 30 v cc 55 rta0 80 cs 6 rrd 31 gnd 56 rta1 81 rd/ wr 7 rwr 32 cha 57 rta2 82 d0 8 rcs 33 cha 58 rta3 83 d1 9 v dd 34 gnd 59 rta4 84 d2 10 v ss 35 v cc 60 v dd 85 d3 11 a0 36 v cc 61 v ss 86 d4 12 a1 37 gnd 62 v dd 87 d5 13 a2 38 gnd 63 teract 88 d6 14 a3 39 v cc 64 ready 89 d7 15 a4 40 v cc 65 msg_ int 90 d8 16 a5 41 gnd 66 yf_ int 91 d9 17 a6 42 chb 67 v ss 92 d10 18 a7 43 chb 68 tclk 93 d11 19 a8 44 gnd 69 lock 94 d12 20 a9 45 v cc 70 a/ b std 95 d13 21 a10 46 gnd 71 msel0 96 d14 22 a11 47 v ee 1 / 72 msel1 97 d15 23 a12 48 v ee 1 / 73 mrst 98 v ss 24 a13 49 tck 74 24 mhz 99 v dd 25 a14 50 tms 75 ssysf 100 v dd 1 / device types 01, 03, 04, 06, 07, 09, and 10 only. for device types 02, 0 5, 08, and 11, this is a n/c (no connection). figure 2. terminal connections - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 23 dscc form 2234 apr 97 figure 3. block diagram .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 24 dscc form 2234 apr 97 device types 01, 02, 03, 04, 05, 06, 10, 11 instruction name instruction code bypass 1111 sample/preload 0010 extest 0000 intest 0001 runbist 0111 idcode 0100 gl -tristate 0011 internal -scan 0101 private 0110 user -selectable 1000 ? 1110 device types 07, 08, 09 instruction name instruction code bypass 1111 sample/preload 0010 extest 0000 figure 4. boundary scan instruction codes .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 25 dscc form 2234 apr 97 figure 5. timing waveforms .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level e sheet 26 dscc form 2234 apr 97 note: the memory read and write timing diagrams are applicable for reads and writes resulting from the auto -initialization sequence. figure 5. timing waveforms - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level e sheet 27 dscc form 2234 apr 97 ( s e e n o t e b e l o w ) note: the memory read and write timing diagrams are applicable for reads and writes resulting from the auto -initialization sequence. figure 5. timing waveforms - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level c sheet 28 dscc form 2234 apr 97 transceiver test circuit mil-std-1553b 24 mhz notes: 1. transformer coupled stub: terminal is defined as transceiver plus isolation transformer. 2. direct coupled stub: terminal is defined as transceiver plus isolation transformer and fault resistors. figure 5. timing waveforms - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 29 dscc form 2234 apr 97 figure 5. timing waveforms - continued.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level f sheet 30 dscc form 2234 apr 97 figure 5. timing waveforms - continued. case outline open v cc = 5.5 v v dd = 5.5 v v ee = -15 v 1 / ground x a2, a4, a6, a8, a18, b3, b5, b7, c2, c6, c12, c18, c22, d1, d3, d9, d13, t7, t15, u16, u18, u22, v3, w2, w4, w12 c24, d19, t19, u24 a10, a12, a14, a16, a20, a22, b1, b9, b11, b13, b15, b17, b19, b21, b23, c4, c10, c14, c16, d7, d15, t1, t3, t5, t9, t13, u2, u4, u6, u10, u12, u14, v5, v7, v9, v11, v13, v15, v17, v19, v21, v23, w6, w8, w10, w14, w16, w18, w20, w22 d21, d23, t21, t23 a24, c8, c20, d5, d11, d17, t11, t17, u8, u20, v1, w24 y 1, 3, 6, 7, 8, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 32, 33, 42, 43, 52, 63, 64, 65, 66, 78 30, 35, 36, 39, 40, 45 2, 4, 9, 11, 12, 13, 14, 15, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 68, 69, 70, 71, 72, 73, 74, 75, 76, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 99, 100 27, 28, 47, 48 5, 10, 29, 31, 34, 37, 38, 41, 44, 46, 61, 67, 77, 98 1 / for device types 01, 03, 04, 06, 07, 09, and 10 only. for device types 02, 05, 08, and 11, these pins are open. figure 6. radiation exposure connections .
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 31 dscc form 2234 apr 97 4. quality assurance provision s 4.1 sampling and inspection . for device classes q and v, sampling and inspection procedures shall be in accordance with mil -prf -38535 or as modified in the device manufacturer's quality management (qm) plan. the modification in the qm plan shall not affect the form, fit, or function as described herein. for device class m, sampling and inspection procedures shall be in accordance with mil-prf-38535, appendix a. 4.2 screening . for device classes q and v, screening shall be in accordance with mil-prf-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. for device class m, screening shall be in accordance with method 5004 of mil -std -883, and shall be conducted on all devices prior to quality con formance inspection. 4.2.1 additional criteria for device class m . a. burn -in test, method 1015 of mil -std -883. (1) test condition a, b, c, or d. the test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) t a = +125 c, minimum. b. interim and final electrical test parameters shall be as specified in table iia herein. 4.2.2 additional criteria for device classes q and v . a. the burn -in test duration, test condition and test temperature, or approved alternatives sh all be as specified in the device manufacturer's qm plan in accordance with mil-prf-38535. the burn -in test circuit shall be maintained under document revision level control of the device manufacturer's technology review board (trb) in accordance with mil -prf -38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of mil-std-883. b. interim and final electrical test parameters shall be as specified in table iia herein. c. additional screening for device class v beyond the requirements of device class q shall be as specified in mil -prf -38535, appendix b. 4.3 qualification inspection for device classes q and v . qualification inspection for device classes q and v shall be in accordance with mil-prf-38535. inspections to be performed shall be those specified in mil-prf-38535 and herein for groups a, b, c, d, and e inspections (see 4.4.1 through 4.4.4). 4.4 conformance inspection . technology conformance inspection for classes q and v shall be in accordance with mil -prf -38535 including groups a, b, c, d, and e inspections and as specified. quality conformance inspec tion for device class m shall be in accordance with mil-prf-38535, appendix a and as specified herein. inspections to be performed for device class m shall be those specified in method 5005 of mil -std -883 and herein for groups a, b, c, d, and e inspection s (see 4.4.1 through 4.4.4). 4.4.1 group a inspection . a. tests shall be as specified in table iia herein. b. for device class m, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. for device classes q and v, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with mil -std -883, test method 5012 (see 1.5 herein). c. subgroup 4 (c in , c out , and c io ) shall be measured only for the initial test and after process or design changes which may affect input capacitance. a minimum sample of 5 devices with zero failures shall be required.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 32 dscc form 2234 apr 97 table iia. electrical test requirements . test requirements subgroups (in accordance with mil-std-883, method 5005, table i) subgroups (in accordance with mil-prf-38535, table iii) device class m device class q device class v interim electrical parameters (see 4.2) --- --- --- final electrical parameters (see 4.2) 1, 2, 3, 7, 8, 9, 10, 11 1 / 1, 2, 3, 7, 8, 9, 10, 11 1 / 1, 2, 3, 7, 8, 9, 10, 11 2 / 3 / group a test requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 group c end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 group d end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 group e end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1 / pda applies to subgroup 1. 2 / pda applies to subgroups 1 and 7. 3 / delta limits, as specified in table iib herein, shall be required when specified and the delta values shall be completed with reference to the zero hour electrical parameters. table iib. burn -in and operating life test, delta parameters (+25 c) . parameter symbol delta limits quiescent current i ddq 10% of measured values or 35 m a whichever is greater note: if the device is tested at or below 35 m a, no deltas are required. 4.4.2 group c inspection . the group c inspection end -point electrical p arameters shall be as specified in table iia herein. 4.4.2.1 additional criteria for device class m . steady -state life test conditions, method 1005 of mil -std -883: a. test condition a, b, c, or d. the test circuit shall be maintained by the manufa cturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of mil-std-883. b. t a = +125 c, minimum. c. test duration: 1,000 hours, except as permitted by method 1005 of mil -std -883.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 33 dscc form 2234 apr 97 4.4.2.2 additional criteria for device classes q and v . the steady -state life test duration , test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's qm plan in accordance with mil -prf -38535. the test circuit shall be maintained under document revision level control by the device manufactu rer's trb in accordance with mil -prf -38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of mil -std -883. 4.4.3 group d inspection . the group d inspection end -point electrical parameters shall be as specified in table iia herein. 4.4.4 group e inspection . group e inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). rha levels for device classes m, q and v shall be as specified in mil-prf-38535. end -point electrical parameters shall be as specified in table iia herein. 4.4.4.1 total dose irradiation testing . total dose irradiation testing shall be performed in accordance with mil-std-883 method 1019 and as specified herein. 4.4.4.1.1 accelerated aging test . accelerated aging tests shall be performed on all devices requiring a rha level greater than 5k rads(si). the post-anneal end-point electrical parameter limits shall be as specified in table ia herein and shall be the pre-irradiation end-point electrical parameter limit at 25 c 5 c. testing shall be performed at initial qualification and after any design or process changes which may affect the rha response of the device. 4.4.4.2 neutron testing . neutron testing shall be performed in accordance with test method 1017 of mil -std -883 and herein (see 1.4). all device classes must meet the post irradiation end -point electrical parameter limits as defined in table ia, for the subgroups specified in table iia herein at t a = +25 c 5 c after an exposure of 2 x 10 12 neutron/cm 2 (minimum). 4.4.4.3 dose rate induced latchup testing . dose rate induced latchup testing shall be performed in accordance with test method 1020 of mil-std-883 and as specified herein (see 1.4). tests shall be performed on devices, sec, or approved test structures at technology qualification and after any design or process changes which may effect the rha capability of the process. 4.4.4.4 dose rate upset testing . dose rate upset testing shall be performed in accordance with test method 1021 of mil -std -883 and herein (see 1.4). a. transient dose rate upset testing shall be per formed at initial qualification and after any design or process changes which may effect the rha performance of the devices. test 10 devices with 0 defects unless otherwise specified. b. transient dose rate upset testing for class q and v devices shall be performed as specified by a trb approved radiation hardness assurance plan and mil -prf -38535. 4.4.4.5 single event phenomena (sep) . sep testing shall be required on class v devices (see 1.4). sep testing shall be performed on the standard evaluation circuit (sec) or alternate sep test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. the recommended test conditions for sep are as follows: a. the ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive (i.e. 0 angle 60 ). no shadowing of the ion beam due to fixturing or package related effects is allowed. b. the fluence shall be 3 100 errors or 3 10 6 ions/cm 2 . c. the flux shall be between 10 2 and 10 5 ions/cm 2 /s. the cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. the particle range shall be 3 20 microns in silicon. e. the test temperature shall be +25 c and the maximum rated operating temperature 10 c. f. bias conditions shall be defined by the manufacturer for latchup measurements.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 34 dscc form 2234 apr 97 g. test four devices with zero failures . h. for sep test limits, see table ib herein. 5. packaging 5.1 packaging requirements . the requirements for packaging shall be in accordance with mil-prf-38535 for device classes q and v or mil-prf-38535, appendix a for device class m. 6. no tes 6.1 intended use . microcircuits conforming to this drawing are intended for use for government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 replaceability . microcircuits covered by this drawing will replace the same generic device covered by a contractor -prepared specification or drawing. 6.1.2 substitutability . device class q devices will replace device class m devices. 6.2 configuration control of smd's . all proposed changes to existing smd's will be coordinated with the users of record for the individual documents. this coordination will be accomplished using dd form 1692, engineering change proposal. 6.3 record of users . military and industrial users should inform defense supply center columbus when a system application requires configuration control and which smd's are applicable to that system. dscc will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. users of drawings covering microelectronic devices (fsc 5962) should contact dscc-va, telephone (614) 692-0544. 6.4 comments . comments on this drawing should be directed to dscc-va , columbus, ohio 43216-5000, or telephone (614) 692 -0547. 6.5 abbreviations, symbols, and definitions . the abbreviations, symbols, and definitions used herein are defined in mil -prf -38535, mil -hdbk -1331, and table iii herein. 6.6 sources of supply . 6.6.1 sources of supply for device classes q and v . sources of supply for device classes q and v are listed in qml -38535. the vendors listed in qml -38535 have submitted a certificate of compliance (see 3.6 herein) to dscc -va and have agreed to this drawing. 6.6.2 approved sources of supply for device class m . approved sources of supply for class m are listed in mil-hdbk-103. the vendors listed in mil-hdbk-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by dscc -va. 6.7 additional information . a copy of the following additional data shall be maintained and available from the device manufacturer: a. rha upset levels. b. test conditions (sep). c. number of upsets (sep). d. number of transients (sep). e. occurrence of latchup (sep).
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 35 dscc form 2234 apr 97 table iii. pin descriptions . name type 1 / active 2 / description data bus d0 ttb -- bit 0 (lsb) of the bi-directional data bus. d1 ttb -- bit 1 of the bi-directional data bus. d2 ttb -- bit 2 of the bi-directional data bus. d3 ttb -- bit 3 of the bi-directional data bus. d4 ttb -- bit 4 of the bi-directional data bus. d5 ttb -- bit 5 of the bi-directional data bus. d6 ttb -- bit 6 of the bi-directional data bus. d7 ttb -- bit 7 of the bi-directional data bus. d8 ttb -- bit 8 of the bi-directional data bus. d9 ttb -- bit 9 of the bi-directional data bus. d10 ttb -- bit 10 of the bi-directional data bus. d11 ttb -- bit 11 of the bi-directional data bus. d12 ttb -- bit 12 of the bi-directional data bus. d13 ttb -- bit 13 of the bi-directional data bus. d14 ttb -- bit 14 of the bi-directional data bus. d15 ttb -- bit 15 (msb) of the bi-directional data bus. address bus a0 ttb -- bit 0 (lsb) of the bi-directional address bus. a1 ttb -- bit 1 of the bi-directional address bus. a2 ttb -- bit 2 of the bi-directional address bus. a3 ttb -- bit 3 of the bi-directional address bus. a4 ttb -- bit 4 of the bi-directional address bus. a5 tto -- bit 5 of the address bus. a6 tto -- bit 6 of the address bus. a7 tto -- bit 7 of the address bus. a8 tto -- bit 8 of the address bus. a9 tto -- bit 9 of the address bus. a10 tto -- bit 10 of the address bus. a11 tto -- bit 11 of the address bus. a12 tto -- bit 12 of the address bus. a13 tto -- bit 13 of the address bus. a14 tto -- bit 14 of the address bus. a15 tto -- bit 15 (msb) of the address bus. see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 36 dscc form 2234 apr 97 table iii. pin descriptions - continued. name type 1 / active 2 / description remote terminal address inputs rta0 tui -- remote terminal address bit 0. this is bit 0 of the rt address. this is the least significant bit for the rt address. rta1 tui -- remote terminal address bit 1. this is bit 1 of the rt address. rta2 tui -- remote terminal address bit 2. this is bit 2 of the rt address. rta3 tui -- remote terminal address bit 3. this is bit 3 of the rt address. rta4 tui -- remote terminal address bit 4. this is the most significant bit of the rt address. rtpty tui -- remote terminal parity. this is an odd parity input for the rt address. jtag testability pins tdo tto -- tdo. this output performs the operation of test data output as defined in the ieee standard 1149.1. this cell provides the output signal for the test access port (tap). this non-inverting output buffer is optimized for driving ttl loads. tck ti -- tck. this input performs the operation of test clock input as defined in the ieee standard 1149.1. this cell provides the input clock for non-inverting input buffer that is optimized for driving ttl input levels. tms tui -- tms. this input performs the operation of test mode select as defined in the ieee standard 1149.1. this cell provides the input signal for the test access port (tap). this non-inverting input buffer is optimized for driving ttl input levels. tdi tui -- tdi. this input performs the operation of test data in as defined in the ieee standard 1149.1. this cell provides the input signal for the test access port (tap). this non- inverting input buffer is optimized for driving ttl input levels. trst tui al trst . this input provides the reset to the tap controller as defined in the ieee standard 1149.1. this non -inverting input buffer is optimized for driving ttl input levels. when not exercising jtag, tie trst to a logical 0. biphase inputs/outputs cha dio -- channel a (true). this is the manchester-encoded true signal for channel a. cha dio -- channel a (complement). this is the manchester-encoded complement signal for channel a. chb dio -- channel b (true). this is the manchester-encoded true signal for channel b. chb dio -- channel b (complement). this is the manchester-encoded complement signal for channel b. dma signals dmar tto 3 / al dma request. this signal is asserted when access to ram is required. it goes inactive upon request of the dmag signal. dmag ti al dma grant. once this input is received, the device is allowed to access ram. dmack tto 3 / al dma acknowledge. this signal is asserted by the device to indicate the receipt of dmag . the signal remains active until all ram bus activity is completed. dtack ti al data transfer acknowledge. this pin indicates that a data transfer is to occur and that the device may complete the memory cycle. see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level b sheet 37 dscc form 2234 apr 97 table iii. pin descriptions - continued. name type 1 / active 2 / description control signals rd/ wr ti -- read/write. this indicates the direction of data flow with respect to the host. a logic high signal means the host is trying to read data from the device, and a logic low signal means the host is trying to write data to the device. cs ti al chip select. this pin selects the device when accessing the internal registers. rrd tto al ram read. this signal is generated by the device to read data from ram. rwr tto al ram write. this signal is generated by the device to write data to ram. rcs tto al ram chip select. this signal is used in conjunction with the rrd / rwr signal to access ram. autoen ti al auto enable. this pin, when active, enables automatic initialization. romen tto 3 / al rom enable. this pin, when active enables the rom for automatic initialization applications. ssysf ti al subsystem fail. upon receipt, this signal propagates directly to the rt 1553 status word. 24 mhz ci -- 24 mhz clock. this 24 mhz input clock requires a 50% 10% duty cycle with an accuracy of 0.01%. mrst tui al master reset. this input pin resets the internal encoders, decoders, all register, and associated logic. msel1 ti -- mode select 1. this pin is the most significant bit for the mode select. for proper mode selection, see below: msel1 msel0 mode of operation 0 0 bus controller = sbc 0 1 remote terminal = srt 1 0 monitor terminal = smt 1 1 smt/srt msel0 ti -- mode select 0. this pin is the least significant bit for the mode select. (see msel1 for proper logic states.) tclk ti -- timer clock. this internal timer is a 16-bit counter with a 64 m s resolution when using the 24 mhz input clock. for different applications, the user may input a clock (0-60 mhz) to establish the timer resolution. (duty cycle = 50% 10%). a/ b std ti -- military standard a or b. this pin defines whether the device will be used a mil -std -1553a or 1553b mode of operation. lock ti al lock. this pin, when set active, prevents software changes to both the rt address, a/ b std, and mode select. see footnotes at end of table.
size a 5962-94663 standard microcircuit drawing defense supply center columbus columbus, ohio 43216 -5000 revision level d sheet 38 dscc for m 2234 apr 97 table iii. pin descriptions - continued. name type 1 / active 2 / description status signals teract to al terminal active. this output pin indicates that the terminal is actively processing a 1553 command. msg_ int tto 3 / al message interrupt. this pin is active for three clock cycles (i. e., 125 ns pulse) upon the occurrence of interrupt events which are enabled. yf_ int tto 3 / al you failed interrupt. this pin is active for three clock cycles (i. e., 125 ns pulse) upon the occurrence of interrupt events which are enabled. ready to al ready. this signal indicates the device has completed initialization or bit, and regular execution may begin. power/ground v dd -- -- +5 volt logic power ( 10%) v cc -- -- device types 01, 03, 04, 06, 07, 09, and 10: +5 volt transceiver power (+10%, -5%). recommended de -coupling capacitors: 4.7 m f and 0.1 m f. device type 02: +5 volt transceiver power ( 5%). device types 05, 08, and 11: +5 volt transceiver power ( 10%). recommended de -coupling capacitors: 4.7 m f and 0.1 m f. v ee -- -- device types 01, 03, 04, 06, 07, 09, and 10 only: -12 or -15 volt transceiver power ( 5%). recommended de -coupling capacitors: 4.7 m f and 0.1 m f. v ss -- -- digital ground. gnd -- -- transceiver ground. 1 / to = ttl output ttb = three-state ttl bi-directional ci = cmos input tui = ttl input (internally pulled high) ti = ttl input tto = thre e-state ttl output dio = differential input/output all pins specified as ttl are actually cmos transistor pairs designed for ttl compatibility. 2 / ah = active high al = active low 3 / high impedance and active low.
standard microcircuit drawing bulletin date: 01-07-27 approved sources of supply for smd 5962-94663 are listed below for immediate acquisition information only and shall be added to mil-hdbk-103 and qml -38535 during the next revision. mil-hdbk-103 and qml -38535 will be revised to include the addition or deletion of sources. the vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by dscc -va. this bulletin is superseded by the next dated revision of mil-hdbk-103 and qml -38 535. standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962-9466301qxa 3 / ut69151lx15/ga 5962-9466301qya 3 / ut69151lx15/wa 5962-9466301qxc 3 / ut69151lx15/gc 5962-9466301qyc 3 / ut69151lx15/wc 5962-9466302qxa 3 / ut69151dx/ga 5962-9466302qya 3 / ut69151dx/wa 5962-9466302qxc 3 / ut69151dx/gc 5962-9466302qyc 3 / ut69151dx/wc 5962-9466303qxa 3 / ut69151lx12/ga 5962-9466303qya 3 / ut69151lx12/wa 5962-9466303qxc 3 / ut69151lx12/gc 5962-9466303qyc 3 / ut69151lx12/wc 5962-9466304qxa 3 / ut69151lx e 15/g q a 5962-9466304qya 3 / ut69151lx e 15/w q a 5962-9466304qxc 3 / ut69151lx e 15/g q c 5962-9466304qyc 3 / ut69151lx e 15/w q c 5962r9466304qxa 3 / ut69151lxe15/g q ar 5962r9466304qya 3 / ut69151lxe15/w q ar 5962r9466304qxc 3 / ut69151lxe15/g q cr 5962r9466304qyc 3 / ut69151lxe15/w q cr 5962r9466304vxa 3 / ut69151lxe15/g v a r 5962r9466304vya 3 / ut69151lxe15/w v a r 5962r9466304vxc 3 / ut69151lxe15/g v c r 5962r9466304vyc 3 / ut69151lxe15/w v c r 5962-9466305qxa 3 / ut69151dx e /g q a 5962-9466305qya 3 / ut69151dxe/ w qa 5962-9466305qxc 3 / ut69151dxe/gq c 5962-9466305qyc 3 / ut69151dxe/wq c see footnotes at end of table.
standard microcircuit drawing bulletin - continued. standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962h9466305qxa 3 / ut69151dxe/g q ah 5962h9466305qya 3 / ut69151dxe/w q ah 5962h9466305qxc 3 / ut69151dxe/g q ch 5962h9466305qyc 3 / ut69151dxe/w q ch 5962h9466305vxa 3 / ut69151dxe/gvah 5962h9466305vya 3 / ut69151dxe/wvah 5962h9466305vxc 3 / ut69151dxe/gvch 5962h9466305vyc 3 / ut69151dxe/wvch 5962-9466306qxa 3 / ut69151lx e 12/g q a 5962-9466306qya 3 / ut69151lx e 12/w q a 5962-9466306qxc 3 / ut69151lxe12/gq c 5962-9466306qyc 3 / ut69151lxe12/wq c 5962-9466307qxa 65342 ut69151lxe15/gqa 5962-9466307qya 65342 ut69151lxe15/wqa 5962-9466307qxc 65342 ut69151lxe15/gqc 5962-9466307qyc 65342 ut69151lxe15/wqc 5962-9466308qxa 65342 ut69151dxe/gqa 5962-9466308qya 65342 ut69151dxe/wqa 5962-9466308qxc 65342 ut69151dxe/gqc 5962-9466308qyc 65342 ut69151dxe/wqc 5962-9466309qxa 65342 ut69151lxe12/gqa 5962-9466309qya 65342 ut69151lxe12/wqa 5962-9466309qxc 65342 ut69151lxe12/gqc 5962-9466309qyc 65342 ut69151lxe12/wqc 5962r9466310qya 65342 ut69151lxe15/wqar 5962r9466310qyc 65342 ut69151lxe15/wqcr 5962r9466310vya 65342 ut69151lxe15/wvar 5962r9466310vyc 65342 ut69151lxe15/wvcr 5962r9466311qya 65342 ut69151dxe/wqar 5962r9466311qyc 65342 ut69151dxe/wqcr 5962r9466311vya 65342 ut69151dxe/wvar 5962r9466311vyc 65342 ut69151dxe/wvcr see footnotes at end of table.
standard microcircuit drawing bulletin - continued. standard microcircuit drawing pin 1 / vendor cage number vendor similar pin 2 / 5962f9466311qya 65342 ut69151dxe/wqaf 5962F9466311QYC 65342 ut69151dxe/wqcf 5962f9466311vya 65342 ut69151dxe/wvaf 5962f9466311vyc 65342 ut69151dxe/wvcf 1 / the lead finish shown for each pin representing a hermetic package is the most readily available from the manufacturer listed for that part. if the desired lead finish is not listed, contact the vendor to determine its availability. 2 / caution . do not use this number for item acquisition. items acquired to this number may not satisfy the performance requirements of this drawing. 3 / no longer available from an approved source of s upply. vendor cage vendor name number and address 65342 aeroflex utmc microelectronics system inc. 4350 centennial boulevard colorado springs, colorado 80907 -3486 the information contained herein is disseminated for convenience only and the government assumes no liability whatsoever for any inaccuracies in the information bulletin.

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