serial input pll with 2.5-ghz prescaler cyw2325 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 february 14, 2000, rev. ** features ? operating voltage 2.7v to 5.5v operating frequency: up to 2.5 ghz with prescaler ratios of 32/33 and 64/65 lock detect feature power-down mode 20-pin tssop (thin shrink small outline package) applications wireless lan wireless communication handsets base stations microcells cyw2325 pll block diagram pin configuration phase detector f in prescaler binary 7-bit (10) 64/65 or 128/129 swallow counter binary 11-bit programmable counter charge pump 18-bit latch 15-bit latch 14-bit reference counter divider output (fr/fp) mux latch selector cntrl 19-bit shift reg osc_in (1) osc_out (3) le (14) data (13) clock (11) f out (17) ld (8) ? p (18) pwdn (19) do (6) fc (15) bisw (16) ? r (20) fr fp v p (4) v cc (5) gnd (7) ? r pwdn ? p f out bisw fc le data nc clock 20 19 18 17 16 15 14 13 12 11 osc_in nc osc_out v p v cc d o gnd ld nc f in 1 2 3 4 5 6 7 8 9 10
cyw2325 2 figure 1. application diagram example - cyw2325 2.5-ghz pll (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (20) (19) (18) (17) (16) (15) (14) (13) (12) (11) osc in nc osc out v p v cc d o gnd ld nc f in ? r pwdn ? p f out bisw fc le data nc clock 1000p crystal 100p 0.1 v p 100p 0.1 v cc v cc 100k ld 33k 0.01 f mmbt200 lock 10k detect vp r5 q1 r4 r6 q2 q4 q3 r7 r8 r9 osc. input vco* from controller c1 r2 c2 r3 c3 100 pf 18 ? 18 ? 18 ? 50 ? v p rf out
cyw2325 3 pin definitions pin name pin no. pin type pin description osc_in 1 i oscillator input: this input has a v cc /2 threshold and cmos logic level sensitivity. nc 2 no connect osc_out 3 o oscillator output v p 4p charge pump rail voltage: this supply for charge pump. must be > v cc . v cc 5p power supply connection for pll: when power is removed from v cc all latched data is lost. d o 6o charge pump output: the phase detector gain is i p /2 . sense polarity can be re- versed by setting fc low (pin 15). gnd 7 g analog and digital ground connection: this pin must be grounded. ld 8 o lock detect pin: this output is high with narrow low pulses when the loop is locked. nc 9 no connect f in 10 i input to prescaler: maximum frequency 2.5 ghz. clock 11 i data clock input: one bit of data is loaded into the shift register on the rising edge of this signal. nc 12 no connect data 13 i serial data input le 14 i load enable: on the rising edge of this signal, the data stored in the shift register is latched into the counters and configuration controls. f c 15 i phase sense control for phase detector with internal pull-up: when pulled low, the polarity of the phase detector is reversed. bisw 16 o analog switch output: connects to output of charge pump when le is high. f out 17 o monitor point for phase detector input ? p 18 o external charge pump output: open drain n-channel fet, pull-up resistor required. pwdn 19 i power down pin with internal pull-up: when pin is high, device is in normal state. when pin is low, device is in power-down mode. when device enters power-down mode the charge pump is in the three-state condition. ? r 20 o external change pump: (cmos logic output).
cyw2325 4 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. handling precautions devices should be transported and stored in antistatic con- tainers. these devices are static sensitive. ensure that equipment and personnel contacting the devices are properly grounded. cover workbenches with grounded conductive mats. always turn off power before adding or removing devices from system. protect leads with a conductive sheet when handling or trans- porting pc boards with devices. if devices are removed from the moisture protective bags for more than 36 hours, they should be baked at 85 c in a mois- ture free environment for 24 hours prior to assembly in less than 24 hours. parameter description rating unit v cc or v p power supply voltage ? 0.5 to +6.5 v v out output voltage ? 0.5 to v cc +0.5 v i out output current 15 ma t l lead temperature +260 c t stg storage temperature ? 55 to +150 c recommended operating conditions parameter description test condition rating unit v cc power supply voltage 2.7 to 5.5 v v p charge pump voltage v cc to +5.5 v t a operating temperature ambient air at 0 cfm flow ? 40 to +85 c
cyw2325 5 note: 1. id o vs t; charge pump current variation vs. temperature. [iid o(si)@t i ? iid o(si)@25 c i]/iid o(si)@25 c i * 100% and [iid o(so)@t i ? iid o(so)@25 c i]/iid o(so)@25 c i *100%. electrical characteristics: v cc = 3.0v, v p = 3.0v, t a = ? 40 c to +85 c, unless otherwise specified parameter description test condition pin min. typ. max. unit i cc power supply current v cc 8ma i pd power-down current power-down, v cc = 3.0v v cc 6 100 a f in maximum operating frequency f in 2.5 ghz f osc oscillator input frequency no load on osc_out osc_in 2 60 mhz with osc_out loaded 2 25 mhz f maximum phase detector frequency 10 mhz pf in input sensitivity v cc = 2.7v f in ? 15 4 dbm v cc = 5.5v ? 10 4 dbm v osc oscillator input sensitivity osc_in 0.5 v p ? p i ih , i il oscillator input current ? 100 100 a v ih high level input voltage v cc = 5.0v data, clock, le v cc * 0.8 v v il low level input voltage v cc * 0.3 v i ih high level input current ? 10 1 10 a i il low level input current ? 10 1 10 a v oh high level output voltage f o /ld 2.2 v v ol low level output voltage 0.4 v id o(so) id o , source current v p = 3.0v, vd o = v p /2 d o ? 3.2 ma v p = 5.0v, vd o = v p /2 ? 3.8 ma id oh(si) id o high, sink current v p = 3.0v, vd o = v p /2 d o 3.2 ma v p = 5.0v, vd o = v p /2 3.8 ma ? id o id o charge pump sink and source mismatch vd o = v p /2 [iid o(si) i ? iid o(so) i]/ [1/2*{iid o(si) ]i+iid o(so) i}]*100% 5% id o vs t charge pump current variation vs. temperature ? 40 c cyw2325 6 timing waveforms phase characteristics phase detector output waveform d o charge pump output current waveform vco input voltage vco output frequency (2) (1) phase comparator sense for normal operation, the fc pin is used to select the output polarity of the phase detector. both the internal and any external charge pump are affected. depending upon vco characteristics, fc pin should be set accordingly: when vco characteristics are like (1), fc should be set high or open circuit: when vco characteristics are like (2), fc should be set low. when fc is set high or open circuit, f out pin is set to the reference divider output, f r . when fc is set low, f out pin is set to the programmable divider output f p . tw tw f r f p ld tw tw f r f p id o three-state d o
cyw2325 7 serial data input data is input serially using the data, clock, and le pins. two control bits direct data into the locations given in table 1 . notes: 2. t1 ? t5 = 50 s > t > 0.5 s. 3. clock may remain high after latching in data. 4. data is shifted in with the msb first. 5. for data definitions, refer to table 2 . 6. the msb is loaded in first. 7. low count ratios may violate frequency limits of the phase detector. serial data input timing waveform [2, 3, 4, 5] timing waveforms (continued) clock // le // // // // // // // t2 t1 t3 t4 t5 data b11 = msb b10 b1 a7 a1 cnt = lsb table 1. control configuration cnt function 1 reference counter: r = 3 to 16383, set prescaler ratio pre =0:64/65, pre=1:32/33 0 program counter: a = 0 to 63, b = 3 to 2047 table 2. shift register configuration [6] 1 2 3 4 5 6 7 8 9 10111213141516171819 reference counter and configuration bits cnt r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 pre programmable counter bits cnt a1 a2 a3 a4 a5 a6 a7 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 bit(s) name function cnt control bit: directs programming data to reference or programmable counters. r1 ? r14 reference counter setting bits: 14 bits, r = 3 to 16383. [7] pre prescaler divide bit: low = 64/65 and high = 32/33. a1 ? a7 swallow counter divide ratio: a = 0 to 63. b1 ? b11 programmable counter divide ratio: b = 3 to 2047. [7]
cyw2325 8 document #: 38-00920 table 3. 7-bit swallow counter (a) truth table [8] divide ratio aa7a6a5a4a3a2a1 0 x000000 1 x000001 ::: x ::: ::: ::: ::: ::: ::: 62 x111110 63 x111111 table 4. 11-bit programmable counter (b) truth table [9] divide ratio bb11b10b9b8b7b6b5b4b3b2b1 3 00000000011 4 00000000100 ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: 2046 1 1 1 11111110 2047 1 1 1 11111111 table 5. 14-bit programmable reference counter truth table [9] divide ratio r r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 3 00000000000011 4 00000000000100 ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: ::: 16382 1 1 1 1 1 1 1 1 1 1 1 1 1 0 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ordering information [10] ordering code package name package type tr cyw2325 zi 20-pin tssop (0.173 ? wide) tape and reel option notes: 8. b is greater than or equal to a. 9. divide ratio less than 3 is prohibited. the divide ratio can be calculated using the following equation: 10. operating temperature range: ? 40 c to +85 c. fvco = {(p * b) + a} * fosc / r where (a < b) fvco: output frequency of the external vco. the divide ratio n = (p * b) + a. r: preset ratio of the 15-bit programmable reference counter (3 to 16383). fosc: the crystal reference oscillator frequency. a: preset divide ratio of the 7-bit swallow counter. b: preset ratio of the 11-bit programmable counter (3 to 2047). p: preset divide ratio of the dual modulus prescaler.
cyw2325 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 20-pin thin shrink small outline package (tssop, 0.173 ? wide) physical dimensions in millimeters 20 lead (0.173" wide) tssop package order number x jedec outline mo-153 20" clear antistatic tubes, 76 units/tube
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