advance data sheet august 1996 4 features n 10 mbit/s ethernet mac designed to operate with industry-standard physical layer transceivers n operation in half- or full-duplex environment n asynchronous reset with no clocks present n interconnection with physical layers that do not produce a continuous rxc n receiver handles seven dribble bits n easy simulation in verilog * or synopsys ? synthesis n compatibility with full internal scan test methodol- ogy * verilog is a registered trademark of cadence design systems, inc. ? synopsys is a registered trademark of synopsys, inc. description the DNCM00 is an 802.3 compliant mac that is designed to interface to industry-standard physical layer transceivers. the DNCM00 operates in a half- or full-duplex envi- ronment. in half duplex, the receiver is not activated if txe is active to avoid buffering one s own transmitted packet. in full-duplex mode, the col input from the physical layer is ignored, and the DNCM00 can transmit and receive data simultaneously. all transmit and receive functions can be asynchro- nously reset with no clocks present. for interconnec- tion with physical layers that do not produce a continuous rxc, the DNCM00 receiver completes a packet reception with as few as three rx clocks after crs falls. the receiver will also correctly handle up to seven dribble bits. the DNCM00 is described in fully synthesizable behavioral verilog with 2-state table format state machines for easy simulation in verilog or synopsys synthesis. the DNCM00 has been designed to be used with a full internal scan test methodology. there are test inputs for controllability of all reset signals, and the DNCM00 can be synthesized in the lucent technolo- gies libraries with ?p-?p types that guarantee scan equivalent types if scan is inserted. the DNCM00 is approximately 10k grids in size without scan, and approximately 12k grids in size with scan. all control inputs to the DNCM00 are assumed to be stable levels that remain valid for the duration of a transmitted or received packet. they are not regis- tered or resynchronized to a clock in the DNCM00. DNCM00 10 mbit/s ethernet mac asic macrocell note: advisories are issued as needed to update product information. when using this data sheet for design purposes, please contact your lucent technologies microelectronics group account manager to obtain the latest advisory on this product.
2 lucent technologies inc. DNCM00 advance data sheet 10 mbit/s ethernet mac asic macrocell august 1996 4 signal information table 1. input terminal descriptions input terminal description txc transmit clock. 10 mhz, 50% duty cycle, continuously running. txc clocks all transmitter and timer logic. rst reset (active-high). assumed to be asynchronous. used to reset state machines and critical logic in the transmitter, and state machines in the receiver. col collision detect (active-high). used to indicate a collision between two stations. assumed to be active a minimum of two txc cycles. col is only sampled when appropriate, during half- duplex transmit operations when txe is active, and during the ?st 6.4 m s of intergap time after any (normal or aborted) transmission if isqe is active. mfdup mac full duplex (active-high). used to control half- or full-duplex operation. when mfdup is low, the col input is monitored and the binary backoff algorithm is employed if collisions occur during transmission. when mfdup is low if crs activates while the mac's own packet is being transmitted, the receiver is not enabled since the received packet is the mac's own transmitted packet. when mfdup is high, the col input is ignored during packet transmission and moni- tored during intergap delay for the presence of sqe if the isqe signal is not active. when mfdup is high, all packets are received regardless of the status of txe. retry_1_, retry_0_ retry. used to control the total number of attempts (initial + retries after collision) the mac will make to transmit a packet. the total attempts follow the below table: retry_1_ retry_0_ attempts 0 0 16 0 1 8 1 0 4 1 1 1 bsel backoff select (active-high). used to control whether the binary backoff algorithm is used dur- ing collision handling. if bsel is high, the backoff algorithm is not used. the transmitter will jam for 32 txc cycles and attempt to retransmit after 9.6 m s of intergap time. if low, the transmitter follows the normal binary backoff algorithm following a collision. pream_1_, pream_0_ preamble control. used to control the length of the preamble sequence preceding packet trans- mission. the total bit count in the preamble (10101010... + 10101011) follows the below table: pream_1_ pream_0_ length 0 0 64 bits 0 1 56 bits 1 0 48 bits 1 1 40 bits isqe ignore sqe (active-high). used to ignore the sqe signal from the physical layer transceiver during the ?st 6.4 m s of interframe gap. if high, the sqe error ?g will not set. defer abort after max deferral (active-high). used to force the transmitter to abort a transmission attempt if it has deferred for more than 24,288 txc cycles. deferring starts when the transmitter is ready to transmit but is prevented from doing so because crs is active. defer time is not cumulative. if the transmitter defers for 10,000 bit times, then transmits and collides, backs off, and then has to defer again after completion of backoff, the deferral timer resets to 0 and restarts. if defer is low, the transmitter will defer inde?itely. txreq transmit request (active-high). used to request a packet transmission. txreq is a hand- shake signal; it should be held high until txack is activated by the transmitter. txreq should then not be reactivated until txeop is returned by the transmitter.
advance data sheet DNCM00 august 1996 10 mbit/s ethernet mac asic macrocell lucent technologies inc. 3 4 txeod transmit end of data (active-high). used to end a transmit operation normally. txeod should activate one clock after the dma receives a txld from the transmitter. the transmitter will load and transmit that byte, and then transmit (inverted) crc data according to the status of apnd- crc and invcrc. abort abort transmit (active-high). used to stop a transmission ungracefully. the transmitter will immediately terminate a transmission if this input is set. abort should be held high for two or more txc cycles. when a packet is aborted during preamble, the preamble is completed and the apndcrc and invcrc inputs are followed. if abort is activated during transmission, trans- mission immediately stops, and the apndcrc and invcrc inputs are followed. apndcrc append crc (active-high). used to control if a 32-bit crc polynomial is appended to the end of a transmitted packet. if high, the crc is appended. invcrc invert crc (active-high). used to invert the polarity of the 32-bit crc polynomial. the normal crc is inverted prior to transmission. if invcrc is high, the normal crc will be reinverted prior to sending, forcing a crc error. tstmode test mode (active-high). used to modify the terminal count of transmit counters to speed up testing. when tstmode is high, the counters are modi?d as follows: counter normal count modi?d count 9.6 m s intergap 96 25 51.2 m s timer 512 8 defer timer 24288 242 txdb_[7:0]_ transmit data byte. transmit data. txdb is loaded into the transmit shift register in the falling edge of the txld input and is transmitted lsb ?st onto the medium. rxc receive clock. 10 mhz receive clock recovered from the receive data stream. rxc is assumed not to be present when the medium is inactive. it is assumed that rxc will be delayed by up to 5 data bit times after crs activates. rxc must be generated for 5 bit times after crs goes low to guarantee proper receiver operation. if rxc is delayed after crs activates, it will cause inac- curacies in some of the rx statistics (short). rxd receive data. rxd is strobed on the rising edge of rxc when crs is active to assemble receive data bytes. signal information (continued) table 1. input terminal descriptions (continued) input terminal description
4 lucent technologies inc. DNCM00 advance data sheet 10 mbit/s ethernet mac asic macrocell august 1996 4 signal information (continued) table 2. output terminal descriptions output terminal description txack transmit acknowledge (active-high) (posedge txc). used in conjunction with txreq as a handshake. when txack goes high in response to txreq, txreq can be deacti- vated. txinprog transmit in progress (active-high) (posedge txc). set high if the mac is currently transmitting preamble, data, or crc. it is not active if jamming or during collision backoff. txd transmit data (posedge txc). serial transmit data out. txld transmit load (active-high) (posedge txc). used to tell the dmac that the transmitter requires a byte of data for transmission. txdb_[7:0]_ will be strobed into the transmit shift register on the falling edge of txld. txeop transmit end of operation (active-high) (posedge txc). used to indicate the end of a transmit operation. the operation may end because of successful transmission, excessive collisions, excess deferral, or an abort command. txeop is active for one txc cycle. transmit statistics, except for sqe, can be monitored after txeop activates. sqe should be latched on the falling edge of txsop of the following frame. late late collision (active-high) (posedge txc). indicates that a collision occurred more than 512 bit times from the start of a transmission. the start of transmission is de?ed as the transmission of the ?st bit of preamble. exdef excess deferral (active-high) (posedge txc). indicates transmission ended because of waiting for more than 24,288 bit times for the medium to become unbusy. def deferred (active-high) (posedge txc). indicates that a transmission deferred for 1 to 24,288 bit times during transmission. coldet collision detected (active-high) (posedge txc). indicates that a collision has been detected. this signal is active from the time a collision was detected until the completion of the 32-bit jam sequence. the col signal is monitored only when the transmitter is actively transmitting data. scol single collision (active-high) (posedge txc). indicates that there was one collision dur- ing transmission of the previous packet. mcol multiple collisions (active-high) (posedge txc). indicates that there was more than one collision during transmission of the previous packet. cerr collision error (active-high) (posedge txc). indicates that the previous transmission was stopped because of excessive collisions as allowed by the retry_[1:0]_ inputs. scol or mcol are also valid if cerr is active. lcrs loss of crs (active-high) (posedge txc). indicates that the crs input was inactive for one or more bit times while the transmitter was active. sqe signal quality error (active-high) (posedge txc). indicates that a col signal was not detected during the ?st 6.4 m s of interframe gap following a transmit attempt. sqe is inac- tive if the isqe input is high. txbyte byte transmitted (active-high) (posedge txc). indicates that a complete byte of data or crc has been transmitted. txbyte is valid for 1 txc bit time immediately after the last bit of a byte was transmitted. txsop transmit start of packet (active-high) (posedge txc). active for 1 bit time at the start of preamble. txe transmit enable (active-high) (posedge txc). indicates that data on the txd line is valid. rxcount_[15:0]_ receive byte count (posedge rxc) . indicates the number of full bytes received in the current packet. this counter freezes at ffff(hex) bytes.
advance data sheet DNCM00 august 1996 10 mbit/s ethernet mac asic macrocell lucent technologies inc. 5 4 rxbyte_[7:0]_ receive byte (posedge rxc) . an 8-bit latch which holds a byte of receive data. rxsop receive start of packet (active-high) (posedge rxc) . indicates that the receiver has detected that crs is high and that rxc is being generated. receive statistics are reset on the falling edge of rxsop. rxsfd start-of-frame detect (active-high) (posedge rxc) . indicates that a start-of-frame delimiter has been detected in a received packet (10101011). rxeop receive end of packet (active-high) (posedge rxc) . indicates that crs has gone inac- tive and that receive statistics are valid for reading. rxbvld rx byte valid (active-high) (posedge rxc) . active for 1 bit time after a new receive byte has been loaded into the rxbyte_[7:0]_ latch. rxjab receiver jabber (active-high) (posedge rxc) . indicates that receive packet length was greater than 1518 bytes and that the packet had a bad crc or a fae. fae frame alignment error (active-high) (posedge rxc) . indicates a packet was received with a bit count with a mod 8 remainder other than 0 and that the packet had an incorrect crc. crc crc error (active-high) (posedge rxc) . indicates a packet was received with a bit count with a mod 8 remainder equal to 0 and that the packet had an incorrect crc. runt runt packet (active-high) (posedge rxc) . indicates a packet was received with a byte count (including crc) < 64 and the packet had a good crc. frag collision fragment (active-high) (posedge rxc) . indicates a packet was received with a byte count (including crc) < 64 and the packet had a bad crc or a fae. long long packet (active-high) (posedge rxc) . indicates that receive packet length was greater than 1518 bytes and the packet had a good crc. phys physical address (active-high) (posedge rxc) . indicates that the ?st bit of the received packet was 0 and that at least 6 bytes of data were received. mult multicast address (active-high) (posedge rxc) . indicates that the ?st bit of the received packet was 1, that all address bits were not 1, and that at least 6 bytes of data were received. brd broadcast address (active-high) (posedge rxc) . indicates that all 36 address bits were 1. short short frame (active-high) (posedge rxc) . indicates a frame was received with less than 80 bits of preamble and data. ifg short interframe gap (active-high) (posedge rxc) . indicates that the interframe gap prior to the start of the packet was less than 9.6 m s. nul null packet (active-high) (posedge rxc) . indicates that crs and rxc were active for some time and that no sfd sequence was detected. table 3. additional scan outputs i/o terminal description test_sei scan data input control (input) (active-high). used to control data input to scan ?p-?ps. test_si1 scan data input to txc scan chain (input). test_si2 scan data input to rxc scan chain (input). test_so1 scan data output for txc scan chain (output) (posedge txc). test_so2 scan data output for rrxc scan chain (output) (posedge txc). signal information (continued) table 2. output terminal descriptions (continued) output terminal description
6 lucent technologies inc. DNCM00 advance data sheet 10 mbit/s ethernet mac asic macrocell august 1996 4 signal information (continued) netlist inputs: xc, rst, col, mfdup, retry_1_, retry_0_, bsel,pream_1_, pream_0_, isqe, defer, txreq, txeod, abort, apndcrc, invcrc, tstmode, txdb_7_, txdb_6_, txdb_5_, txdb_4_, txdb_3_, txdb_2_, txdb_1_, txdb_0_, rxc, rxd, crs outputs: txack, txinprog, txd, txld, txeop, late, exdef, def, coldet, scol, mcol, cerr, lcrs, sqe, txbyte, txsop, txe, aborted, rxcount_15_, rxcount_14_, rxcount_13_, rxcount_12_, rxcount_11_, rxcount_10_, rxcount_9_, rxcount_8_, rxcount_7_, rxcount_6_, rxcount_5_, rxcount_4_, rxcount_3_, rxcount_2_, rxcount_1_, rxcount_0_, rxbyte_7_, rxbyte_6_, rxbyte_5_, rxbyte_4_, rxbyte_3_, rxbyte_2_, rxbyte_1_, rxbyte_0_, rxsop, rxeop, rxbvld, rxjab, fae, crc, runt, frag, long, phys, rxmult, brd, short, ifg, nul functional description the DNCM00 consists of two main blocks, the trans- mitter and receiver. a brief description of each block follows. transmitter the transmitter in the DNCM00 is made up of a state machine, a preamble-jam counter block, a transmit counters block, a 32-bit crc generator, a 15-bit deferral time-out counter, and a transmit serializer. a transmit operation is initiated by the host activating txreq. when txreq is recognized, the DNCM00 will respond by activating txack. the DNCM00 will hold txack active until txreq is dropped, until the trans- mitter successfully sends the packet, or until transmit is aborted because of excessive collisions, excessive deferral, or a host initiated abort. transmission will begin if the 9.6 m s intergap timer has expired. if the timer has reached 9.6 m s prior to txreq packet, transmission will begin immediately. if txreq is given before 6.4 m s of intergap and the DNCM00 was the last station transmitting, the new packet will begin transmission at 9.6 m s regardless of crs. if the timer is greater than 6.4 m s and crs is high, the transmission will defer until crs deactivates, at which time the 9.6 m s timer will activate and transmission will start after time-out. transmitter operation is controlled by a state machine modelled after the one shown in appendix b of the 1993 version of ieee * 802.3. immediately prior to starting preamble, the DNCM00 will send a 1 txc signal, txsop, to the host. another DNCM00 output txinprog is valid while the DNCM00 is actively transmitting. preamble is programmable by pream[1:0] to be 32, 40, 48 or 56 bits, and an 8-bit sfd (10101011) is appended after preamble. the DNCM00 has no address registers, so source and destination addresses must be included in the byte stream sent by the host. the DNCM00 does not provide automatic frame padding. * ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
advance data sheet DNCM00 august 1996 10 mbit/s ethernet mac asic macrocell lucent technologies inc. 7 4 functional description (continued) transmitter (continued) at the end of preamble the DNCM00 sends a one txc signal, txld, to the host. the DNCM00 strobes in the byte to be transmitted on the falling edge of txld. after the ?st txld, subsequent requests will be sent every eight txc cycles. after the last byte has been sent by the host, the host will signify end of data by activating txeod for one txc. after transmitting the last byte, the DNCM00 will append the crc to the data stream if the crc input to the DNCM00 is high. the crc can also be sent inverted if desired (to force a bad crc) by setting the invcrc input high. after completing trans- mission, the DNCM00 will send a txeop signal to the host. all transmit statistics (scol, mcol, cerr, aborted, exdef, etc.) except sqe can be latched on the falling edge of txeop. during transmission, the DNCM00 will activate txbyte for one txc for each byte it sends. for an n-byte packet, the DNCM00 will send n + 4 txbyte signals if crc was appended. after successful transmission, the DNCM00 will monitor the col input for an sqe test signal if the isqe input is low. col is monitored for the ?st 6.4 m s of intergap time. if sqe test is not observed, the sqe output will be set to 1 and held until the next txsop signal. a control output sqevalid will be valid from 6.4 m s until txsop of the next packet, and sqe is valid when sqevalid is high. if another txreq is sent before 6.4 m s of intergap, the DNCM00 will attempt to transmit the new packet regardless of crs. crs will normally not activate during this time if all stations are observing proper protocol, so this should be an infrequent event. the DNCM00 handles collision situations in accor- dance with 802.3. the retry[1:0] inputs select 1, 4, 8, or 16 attempts to transmit, with 00 giving the standard 16 attempts. the standard backoff algorithm is used. the DNCM00 has a 12-bit pseudorandom shift register counter that free runs. the counter can be frozen for periods of time by driving the modrndm input high. this signal can be a decoded chip enable or some other unique signal to increase the randomness of a group of attmacs. when a collision is sensed, a 32- bit jam pattern (1111) is transmitted. after jam is complete, n bits of the counter (n depends on the colli- sion number) is dumped into a 10-bit counter, which in turn is decremented by the turnover of the 51.2 m s timer. backoff lasts until the 10-bit counter reaches 0. transmission is reattempted if the 9.6 m s timer has expired or is deferred until crs deactivates and the 9.6 m s timer expires. if a deferral lasts longer than 24,288 bit times, the DNCM00 will abort the transmis- sion if the defer input is set high. this also applies to a deferral at the start of a regular transmission. deferral is not cumulative; it restarts from 0 each time a deferral state is entered. if a packet cannot be transmitted after making the selected number of attempts, the transmit is aborted and the cerr output is activated. if a colli- sion occurs during preamble, the preamble-sfd sequence is completed prior to jamming. the coldet output indicates the presence of a colli- sion situation to the host. if a late collision (after 512 bit times, including preamble and sfd) occurs, the late output will be set high. the mac does not abort after a late collision is detected. this must be done by the host. if the DNCM00 detects a collision while transmit- ting, it will always send a jam pattern prior to deacti- vating txe regardless of the status of abort, txeod, or the status of the collision counter. the host should always reset its transmit stack if the coldet output goes high to ensure complete packet transmission. the bsel input can be used to override the backoff timer if desired. if bsel is 1 and a collision is detected, the DNCM00 will jam and retransmit when the 9.6 m s igt has expired. if the mfdup is high (full-duplex mode), the DNCM00 ignores the collision signal.
DNCM00 advance data sheet 10 mbit/s ethernet mac asic macrocell august 1996 for additional information, contact your microelectronics group account manager or the following: u.s.a.: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 14 science park drive, #03-02a/04 the maxwell, singapore 0511 tel. (65) 778 8833 , fax (65) 777 7495 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 for data requests in europe: microelectronics group dataline: tel. (44) 1734 324 299 , fax (44) 1734 328 148 for technical inquiries in europe: central europe: (49) 89 95086 0 (munich), northern europe: (44) 1344 865 900 (bracknell uk), france: (33) 1 47 67 47 67 (paris), southern europe: (39) 2 6601 1800 (milan) or (34) 1 807 1700 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a trademark of lucent technologies inc. copyright ?1996 lucent technologies inc. all rights reserved printed in u.s.a. august 1996 ds95-217asic printed on recycled paper 4 functional description (continued) receiver the DNCM00 receiver consists of a state machine, crc generator, 64 kbyte counter, and deserializer. when the DNCM00 detects a low-to-high transition of crs and rxc is operating, it will send an rxsop signal to the host. the ?st 10 bits of preamble sensed are ignored. after the ?st 10 bits of preamble, a sfd sequence (10101011) will cause an rxsfd signal to be sent. after rxsfd, the receiver will buffer each byte of received data. after assembling the byte, a 1 rxc rxbvld signal will be sent to the host. the host has eight rxc times to read the byte from the rxbyte register. when crs falls, the receiver monitors the result of crc calculated on the last full byte. if crs falls on a byte boundary, the packet is either good or a crc error. if crs falls on a nonbyte boundary, but the last full byte received had a good crc, its a good packet with dribble bits. if crs falls on a nonbyte boundary and the last full byte crc was bad, it is a frame alignment error. the receiver will inform the host of the end of packet by activating the rxeop output for one rxc. other receive statistics include rxjab (packet with >1518 bytes and a crc or fae), long (>1518 bytes with good crc), nul (crs high for inde?ite time with no sfd), and others that are described in the terminal descriptions list. receive statistics are valid from rxeop to the next rxsop. if the mfdup input is low (half duplex), the receiver will ignore any packets that start while txe is high to avoid buffering ones own transmitted packet. in order to prevent glitches on crs during a collision situation from affecting the receiver, the receiver will ignore high- to-low transitions of crs if a packet reception is in progress and the col signal is present. if mfdup is high (full duplex), the receiver will ignore the col signal. the DNCM00 does not have any physical address registers or multicast address registers, nor does it have any multicast address group detection logic. it does have three outputs, phys, rxmult and brd, one of which will activate after 6 bytes of data have been received. phys means the ?st bit of data in the packet was 0; rxmult means the ?st bit was 1, and at least 1 of the next 47 was 0; and brd is a 48-bit address of all 1s. general information the DNCM00 is approximately 4100 gates without scan logic. it exists as a fully synthesizable verilog hdl behavioral/state table description and can be easily modi?d for speci? customer requirements.
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