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quad isdn 2b1q echocanceller digital front end dfe-q v2.1 pef 24911 version 2.1 ds 6, 2000-12-01 delta sheet pef 24911 revision history: 2000-12-01 ds 6 previous version: 09.00 ds 5 major changes since last revision: mto function removed state diagram updated previous version: 06.00 ds 4 major changes since revision 05.99: typical values of power consumption added delay for recognition of c/i code changed 2nd time mon 8 messages in state ?reset? delta sheet 2000-12-01 this delta sheet lists the add-on features and differences between the dfe-q v2.1 and the dfe-q v1.3. 1 power supply the dfe-q v2.1 requires a +3.3 v 0.3 v power supply. the inputs and outputs remain 5 v ttl compatible. all measurements of the power consumption are performed with random 2b+d data in active states, 3.3 v (0 c - 70 c) table 1 power consumption mode typ. values max. values unit test conditions power-up all channels 85 100 ma 3.3 v, open outputs, inputs at v dd / v ss power-down 35 t.b.d. ma 3.3 v, open outputs, inputs at v dd / v ss
pef 24911 pinning delta sheet 2 2000-12-01 2 pinning table 2 lists the changes that were made concerning the pinning, table 3 specifies new pin functions that were introduced with version 2.1. table 2 pinning changes pin no. v2.1 v1.3 comment 32 pup n.c. additional push-pull mode for pin dout eases interface adaptation 36 n.c. dsync obsolete 55 slot0 slot renamed 45 slot1 n.c. increased max data rate (4 mbit/s) requires an additional slot pin 53 lt lt dedicated lt mode pin is obsolete 56 ssp tsp dedicated pin for ? send single pulses ? test mode 58 pbx pbx function removed 62 dt tp dedicated pin for ? data through ? test mode 63 trst tp1 bscan power-on-reset is replaced by a dedicated reset line
pef 24911 pinning delta sheet 3 2000-12-01 table 3 pin definitions and functions pin no. symbol input (i) output (o) function 32 pup i (pd) push pull mode in push pull mode ? 0 ? and ? 1 ? is actively driven during an occupied time-slot, outside the active time-slots dout is high impedance (tristate) ? 1 ? = configures dout as push/pull output ? 0 ? = configures dout as open drain output 55 slot0 i iom ? -2 channel slot selection 0 assigns iom ? -2 channels in blocks of 4 slot1, 0: ? 00 ? = iom ? -2 channels 0 to 3 ? 01 ? = iom ? -2 channels 4 to 7 ? 10 ? = iom ? -2 channels 8 to 11 ? 11 ? = iom ? -2 channels 12 to 15 45 slot1 i (pd) iom ? -2 channel slot selection 1 assigns iom ? -2 channels in blocks of 4 53 lt i reserved, clamp to one 56 ssp i send single pulses (ssp) test mode enables/disables ssp test mode ? 1 ? = ssp test mode enabled, alternating +/-3 pulses are issued at the four line ports in 1.5 ms intervals ? 0 ? = ssp test mode disabled 58 pbx i reserved, clamp to zero
pef 24911 pinning delta sheet 4 2000-12-01 pu:pull up pd:pull down 62 dt i data through (dt) test mode enables/disables dt test mode ? 1 ? = dt test mode enabled, the u-transceiver is forced on all line ports to enter the ? transparent ? state ? 0 ? = dt test mode disabled 63 trst i (pu) jtag boundary scan disable resets the tap controller state machine (asynchronous reset), internal pullup ? 1 ? = reset inactive ? 0 ? = reset active table 3 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function
pef 24911 max. data rate on iom?-2 doubled delta sheet 5 2000-12-01 figure 1 pin diagram of the dfe-q v2.1 3 max. data rate on iom ? -2 doubled with version 2.1 the maximum data rate on iom ? -2 is doubled from 2 mbit/s to 4mbit/s. the 4mbit/s mode corresponds to a dcl frequency of 8192 khz. trst dt cls3 res auto ssp slot0 vdd lt cls2 d3d d2d crcon vss tck p-mqfp-64 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 13 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 tms tdi tdo cl15 sdr vdd pdm3 pdm2 vss pdm1 pdm0 dcl fsc din dout tpd 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 d2a d3a d0b n.c. d1b vdd d2b d3b vss d0c slot1 d3c d0d d1d 44 d1c d2c pup 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 cls1 st21 vss st01 d1a d0a cls0 st00 st10 st11 st30 st31 sdx st20 vdd pbx pinning.emf
pef 24911 mon-12 protocol delta sheet 6 2000-12-01 4 mon-12 protocol mon-12 commands feature via the iom ? -2 monitor channel direct access to the device internal register map. the mon-12 protocol works in the manner of a serial microprocessor interface. new functions such as digital local loopbacks, ber measurement etc. are only accessible via mon-12 commands. functions that were so far provided via mon-8 commands, e.g. febe/nebe counter status retrieval, can be accessed as well via the mon-12 protocol. for a detailed description of the register set please refer to the data sheet of the dfe-q v2.1 5 bit error rate measurement for bit error rate monitoring the dfe-q v2.1 features an 16-bit bit error rate counter (berc) per line. as soon as the ber function is enabled zeros are sent in the selected channels and incoming ones are counted until the ber function has been disabled again by the user. 6 advanced filter options for mon-0 and mon-2 messages additionally to the existing mode pins, auto and crcon, the internal mfilt register provides a wide range of filter options for the passing on of mon-0 and mon-2 messages. the new mon-12 protocol gives access to the mfilt register. the following options are provided, ? mon-0: transparent, on change, tll in transparent mode tll (triple-last-look) in automode ? mon-2: on change, tll, crc, crc & tll vs. iom ? -2 on change, tll, crc, crc & tll vs. state machine 7 digital local loops besides the remote loopback stimulation and the local analog loopback (c/i= arl) the dfe-q v2.1 features digital local loopbacks via its internal register set. the local loopbacks that are additionally provided by the loop register are shown in figure 2 . the local loops can be activated at any time independent of the current activation status using the mon-12 protocol.
pef 24911 digital local loops delta sheet 7 2000-12-01 figure 2 loopbacks featured by register loop iom ? -2 dfe-q v2.1 loop.lb1=1 or loop.lb2=1 or loop.lbbd= 1 & loop.u/iom= 1 loop.lb1=1 or loop.lb2=1 or loop.lbbd= 1 & loop.u/iom= 0 iom ? -2 dfe-q v2.1 loop.dlb= 1 dsp a g c eq u a l iz e r pdm filter + activation/deactivation controller u protocol processing unit siu de - scram ble r u de - fr am ing 2b1q decoder system interface un it ech o canceller timing re covery scram ble r u fr am in g 2b1q en c o d e r dsp a g c equalizer pdm filter + activation/deactivation controller u protocol processing unit siu de - scram ble r u de - fr am ing 2b1q decoder system inte rface unit timing re cove ry scram ble r u fr am in g 2b1q en c o d e r ech o canceller loopreg.emf
pef 24911 d-channel arbitration delta sheet 8 2000-12-01 8 d-channel arbitration d-channel arbitration is not supported by version 2.1. 9 c/i code ? ltd ? omitted the c/i command ? ltd ? is no more supported, since the ltd function corresponds to that of c/i ? res ? . upon c/i ? res ? the dfe-q v2.1 stops transmitting signals on u and ignores wake-up signals. on contrast to the dfe-q v1.x the relay driver and status pins are not affected by the software reset c/i ? res ? in version 2.1. the relay driver and status pins are only reset by a hardware reset. 10 state machine some minor changes were made regarding the state machine. the improvements are summarized and listed in table 4 . see also the state diagrams in figure 3 (v2.1) and figure 4 (v1.3).
pef 24911 state machine delta sheet 9 2000-12-01 figure 3 state diagram of v2.1 lt_sm_2b1q_cust.emf sl0 deactivated di sl0 reset for loop di sl1 ec-training ar sl2 sl2 ec-converged eq-training arm a=0,d=1 a=0,d=1 . . . tl alerting di . di sl0 wait for tn . sl0 awake ar . a=0,d=1 sl3t loss of synchr. rsy sl0 reset deac . ar awake error sl0 . dr t1s, t2s t1s, t5s t1s t4s, a=0,d=1 a=0,d=1 line active s/t deactivated uai/fj sl3t** ) ar/fj uai/fj sl3t a=1,d=1 pend.transparent uai, fj sl3t a=1,d=1 ai/fj ei2/fj transparent any state pin-dt or dt arl t2s t9s, t4s sec or t6e or arl lsec or t5e t2e t3s res1 t4s , t1s t1e (t9e & lsec) or t4e dr or lof or lsue dr or lof or lsue t8s ar0 act=0 sai=1 act =1 & /ar0 tn lsec or t4e t1s, t2s t5s dr or lof or lsue t8e sai=0 & act=0 lof dr t10s lsue res1 res1 t7s t7s t7e t10e lsu sp/sl0 test deac . pin-res or c/i= ? res ? pin-ssp or c/i= ? ssp ? ( ar or ar0 or arx or uar ) & /tn res1 dr t3e t6s act=1 sai=0 uar ar0 tn lsu sl3t sl0 tear down error rsy . a=0,d=1 sl0 sl3t loss of signal receive reset lsl lsl . a=0,d=0 sl0 sl3t tear down pend. deactivation deac deac . sl0 alerting_error . ei3 res1 t2e t2s when state line active is entered the first time at startup the 2b+d data must be clamped to ? 0 ? , until act= ? 1 ? has been received from the nt **) tn & ( ar or ar0 or arx or uar or dc) dr or lof or lsue (/t1e or arx) & sfd & (bbd0 or bbd1 or crcok) arm ei 3 t1e t2s res1
pef 24911 state machine delta sheet 10 2000-12-01 figure 4 state diagram of v1.3 deac ltd
pef 24911 ritl/wll functions delta sheet 11 2000-12-01 11 ritl/wll functions ritl/wll functions are not supported by the dfe-q version 2.1. 12 retrieving coefficients mon-8 commands with bit r=1, that were defined for former versions, are no more supported. table 4 differences to lt-sm of dfe-q v1.3 no. v1.3 state/ signal change in v2.1 comment 1. ? test ? state split into two states - reset state - test state defined reset and test states 2. state ? alerting error ? introduced for a clear separation of the normal operation state from the error condition state (which will result in a deactivation) 3. state ? transparent ? c/i code output in state ? transparent ? dependent on received act bit 4. state ? s/t deactivated ? c/i code output in state ? s/t deactivated ? dependent on sai bit status 5. c/i code ltd c/i code ? ltd ? is omitted function corresponds to that of c/i ? res ? 6. c/i code int c/i code ? int ? is not supported int was listed in former documents of v1.x due to an editorial fault
pef 24911 boundary scan instruction set delta sheet 12 2000-12-01 13 boundary scan instruction set the boundary-scan instructions ? clamp ? and ? highz ? are introduced in version 2.1. the instruction ? ssp ? and ? dt ? are omitted since these test functions can be triggered either by the pins ssp and dt or - channel selective - by the c/i codes ssp and dt. clamp allows the state of the signals included in the boundary scan driven from the peb 24911 to be determined from the boundary scan register while the bypass register is selected as the serial path between tdi and tdo. these output signals driven from the dfe-q v2.1 will not change while clamp is selected. highz sets all output pins included to the boundary scan path into a high impedance state. in this state, an in-circuit test system may drive signals onto the connections normally driven by the dfe-q v2.1 outputs without incurring the risk of damage to the dfe-q v2.1. table 5 tap controller instructions 14 version update of the boundary scan idcode register code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code 0100 clamp reading outputs 0101 highz z-state of all boundary scan output pins 1111 bypass bypass operation version device code manufacturer code output 0001 0000 0000 0111 0010 0000 1000 001 1 --> tdo
pef 24911 mon-8 aid version identification delta sheet 13 2000-12-01 15 mon-8 aid version identification on receiving the mon-8 command rid the dfe-q responds with the monitor message aid coded 8006 h . this code is unique for version 2.1 with respect to other dfe-q versions 16 recognition delay of c/i code changes the dfe-q v2.1 has implemented a new architecture for low power consumption. furthermore it is developed for complete compatibility in monitor and c/i messages. the new architecture , however, leads to changes in response times compared to former versions, that could affect the compatibility to software with rigid time-out settings. the evaluation of changes of the incoming c/i-code takes longer than in former versions of the peb 24911: recognition of changes to unconditional commands (i.e.: to res, ssp, and dt) takes up to 2,5 msec instead of 0.25 msec in former versions in the c/i channel in states ? test ? and ? reset ? recognition of changes can also take up to 2,5 msec instead of 0.25 msec in former versions in states other than ? reset ? or ? test ? recognition of changes to all other conditional commands takes up to 0,5 ms instead of 0.25 msec in former versions the c/i codes shall be repeated at least the times above, before the c/i code may be changed. surveillance timers have to be set to values beyond the named times. 17 mon-8 messages in state ? reset ? the issuing of mon-8 messages has been improved in state ? reset ? if the state ? reset ? is entered due to a hardware reset (pin res =0) the device will issue a mon-8 message ast afterwards if one of the pins stxy is high to communicate this status to the system software. the usage of mon-8 commands is not blocked during a software reset, i.e. the c/i- command res is applied. even while the sw-reset is activated, the relay driver pins can be programmed by the mon-8 message setd, and the status pins can be read with rst messages or will autonomously communicate changes of the status. the device will also answer on a rid-command with a aid-message. 18 c/i-channel indication in hardware reset as long as pin res is low, the issued c/i-code is di (1111 b ) instead of deac (0001 b ) for all channels. after putting res to high the c/i-codes change to deac.

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