? semiconductor components industries, llc, 2003 january, 2003 - rev. 0 1 publication order number: nth4301/d nth4302 product preview hd3e quad n-channel the nth4302 is the first integrated quad fet in a single package. it is the integration of 4 planar tmos devices. it uses the latest hd3e tmos technology from on semiconductor, with very high cell density and improved switching capability the nth4302 is a 16-pin leadless device packaged in the new pinpak from on semiconductor. the pinpak is a new flexible power package that uses the map process. the nth4302 uses the same mosfet as the ntd60n02r. however, with the pinpak package, various other pairs of mosfets can be used to create additional custom applications. features ? ultra low r ds (on) provides higher efficiency ? very fast switching due to planar technology and leadless package ? 200% footprint reduction compared to similar dpak solution for the same power ? up to 80 amp per fet ? very low v f (0.8 mv) ideal for synchronous rectification ? specifically designed for dc-dc buck converter in vrm9.1 application (80 amp per phase, 500 khz) application ? dc-dc converter ? motherboard/server buck converter ? telecom/industrial power supply ? automotive motor drive ? h-bridge application note and8086/d, board mounting notes for quad flat-pack no-lead package (qfn)o, is available on our web site www.onsemi.com. this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. quad tmos power mosfet 40 amperes 24 volts r ds(on) = 7.5 m c iss = 2050 pf r jc = 1.3 c/w pinout diagram http://onsemi.com device package shipping ordering information nth4301 onipak tbd case tbd pinpak tbd tbd xx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week marking diagram
nth4302 http://onsemi.com 2 g1 d1 s1 v cc g3 d3 s3 m g2 d2 s2 v ccc g4 d4 s4 g1 d1 s1 v ccc d2 d2 s2 out figure 1. maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain-to-source voltage v dss 24 vdc drain-to-gate voltage v dgr 24 vdc gate-to-source voltage v gs 20 vdc operating and storage temperature t j and t stg -55 to 150 c single pulse drain-to-source avalanche energy - starting t j = 25 c (note 1) (v dd = 25 v dc , v gs = 5 v dc , l = 0.1 mh, i l (pk) = 20 a, r g = 1 k ) e as 450 mj drain current - continuous @ t a = 25 c - continuous @ t a = 70 c - single pulse (t p 10 s) i d i d i dm 30 tbd tbd a dc total power dissipation, t 10 seconds linear derating factor p d @ t a = 25 c tbd w mw/ c thermal resistance - junction-to-case - junction-to-ambient - junction-to-ambient (note 1) r q jc r q ja r q ja 1.5 30 tbd c/w 1. when surface mounted to an fr4 board using 1 pad size, (cu area 1.127 in 2 ).
nth4302 http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain-to-source breakdown voltage (v gs = 0 vdc, i d = 250 a) positive temperature coefficient v (br)dss 24 - - 25 - - vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 30 vdc, t j = 25 c) (v gs = 0 vdc, v ds = 30 vdc, t j = 125 c) i dss - - - - 1.0 10 adc gate-body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss - - 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = 250 adc) negative threshold temperature coefficient v gs(th) 1.0 - 1.9 -3.8 3.0 - vdc static drain-to-source on-resistance (v gs = 10 vdc, i d = 20 adc) (v gs = 10 vdc, i d = 10 adc) (v gs = 4.5 vdc, i d = 5.0 adc) r ds(on) - - - 0.0078 0.0078 0.010 0.010 0.010 0.013 forward transconductance (v ds = 15 vdc, i d = 10 adc) g fs - 20 - mhos dynamic characteristics input capacitance (v 24 vd v 0vd c iss - 2050 2400 pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss - 640 800 reverse transfer capacitance f = 1 . 0 mhz) c rss - 225 310 switching characteristics (note 2) turn-on delay time t d(on) - 11 20 ns rise time ( v dd = 25 vdc, i d = 1.0 vdc, t r - 15 25 turn-of f delay time (v dd = 25 vdc , i d = 1 . 0 vdc , v gs = 10 adc, r g = 6.0 ) t d(off) - 85 130 fall time t f - 55 90 turn-on delay time t d(on) - 11 20 ns rise time (v dd = 25 vdc, i d = 1.0 vdc, t r - 13 20 turn-of f delay time (v dd = 25 vdc , i d = 1 . 0 vdc , v gs = 10 adc, r g = 2.5 ) t d(off) - 55 90 fall time t f - 40 75 turn-on delay time t d(on) - 15 - ns rise time (v dd = 24 vdc, i d = 20 vdc, t r - 25 - turn-of f delay time (v dd = 24 vdc , i d = 20 vdc , v gs = 10 adc, r g = 2.5 ) t d(off) - 40 - fall time t f - 58 - gate charge (v 24 vd i 20ad q t - 55 80 nc g (v ds = 24 vdc, i d = 2.0 adc, v gs = 10 vdc ) q gs (q1) - 5.5 - v gs = 10 vdc) q gd (q2) - 15 - body-drain diode ratings (note 3) diode forward on-voltage (i 23ad v 0vd ) v sd 075 10 vdc ode o a d o o age (i s = 2.3 adc, v gs = 0 vdc) (i s = 20 adc, v gs = 0 vdc) sd - - 0.75 0.90 1.0 - dc (i s = 20 adc , v gs = 0 vdc) (i s = 2.3 adc, v gs = 0 vdc, t j = 125 c) - - 0 . 90 0.65 - - reverse recovery time (i 23ad v 0vd t rr - 30 65 ns y (i s = 2.3 adc, v gs = 0 vdc, di s /dt = 100 a/ s ) t a - 20 - di s /dt = 100 a/ s) t b - 19 - reverse recovery stored charge q rr - 0.043 - c 2. switching characteristics are independent of operating junction temperature. 3. indicates pulse test: pulse width 300 sec max, duty cycle 2%.
nth4302 http://onsemi.com 4 0 20 40 60 80 100 120 0246810 v ds , drain-to-source voltage (v) figure 2. on-region characteristics i d , drain current (a) 0.004 0.008 0.012 0.016 0.02 0.024 0.028 10 20 30 40 50 60 70 80 90 100 110 120 r ds(on) , drain-to-source resistance ( ) figure 3. transfer characteristics figure 4. on-resistance versus drain current and temperature i d , drain current (a) v ds , drain-to-source voltage (v) i d , drain current (a) t j = 150 c t j = 125 c t j = 25 c t j = -55 c v gs = 10 v 0.004 0.008 0.012 0.016 0.02 0.024 0.028 10 20 30 40 50 60 70 80 90 100 110 120 t j = 25 c t j = -55 c t j = 150 c t j = 125 c v gs = 4.5 v figure 5. on-resistance versus drain current and temperature i d , drain current (a) r ds(on) , drain-to-source resistance ( ) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 150 figure 6. on-resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain-to-source resistance (normalized) 10 100 1000 10000 0 5 10 15 20 2 5 figure 7. drain-to-source leakage current versus voltage v ds , drain-to-source voltage (v) i dss , leakage (na) t j = 100 c t j = 150 c t j = 125 c 0 20 40 60 80 100 120 0123 5 6 t j = -55 c t j = 25 c t j = 150 c v gs = 4.5 v v gs = 10 v v gs = 4.0 v v gs = 6.0 v v gs = 5.5 v v gs = 8.0 v v gs = 5.0 v v gs = 3.5 v v gs = 3.0 v v gs = 2.5 v v ds 10 v i d = 30 a v gs = 4.5 v and 10 v
nth4302 http://onsemi.com 5 0 400 800 1200 1600 2000 -10 -5 0 5 10 15 20 gate-t o-source or drain-to-source voltage (v) figure 8. capacitance variation c, capacitance (pf) t j = 25 c v gs = 0 v c iss c oss c rss c iss v ds = 0 v c rss v gs v ds 0 2 4 6 8 10 0 4 8 12 16 q g , total gate charge (nc) figure 9. gate-to-source and drain-to-source voltage versus total charge q 1 q 2 q t v gs i d = 30 a t j = 25 c 1 10 100 1000 1 10 100 r g , gate resistance ( ) figure 10. resistive switching time variation versus gate resistance t, time (ns) v ds = 10 v i d = 30 a v gs = 10 v 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 figure 11. diode forward voltage versus current v sd , source-to-drain voltage (v) i s , source current (a) t j = 25 c t j = 150 c t r t d(off) t f t d(on) v gs , gate-t o-source (v)
nth4302 http://onsemi.com 6 package dimensions pinpak case tbd issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provide d in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, i ncluding typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent ri ghts nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemn ify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employe r. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nth4301/d pinpak is a registered trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
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