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rts-1 UTI760A rts remote terminal for stores f eatures p complete mil-std-1760a notice i through iii remote terminal interface p 1k x 16 of on-chip static ram for message data, completely accessible to host p self-test capability, including continuous loop-back compare p programmable memory mapping via pointers for ef?cient use of internal memory, including buffering multiple messages per subaddress p rt-rt terminal address compare p command word stored with incoming data for enhanced data management p user selectable ram busy (rbusy) signal for slow or fast processor interfacing p full military operating temperature range, -55 c to +125 c, screened to the speci?c test methods listed in table i of mil-std-883, method 5004, class b, also standard military drawing available p available in 68-pin pingrid array package i ntroduction the ut1760a rts is a monolithic cmos vlsi solution to the requirements of the dual-redundant mil-std-1553b interface as speci?ed by mil-std-1760a. designed to reduce cost and space in the mission stores interface, the rts integrates the remote terminal logic with a user- con?gured 1k x 16 static ram. in addition, the rts has a ?exible subsystem interface to permit use with most processors or controllers. the rts provides all protocol, data handling, error checking, and memory control functions, as well as comprehensive self-test capabilities. the rtss memory meets all of a mission stores message storage needs through user-de?ned memory mapping. this memory-mapped architecture allows multiple message buffering at decoder command recognition decoder encoder mux out out in in mcsa(4:0) rta(4:0) remote terminal address mode code/ subaddress control and error logic control inputs status outputs 1k x 16 ram addr(9:0) ptr register data(15:0) 2mhz 12mhz reset clock and reset logic figure 1. ut1760a rts functional block diagram output multiplexing and self-test wraparound logic
rts-2 table of contents 1.0 architecture and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 memory map and host memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 rts ram pointer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 internal register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 mode code and subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 mil-std-1760a subaddress and mode code de?nitions . . . . . . . . . . . . . . . 9 1.6 terminal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.7 internal self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.8 power-up and master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.9 encoder and decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.10 rt-rt transfer compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.11 illegal command decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.0 memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.0 pin identification and description . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.0 maximum and recommended operating conditions 22 5.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.0 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7.0 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
rts-3 1.0 a rchitecture a nd o peration the ut1760a rts is an interface device linking a mil- std-1553 serial data bus and a host microprocessor system. the rtss mil-std-1553b interface includes encoding/ decoding logic, error detection, command recognition, 1k x 16 of sram, pointer registers, clock, and reset circuits. illegal subaddress circuitry makes the rts mil-std- 1760a-speci?c. 1.1 memory map and host memory interface the host can access the 1k x 16 ram memory like a standard ram device through the 10-bit address and 16-bit data buses. the host uses the chip select (cs ), read/write (rd/wr ), and output enable (oe ) signals to control data transfer to and from memory. when the rts requires access to its own internal ram, it asserts the rbusy signal to alert the host. the rbusy signal is programmable via the internal control register to be asserted either 5.7ms or 2.7ms prior to the rts needing access to its internal ram. the rts stores mil-std-1760a messages in 1k x 16 of on-chip ram. for ef?cient use of the 1k x 16 memory on the rts, the host programs a set of pointers to map where the 1760a message is stored. the rts uses the upper 64 words (address 3c0 (hex) through 3ff (hex)) as pointers. the rts provides pointers for all 30 receive subaddresses, all 30 transmit subaddresses, and four mode code commands with associated data words as de?ned in mil-std-1553b. the remaining 960 words of memory contain receive, transmit, and mode code data in a host-de?ned structure. figure 2. rts memory map 15 msb 0 lsb rts memory map 3c0 (hex) 3df (hex) 3c1 (hex) 3de (hex) rcv subaddress 01 rcv subaddress 30 xmit vector word mode code (w/data) synchronize mode code (w/data) 15 msb 0 lsb 3ff (hex) xmit last command mode code (w/data) xmt bit word mode code (w/data) 3e0 (hex) xmt subaddress 30 3fe (hex) 3e1 (hex) 15 msb 0 lsb 000 (hex) 3bf(hex) message storage locations receive message pointers transmit message pointers (3c1 to 3de) (3e1 to 3fe) xmt subaddress 01
rts-4 1.2 rts ram pointer structure the ram 16-bit pointers have a 6-bit index ?eld and a 10-bit address ?eld. the 6-bit index ?eld allows for the storage of up to 64 messages per subaddress. a message consists of the 1553 command word and its associated data words. the 16-bit pointer for transmit last command mode code is located at memory location 3e0 (hex). the transmit last command mode code pointer buffers up to 63 command words. an example of command word storage follows: example: 3e0 (hex) contents = fc00 (hex) 11 1111 00 0000 0000 address field = 000 (hex) index field = 3f (hex) first command word storage location (3e0 = f801): address field = 001 (hex) index field = 3e (hex) sixty-third command word storage location (3e0 = 003f): address field = 03f (hex) index field = 00 (hex) sixty-fourth command word storage location (3e0 = 003f) (previous command word overwritten): address field = 03f (hex) index field = 00 (hex) the transmit last command mode code has address field boundary conditions for the location of command word buffers. the host can allocate a maximum 63 sequential locations following the address field starting address. for proper operation, the address field must start on an i x 40 (hex) address boundary, where i is greater than or equal to zero and less than or equal to 14. a list of valid index and address fields follows: figure 3. message pointer structure message index message data address 15 (msb) 0 (lsb) message index: de?nes the maximum messages buffered for the given subaddress. message data address: indicates the starting memory address for incoming message storage. 10 9 i valid index fields valid address fields 0 3f (hex) to 00 (hex) 000 (hex) to 03f(hex) 1 3f (hex) to 00 (hex) 040 (hex) to 07f (hex) 2 3f (hex) to 00 (hex) 080 (hex) to 0bf(hex) 3 3f (hex) to 00 (hex) 0c0 (hex) to 0ff (hex) 4 3f (hex) to 00 (hex) 100 (hex) to 13f (hex) 5 3f (hex) to 00 (hex) 140 (hex) to 17f (hex) 6 3f (hex) to 00 (hex) 180 (hex) to 1bf (hex) 7 3f (hex) to 00 (hex) 1c0 (hex) to 1ff (hex) 8 3f (hex) to 00 (hex) 200 (hex) to 23f (hex) 9 3f (hex) to 00 (hex) 240 (hex) to 27f (hex) 10 3f (hex) to 00 (hex) 280 (hex) to 2bf (hex) 11 3f (hex) to 00 (hex) 2c0 (hex) to 2ff (hex) 12 3f (hex) to 00 (hex) 300 (hex) to 33f (hex) 13 3f (hex) to 00 (hex) 340 (hex) to 37f (hex) 14 3f (hex) to 00 (hex) 380 (hex) to 3bf (hex)
rts-5 1.3 internal registers the rts uses two internal registers to allow the host to control the rts operation and monitor its status. the host uses the control (ctrl ) signal along with chip select (cs ), read/write (rd/wr ), and output enable (oe ) to read the 16-bit status register or write to the 13-bit control register. no address data is needed to select a register. the control register toggles bits in the mil-std-1553b status word, enables the biphase inputs, recognizes broadcast commands, selects notice i and ii or iii, determines ram busy (rbusy) timing, selects disconnect or terminal active ?ag, and puts the part in self-test mode. the status register supplies operational status of the ut1760a rts to the host. these registers must be initialized before attempting rts operation. internal registers can be accessed while rbusy is active. subaddress/mode code ram location subaddress/mode code ram location transmit vector word mode code 3c0 (hex) transmit last command mode code 3e0 (hex) receive subaddress 01 3c1 (hex) transmit subaddress 01 3e1 (hex) receive subaddress 02 3c2 (hex) transmit subaddress 02 3e2 (hex) receive subaddress 03 3c3 (hex) transmit subaddress 03 3e3 (hex) receive subaddress 04 3c4 (hex) transmit subaddress 04 3e4 (hex) receive subaddress 05 3c5 (hex) transmit subaddress 05 3e5 (hex) receive subaddress 06 3c6 (hex) transmit subaddress 06 3e6 (hex) receive subaddress 07 3c7 (hex) transmit subaddress 07 3e7 (hex) receive subaddress 08 3c8 (hex) transmit subaddress 08 3e8 (hex) receive subaddress 09 3c9 (hex) transmit subaddress 09 3e9 (hex) receive subaddress 10 3ca (hex) transmit subaddress 10 3ea (hex) receive subaddress 11 3cb (hex) transmit subaddress 11 3eb (hex) receive subaddress 12 3cc (hex) transmit subaddress 12 3ec (hex) receive subaddress 13 3cd (hex) transmit subaddress 13 3ed (hex) receive subaddress 14 3ce (hex) transmit subaddress 14 3ee (hex) receive subaddress 15 3cf (hex) transmit subaddress 15 3ef (hex) receive subaddress 16 3d0 (hex) transmit subaddress 16 3f0 (hex) receive subaddress 17 3d1 (hex) transmit subaddress 17 3f1 (hex) receive subaddress 18 3d2 (hex) transmit subaddress 18 3f2 (hex) receive subaddress 19 3d3 (hex) transmit subaddress 19 3f3 (hex) receive subaddress 20 3d4 (hex) transmit subaddress 20 3f4 (hex) receive subaddress 21 3d5 (hex) transmit subaddress 21 3f5 (hex) receive subaddress 22 3d6 (hex) transmit subaddress 22 3f6 (hex) receive subaddress 23 3d7 (hex) transmit subaddress 23 3f7 (hex) receive subaddress 24 3d8 (hex) transmit subaddress 24 3f8 (hex) receive subaddress 25 3d9 (hex) transmit subaddress 25 3f9 (hex) receive subaddress 26 3da (hex) transmit subaddress 26 3fa (hex) receive subaddress 27 3db (hex) transmit subaddress 27 3fb (hex) receive subaddress 28 3dc (hex) transmit subaddress 28 3fc (hex) receive subaddress 29 3dd (hex) transmit subaddress 29 3fd (hex) receive subaddress 30 3de (hex) transmit subaddress 30 3fe (hex) synchronize w/data word mode code 3df (hex) transmit bit word mode code 3ff (hex)
rts-6 control register (write only) the 13-bit write-only control register manages the operation of the rts. write to the control register by applying a logic one to oe , and a logic zero to ctrl , cs , and rd/wr . data is loaded into the control register via i/o pins data(12:0). control register write must occur 50ns before the rising edge of comstr to latch data into the outgoing status word. bit number initial condition description bit 0 [1] channel a enable. a logic 1 enables channel a biphase inputs. bit 1 [1] channel b enable. a logic 1 enables channel b biphase inputs. bit 2 [0] terminal flag. a logic 1 sets the terminal flag bit of the status word. bit 3 [1] system busy. a logic 1 sets the busy bit of the status word and limits rts access to the memory. no data word can be retrieved or stored; command words will be stored. bit 4 [0] subsystem busy. a logic 1 sets the subsystem flag bit of the status word. bit 5 [0] self-test channel select. this bit selects which channel the self-test checks; a logic 1 selects channel a and a logic 0 selects channel b. bit 6 [0] self-test enable. a logic 1 places the rts in the internal self-test mode and inhibits normal operation. channels a and b should be disabled if self-test is chosen. bit 7 [0] service request. a logic 1 sets the service request bit of the status word. bit 8 [0] instrumentation. a logic 1 sets the instrumentation bit of the status word. bit 9 [1] broadcast enable. a logic 1 enables the rts to recognize broadcast commands. bit 10 [1] notice select. a logic 1 enables notice iii operation; logic 0 enables notice i or ii operation. bit 11 [1] dscnct/tera ct pin select. a logic 1 selects the disconnect function; a logic 0 selects the terminal active function. bit 12 [1] rbusy time select. a logic 1 selects a 5.7 m s rbusy alert; a logic 0 selects a 2.7 m s rbusy alert. [] - values in parentheses indicate the initialized values of these bits. x x x no tice ps bcen ins srq itst subs busy tf ch b en ch a en itcs rbusy ts [1] figure 4a. control register [1] [0] [1] [0] [0] [0] [0] [0] [1] [1] [1] [1] [ ] de?nes reset state control register (write only): msb lsb
rts-7 status register (read only): the 16-bit read-only status register provides the rts system status. read the status register by applying a logic 0 to ctrl , cs , and oe , and a logic 1 to rd/wr . the 16-bit contents of the status register are read from data i/o pins data(15:0). bit number initial condition description bit 0 [0] mcsa0. the lsb of the mode code or subaddress as indicated by the logic state of bit 5. bit 1 [0] mcsa1. mode code or subaddress as indicated by the logic state of bit 5. bit 2 [0] mcsa2. mode code or subaddress as indicated by the logic state of bit 5. bit 3 [0] mcsa3. mode code or subaddress as indicated by the logic state of bit 5. bit 4 [0] mcsa4. mode code or subaddress as indicated by the logic state of bit 5. bit 5 [0] mc /sa. a logic 1 indicates that bits 4 through 0 are the subaddress of the last command word, and that the last command word was a normal transmit or receive command. a logic 0 indicates that bits 4 through 0 are a mode code, and that the last command was a mode command. bit 6 [1] channel a/b . a logic 1 indicates that the most recent command arrived on channel a; a logic 0 indicates that it arrived on channel b. bit 7 [1] channel b enabled. a logic 1 indicates that channel b is available for both reception and transmission. bit 8 [1] channel a enabled. a logic 1 indicates that channel a is available for both reception and transmission. bit 9 [1] terminal flag enabled. a logic 1 indicates that the bus controller has not issued an inhibit terminal flag mode code. a logic 0 indicates that the bus controller, via the above mode code, is overriding the host systems ability to set the terminal flag bit of the status word. bit 10 [1] busy. a logic 1 indicates the busy bit is set. this bit is reset when the system busy bit in the control register is reset. bit 11 [0] self-test. a logic 1 indicates that the chip is in the internal self-test mode. this bit is reset when the self-test is terminated. bit 12 [0] ta parity error. a logic 1 indicates the wrong terminal address parity; it causes the biphase inputs to be disabled. ta parity error results in the message error bit being set to a logic one, and channels a and b become disabled. bit 13 [0] message error. a logic 1 indicates that a message error has occurred since the last status reg- ister read. this bit is not reset until the status register has been examined. message error con- dition must be removed before reading the status register to reset the message error bit. bit 14 [0] valid message. a logic 1 indicates that a valid message has been received since the last status register read. this bit is not reset until the status register has been examined. bit 15 [0] terminal active. a logic 1 indicates the device is executing a transmit or receive operation. same as tera ct output except active high. (always tera ct ; never dscnct.) [] - values in parentheses indicate the initialized values of these bits. self- test term actv val mess mess err tapa err busy tfen ch a en ch b en chnl a/b mcsa 4 mcsa 3 mcsa 2 mcsa 1 mcsa 0 mc / sa [0] [0] [0] [0] [0] [0] [1] [1] [1] [1] [1] [0] [0] [0] [0] [0] [ ] de?nes reset state status register (read only): msb lsb figure 4b. status register
rts-8 1.4 mode code and subaddress the ut1760a rts provides two modes of illegal subaddress decoding, one meeting mil-std-1760a notices i and ii, and the other meeting mil-std-1760a notice iii. in addition, the device has automatic internal illegal command decoding for reserved mil-std-1553b mode codes. these de?nitions are extracted from mil- std-1760a and reviewed in section 1.5 of this document. upon command word validation and decode, status pins mcsa(4:0) and mc /sa become valid. status pin mc /sa will indicate whether the data on pins mcsa(4:0) is mode code or subaddress information. status register bits 0 through 5 contain the same information as pins mcsa(4:0) and mc /sa. the system designer can use signals mcsa(4:0), mc /sa, brdcst , rtrt, etc. to illegalize mode codes, subaddresses, and other message formats (broadcast and rt-to-rt) via the illegal command (illcom) input to the part. rts mode code handling procedure t/r mode code function operation 0 10100 selected transmitter shutdown 2 1. command word stored 2. merr pin asserted 3. merr bit set in status register 4. status word transmitted 0 10101 override selected transmitter shutdown 2 1. command word stored 2. merr pin asserted 3. merr bit set in status register 4. status word transmitted 0 10001 synchronize (w/data) 1. command word stored 2. data word stored 3. status word transmitted 1 00000 dynamic bus control 2 1. command word stored 2. merr pin asserted 3. merr bit set in status register 4. status word transmitted 1 00001 synchronize 1 1. command word stored 2. status word transmitted 1 00010 transmit status word 3 1. command word stored 2. status word transmitted 1 00011 initiate self-test 1 1. command word stored 2. status word transmitted 1 00100 transmitter shutdown 1. command word stored 2. alternate bus shutdown 3. status word transmitted 1 00101 override transmitter shutdown 1. command word stored 2. alternate bus enabled 3. status word transmitted 1 00110 inhibit terminal flag bit 1. command word stored 2. terminal flag bit set to zero and disabled 3. status word transmitted 1 00111 override inhibit terminal flag 1. command word stored 2. terminal flag bit enabled, but not set to logic one 3. status word transmitted 1 01000 reset remote terminal 1 1. command word stored 2. status word transmitted 1 10010 transmit last command word 3 1. status word transmitted 2. last command word transmitted 1 10000 transmit vector word 1. command word stored 2. status word transmitted 3. data word transmitted 1 10011 transmit bit word 1. command word stored 2. status word transmitted 3. data word transmitted notes: 1. further host interaction required for mode code operation. 2. reserved mode code; a) merr pin asserted, b) mess err bit set, c) status word transmitted (me bit set to logic one). 3. status word not affected. 4. unde?ned mode codes are treated as reserved mode codes.
rts-9 1.5 mil-std-1760a subaddress and mode code de?nitions table 1. subaddress and mode code de?nitions per mil-std-1760a notice i subaddress field binary (decimal) message format description receive transmit 00000 (00) b.40.1.1.3 1 b.40.1.1.3 mode code indicator 00001 (01) reserved b.40.2.1 2 store description 00010 (02) user de?ned user de?ned 00011 (03) reserved reserved 00100 (04) user de?ned user de?ned 00101 (05) reserved reserved 00110 (06) user de?ned user de?ned 00111 (07) user de?ned user de?ned 01000 (08) reserved reserved 01001 (09) user de?ned user de?ned 01010 (10) user de?ned user de?ned 01011 (11) reserved reserved 01100 (12) user de?ned user de?ned 01101 (13) user de?ned user de?ned 01110 (14) reserved reserved 01111 (15) reserved user de?ned 10000 (16) user de?ned user de?ned 10001 (17) user de?ned user de?ned 10010 (18) user de?ned user de?ned 10011 (19) reserved reserved nuclear weapon 10100 (20) user de?ned user de?ned 10101 (21) reserved user de?ned 10110 (22) user de?ned user de?ned 10111 (23) user de?ned user de?ned 11000 (24) user de?ned user de?ned 11001 (25) user de?ned user de?ned 11010 (26) user de?ned user de?ned 11011 (27) reserved reserved nuclear weapon 11100 (28) user de?ned user de?ned 11101 (29) user de?ned user de?ned 11110 (30) user de?ned user de?ned 11111 (31) b.40.1.1.3 b.40.1.1.3 mode code indicator notes: 1. refer to section b.40.1.1.3 of the mil-std-1760a speci?cation for de?nition. 2. refer to section b.40.2.1 of the mil-std-1760a speci?cation for de?nition. 3. reserved subaddresses illegalized; message error bit and pin set; sw transmitted.
rts-10 table 2. subaddress and mode code de?nitions per mil-std-1760a notice ii subaddress field binary (decimal) message format description receive transmit 00000 (00) b.40.1.1.3 1 b.40.1.1.3 mode code indicator 00001 (01) reserved b.40.2.1 2 store description 00010 (02) user de?ned user de?ned 00011 (03) reserved reserved 00100 (04) user de?ned user de?ned 00101 (05) reserved reserved 00110 (06) user de?ned user de?ned 00111 (07) user de?ned user de?ned 01000 (08) reserved reserved 01001 (09) user de?ned user de?ned 01010 (10) user de?ned user de?ned 01011 (11) reserved reserved 01100 (12) user de?ned user de?ned 01101 (13) user de?ned user de?ned 01110 (14) reserved reserved 01111 (15) reserved user de?ned 10000 (16) user de?ned user de?ned 10001 (17) user de?ned user de?ned 10010 (18) user de?ned user de?ned 10011 (19) reserved reserved nuclear weapon 10100 (20) user de?ned user de?ned 10101 (21) reserved user de?ned 10110 (22) user de?ned user de?ned 10111 (23) user de?ned user de?ned 11000 (24) user de?ned user de?ned 11001 (25) user de?ned user de?ned 11010 (26) user de?ned user de?ned 11011 (27) reserved reserved nuclear weapon 11100 (28) user de?ned user de?ned 11101 (29) user de?ned user de?ned 11110 (30) user de?ned user de?ned 11111 (31) b.40.1.1.3 b.40.1.1.3 mode code indicator notes: 1. refer to section b.40.1.1.3 of the mil-std-1760a speci?cation for de?nition. 2. refer to section b.40.2.1 of the mil-std-1760a speci?cation for de?nition. 3. reserved subaddresses illegalized; message error bit and pin set; sw transmitted.
rts-11 table 3. subaddress and mode code de?nitions per mil-std-1760a notice iii subaddress field binary (decimal) message format description receive transmit 00000 (00) b.40.1.1.3 1 b.40.1.1.3 mode code indicator 00001 (01) reserved b.40.2.1 2 store description 00010 (02) user de?ned user de?ned 00011 (03) user de?ned user de?ned 00100 (04) user de?ned user de?ned 00101 (05) user de?ned user de?ned 00110 (06) user de?ned user de?ned 00111 (07) user de?ned user de?ned 01000 (08) reserved reserved test only 01001 (09) user de?ned user de?ned 01010 (10) user de?ned user de?ned 01011 (11) b.40.2.2.1 3 b.40.2.2.1 mission store control/monitor 01100 (12) user de?ned user de?ned 01101 (13) user de?ned user de?ned 01110 (14) b.40.1.1.5.8 4 b.40.1.5.8 mass data transfer 01111 (15) user de?ned user de?ned 10000 (16) user de?ned user de?ned 10001 (17) user de?ned user de?ned 10010 (18) user de?ned user de?ned 10011 (19) b.40.2.2.4 5 b.40.2.2.5 6 nuclear weapon 10100 (20) user de?ned user de?ned 10101 (21) user de?ned user de?ned 10110 (22) user de?ned user de?ned 10111 (23) user de?ned user de?ned 11000 (24) user de?ned user de?ned 11001 (25) user de?ned user de?ned 11010 (26) user de?ned user de?ned 11011 (27) b.40.2.2.4 b.40.2.2.5 nuclear weapon 11100 (28) user de?ned user de?ned 11101 (29) user de?ned user de?ned 11110 (30) user de?ned user de?ned 11111 (31) b.40.1.1.3 b.40.1.1.3 mode code indicator notes: 1. refer to section b.40.1.1.3 of the mil-std-1760a speci?cation for de?nition. 2. refer to section b.40.2.1 of the mil-std-1760a speci?cation for de?nition. 3. refer to section b.40.2.2.1 of the mil-std-1760a speci?cation for de?nition. 4. refer to section b.40.1.1.5.8 of the mil-std-1760a speci?cation for de?nition. 5. refer to section b.40.2.2.4 of the mil-std-1760a speci?cation for de?nition. 6. refer to section b.40.2.2.5 of the mil-std-1760a speci?cation for de?nition. 7. reserved subaddresses illegalized; message error bit and pin set; sw transmitted.
rts-12 1.6 terminal address the terminal address of the rts is programmed via ?ve input pins: rta(4:0) and rtpty. asserting mrst latches the rtss terminal address from pins rta(4:0) and parity bit rtpty. the address and parity cannot change until the next assertion of the mrst . the parity of the terminal address is odd; input pin rtpty is set to a logic state to satisfy this requirement. a logic 1 on status register bit 12 indicates incorrect terminal address parity. an example follows: rta(4:0) = 05 (hex) = 00101 rtpty = 1 (hex) = 1 sum of 1s = 3 (odd), status register bit 12 = 0 rta(4:0) = 04 (hex) = 00100 rtpty = 0 (hex) = 0 sum of 1s = 1 (odd), status register bit 12 = 0 rta(4:0) = 04 (hex) = 00100 rtpty = 1 (hex) = 1 sum of 1s = 2 (even), status register bit 12 = 1 the rts checks the terminal address and parity on master reset. the state of the dscnct signal indicates the mated status of the store. when all six terminal address pins (rta(4:0), rtpty) go to a logic one, the dscnct pin is asserted. to enable the disconnect function (dscnct pin) bit 11 of the control register is set to a logic one. with broadcast disabled, rta (4:0) = 11111 operates as a normal rt address. 1.7 internal self-test setting bit 6 of the control register to a logic one enables the internal self-test. disable channels a and b at this time to prevent bus activity during self-test by setting bits 0 and 1 of the control register to a logic zero. normal operation is inhibited when internal self-test is enabled. the self-test capability of the rts is based on the fact that the mil-std- 1553b status word sync pulse is identical to the command word sync pulse. thus, if the status word from the encoder is fed back to the decoder, the rts will recognize the incoming status word as a command word and thus cause the rts to transmit another status word. after the host invokes self-test, the rts self-test logic forces a status word transmission even though the rts has not received a valid command. the status word is sent to decoder a or b depending on the channel the host selected for self-test. the self-test is controlled by the host periodically changing the bit patterns in the status word being transmitted. writing to the control register bits 2, 3, 4, 7, 8, and 10 changes the status word. monitor the self-test by sampling either the status register or the external status pins (i.e., command strobe (comstr ), transmit/receive (t/r )). for more detailed explanation of internal self-test, consult utmc publication rtr/rts internal self-test routine. 1.8 power-up and master reset after power-up, reset initializes the part with its biphase ports enabled, latches the terminal address, selects notice iii subaddress decoding, and turns on the busy option. the device is ready to accept commands from the mil-std- 1553b bus. the busy ?ag is asserted while the host is loading the message pointers and messages. after this task is completed, the host removes the busy condition via a control register write to the rts. on power-up if the terminal address parity (odd) is incorrect, the biphase inputs are disabled and the message error pin (merr) is asserted. this condition can also be monitored via bit 12 of the status register. the merr pin is negated on reception of ?rst valid command. 1.9 encoder and decoder the rts interfaces directly to a bus transmitter/ receiver via the rts manchester ii encoder/decoder. the ut1760a rts receives the command word from the mil-std- 1553b bus and processes it either by the primary or secondary decoder. each decoder checks for the proper sync pulse and manchester waveform, edge skew, correct number of bits, and parity. if the command is a receive command, the rts processes each incoming data word for correct format and checks the control logic for correct word count and contiguous data. if an invalid message error is detected, the message error pin is asserted, the rts ceases processing the remainder (if any) of the message, and it then suppresses status word transmission. upon command validation recognition, the external status outputs are enabled. reception of illegal commands does not suppress status word transmission. the rts automatically compares the transmitted word (encoder word) to the re?ected decoder word by way of the continuous loop-back feature. if the encoder word and re?ected word do not match, the transmitter error pin (txerr) is asserted. in addition to the loop-back compare test, a timer precludes a transmission greater than 760s by the assertion of fail-safe timer (timer on ). this timer is reset upon receipt of another command. (rt-to-rt transfer time-out = 57s). 1.10 rt-rt transfer compare the rt-to-rt terminal address compare logic makes sure that the incoming status words terminal address matches the terminal address of the transmitting rt speci?ed in the command word. an incorrect match results in setting the message error bit and suppressing transmission of the status word.
rts-13 1.11 illegal command decoding the host has the option of asserting the illcom pin to illegalize a received command word. on receipt of an illegal command, the rts sets the message error bit in the status word, sets the message error output, and sets the message error latch in the status register. the following rts outputs may be used to externally decode an illegal command, mode code or subaddress indicator (mc /sa), mode code or subaddress bus mcsa(4:0), command strobe (comstr ), broadcast (brdcst ), and remote terminal to remote terminal transfer (rtrt) (see ?gure 21 on page 34.) to illegalize a transmit command, the illcom pin must be asserted within 3.3s after valmsg goes to a logic 1 if the rts is to respond with the message error bit of the status word at a logic 1. if the illegal command is mode code 2, 4, 5, 6, 7, or 18, the illcom pin must be asserted within 664ns after command strobe (comstr ) transitions to logic 0. asserting the illcom pin within the 664ns inhibits the mode code function. for mode code illegalization, assert the illcom pin until the valmsg signal is asserted. for an illegal receive command, the illcom pin must be asserted within 18.2s after the comstr transitions to a logic 0 in order to suppress data words from being stored. in addition, the illcom pin must be at a logic 1 throughout the reception of the message until valmsg is asserted. this does not apply to illegal transmit commands since the status word is transmitted ?rst. the above timing conditions also apply when the host externally decodes an illegal broadcast command. the host must remove the illegal command condition so that the next command is not falsely decoded as illegal. 2.0 m emory m ap e xample figures 5 and 6 illustrate the ut1760a rts buffering three receive command messages to subaddress 4. the receive message pointer for subaddress 4 is located at 03c4 (hex) in the 1k x 16 ram. the 16-bit contents of location 03c4 (hex) point to the memory location where the ?rst receive message is stored. the address field de?ned as bits 0 through 9 of address 03c4 (hex) contain address information. the index field de?ned as bits 10 through 15 of address 03c4 (hex) contain the message buffer index (i.e., number of messages buffered). figure 5 demonstrates the updating of the message pointer as each message is received and stored. the memory storage of these three messages is shown in ?gure 6. after receiving the third message for subaddress 4 (i.e., index field equals zero) the address field of the message pointer is not incremented. if the host does not update the receive message pointer for subaddress 4 before the next receive command for subaddress 4 is accepted, the third message will be overwritten. figures 7 and 8 show an example of multiple message retrieval from subaddress 16 upon reception of a mil-std- 1553b transmit command. the message pointer for transmit subaddress 16 is located at 03f0 (hex) in the 1k x 16 ram. the 16-bit contents of location 03f0 (hex) point to the memory location where the ?rst message data words are stored. figure 7 demonstrates the updating of the message pointer as each message is received and stored. the data memory for these three messages is shown in ?gure 8.
rts-14 mil-std-1553 bus activity: figure 5. rts message handling receive subaddress 4; data pointer at 03c4 (hex). (initial condition) 0840 (hex) 03c4 (hex) index = 0000 10 address = 00 0100 0000 0445 (hex) 03c4 (hex) index = 0000 01 address = 00 0100 0101 after message #1, 4 data words plus command word. 0048 (hex) 03c4 (hex) index = 0000 00 address = 00 0100 1000 after message #2, 2 data words plus command word. 0048 (hex) 03c4 (hex) index = 0000 00 address = 00 0100 1000 after message #3, 4 data words plus command word. example: remote terminal will receive and buffer three mil-std-1553 receive commands of various word lengths to subaddress 4. cmd word #1 dw1 dw2 dw3 dw0 cmd word #2 dw1 dw0 cmd word #3 dw1 dw3 dw0 sa = 4 sa = 4 sa = 4 t/r = 0 t/r = 0 t/r = 0 wc = 4 wc = 2 wc = 4 dw2 040 (hex) 041 (hex) 042 (hex) 043 (hex) 044 (hex) 045 (hex) 046 (hex) 047 (hex) 048 (hex) 049 (hex) 04a (hex) 04b (hex) 04c (hex) figure 6. memory storage subaddress 4 command word #2 data word 0 data word 1 data word 2 data word 3 command word #1 data word 1 command word #3 data word 0 data word 1 data word 2 data word 3 data word 0 0840 (hex) 03c4 (hex) 0445 (hex) 03c4 (hex) 0048 (hex) 03c4 (hex) 0048 (hex) 03c4 (hex)
rts-15 figure 7. rts message handling 0830 (hex) index = 0000 10 address = 00 0011 0000 0434 (hex) 03f0 (hex) index = 0000 01 address = 00 0011 0100 after message #1, 4 data words. 0036 (hex) 03f0 (hex) index = 0000 00 address = 00 0011 0110 after message #2, 2 data words. 0036 (hex) 03f0 (hex) index = 0000 00 address = 00 0011 0110 after message #3, 4 data words. example: remote terminal will transmit and buffer three mil-std-1553 transmit commands of various word lengths to subaddress 16. cmd word #1 dw1 sw cmd word #2 dw1 cmd word #3 dw1 dw2 dw3 dw0 mil-std-1553 bus activity: sa = 16 t/r = 1 sa = 16 t/r = 1 wc = 4 sa = 16 t/r = 1 wc = 2 wc = 4 transmit subaddress 16; data pointer at 03f0 (hex). (initial condition) 03f0 (hex) dw0 sw sw dw3 dw2 sw0 030 (hex) 031 (hex) 032 (hex) 033 (hex) 034 (hex) 035 (hex) 036 (hex) 037 (hex) 038 (hex) 039 (hex) figure 8. memory storage subaddress 16 data word 0 data word 1 data word 2 data word 3 data word 1 data word 0 data word 1 data word 2 data word 3 data word 0 0830 (hex) 03f0(hex) 0434 (hex) 03f0 (hex) 0036 (hex) 0 3f0 (hex) 0036 (hex) 0 3f0 (hex) 034 (hex) n ote: e xample is valid only if message structure is known in advance.
rts-16 3.0 p in i dentification a nd d escription v dd v dd v ss v ss mrst biphase out taz tao tbz tbo biphase in raz rao rbz rbo terminal address rta0 rta1 rta2 rta3 rta4 rtpty mode/code subaddress mcsa0 mcsa1 mcsa2 mcsa3 mcsa4 status signals merr dscnct/tera ct txerr timer on comstr mc /sa brdcst t/r rtrt valmsg rbusy cs rd/wr ctrl oe illcom control signals addr9 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 address bus addr(9:0) data12 data13 data14 data15 data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data bus data(15:0) 12mhz 2mhz clock figure 9. ut1760a rts pin description ut1760a rts ground reset a10 b10 a9 b9 l7 k8 l6 k7 l5 k5 k4 l4 l3 k6 b2 a2 a3 b3 a4 a5 a6 b5 b6 b8 b1 a7 b4 b7 l8 c2 k2 k1 j1 l9 k9 l2 a8 k3 f10 e1 f2 g11 e10 e11 d10 d11 c10 c11 b11 f11 g10 l10 k10 k11 j10 j11 h10 h11 j2 h1 h2 g1 g2 f1 e2 d1 d2 c1 power
rts-17 legend for type and active fields: ti = ttl input tui = ttl input (pull-up) tdi = ttl input (pull-down) to = ttl output tto = three-state ttl output ttb = three-state ttl bidirectional al = active low ah = active high [] - value in parentheses indicates initial state of these pins. data bus address bus name pin number (pga) type active description data15 b11 ttb -- bit 15 (msb) of the bidirectional data bus. data14 c11 ttb -- bit 14 of the bidirectional data bus. data13 c10 ttb -- bit 13 of the bidirectional data bus. data12 d11 ttb -- bit 12 of the bidirectional data bus. data11 d10 ttb -- bit 11 of the bidirectional data bus. data10 e11 ttb -- bit 10 of the bidirectional data bus. data9 e10 ttb -- bit 9 of the bidirectional data bus. data8 f11 ttb -- bit 8 of the bidirectional data bus. data7 g10 ttb -- bit 7 of the bidirectional data bus. data6 h11 ttb -- bit 6 of the bidirectional data bus. data5 h10 ttb -- bit 5 of the bidirectional data bus. data4 j11 ttb -- bit 4 of the bidirectional data bus. data3 j10 ttb -- bit 3 of the bidirectional data bus. data2 k11 ttb -- bit 2 of the bidirectional data bus. data1 k10 ttb -- bit 1 of the bidirectional data bus. data0 l10 ttb -- bit 0 (lsb) of the bidirectional data bus. name pin number (pga) type active description addr9 c1 ti -- bit 9 (msb) of the address bus. addr8 d2 ti -- bit 8 of the address bus. addr7 d1 ti -- bit 7 of the address bus. addr6 e2 ti -- bit 6 of the address bus. addr5 f1 ti -- bit 5 of the address bus. addr4 g2 ti -- bit 4 of the address bus. addr3 g1 ti -- bit 3 of the address bus. addr2 h2 ti -- bit 2 of the address bus. addr1 h1 ti -- bit 1 of the address bus. addr0 j2 ti -- bit 0 (lsb) of the address bus.
rts-18 control inputs name pin number (pga) type active description cs k2 ti al chip select. the host processor uses the cs signal for rts status register reads, control register writes, or host access to the rts internal ram. rd/wr k1 ti -- read/write. the host processor uses a high level on this input in conjunction with cs to read the rts status register or the rts internal ram. a low level on this input is used in conjunction with cs to write to the rts control register or the rts internal ram. ctrl j1 ti al control. the host processor uses the active low ctrl input signal in conjunction with cs and rd/wr to access the rts registers. a high level on this input means access is to rts internal ram only. oe l9 ti al output enable. the active low oe signal is used to control the direction of data ?ow from the rts. for oe = 1, the rts data bus is three-state; for oe = 0, the rts data bus is active. illcom k9 tdi ah illegal command. the host processor uses the illcom input to inform the rts that the present command is illegal.
rts-19 status outputs name pin number (pga) type active description merr [0] a5 to ah message error. the active high merr output signals that the message error bit in the status register has been set due to receipt of an illegal command, or an error during message sequence. merr will reset to logic zero on the receipt of the next valid command. txerr [0] b5 to ah transmission error. the active high txerr output is asserted when the rts detects an error in the re?ected word versus the transmitted word, using the continuous loop-back compare feature. reset on next comstr assertion. timer on [1] b6 to al fail-safe timer. the timer on output pulses low for 760s when the rts begins transmitting (i.e., rising edge of valmsg) to provide a fail-safe timer meeting the requirements of mil-std-1553b. this pulse is reset when comstr goes low or during a master reset. comstr [1] b8 to al command strobe. comstr is an active low output of 500ns duration identifying receipt of a valid command. brdcst [1] a7 to al broadcast. brdcst is an active low output that identi?es receipt of a valid broadcast command. rtrt [0] b7 to ah remote terminal to remote terminal. rtrt is an active high output indicating that the rts is processing a remote terminal to remote terminal command. dscnct or tera ct [x] a6 to -- disconnect or terminal active. bit 11 of the control register selects the mode of this dual-function pin. in the disconnect mode (bit 11 = 1), the active high dscnct output is asserted when all six terminal address pins (rta0 - rta4, rtpty) go high, indicating a disconnect condition. in the terminal active mode (bit 11 = 0), the active low tera ct output is asserted at the beginning of the rts access to internal ram for a given command and negated after the last access for that command. valmsg [0] l8 to ah valid message. valmsg is an active high output indicating a valid message (including broadcast) has been received. valmsg goes high prior to transmitting the 1553 status word and is reset upon receipt of the next command. rbusy [0] c2 to ah rts busy. rbusy is asserted high while the rts is accessing its own internal ram either to read or update the pointers or to store or retrieve data words. rbusy becomes active either 2.7s or 5.7s before rts requires ram access. this timing is controlled by control register bit 12 (see section 1.3). t/r [0] b4 to -- transmit/receive. a high level on this pin indicates a transmit command message transfer is being or was processed, while a low level indicates a receive command message transfer is being or was processed.
rts-20 mode code/subaddress outputs remote terminal address inputs name pin number (pga) type active description mc /sa [0] b1 to -- mode code/subaddress indicator. if mc /sa is low, it indi- cates that the most recent command word is a mode code command. if mc /sa is high, it indicates that the most recent command word is for a subaddress. this output indicates whether the mode code/subaddress ouputs (i.e., mcsa(4:0)) contain mode code or subaddress information. mcsa0 [0] b2 to -- mode code/subaddress output 0. if mc /sa is low, this pin represents the least signi?cant bit of the most recent command word (the lsb of the mode code). if mc /sa is high, this pin represents the lsb of the subaddress. mcsa1 [0] a2 to -- mode code/subaddress output 1. mcsa2 [0] a3 to -- mode code/subaddress output 2. mcsa3 [0] b3 to -- mode code/subaddress output 3. mcsa4 [0] a4 to -- mode code/subaddress output 4. if mc /sa is low, this pin represents the most signi?cant bit of the mode code. if mc / sa is high, this pin represents the msb of the subaddress. name pin number (pga) type active description rta4 l3 tui -- remote terminal address bit 4 (msb). rta3 k4 tui -- remote terminal address bit 3. rta2 l4 tui -- remote terminal address bit 2. rta1 k5 tui -- remote terminal address bit 1. rta0 l5 tui -- remote terminal address bit 0 (lsb). rtpty k6 tui -- remote terminal address parity. this input must provide odd parity for the remote terminal address.
rts-21 biphase inputs 1 note : 1. for uniphase operation, tie raz (or rbz) to v dd and apply true uniphase input signal to rao (or rbo). biphase outputs master reset and clock name pin number (pga) type active description raz l7 ti -- receiver - channel a, zero input. idle low manchester input form the 1553 bus receiver. rao k8 ti -- receiver - channel a, one input. this input is the complement of raz. rbz l6 ti -- receiver - channel b, zero input. idle low manchester input from the 1553 bus receiver. rbo k7 ti -- receiver - channel b, one input. this input is the complement of rbz. name pin number (pga) type active description taz [0] a10 to -- transmitter - channel a, zero output. this manchester encoded data output is connected to the 1553 bus transmitter input. the output is idle low. tao [0] b10 to -- transmitter - channel a, one output. this output is the complement of taz. the output is idle low. tbz [0] a9 to -- transmitter - channel b, zero output. this manchester encoded data output is connected to the 1553 bus transmitter input. the output is idle low. tbo [0] b9 to -- transmitter - channel b, one output. this output is the complement of tbz. the output is idle low. name pin number (pga) type active description mrst k3 tui al master reset. initializes all internal functions of the rts. mrst must be asserted 500ns before normal rts operation (500ns minimum). does not reset ram. 12mhz l2 ti -- 12 mhz input clock. this is the rts system clock that requires an accuracy greater than 0.01% with a duty cycle of 50% 10%. 2mhz a8 to -- 2mhz clock output. this is a 2mhz clock output generated by the 12mhz input clock. this clock is stopped when mrst is low.
rts-22 power and ground 4.0 o perating c onditions absolute maximum ratings* (referenced to v ss ) recommended operating conditions name pin number (pga) type active description v dd f10 e1 pwr pwr -- -- +5 v dc power. power supply must be +5 v dc 10%. v ss f2 g11 gnd gnd -- -- reference ground. zero v dc logic ground. symbol parameter limits unit v dd dc supply voltage -0.3 to +7.0 v v io voltage on any pin -0.3 to v dd +0.3 v i i dc input current 10 ma t stg storage temperature -65 to +150 c p d maximum power dissipation 1 300 mw t j maximum junction temperature +175 c q jc thermal resistance, junction-to-case 20 c/w note: 1. does not re?ect the added p d due to an output short-circuited. * stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this speci?cation is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter limits unit v dd dc supply voltage 4.5 to 5.5 v v in dc input voltage 0 to v dd v t c temperature range -55 to +125 c f o operating frequency 12 .01% mhz
rts-23 5.0 dc e lectrical c haracteristics v dd = 5.0v 10%; -55 c < t c <+125 c) symbol parameter condition minimum maximum unit v il low-level input voltage 0.8 v v ih high-level input voltage 2.0 v i in input leakage current ttl inputs inputs with pull-down resistors inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -1 110 -2000 1 2000 -110 m a m a m a v ol low-level output voltage i ol = 3.2a 0.4 v v oh high-level output voltage i oh = -400a 2.4 v i oz three-state output leakage current v o = v dd or v ss -10 +10 m a i os short-circuit output current 1, 2 v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -90 90 ma ma c in input capacitance 3 ? = 1mhz @ 0v 10 pf c out output capacitance 3 ? = 1mhz @ 0v 15 pf c io bidirect i/o capacitance 3 ? = 1mhz @ 0v 20 pf i dd average operating current 1, 4 ? = 12mhz, cl = 50pf 50 ma qi dd quiescent current note 5 1.5 ma notes: 1. supplied as a design limit but not guaranteed or tested. 2. not more than one output may be shorted at a time for a maximum duration of one second. 3. measured only for initial quali?cation, and after process or design changes that could affect input/output capacitance. 4. includes current through input pull-ups. instantaneous surge currents on the order of 1 ampere can occur during output switc hing. voltage supply should be adequately sized and decoupled to handle a large surge current. 5. all inputs with internal pull-ups or pull-downs should be left open circuit. all other inputs tied high or low. sync bit times command word 5 5 5 1 data word 1 status word sync sync 5 1 remote terminal address subaddress/mode code t/r data word count/ mode code p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 p data 1 1 1 1 1 1 1 figure 10. mil-std-1553b word formats 16 remote terminal address message error instrumentation service request reserved broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag parity 1 1
rts-24 6.0 ac e lectrical c haracteristics (over recommended operating conditions) to data valid to high z to response to response to response input input input input input input input to high z to data valid to response input parameter symbol bus input notes: 1. timing measurements made at (v ih min + v il max)/2. 2. timing measurements made at (v ol max + v oh min)/2. 3. based on 50pf load. 4. unless otherwise noted, all ac electrical characteristics are guaranteed by design or characterization. 1 1 2 2 2 2 v ih min v il max v ih min v il max v oh min v ol max v oh min v ol max v oh min v ol max t a t b t c t d t e t f t g t h - - - - - - t a t b t c t d t e t f t g t h in-phase output out-of-phase output figure 11a. typical timing measurements 90% figure 11b. ac test loads and input waveforms note: 50pf including scope probe and test socket input pulses 10% 10% 90% < 2ns < 2ns 50pf 3v 0v 5v d i ref (source) i ref (sink) v ref
rts-25 symbol parameter min max units t 12a ctrl - set up wrt cs 1 10 -- ns t 12b rd/wr - set up wrt cs 10 -- ns t 12c addr(9:0) valid to cs (address set up) 10 -- ns t 12d cs to data(15:0) valid -- 155 ns t 12e oe to data(15:0) dont care (active) -- 65 ns t 12f cs - to ctrl dont care 0 -- ns t 12g cs - to addr(9:0) dont care 0 -- ns t 12h oe - to data(15:0) high impedance -- 40 ns t 12i cs to cs - 2 220 5500 ns t 12j cs - to cs 85 -- ns t 12k cs - to rd/wr dont care 0 -- ns t 12l cs - to data(15:0) invalid 3 25 -- ns t 12m oe to oe - 65 -- ns notes: 1. wrt de?ned as with respect to. 2. the maximum amount of time that cs can be held low is 5500ns if the user has selected the 5.7 m s rbusy option. for the 2.7 m s rbusy option, the maximum cs low time is 2500ns. 3. assumes oe is asserted. 12mhz rd/wr cs addr(9:0) oe data valid data(15:0) figure 12. microprocessor ram read t 12i t 12a t 12b t 12c t 12d t 12e t 12m t 1h t 12l t 12g t 12k t 12f t 12j ctrl
rts-26 symbol parameter min max units t 13a ctrl - set up wrt cs 10 -- ns t 13b rd/wr - set up wrt cs 10 -- ns t 13c addr(9:0) valid to cs (address set up) 10 -- ns t 13d cs to data(15:0) valid cs (data set up) 0 -- ns t 13e oe to data(15:0) high impedance 40 -- ns t 13f cs - to rd/wr dont care 0 -- ns t 13g cs - to addr(9:0) dont care 0 -- ns t 13h cs - to data(15:0) dont care (hold-time) 20 -- ns t 13i cs to cs - 1 180 5500 ns t 13j cs - to cs 85 -- ns t 13k cs - to ctrl dont care 0 -- ns note: 1. the maximum amount of time that cs can be held low is 5500ns if the user has selected the 5.7 m s rbusy option. for the 2.7 m s rbusy option, the maximum cs low time is 2500ns. data(15:0) 12mhz ctrl rd/wr cs addr(9:0) oe figure 13. microprocessor ram write valid data t 13i t 13a t 13b t 13c t 13d t 13e t 13h t 13g t 13f t 13k t 13j
rts-27 symbol parameter min max units t 14a ctrl set up wrt cs 0 -- ns t 14b rd/wr set up wrt cs 0 -- ns t 14c cs to cs - 1 50 5500 ns t 14d cs - to data(15:0) dont care (hold-time) 0 -- ns t 14e cs - to ctrl dont care 0 -- ns t 14f cs - to rd/wr dont care 0 -- ns t 14g oe - to data(15:0) high impedance 40 -- ns t 14h d ata (15:0) valid to cs (data set up) 0 -- ns note: 1. the maximum amount of time that cs can be held low is 5500ns if the user has selected the 5.7 m s rbusy option. for the 2.7 m s rbusy option, the maximum cs low time is 2500ns. 12mhz ctrl rd/wr cs oe data(15:0) figure 14. control register write valid data t 14c t 14a t 14b t 14h t 14g t 14d t 14f t 14e
rts-28 symbol parameter min max units t 15a ctrl set up wrt cs 0 -- ns t 15b cs to cs - 1 65 5500 ns t 15c rd/wr - set up wrt cs 0 -- ns t 15d cs to data(15:0) valid -- 65 ns t 15e cs - to ctrl dont care 5 -- ns t 15f cs - to rd/wr dont care 5 -- ns t 15g oe to data(15:0) dont care (active) -- 65 ns t 15h oe - to data(15:0) high impedance -- 40 ns t 15i oe to oe - 65 -- ns t 15j cs to data(15:0) dont care (active) 25 -- ns note: 1. the maximum amount of time that cs can be held low is 5500ns if the user has selected the 5.7 m s rbusy option. for the 2.7 m s rbusy option, the maximum cs low time is 2500ns. 12mhz ctrl cs oe data(15:0) figure 15. status register read valid data t 15b rd/wr t 15a t 15c t 15d t 15g t 15i t 15h t 15j t 15f t 15e
rts-29 symbol parameter min max units t 16a valmsg - before timer on 0 35 ns t 16b timer on before ?rst biphase out o - 1.2 -- m s t 16c timer on low pulse width (time-out) 727.3 727.4 m s t 16d comstr to timer on - -- 25 ns t 16e valmsg - to illcom - -- 3.3 m s t 16f comstr to illcom - 1 -- 664 ns t 16f comstr to illcom - 2 -- 18.2 m s t 16g illcom - to illcom 3 500 -- ns notes: 1. mode code 2, 4, 5, 6, 7, or 18 received. 2. to suppress data word storage. 3. for transmit command illegalization. a/b biphase output zero valmsg timer on figure 16. rt fail-safe timer signal relationships t 16a comstr illcom t 16c t 16b t 16e t 16g t 16d t 16f
rts-30 symbol parameter min max units t 17a 4 12mhz - to mc /sa valid 0 14 ns t 17b command word to mc /sa valid 3 2.1 2.8 m s t 17c 4 12mhz - to comstr 0 17 ns t 17d command word to comstr 3 3.2 3.7 m s t 17e 4 12mhz - to brdcst 0 32 ns t 17f command word to brdcst 3 2.6 3.2 m s t 17g 4 12mhz - to t/r valid 0 57 ns t 17h command word tot/r valid 3 2.2 2.7 m s t 17i 4 12mhz - to valmsg - 0 32 ns t 17j command word tovalmsg - 1,2,3 6.2 6.7 m s t 17k 4 12mhz - to merr - 0 37 ns t 17l comstr to comstr - 485 500 ns notes: 1. receive last data word to valid message active (valmsg - ). 2. transmit command word to valid message active (valmsg - ). 3. command word measured from mid-bit crossing. 4. guaranteed by test. 12mhz biphase in cs command word p mc /sa and mcsa(4:0) t 17a comstr brdcst t/r merr valmsg figure 17. status output timing 1 note: 1. measured from the mid-bit parity crossing. t 17b t 17c t 17d t 17e t 17f t 17g t 17h t 17i t 17j t 17k t 17l
rts-31 symbol parameter min max units t 18a 12mhz - to rbusy - -- 37 ns t 18b command word torbusy - 3 3.2 3.8 m s t 18c 2 12mhz - to tera ct 0 37 ns t 18d command word to tera ct 1,3 3.1 3.7 m s t 18e 2 12mhz - to rtrt - 0 32 ns t 18f command word to rtrt - 3 21.0 22 m s t 18g mrst to mrst - 500 -- ns t 18h rbusy - to rbusy (2.7 m s) (5.7 m s) -- -- 5.5 8.5 m s m s t 18i rbusy to rbusy - (2.7 m s) (5.7 m s) 3.10 240 -- -- m s ns notes: 1. tera ct enabled via control register. 2. guaranteed by test. 3. command word measured from mid-bit crossing 12mhz biphase in cs command word p rbusy t 18a tera ct rtrt mrst note: 1. measured from mid-bit parity crossing. t 18b t 18c t 18d t 18e t 18f t 18g t 18h t 18i figure 18. status output timing
rts-32 ss status word p biphase out figure 19a. receive command with two data words ds data word p ds data word p biphase in comstr t/r biphase out rbusy cs command word p biphase in comstr t/r rbusy ds data word p ds data word p cs = command sync ss = status sync ds = data sync p = parity 1 23 notes: 1. burst of 4 dmas: read command pointer, store command word, update command pointer, read data word pointer. 2. burst of 1 dma: read data word. 3. burst of 2 dmas: read data word, update data word pointer. 4. approximately 560ns per dma access. tera ct valmsg tera ct valmsg notes: 1. burst of 5 dmas: read command pointer, store command word, update command pointer, read data word pointer, store command word. 2. burst of 1 dma: store data word. 3. burst of 2 dmas: store data word, update data word pointer. 4. approximately 560ns per dma access. ss p status word 1 23 cs command word figure 19b. transmit command with two data words
rts-33 ut1760a rts addr(9:0) data(15:0) control ut63m125 1553 transceiver 1553 bus a 1553 bus b figure 20a. rts general system diagram (idle low interface) channel a channel b rts rao raz tao taz rbo rbz tbo tbz timer on utmc 63m125 channel a channel b txinhb txinhb rxout rxout txin txin rxout rxout txin txin host subsystem figure 20b. rts transceiver interface diagram
rts-34 7.0 p ackage o utline d rawing illegal command decoder rts figure 21. mode code/subaddress illegalization circuit mc /sa mcsa0 mcsa1 mcsa2 mcsa3 mcsa4 comstr brdcst t/r rtrt illcom
rts-35 k1 rd/wr k2 cs k3 mrst k4 rta3 k5 rta1 k6 rtpty k7 rbo k8 rao k9 illcom k10 data1 k11 data2 l2 12mhz l3 rta4 l4 rta2 l5 rta0 l6 rbz l7 raz l8 valmsg l k j h g f e d c b a 1234567891011 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 c1 c2 c10 c11 d1 d2 d10 d11 e1 e2 e10 e11 f1 f2 f10 f11 g1 g2 g10 g11 h1 h2 h10 h11 l2 l3 l4 l5 l6 l7 l8 l9 l10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 j1 j2 j10 j11 a2 mcsa1 a3 mcsa2 a4 mcsa4 a5 merr a6 tera ct or dscnct a7 brdcst a8 2mhz a9 tbz a10 taz b1 mc /sa b2 mcsa0 b3 mcsa3 b4 t/r b5 txerr b6 timer on b7 rtrt b8 comstr c1 addr9 c2 rbusy c10 data13 c11 data14 d1 addr7 d2 addr8 d10 data11 d11 data12 e1 v dd e2 addr6 e10 data9 e11 data10 f1 addr5 g1 addr3 g2 addr4 g10 data7 g11 v ss h1 addr1 h2 addr2 h10 data5 h11 data6 j1 ctrl j2 addr0 figure 22. ut1760a rts pingrid array con?guration (bottom view)
packaging -1 package selection guide note: 1. 84lcc package is not available radiation-hardened. product rti rtmp rtr bcrt bcrtm bcrtmp rts xcvr 24-pin dip (single cavity) x 36-pin dip (dual cavity) x 68-pin pga x x 84-pin pga x x x x 1 144-pin pga x 84-lead lcc x x x 1 36-lead fp (dual cavity) (50-mil ctr) x 84-lead fp x x 132-lead fp x x
packaging-2 1 144-pin pingrid array e 1.565 0.025 -b- d 1.565 0.025 -a- 0.080 ref. (2 places) 0.040 ref. 0.100 ref. (4 places) a 0.130 max. q 0.050 0.010 a a l 0.130 0.010 pin 1 i.d. (geometry optional) -c- (base plane) b 0.018 0.002 0.030 0.010 c a b c side view top view 0.003 min. typ. d1/e1 1.400 0.100 typ. e pin 1 i.d. (geometry optional) 2 r p n m l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all package finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. bottom view
packaging -3 132-lead flatpack (25-mil lead spacing) side view top view bottom view a-a detail a 0.018 max. ref. 0.014 max. ref. (at braze pads) l 0.250 min. ref. lead kovar see detail a a a c 0.005 + 0.002 - 0.001 a 0.110 0.006 d1/e1 0.950 0.015 sq. d/e 1.525 0.015 sq. pin 1 i.d. (geometry optional) e 0.025 notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. s1 0.005 min. typ.
packaging-4 84- lcc side view top view bottom view a-a notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. l/l1 0.050 0.005 typ. b1 0.025 0.003 e 0.050 e1 0.015 min. pin 1 i.d. (geometry optional) j 0.020 x 455 ref. h 0.040 x 45_ ref. (3 places) d/e 1.150 0.015 sq. a 0.115 max. a1 0.080 0.008 a a pin 1 i.d. (geometry optional)
packaging -5 84-lead flatpack (50-mil lead spacing) side view top view bottom view a-a d/e 1.810 0.015 sq. notes: 1. all package finishes are per mil-m-38510. 2. letter designations are for cross-reference to mil-m-38510. detail a d1/e1 1.150 0.012 sq. a 0.110 0.060 a a c 0.007 0.001 lead kovar see detail a pin 1 i.d. (geometry optional) b 0.016 0.002 l 0.260 min. ref. s1 0.005 min. typ. 0.050 e 0.014 max. ref. (at braze pads) 0.018 max. ref.
packaging-6 84-pin pingrid array side view top view bottom view a-a d 1.100 0.020 e 1.100 0.020 -b- -a- a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -c- (base plane) b 0.018 0.002 pin 1 i.d. (geometry optional) 1.000 d1/ e 0.100 typ. 0.003 min. l k j h g f e d 1 2 3 4 5 6 7 8 9 10 11 notes: 1. true position applies to pins at base plane (datum c). 2. true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) 1 0.030 0.010 c a b c 2
packaging -7 side view top bottom view a-a d 1.100 0.020 pin 1 i.d. (geometry optional) l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 notes: 1 true position applies to pins at base plane (datum c). 2 true position applies at pin tips. 3. all packages finishes are per mil-m-38510. 4. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) d1/e1 1.00 0.003 min. typ. e 0.100 typ. a 0.130 max. q 0.050 0.010 l 0.130 0.010 a a -a- -b- e 1.100 0.020 -c- (base plane) 68-pin pingrid array 0.030 0.010 c a b 1 2 c ? ? b 0.010 0.002
packaging-8 d 1.800 0.025 36-lead flatpack, dual cavity (100-mil lead spacing) top view end view e 0.750 0.015 notes: 1 all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) l 0.490 min. b 0.015 0.002 e 0.10 c 0.008 + 0.002 - 0.001 q 0.080 0.010 (at ceramic body) a 0.130 max.
packaging -9 36-lead flatpack, dual cavity (50-mil lead spacing) top e 0.700 + 0.015 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. c 0.007 + 0.002 - 0.001 q 0.070 + 0.010 (at ceramic body) a 0.100 max. end d 1.000 0.025 b 0.016 + 0.002 e 0.050 pin 1 i.d (geometry optional) l 0.330 min.
packaging-10 36-lead side-brazed dip, dual cavity top view end view e 0.590 0.012 notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. pin 1 i.d. (geometry optional) side view s1 0.005 min. d 1.800 0.025 s2 0.005 max. e 0.100 a 0.155 max. l/l1 0.150 min. c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002
packaging -11 e 0.590 0.015 s1 0.005 min. s2 0.005 max. top view pin 1 i.d. (geometry optional) d 1.200 0.025 side view a 0.140 max. l/l1 0.150 min. 0.100 e notes: 1. all package finishes are per mil-m-38510. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-m-38510. end view c 0.010 + 0.002 - 0.001 e1 0.600 + 0.010 (at seating plane) b 0.018 0.002 24-lead side-brazed dip, single cavity
ordering information ut1553b rts remote terminal for stores: s lead finish: (a) = solder (c) = gold (x) = optional case outline: (x) = 68 pin pga class designator: (-) = blank or no field is qml q drawing number: 8957501 total dose: (-) = none federal stock class designator: no options 5962 * * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. for qml q product, the q designator is intentionally left blank in the smd number (e.g. 5962-8957501xc).
ut1553b rts remote terminal for stores lead finish: (a) = solder (c) = gold (x) = optional package type: (g) = 68 pin pga utmc core part number no ut part number- * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold).

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