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slus419c ? august 1999 ? revised november 2001 1 www.ti.com features combines pfc and downstream converter controls controls boost preregulator to near-unity power factor accurate power limiting improved feedforward line regulation peak current-mode control in second stage programmable oscillator leading-edge/trailing-edge modulation for reduced output ripple low start-up supply current synchronized second stage start-up, with programmable soft-start programmable second stage shutdown description the ucc2850x family provides all of the control functions necessary for an active power-factor- corrected preregulator and a second-stage dc-to- dc converter. the controller achieves near-unity power factor by shaping the ac input line current waveform to correspond to the ac input-line voltage using average current-mode control. the dc-to-dc converter uses peak current-mode control to perform the step-down power conversion. the pfc stage is leading-edge modulated while the second stage is trailing-edge synchronized to allow for minimum overlap between the boost and pwm switches. this reduces ripple current in the bulk-output capacitor.in order to operate with over three-to-one range of input-line voltages, a line feedforward (v ff ) is used to keep input power constant with varying input voltage. generation of v ff is accomplished using i ac in conjunction with an external single-pole filter. this not only reduces external parts count, but also avoids the use of high-voltage components, offering a lower-cost solution. the multiplier then divides the line current by the square of v ff . the ucc2850x pfc section incorporates a low offset-voltage amplifier with 7.5-v reference, a highly-linear multiplier capable of a wide current range, a high-bandwidth, low offset-current amplifier, with a novel noise-attenuation configuration, pwm comparator and latch, and a high-current output driver. additional pfc features include over-voltage protection, zero-power detection to turn off the output when vaout is below 0.33 v and peak current and power limiting. the dc-to-dc section relies on an error signal generated on the secondary-side and processes it by performing peak current mode control. the dc-to-dc section also features current limiting, a controlled soft-start, preset operating range with selectable opti ons, and 50% maximum duty cycle. the ucc28500 and ucc28502 have a wide pfc-uvlo threshold (16.5 v/10 v) for bootstrap bias supply operation. the ucc28501 and ucc28503 are designed with a narrow uvlo range (10.5 v/10 v) more suitable for fixed bias operation. the ucc28500 and ucc28501 have a narrow uvlo threshold for pwm stage (to allow operation down to 75% of nominal bulk voltage), while the ucc28502 and ucc38503 are configured for a much wider operation range for the pwm stage (down to 50% of bulk nominal voltage). available in 20-pin n and dw packages. copyright ? 2001, texas instruments incorporated
slus419c ? august 1999 ? revised november 2001 2 www.ti.com absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage vcc 18 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gate drive current continuous 0.2 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pulsed 1.2 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage isense1, isense2, mout, vsense, ovp/enbl 10 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cai, mout, ct 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pklmt, verr 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input current rset, rt, iac, pklmt, ena 10 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vcc (no switching) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum negative voltage gt1, gt2, pklmt, mout ? 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not i mplied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ? currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitatio ns and considerations of packages. all voltages are referenced to gnd. available options pfc threshold packaged devices t j pfc uvlo turn?on threshold (v) uvlo2 hysteresis (v) plastic dip (n) small outline (dw) 16 1.2 ucc28500n ucc28500dw 40 cto85 c 10.5 1.2 ucc28501n ucc28501dw ? 40 c to 85 c 16 3.0 ucc28502n ucc28502dw 10.5 3.0 ucc28503n ucc28503dw 16 1.2 ucc38500n ucc38500dw 0 cto70 c 10.5 1.2 ucc38501n ucc38501dw 0 c to 70 c 16 3.0 UCC38502N ucc38502dw 10.5 3.0 ucc38503n ucc38503dw the dw package is available taped and reeled. add tr suffix to device type (e.g. ucc38500dwtr) to order quantities of 2000 devices per reel. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vaout rt vsense ovp/enbl ct gnd verr isense2 vcc gt2 vref vff iac mout isense1 caout pklmt ss2 gt1 pwrgnd n package (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vaout rt vsense ovp/enbl ct gnd verr isense2 vcc gt2 vref vff iac mout isense1 caout pklmt ss2 gt1 pwrgnd dw package (top view)
slus419c ? august 1999 ? revised november 2001 3 www.ti.com electrical characteristics t a = 0 c to 70 c for the ucc3850x, ? 40 c to 85 c for the ucc2850x, t a = t j , vcc = 12 v, rt = 22 k ? , ct = 330 pf (unless otherwise noted) supply current parameter test conditions min typ max units supply current, off vcc turn-on threshold ? 300 mv 150 300 a supply current, on vcc = 12 v (no load on gt1 or gt2) 4 6 ma undervoltage lockout parameter test conditions min typ max units vcc turn-on threshold (uccx8500/502) 15.4 16 16.6 v uvlo hysteresis (uccx8500/502) 5.8 6.3 v shunt voltage (uccx8500/502) i vcc = 10 ma 15.4 16.2 17.0 v vcc turn-on threshold (uccx8501/503) 9.7 10.2 10.8 v vcc turn-off threshold 9.4 9.7 v uvlo hysteresis (uccx8501/503) 0.3 0.5 v voltage amplifier parameter test conditions min typ max units inp t oltage 0 c t a 70 c 7.387 7.500 7.613 v input voltage ? 40 c t a 85 c 7.35 7.50 7.65 v v sense bias current 50 200 na open loop gain vaout = 2 v to 5 v 50 90 db high-level output voltage i load = ? 150 a 5.3 5.5 5.6 v low-level output voltage i load = 150 a 0.00 0.05 0.15 v overvoltage protection and enable parameter test conditions min typ max units over voltage reference vref + 0.480 vref + 0.500 vref + 0.520 v hysteresis 300 500 600 mv enable threshold 1.7 1.9 2.1 v enable hysteresis 0.1 0.2 0.3 v current amplifier parameter test conditions min typ max units input offset voltage v cm = 0 v, v caout = 3 v ? 6 0 6 mv input bias current v cm = 0 v, v caout = 3 v ? 50 ? 100 na input offset current v cm = 0 v, v caout = 3 v 25 100 na open loop gain v cm = 0 v, v caout = 2 v to 5 v 90 db common ? mode rejection ratio v cm = 0 v to 1.5 v, v caout = 3 v 90 db high-level output voltage i load = ? 120 a 5.6 7.0 7.5 v low-level output voltage i load = 1 ma 0.1 0.2 0.5 v gain bandwidth product see note 1 2.5 mhz notes: 1. ensured by design. not production tested. 2. see figure 6 for reference variation. 3. see figure 5 for reference variation for vcc < 10.8 v.
slus419c ? august 1999 ? revised november 2001 4 www.ti.com electrical characteristics t a = 0 c to 70 c for the ucc3850x, ? 40 c to 85 c for the ucc2850x, t a = t j , vcc = 12 v, rt = 22 k ? , ct = 330 pf (unless otherwise noted) voltage reference parameter test conditions min typ max units inp t oltage t a = 0 c to 70 c 7.387 7.500 7.613 v input voltage t a = ? 40 c to 85 c 7.35 7.50 7.65 v load regulation i ref = ? 1 ma to ? 2 ma, see note 2 0 10 mv line regulation vcc = 10.8 v to 15 v, see note 3 0 10 mv short circuit current vref = 0v ? 20 ? 25 ? 50 ma oscillator parameter test conditions min typ max units frequency, initial accuracy t a = 25 c 85 100 115 khz frequency, voltage stability vcc = 10.8 v to 15 v ? 1% 1% frequency, total variation line, temp 80 120 khz ramp peak voltage 4.5 5 5.5 v ramp amplitude voltage (peak to peak) 3.5 4 4.5 v peak current limit parameter test conditions min typ max units pklmt reference voltage ? 15 0 15 mv pklmt propagation delay 150 300 500 ns multiplier parameter test conditions min typ max units i mout , high-line low-power output current i ac = 500 a, vff = 4.7 v, vaout = 1.25 v, 0 c t a 85 c 0 ? 6 ? 20 i mout , high-line low-power output current i ac = 500 a, vff = 4.7 v, vaout = 1.25 v, ? 40 c t a 85 c 0 ? 6 ? 23 i mout , high-line high-power output current i ac = 500 a, vff = 4.7 v, vaout = 5 v ? 70 ? 90 ? 105 a i mout , low-line low-power output current i ac = 150 a, vff = 1.4 v, vaout = 1.25 v ? 10 ? 19 ? 50 i mout , low-line high-power output current i ac = 150 a, vff = 1.4 v, vaout = 5 v ? 268 ? 300 ? 345 i mout , iac-limited output current i ac = 150 a, vff = 1.3 v, vaout = 5 v ? 250 ? 300 ? 400 gain constant (k) i ac = 300 a, vff = 2.8 v, vaout = 2.5 v 0.5 1 1.5 1/v i ac = 150 a, vff = 1.4 v, vaout = 0.25 v 0 ? 2 1/v i ac = 500 a, vff = 4.7 v, vaout = 0.25 v 0 ? 2 a i mout , zero current i ac = 500 a, vff = 4.7 v, vaout = 0.5 v, 0 c t a 85 c 0 ? 3 a i ac = 500 a, vff = 4.7 v, vaout = 0.5 v, ? 40 c t a 85 c 0 ? 3.5 a power limit (i mout v ff ) i ac = 150 a, vff = 1.4 v, vaout = 5 v ? 375 ? 420 ? 485 w zero power parameter test conditions min typ max units zero power comparator threshold measured on vaout 0.175 0.330 0.500 v notes: 1. ensured by design. not production tested. 2. see figure 6 for reference variation. 3. see figure 5 for reference variation for vcc < 10.8 v .
slus419c ? august 1999 ? revised november 2001 5 www.ti.com electrical characteristics t a = 0 c to 70 c for the ucc3850x, ? 40 c to 85 c for the ucc2850x, t a = t j , vcc = 12 v, rt = 22 k ? , ct = 330 pf (unless otherwise noted) pfc gate driver parameter test conditions min typ max units gt1 pull up resistance i out from ? 100 ma to ? 200 ma 5 12 ? gt1 pull down resistance i out = 100 ma 2 10 ? gt1 output rise time c load = 1 nf, r load = 10 ? v gt1 from 0.7 v to 9.0 v 25 50 ns gt1 output fall time c load = 1 nf, r load = 10 ? v gt1 from 9.0 v to 0.7 v 10 50 ns maximum duty cycle 93% 95% 100% minimum controlled duty cycle f = 100 khz 2% second stage undervoltage lockout (uvlo2) parameter test conditions min typ max units pwm turn-on reference (uccx8500/501) 6.30 6.75 7.30 v hysteresis (uccx8500/501) 0.96 1.20 1.44 v pwm turn ? on reference (uccx8502/503) 6.30 6.75 7.30 v hysteresis (uccx8502/503) 2.4 3 3.6 v second stage soft-start parameter test conditions min typ max units ss2 charge current ? 7.3 ? 10 ? 12.5 a input voltage (verr) i verr = 2 ma,uvlo = low 300 mv ss2 discharge current enbl = high, uvlo = low, ss2 = 2.5 v 3 10 ma second stage duty cycle clamp parameter test conditions min typ max units maximum duty cycle 44% 50% second stage pulse-by-pulse current sense parameter test conditions min typ max units current sense comparator threshold verr = 2.5 v measured on isense2 0.94 1.05 1.15 v second stage overcurrent limit parameter test conditions min typ max units peak current comparator threshold 1.15 1.30 1.45 v input bias current 50 na second stage gate driver parameter test conditions min typ max units gt2 pull up resistance i out from ? 100 ma to ? 200 ma 5 12 ? gt2 pull down resistance i out = 100 ma 3 10 ? gt2 output rise time c load = 1 nf,r load = 10 ? v gt2 from 0.7 v to 9.0 v 25 50 ns gt2 output fall time c load = 1 nf,r load = 10 ? v gt2 from 9.0 v to 0.7 v 25 50 ns notes: 1. ensured by design. not production tested. 2. see figure 6 for reference variation. 3. see figure 5 for reference variation for vcc < 10.8 v .
slus419c ? august 1999 ? revised november 2001 6 www.ti.com pin assignments caout: ( current amplifier output) this is the output of a wide bandwidth operational amplifier that senses line current and commands the pfc pulse width modulator (pwm) to force the correct duty cycle. this output can swing close to gnd, allowing the pwm to force zero duty cycle when necessary. ct: (oscillator timing capacitor) a capacitor from ct to gnd sets the oscillator frequency according to: f 0.725 r t c t gnd: (ground) all voltages measured with respect to ground. vcc and vref should be bypassed directly to gnd with a 0.1- f or larger ceramic capacitor. the timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to gnd should be as short and direct as possible. gt1: (gate drive) the output drive for the pfc stage is a totem pole mosfet gate driver on gt1. use a series gate resistor of at least 10.5 ? to prevent interaction between the gate impedance and the gt1 output driver that m ight cause the gt1 to overshoot excessively. some overshoot of the gt1 output is always expected when driving a capacitive load. refer to figure 4 for gate drive resistor selections. gt2: (gate drive) same as output gt1 for the second stage output drive. limited to 50% maximum duty cycle. iac: (input ac current) this input to the analog multiplier is a current. the multiplier is tailored for very low distortion from this current input (i ac ) to mout, so this is the only multiplier input which should be used for sensing instantaneous line voltage. recommended maximum i ac is 500 a. isense1: (current sense) this is the non-inverting input to the current amplifier. this input and the inverting input mout remain functional down to and below gnd. isense2: (current sense) a resistor from the source of the lower fet to ground generates the input signal for the peak limit control of the second stage. the oscillator ramp can also be summed into this pin, for slope compensation. mout: (multiplier output and current sense amplifier inverting input) the output of the analog multiplier and the inverting input of the current amplifier are connected together at mout. as the multiplier output is a current, this is a high impedance input so the amplifier can be configured as a differential amplifier to reject ground noise. multiplier output current is given by: i mout v vaout 1.0 i iac k v vff 2 connect current loop compensation components between mout and caout. ovp/enbl: (over-voltage/enable) a window comparator input which disables the pfc output driver if the boost output is 6.67% above nominal or disables both the pfc and second stage output drivers and reset ss2 if pulled below 1.9 v. this input is also used to determine the active range of the second stage pwm. pklmt: (pfc peak current limit) the threshold for peak limit is 0 v. use a resistor divider from the negative side of the current sense resistor to vref to level-shift this signal to a voltage corresponding to the desired overcurrent threshold across the current sense resistor. pwrgnd: ground for totem pole output drivers. rt: (oscillator charging current) a resistor from rt to gnd is used to program oscillator charging current. a resistor between 10 k ? and 100 k ? is recommended. nominal voltage on this pin is 3 v.
slus419c ? august 1999 ? revised november 2001 7 www.ti.com pin assignments (continued) ss2: (soft-start for pwm) ss2 is at ground for either enable low or ovp/enbl below the uvlo2 threshold conditions. when enabled, ss2 charges an external capacitor with a current source. this voltage is used as the voltage error signal during start-up, enabling the pwm duty cycle to increase slowly. in the event of a disable command or a uvlo2 dropout, ss2 quickly discharges to disable the pwm. vaout: (voltage amplifier output) this is the output of the operational amplifier that regulates output voltage. the voltage amplifier output is internally limited to approximately 5.5 v to prevent overshoot. vcc: (positive supply voltage) connect to a stable source of at least 20 ma between 12 v and 17 v for normal operation. bypass vcc directly to gnd to absorb supply current spikes required to charge external mosfet gate capacitances. to prevent inadequate gate drive signals, the output devices are inhibited unless vcc exceeds the upper under-voltage lockout threshold and remains above the lower threshold. verr: (voltage amp error signal for the second stage) the error signal is generated by an external amplifier which drives this pin. this pin has an internal 4.5-v voltage clamp that limits gt2 to less than 50% duty cycle to ensure transformer reset in the typical application. vff: (rms feed forward signal) vff signal is generated at this pin by mirroring one-half of i ac into a single pole external filter. at low line, the vff voltage should be 1.4 v. vsense: (voltage amplifier inverting input) this is normally connected to a compensation network and to the boost converter output through a divider network. vref: (voltage reference output) vref is the output of an accurate 7.5-v voltage reference. this output is capable of delivering 10 ma to peripheral circuitry and is internally short-circuit current limited. vref is disabled and remains at 0 v when vcc is below the uvlo threshold. bypass vref to gnd with a 0.1- f or larger ceramic capacitor for best stability.
slus419c ? august 1999 ? revised november 2001 8 www.ti.com block diagram udg ? 98189 vref 20 14 12 11 9 4 17 16 gt1 pwrgnd isense1 vcc ovp/enbl vaout 1.9 v pklmt 7.5 v reference uvlo 16 v/10 v 10.5 v/10 v vcc 15 oscillator 2 rt 5 ct s q r pwm latch caout ss2 voltage error amp 8.0 v 13 1 3 vsense vff 19 iac 18 mout mirror 2:1 7.5 v enable pfcovp x x mult clk1 current amp 6.75 v 6 gnd 10 gt2 vcc 7 8 clk2 1.5 v r i limit clk2 osc clk1 clk2 verr isense2 i limit s q uvlo2 pwm 0.33 v (v ff ) 2 zero power second stage soft start + + pwm + + + + + + + + 4.5 v pwm 2nd stage section pfc section pwm 2nd stage section pfc section 1.3 v r r
slus419c ? august 1999 ? revised november 2001 9 www.ti.com typical characteristics figure 1 multiplier output current vs. voltage error amplifier output 50 200 250 350 0 100 300 150 iac = 150 a iac = 300 a iac = 500 a i mout - multiplier output current ? a vaout ? voltage error amplifier output ? v 01 23 45 figure 2 multiplier gain vs. voltage error amplifier output 0.7 1.1 1.3 1.5 0.5 0.9 iac = 300 a iac = 500 a iac = 150 a multiplier gain ? k vaout ? voltage error amplifier output ? v 12 345 figure 3 vff ? feedforward voltage ? v 100 300 400 500 0 200 vaout = 3 v vaout = 2 v vaout = 4 v vaout = 5 v (vff i mout ) ? w multiplier constant power performance 0 1234 5 figure 4 10 12 14 16 20 10 14 15 17 8 12 18 9 11 13 16 recommended minimum gate resistance vs. supply voltage r gate - recommended minimum gate resistance ? ? vcc ? supply voltage ? v
slus419c ? august 1999 ? revised november 2001 10 www.ti.com figure 5 14 12 10 7.45 7.50 7.55 7.60 7.40 vcc ? supply voltage ? v 13 11 9 vref ? reference voltage ? v reference voltage vs. supply voltage figure 6 reference voltage vs. reference current 0 5 10 15 20 25 7.495 7.500 7.505 7.510 7.490 vref ? reference voltage ? v i vref ? reference current ? ma
slus419c ? august 1999 ? revised november 2001 11 www.ti.com typical application the ucc38500 series is designed to incorporate all the control functions required for a power factor correction circuit and a second stage dc-to-dc converter. the pfc function is implemented as a full-feature, average-current-mode controller integrated circuit. in addition, the input voltage feedforward function is implemented in a simplified manner. current from iac input is mirrored over to the vff pin. by simply adding a resistor and capacitor (to attenuate 120-hz ripple) a voltage is developed which is proportional to rms line voltage, eliminating the need for several components normally connected to the line. the ucc3850x uses leading-edge modulation for the pfc stage and trailing-edge modulation for the dc-to-dc stage. this r educes ripple current in the output capacitor by reducing the overlap in conduction time of the pfc and dc-to-dc switches. figures 7 and 8 depict the ripple current reduction in the boost switch. in addition to the reduced ripple current, noise immunity is improved through the current error amplifier implementation. please refer to the ucc3817 datasheet (ti literature no. slus395) for a detailed explanation of current error amplifier implementation. udg ? 97130 ? 1 figure 7. simplified representation of a 2 ? stage pfc power supply i cbst i cbst = i d1 ? i q2 figure 8. timing waveforms for synchronization scheme
slus419c ? august 1999 ? revised november 2001 12 www.ti.com typical application the ucc3850x is optimized to control a boost pfc stage operating in continuous conduction mode, followed by a dc-to-dc converter (typically a forward topology). the dc-to-dc converter is transformer isolated and therefore its error amplifier is located on the secondary side. for this reason the ucc3850x is configured without an internal error amplifier for the second power stage. the externally generated error signal is fed into the verr pin typically through an opto coupler. the ucc3850x can be configured for voltage-mode control or current-mode control of the second stage. the application figure shows a typical current-mode configuration. for voltage-mode control, the ramp generated by ct can be fed back into the isense2 pin through a voltage divider. one of the main system challenges in designing systems with a pfc front end is coordinating the turn-on and turn-off on the dc-to-dc converter. if the dc-to-dc converter is allowed to turn on before the boost converter is operational, it must operate at a much-reduced voltage and therefore represents a large current draw to the boost converter. this start-up sequencing is handled internally by the ucc3850x. the ucc3850x monitors the output voltage of the pfc converter and holds the dc-to-dc converter off until the output is within 10% of its regulation point. once the trip point is reached the dc-to-dc section goes through a soft start sequence for a controlled, low stress start-up. similarly, if the output voltage drops too low (two voltage options are available) the dc-to-dc converter shuts down thereby preventing overstress of the converter. for the ucc38500 and ucc38501, the dc-to-dc converter shuts down when the pfc output falls below 74% of its nominal value, while for the ucc38502 and ucc38503, the threshold is lowered to 50%. design example: an off-line, 100-w, power converter the following design example shows how to implement the ucc38500 in an off-line 100-w power converter. the system requires the converter to operate from a universal input of 85 v rms to 265 v rms with a 12-v, 100-w, dc output. this design example is divided into two parts. the first part is the pfc stage design and the second section is the dc-to-dc power stage design. the design goal of the system is to achieve an efficiency of approximately 80%. this is accomplished by requiring the boost regulator to be designed for an efficiency of 95% and the dc-to-dc power stage to be designed for 85% efficiency. the efficiency of the boost converter is designated by variable 1 and the efficiency of the dc-to-dc converter is designated by variable 2. figure 9 shows the schematic of the typical application upon which this design example is based. the ucc38500 control device is chosen for this design because of it ? s self-biasing scheme and minimum input voltage requirements of the dc-to-dc power stage.
slus419c ? august 1999 ? revised november 2001 13 www.ti.com udg ? 99138 12 10 9 5 2 6 11 13 7 8 4 3 1 16 17 15 18 19 14 20 ovp/enbl vsense vaout isense mout caout iac vff pklimit vref gt1 gt2 vcc ct rt gnd pwrgnd ss2 verr isense2 ucc38500 v ref q5 r25 v cc r7 r6 gt1 gt2 d10 d9 c27 pklimit c28 r17 c19 c22 r28 c25 r23 r34 r21 r22 r33 r20 c2 r15 r5 l1 d3 d1 gt1 r14 r29 pklimit r19 c26 v ref r18 r24 c29 c30 isense2 gt2 r13 r2 c5 pwr gnd gt2 12v 10a + ? l2 t1 q2 q1 q3 d11 vac 85 ? 265v rms d6 d4 t2 d8 u1 c7 sgnd sgnd sgnd pgnd2 pgnd pgnd pgnd pgnd sgnd pgnd d5 d7 c12 c20 l1 v cc bias circuit v cc v cc bias circuit pgnd c23 pgnd2 pgnd2 d14 r36 r16 c14 r35 r27 d13 r31 c8 r30 r10 r12 r11 c21 c16 c3 pgnd c24 d2 r1 c4 c18 r4 c6 d15 d12 d16 ac ? n ac ? l vout + vout ? v ref r3 r39 c13 isense2 c17 h11av1 3 2 1 4 5 6 u3 sgnd r38 c15 q5 figure 9. typical application circuit
slus419c ? august 1999 ? revised november 2001 14 www.ti.com typical application i. pfc boost power stage lboost (l1 in figure 9) the boost inductor value is determined by the following equations : i p out 0.25 2 1 2 v in (min) , d 1 v in (min) 2 v boost , l boost v in (min) 2 d i f s where ? i, the inductor current ripple was set to approximately 25% of the peak inductor current. in this design example ? i is approximately 505 ma. d represents the duty cycle at the peak of low line voltage, v in(min) is the minimum rms input voltage, and v boost is the controlled output voltage of the pfc stage. v boost for this design is selected to be 385 v to ensure the pfc stage regulates for the full input voltage range. variable f s represent the switching frequency. the switching frequency was selected to be 100 khz for this design. the calculated boost inductor required for this design is approximately 1.7 mh. cboost (c2 in figure 9) two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. the value of capacitance is determined by the holdup time required for supporting the load after the input ac voltage is removed. hol dup is the amount of time that the output stays in regulation after the input has been removed. for this circuit, the desired holdup time is approximately 16 ms. expressing the capacitor value in terms of output power, output voltage, and holdup time is described in equation (4): c boost 2 p out t v boost 2 v boost (min) 2 in practice, the calculated minimum capacitor value may be inadequate because output ripple voltage specifications limit the amount of allowable output capacitor esr. attaining a sufficiently low value of esr often necessitates the use of a much larger capacitor value than calculated. the amount of output capacitor esr allowed is determined by dividing the maximum specified output ripple voltage by the capacitor ripple current. in this design, holdup time is the dominant determining factor and a 100 f, 450 v aluminum electrolytic capacitor from panasonic, part number ecos2tb101ba, is used. the voltage rating and the low esr of 0.663 ? make it an ideal choice for this design. (1) (2) (3) (4)
slus419c ? august 1999 ? revised november 2001 15 www.ti.com typical application power switch selection (q3 in figure 9) as in any power supply design, tradeoffs between performance, cost and size are necessary. when selecting a power switch, it is useful to calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter. total power dissipation in the switch is the sum of switching loss and conduction loss. switching losses are the combination of the gate charge loss, drain source capacitance of the mosfet loss and turnon and turnoff losses: p gate q gate v gate f s p coss 1 2 c oss v off 2 f s p sw 1 2 v off i l t on t off f s where q gate is the total gate charge, v gate is the gate drive voltage, f s is the switching frequency, c oss is the drain source capacitance of the mosfet, t on and t off are the switching times (estimated using device parameters r gate , q gd and v th ) and v off is the voltage across the switch during the off time, in this case v off = v boost . conduction loss is calculated as the product of the r ds(on) of the switch (at the worst case junction temperature) and the square of rms current: p cond r ds(on) k i rms 2 where k is the temperature factor found in the manufacturer ? s r ds(on) vs junction temperature curves. calculating these losses and plotting against frequency gives a curve that enables the designer to determine either which manufacturer ? s device has the best performance at the desired switching frequency, or which switching frequency has the least total loss for a particular power switch. for this design example an irfp450 hexfet from international rectifier is chosen because of its low r ds(on) and its v dss rating. the irfp450 ? s r ds(on) of 400 m ? and the maximum v dss of 500 v makes it an ideal choice. a comprehensive review of this procedure can be found in the unitrode power supply design seminar sem ? 1200, topic 6, ti literature no. slup117. more recently, faster switching insulated gate bipolar transistors (igbts) have become widely available. depending on the system power level (and the switching frequency), use of igbts may make sense for the power switch. boost diode selection (d3 in figure 9) in order to keep the switching losses to a minimum and meet the voltage and current requirements, a hfa08tb60 fast recovery diode from international rectifier is selected for the design. this diode is rated for a maximum reverse voltage of 600 v and a maximum forward current of 8 a. the typical reverse recovery of 18 ns made this diode ideal for this design. (5) (6) (7) (8)
slus419c ? august 1999 ? revised november 2001 16 www.ti.com typical application peak current limit resistor divider r14 and r29 along with current sense resistor r5, devise the peak-limit comparator of the ucc38500 and are used to protect the boost switch q3 from excessive currents. proper preparation of this comparator requires that it not interfere with the boost converter ? s power limit or the forward converter ? s pulse-by-pulse current limiting. for this design example the forward converter is selected to go into pulse-by-pulse current limiting at approximately 130% of maximum output power. the power limit of the boost converter is set at 140% of the maximum output power. the peak current limit for the boost stage was selected to engage at 150% of the maximum output power to ensure circuit stability. the following equation is used to select the current-sense resistor r5, where the current-sense resistor is selected to operate over a 1-v dynamic range (v dynamic ). the current-sense resistor required for the design needed to be approximately 0.43 ? . r5 r sense v dynamic i pk ( 0.5 ) i 0.43 the following equation is used to size resistor r14 properly by first selecting r29 to be a standard resistance value. for this design resistor r29 was selected to be 10 k ? . with a typical reference voltage (v ref ) of 7.5 v gives a calculated value of approximately 1.91 k ? for resistor r14. r14 p out 1.5 2 v in (min) 1 2 i r5 r29 v ref multiplier the output of the multiplier of the ucc38500 is a signal representing the desired input line current. it is an input to the current amplifier, which programs the current loop to control the input current to give high power-factor operation. as such, the proper functioning of the multiplier is key to the success of the design. the inputs to the multiplier are v vaout , the voltage amplifier output, i iac , a representation of the input rectified ac line voltage, and an input voltage feed forward signal, v vff . the output of the multiplier, i mout , can be expressed: i mout i iac v vaout 1 k v vff 2 where k is a constant typically equal to 1 / v. the i iac signal is obtained through a high-value resistor connected between the rectified ac line and the iac pin of the ucc3850x. this resistor (r iac ) is sized to provide the maximum i iac current at high line. for the ucc3850x the maximum i iac current is about 500 a, and a higher current can drive the multiplier out of its linear range. a smaller current level is functional, but noise can become an issue, especially at low input line. assuming a universal line operation of 85 v rms to 265 v rms gives a r iac value of 750 k ? . because of voltage rating constraints of the standard 1/4-w resistor, this application requires a combination of lower value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. for this design example two 383 k ? resistors are used in series. (9) (10) (11)
slus419c ? august 1999 ? revised november 2001 17 www.ti.com typical application the current into the iac pin is mirrored internally to the vff pin where it is filtered to produce a voltage feed forward signal proportional to line voltage. the vff voltage is used to keep the power stage gain constant and to providing input power limiting. please refer to texas instruments application note on power limiting with sinusoidal input ti literature no. slua196, for detailed explanation on how the vff pin provides power limiting. the following equation is used to determine the vff resistor size (r vff ) to provide power limiting where v in(min) is the minimum rms input voltage and r iac is the total resistance connected between the iac pin and the rectified line voltage. r vff 1.4 v v in (min) 0.9 2 r iac 28.7 k because the vff voltage is generated from line voltage it needs to be adequately filtered to reduce total harmonic distortion caused by the 120-hz rectified line voltage. refer to unitrode power supply design seminar, sem ? 700 topic 7, optimizing a high power factor switching preregulator , ti literature no. slup093. a single pole filter is adequate for this design. assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is: 1.5% 66% 0.022 with a ripple frequency (f r ) of 120-hz and an attenuation of 0.022 requires that the pole of the filter (f p ) be placed at: f p 120 hz 0.022 2.6 hz the following equation is used to select the filter capacitor (c vff ) required to produce the desired low pass filter. c vff 1 2 r vff f p 2.2 f this results in a single-pole filter, which adequately attenuates the harmonic distortion and provides power limiting. the r mout resistor is sized to provide power limiting for the circuit. the power limit is set to 140% of the maximum output power. this is done so that the power limit of the pfc stage does not interfere with power limiting of the dc-to-dc converter, which is set to 130% of the maximum output power. the following equations are used to size the r mout resistor, r19. in these equations p limit is the power limit level, p out is the maximum output power. i mout(max) is the maximum multiplier output current, i iac @v in(min) is the minimum current into the iac pin at low line and v vaout(max) is the maximum voltage amplifier output voltage. for this design r19 and r15 need to be approximately 3.57 k ? . p limit p out 1.4 1 2 i mout(max) i iac @v in(min) v vaout(max) 1v k v ff 2 (12) (13) (14) (15) (16) (17)
slus419c ? august 1999 ? revised november 2001 18 www.ti.com typical application r mout p limit 2 r sense v in (min) i mout(max) current loop the ucc38500 current amplifier has the input from the multiplier applied to the inverting input. this change in architecture from previous texas instruments pfc controllers improves noise immunity in the current amplifier. it also adds a phase inversion into the control loop. the ucc38500 takes advantage of this phase inversion to implement leading-edge duty cycle modulation. please refer to figure 10 for the typical configuration of the current amplifier. the following equation defines the gain of the power stage, where v p is the voltage swing of the oscillator ramp, 4 v for the ucc38500. g id (s) v boost r sense s l boost v p in order to have a good dynamic response the crossover frequency of the current loop was set to 10% of the switching frequency. this can be achieved by setting the gain of the current amplifier (g ca ) to the inverse of the current loop power stage gain at the crossover frequency. this design requires that the current amplifier have a gain of 2.581 at 10 khz. g ca 1 g id (s) 2.581 r i is the r mout resistor, previously calculated to be 3.57 k ? (refer to figure 10). the gain of the current amplifier is r f /r i , so multiplying r i by g ea gives the value of r f , in this case approximately 9.09 k ? . setting a zero at the crossover frequency and a pole at half the switching frequency to roll off the high-frequency gain completes the current loop compensation. c z 1 2 r f f c c p 1 2 r f f s 2 (18) (19) (20) (21) (22)
slus419c ? august 1999 ? revised november 2001 19 www.ti.com typical application r i + ? r f c p caout c z figure 10. current loop compensation voltage loop the second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. this ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple at the input to the multiplier. the voltage loop must be compensated not just for stability but also to attenuate the contribution of this ripple to the total harmonic distortion of the system (refer to figure 11). r in r d + ? r f c f v ref v out c z figure 11. voltage amplifier configuration the gain of the voltage amplifier, g va , can be determined by first calculating the amount of peak ripple present on the output capacitor v opk. the peak value of the second harmonic voltage is given by equation (23), where f r is the frequency of the rectified line voltage. for this design f r is equal to 120 hz. v opk p in 2 f r c boost v boost (23)
slus419c ? august 1999 ? revised november 2001 20 www.ti.com typical application in this example v opk is equal to 4 v. assuming an allowable contribution of 0.75% (1.5% peak-to-peak) from the voltage loop to the total harmonic distortion budget sets the gain equal to: g va v vaout ( 0.015 ) 2 v opk where ? v vaout is the ef fective output voltage range of the error amplifier (5 v for the ucc38500). the network needed to realize this filter is comprised of an input resistor, r in , and feedback components c f , c z , and r f . the value of r in is already determined because of its function as one-half of a resistor divider from v out feeding back to the vo ltage amplifier for output voltage regulation. in this case the value is 1.12 m ? . this high value was chosen to reduce power dissipation in the resistor. in practice, the resistor value would be realized by the use of two 560-k ? resistors in series because of the voltage rating constraints of most standard 1/4 w resistors. the value of c f is determined by the equation: c f 1 2 f r g va r in in this example c f equals 150 nf. resistor r f and c f generate a pole in the voltage amplifier feedback to reduce total harmonic distortion (thd). the location of the pole is found by setting the gain of the loop equation to one and solving for the crossover frequency. the frequency, expressed in terms of input power, is calculated by the equation: f vi p in 2 v vaout v out r in c boost c f f vi for this converter is 10 hz. a derivation of this equation can be found in the unitrode power supply design seminar sem ? 1000, topic 1, power factor correction circuit, ti literature no. slup106. solving for r f becomes: r f 1 2 f vi c f or r f equals approximately 118 k ? . due to the low output impedance of the voltage amplifier, capacitor c z is added to improve dc regulation. to maintain good phase margin, the zero from c z is set to 10% of f vi . for this design, c z is a 2.2- f capacitor. the following equation is used to calculate c z . c z 1 2 f vi 10 r f (24) (25) (26) (27) (28)
slus419c ? august 1999 ? revised november 2001 21 www.ti.com typical application ii. two switch forward dc ? to ? dc power stage a two-switch forward converter topology was selected for the second stage of this design. the two-switch forward power converter has two major advantages over a traditional forward converter, making it ideal for this application. first, the fets used in the two-switch forward required only one-half the maximum v ds as compared to the traditional forward converter. second, the transformer ? s reset energy is returned to the input through clamping diodes for higher efficiency. transformer turns ratio equation (29) calculates the transformer turns ratio required for the two-switch forward power converter of this design example. it can be derived from the dc transfer function of a forward converter. v out is the output voltage of the forward converter and is 12-v for this design. v f is the forward voltage drop of the secondary rectifier diode and is set to 1v. v boost(min) is the minimum input voltage to the forward converter. the level of this voltage is determined by where the control device forces the dc-to-dc converter into undervoltage lockout (uvlo). the ucc38500 control device is configured to drive the dc-to-dc power stage into uvlo at approximately 74% of the nominal boost converters output voltage. v boost(min) for this design is approximately 285 v. d max is 0.44 and is the guaranteed maximum duty cycle of the forward converter. for this design example the calculated turns ratio is approximately 0.101. transformer turns v out v f v boost(min) d max n s n p output inductor the following equations can be used to calculate the inductor required for this design example. first, the minimum duty cycle d min , which occurs at the maximum boost voltage, needs to be calculated. the maximum boost voltage is limited by the ovp trip point, which is set to approximately 425 v. for this design d min is approximately 31%. the output inductor ripple current ( ? i l ) for this design is given at 30% of the maximum load current. next calculate the output inductor (l), where the switching frequency (f s ) is 100 khz. the calculated output inductor for this design is approximately 38 h. d min v out v f v boost(min) n s n p i l p out 0.3 v out l v out v f 1 d min i l f s (29) (30) (31) (32)
slus419c ? august 1999 ? revised november 2001 22 www.ti.com typical application output capacitor the following equations can be used to estimate the minimum output capacitance and the capacitor ? s maximum allowable equivalent series resistance (esr), where c out is the minimum output capacitance and t s is the period of the switching frequency. ? v out is the maximum allowable output ripple voltage, selected as approximately 1% of the output voltage. for this design, the minimum calculated output capacitance is 170 f and the maximum allowable esr is 96 m ? . a panasonic hfq 1800- f electrolytic capacitor with an esr of 0.048 ? is used. c out 1 8 v out v f d max t s 2 l v out esr v out i l r sense2 the dc-to-dc power converter is designed for peak current mode control. r sense2 is the resistor that senses the current in the forward converter. the sense resistor in figure 9 is referred to as r4. the following equations can be used to calculate r sense2 . where i m is the magnetizing current of the transformer used in the step-down converter and v boost is the output voltage of the boost stage. d is the typical duty ratio of the forward converter. v isense2_peak is the peak current sense comparator voltage that is typically 1.15 v. for this design example l m is approximately 8 mh and the r sense2 is approximately 1 ? . i m v boost l m d f s r sense2 v isense2_peak i m n s n p i l 2 i out(max) 1.3 soft-start the ucc38500 has soft-start circuitry to allow for a controlled ramp of the second stage ? s duty cycle during start-up. this is accomplished through the ss2 circuitry described earlier in this data sheet. equation (37) calculates the approximate capacitance needed based on the designer ? s soft-start requirements. where i ss2 is the soft-start charging current, which is typically 10 a. ? t is the desired soft start time, which was selected to be approximately 5 ms for this example. the calculated soft-start capacitor (c ss ) for this example is approximately 10 nf. c ss i iss2 t 4.5 slope compensation when designing with peak current-mode control, slope compensation may be necessary to prevent instability. in this design, the magnetizing current provided more than enough slope compensation. if slope compensation is needed with external components, please refer to unitrode/texas instruments application note, practical considerations in current mode power supplies , ti literature no. slua110. (33) (34) (35) (36) (37)
slus419c ? august 1999 ? revised november 2001 23 www.ti.com typical application control loop figure 12 shows the control block diagram for the typical application shown in figure 9. g c (s) is the compensation net work ? s transfer function (tf), g opto (s) is the opto-isolator tf, g co (s) is the control-to-output tf, and h(s) is the divider tf. the following equations can be used to estimate the frequency response of each gain block, where f opto_pole is the frequency, where the optoisolator is ? 3 db from its dc operating point, and v ref_tl431 is the reference voltage of the tl431 shunt regulator. r load represents the typical load impedance for the design. g opto (s) r13 r36 1 1 s 2 f opto_pole g c (s) s r35 c14 1 s c14 r31 ( 1 ( s r35 c15 )) r13 r36 1 1 s 2 f opto_pole h(s) r27 r27 r31 v vref_tl431 v out g co (s) v out v c r load r sense2 n p n s 1 s c out esr 1 s c out r load v ref_tl431 g c (s) g co (s) v boost v out h(s) v c figure 12. ucc38500 control block (38) (39) (40) (41)
slus419c ? august 1999 ? revised november 2001 24 www.ti.com typical application figure 13 shows the circuitry for the voltage feedback loop. d13 is a tl431 shunt regulator that functions as an operational amplifier, providing feedback control. v c = v err g co(s) udg ? 01091 r13 pgnd2 r27 q5 d14 r36 r16 d13 r31 h11av1 3 2 1 4 5 6 u3 sgnd v ref v boost v out c14 r35 c15 g co (s) figure 13. ucc38500 feedback loop initially the desi gner must select the resistor values for the divider gain h(s). equation (42) is used to determine resistor size. selecting r27 to be a standard value of 10-k ? requires r31 to be approximately 38.3 k ? . r31 r27 v out v ref v ref it is important to correctly bias the tl431 and the optoisolator for proper operation. zener diode d14 and a depletion mode j-fet, q5, supply the bias voltage for the tl431. resistors r16 and r13 provide the minimum bias currents for the tl431 and the optoisolator respectively and can be calculated with the following equations. where i op(min) is the minimum optoisolation current, and v verr(max) is the maximum voltage seen at the verr pin of the ucc38500. verr has an internal clamp that limits this pin to 4.5 v. v f is the typical forward voltage of the diode in the opto isolator, and i tl431(min) is the minimum cathode current of the tl431. for the components used in this design example r13 is calculated to be approximately 2.0 k ? and r16 was calculated to be approximately 680 ? . the optoisolator is configured to have dc gain of approximately 20 db and the optoisolator ? 3 db point is approximately 8 khz. figure 14 shows the frequency response of the optoisolator. (42)
slus419c ? august 1999 ? revised november 2001 25 www.ti.com typical application r16 v f i tl431 (min) r13 v ref v verr (max) i op (min) to compensate the loop, it is necessary to estimate or measure the control-to-output gain ? s frequency response g co (s). the frequency response for g co (s) was measured with a network analyzer and the measured frequency response is shown in figure 15. figure 14 optoisolator transfer function (gain and phase) vs. frequency ? 20 0 100 20 ? 60 ? 40 60 40 60 180 120 0 ? 60 ? 180 ? 120 1 k 10 k 100 k f ? frequency ? hz gain ? db phase ? degrees phase gain figure 15 100 1 k 10 k 100 k ? 40 ? 50 ? 20 ? 30 0 ? 10 20 10 30 50 40 ? 144 ? 180 ? 72 ? 108 0 ? 36 72 36 108 180 144 gain ? db phase ? degrees power stage control-to-output transfer function (gain and phase) vs. frequency f ? frequency ? hz gain phase after determining the frequency response of g co (s) it is necessary to define some closed loop frequency response design goals. the following equation describes the frequency response of the loop gain (t(s) db ) of the system in decibels. typically, the loop is designed to crossover at a frequency below one-sixth of the switching frequency. in order for this design example to have good transient response, the design goal is to have the loop gain crossover at approximately 1 khz, which is less than one-sixth of the switching frequency. the gain crossover frequency for this design example is referenced as f c . t(s) db g c (s) g co (s) h(s) the compensation network that is used (g c (s)) has three poles and one zero. one pole occurs at the origin, and a second pole is caused by the limitations of the opto-isolator. the third pole is set to attenuate the high-frequency gain and needs to be set to one-half of the switching frequency. the zero is set at the desired crossover frequency. the following equations can be used to select r35, c14 and c15, where g co (s), g opto (s), and h(s) are the gains in decibels (db) of each control block at the desired f c . from the graphs in figures 14 and 15 it can be observed at the desired crossover frequency g co (s) is approximately 0 db and g opto (s) is approximately (43) (44) (45)
slus419c ? august 1999 ? revised november 2001 26 www.ti.com 23 db. therefore the compensation circuitry needs to have a gain of ? 23 db at the desired crossover frequency. for this example r35 is calculated at approximately 18.2 k ? . capacitor c14 is estimated to be approximately 10 nf and c15 is calculated at approximately 180 pf. h(s) 20 log v ref v out
r35 r31 10 g co (s) db g opto (s) db h(s) db c14 1 2 r35 f c c15 1 2 r35 f sw 2 figure 16 shows the frequency response of the compensation network g c (s) and figure 17 shows the measured frequency response of the loop gain t(s). the frequency response characteristics in figure 17 show that f c is approximately 1.5 khz with a phase margin of about 55 degrees. the gain margin is approximately 50 db. figure 16 feedback control transfer function (gain and phase) vs. frequency ? 20 0 100 20 ? 60 ? 40 60 40 60 180 120 0 ? 60 ? 180 ? 120 1 k 10 k 100 k compensation gain compensation phase g opto ? gain ? db phase ? degrees f ? frequency ? hz ? 20 0 20 ? 60 ? 40 60 40 100 1 k 10 k 100 k 60 180 120 0 ? 60 ? 180 ? 120 figure 17 g opto ? gain ? db phase ? degrees total loop transfer function (gain and phase) vs. frequency f ? frequency ? hz loop gain loop phase (46) (47) (48) (49)
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