1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv7224 features hvcmos ? technology symmetric row drive (reduces latent imaging in actfel displays) output voltage up to +240v low power level shifting source/sink current minimum 70ma shift register speed 3.0mhz pin-programmable shift direction (dir, shift) ? ? ? ? ? ? ? functional block diagram 40-channel symmetric row driver general description the hv7224 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. it is especially suitable for use as a symmetric row driver in ac thin-?lm electroluminescent (actfel) displays. when the data reset pin (dr io a/dr io b) is at logic high, it will reset all the outputs of the internal shift register to zero. at the same time, the output of the shift register will start shifting a logic high from the least signi?cant bit to the most signi?cant bit. the dr io a/ dr io b can be triggered at any time. the dir and shift pins control the direction of data shift through the device. when dir is at logic high, dr io a is the input and dr io b is the output. when dir is grounded, dr io b is the input and the dr io a is the output. see the output sequence operation table for output sequence. the pol and oe pins perform the polarity select and output enable function respectively. data is loaded on the low to high transition of the clock. a logic high will cause the output to swing to vpp if pol is high, or to gnd if pol is low. all outputs will be in high-z state if oe is at logic high. data output buffers are provided for cascading devices. hv out 1 hv out 2 hv out 40 oe clk dir pol shift p n gnd level translator vdd vpp dr io a dr io b s/r p n p n level translator level translator
2 hv7224 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package option 64-lead pqfp (3-sided) 20.00x14.00mm body 3.40mm height (max) 0.80mm pitch 3.90mm footprint hv7224 HV7224PG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value supply voltage, v dd -0.5v to +7.0v supply voltage , v pp -0.5v to +260v logic input levels -0.5v to v dd + 0.5v continuous total power dissipation 1 1200mw operating temperature range -40c to +85c storage temperature range -65c to +150c lead temperature 1.6mm from case for 10 seconds 260c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note: for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c. 1. recommended operating conditions sym parameter min max units v dd logic supply voltage 4.5 5.5 v v pp high voltage supply 1 0 240 v v ih high-level input voltage 0.7 v dd v dd v v il low-level input voltage 0 0.2v dd v f clk clock frequency - 3.0 mhz t a operating free-air temperature -40 +85 c i o high voltage output current - 70 ma i od allowable pulsed current through output diode - 300 ma note: output will not switch at v pp = 0v. power-up sequence should be the following: connect ground. apply v dd . set all inputs (data, clk, enable, etc.) to a known state. apply v pp . the v pp should not drop below v dd or ?oat during operation. power-down sequence should be the reverse of the above. 1. 1. 2. 3. 4. pin con?guration 1 64 product marking l = lot number yy = year sealed ww = week sealed c = country of origin a = assembler id = green packagin g top marking h v 7 2 2 4 p g l l l l l l l l l l y y w w c c c c c c c c a a a 64-lead pqfp (3-sided) (pg) 64-lead pqfp (3-sided) (pg) (top view) package may or may not include the following marks: si or
3 hv7224 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com dc electrical characteristics (over recommended operating conditions of v dd = 5.0v, v pp = 240v, and t a = 25c unless noted) sym parameter min max units conditions i dd v dd supply current - 10 ma f clk = 3.0mhz, v dd = 5.5v i pp v pp supply current - 2.0 ma all outputs low or high-z - 4.0 ma one output high 1 i ddq quiescent v dd supply current - 100 a all v in = gnd or v dd v oh high-level output hv out 190 - v i o = -70ma data out 4.5 - v i o = -100 a v ol low-level output hv out - 50 v i o = +70ma data out - 0.5 v i o = +100 a i ih high-level logic input current - 1.0 a v ih = v dd i il low-level logic input current - -1.0 a v il = 0v i sat hv out saturation current p-channel -80 - ma --- n-channel 75 - ma --- note: only one output can be turned on at a time. 1. ac electrical characteristics (v dd = 5.0v and t a = 25c) sym parameter min max units conditions f clk clock frequency - 3.0 mhz per register, c l = 15pf t wh , t wl clock width high or low 150 - ns --- t sud data set-up time before clock rises 50 - ns --- t hd data hold time after clock rises 50 - ns --- t suc hv out delay from clock rises (hi-z to h or l) - 1.0 s c l = 330pf // r l = 10k t sue hv out delay from output enable falls - 600 ns c l = 330pf // r l = 10k t hc hv out delay from clock rises (h or l to hi-z) - 2.0 s c l = 330pf // r l = 10k t he hv out delay from output enable rises - 600 ns c l = 330pf // r l = 10k t dhl delay time clock to data output falls* - 250 ns c l = 15pf t dlh delay time clock to data output rises* - 250 ns c l = 15pf t onf hv out fall time - 2.0 s c l = 330pf // r l = 10k t onr hv out rise time - 2.0 s c l = 330pf // r l = 10k t pow pol pulse width 3.0 - s --- t oew output enable pulse width 3.0 - s --- sr slew rate, v pp - 45 v/s one active output driving 4.7nf load note: * the delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. there is an internal delay for the data output which is equal to t wh .
4 hv7224 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com input and output equivalent circuits switching waveforms vd d vp p hv ou t logic input s gn d (logic ) data out logic data output high voltage output s vd d gn d (logic ) gn d (power) data reset inpu t (d r io a/dr io b) 50 % 50 % t po w data reset output (d r io a/dr io b) t hd 50 % 50 % high impedanc e 90 % 10 % 10 % 90 % t su e t onr 90 % t he 10 % 50 % t dl h 50 % t dh l 50 % t oe w 50 % high impedance high impedanc e high impedance 90 % 10 % 10 % 90 % t su c t onr 90 % t hc 10 % hv ou t (pol = h) (pol = l) po l oe data valid t su d data vali d cl k t wl 1/ f clk 50% 50% 50% 50% t wh t su c t onf t hc t su e t onf t he v ih v il v oh v ol hv ou t hv ou t hv ou t v ih v il v ih v il v ih v il v oh v ol v oh v ol
5 hv7224 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com function table i/o relations inputs hv outputs clk dir s/r data pol oe o/p high x x h h l h o/p off x x l x l high-z o/p low x x h l l l o/p off x x x x h all o/p high-z notes: h = logic high level, l = logic low level, x = irrelevant data input (dr io ) loaded on the low-to-high transition of the clock. only one active output can be set at a time. dir shift data reset in data reset out hv out # sequence direction* l l dr io b dr io a 1 40 1 h l dr io a dr io b 2 1 40 l h dr io b dr io a 1 20 1 40 21 h h dr io a dr io b 2 21 40 1 20 notes: * reference to package outline or chip layout drawing. 1. dr io a is dr io b delayed by 40 clock pulses. 2. dr io b is dr io a delayed by 40 clock pulses. output sequence operation table
6 hv7224 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin descriptions - 64-lead pqfp (3-sided) (pg) option a pin # function 1 hv out 1/40 2 hv out 2/39 3 hv out 3/38 4 hv out 4/37 5 hv out 5/36 6 hv out 6/35 7 hv out 7/34 8 hv out 8/33 9 hv out 9/32 10 hv out 10/31 11 hv out 11/30 12 hv out 12/29 13 hv out 13/28 14 hv out 14/27 15 hv out 15/26 16 hv out 16/25 pin # function 17 hv out 17/24 18 hv out 18/23 19 hv out 19/22 20 hv out 20/21 21 vpp 22 n/c 23 gnd (power) 24 gnd (logic) 25 dir 26 vdd 27 clk 28 n/c 29 shift 30 n/c 31 dr io a 32 n/c pin # function 33 n/c 34 dr io b 35 oe 36 n/c 37 pol 38 n/c 39 vdd 40 n/c 41 gnd (logic) 42 gnd (power) 43 n/c 44 vpp 45 hv out 21/20 46 hv out 22/19 47 hv out 23/18 48 hv out 24/17 pin # function 49 hv out 25/16 50 hv out 26/15 51 hv out 27/14 52 hv out 28/13 53 hv out 29/12 54 hv out 30/11 55 hv out 31/10 56 hv out 32/9 57 hv out 33/8 58 hv out 34/7 59 hv out 35/6 60 hv out 36/5 61 hv out 37/4 62 hv out 38/3 63 hv out 39/2 64 hv out 40/1 pin descriptions - 64-lead pqfp (3-sided) (pg) option b pin # function 1 hv out 20/21 2 hv out 19/22 3 hv out 18/23 4 hv out 17/24 5 hv out 16/25 6 hv out 15/26 7 hv out 14/27 8 hv out 13/28 9 hv out 12/29 10 hv out 11/30 11 hv out 10/31 12 hv out 9/32 13 hv out 8/33 14 hv out 7/34 15 hv out 6/35 16 hv out 5/36 pin # function 17 hv out 4/37 18 hv out 3/38 19 hv out 2/39 20 hv out 1/40 21 vpp 22 n/c 23 gnd (power) 24 gnd (logic) 25 dir 26 vdd 27 clk 28 n/c 29 shift 30 n/c 31 dr io a 32 n/c pin # function 33 n/c 34 dr io b 35 oe 36 n/c 37 pol 38 n/c 39 vdd 40 n/c 41 gnd (logic) 42 gnd (power) 43 n/c 44 vpp 45 hv out 40/1 46 hv out 39/2 47 hv out 38/3 48 hv out 37/4 pin # function 49 hv out 36/5 50 hv out 35/6 51 hv out 34/7 52 hv out 33/8 53 hv out 32/9 54 hv out 31/10 55 hv out 30/11 56 hv out 29/12 57 hv out 28/13 58 hv out 27/14 59 hv out 26/15 60 hv out 25/16 61 hv out 24/17 62 hv out 23/18 63 hv out 22/19 64 hv out 21/20 note: pin designation for dir h/l, shift = l example: for dir = h, pin 1 is hv out 1 for dir = l, pin 1 is hv out 40 note: pin designation for dir h/l, shift = h example: for dir = h, pin 1 is hv out 20 for dir = l, pin 1 is hv out 21
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2009 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 7 hv7224 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv7224 a021810 64-lead pqfp (3-sided) package outline (pg) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint symbol a a1 a2 b d d1 e e1 e l l1 l2 l3 1 dimen - sion (mm) min 2.80 0.25 2.55 0.30 22.25 19.80 17.65 13.80 0.80 bsc 0.73 1.95 ref 0.25 bsc 0.55 ref 0 o 5 o nom - - 2.80 - 22.50 20.00 17.90 14.00 0.88 3.5 o - max 3.40 0.50 3.05 0.45 22.75 20.20 18.15 14.20 1.03 7 o 16 o drawings not to scale. supertex doc. #: dspd-64pqfppg, version nr090608. note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. the leads on this side are trimmed. 1. 2. 1 64 seating plane gauge plane l l1 l2 vi ew b vi ew b 1 b e side v iew a2 a a1 e e1 d d1 seating plane to p v iew note 1 (index area d1/4 x e1/4) l3 note 2
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