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| HT82K73E 2.4ghz keyboard tx 8-bit otp mcu block diagram rev. 1.00 1 april 16, 2008 general description the device is an 8-bit high performance, risc architec- ture microcontroller devices specifically designed for multiple i/o control product applications. the advantages of low power consumption, i/o flexibil- ity, timer functions, oscillator options, power down and wake-up functions, watchdog timer, motor driving, in- dustrial control, consumer products, subsystem control- lers, etc. features operating voltage: f sys = 27mhz: 2.0v~3.3v for crystal mode f sys = 4mhz: 2.0v~3.3v for external rc mode 39 bidirectional i/o lines watchdog timer function single 16-bit internal timer with overflow interrupt and timer input 27mhz external crystal oscillator and 4mhz external rc mode two bit to define micro-controller system clock (f sys /1, f sys /4, f sys /8, f sys /16) built-in dc/dc to provide stable (2.8, 3.1, 3.4, 3.8, 4.1, 4.6v use otp option) vdd with error 5% 39 i/o bi-directional lines with pull-high options power down and wake-up functions to reduce power consumption 4-level subroutine nesting bit manipulation instruction table read instructions 63 powerful instructions all instructions executed in one or two machine cy - cles low voltage reset function 48 ssop package technical document tools information faqs application note ha0075e mcu reset and oscillator circuits application note ! " # $ " # $ % ! pin assignment pin description pin name i/o options description pa0~pa1 pa2/tmr pa3~pa7 i/o pull-high or none wake-up bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pa2 is shared with the external timer input pin tmr. pb0~pb7 i/o pull-high or none wake-up bidirectional 8-bit input/output port. each nibble, pb0~pb3 and pb4~pb7, pin can be configured as wake-up inputs by configuration options. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pc0~pc3 pc4/sdo pc5/sdi pc6 pc7/sclk i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble, pc0~pc3 andpc4~pc7, can be configured as wake-up inputs by configuration options. software in - structions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pc4, pc5, pc7 are pins shared with spi interface. pd0~pd7 i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble, pd0~pd3 and pd4~pd7, can be configured as wake-up inputs by configuration options. software in - structions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pe0/v1 pe1/v2 pe2/z1 pe3/z2 pe4/scb pe5/scl pe6/sda i/o pull-high wake-up bidirectional 7-bit input/output port. each bit, pe0~pe3 can be configured as wake-up inputs by configuration options. software instructions determine if the pin is a cmos output or schmitt trigger input. each nibble, pe0~pe3 and pe4~pe7,can be configuration options determine if the pins have pull-high resistors. pe0 and pe1 are shared with the v1 and v2 pins. pe2 and pe3 are shared with the z1 and z2 pins. pe4 is shared with the scb pins. pe5 is shared with the scl pins. pe6 is shared with the sda pins. HT82K73E rev. 1.00 2 april 16, 2008 & & ' & & ( & & & ) & * & & + ) , ) ) ' ) ) ( ) & ) ) ) * ) ) + * , * * ' * * ( * ) & ( ' , + * ) & ( ' , * + * * * * ) * & ( ' ) * + % * - & - ( - - ' - + - ) + - * - ) ( * & . ) / * . * / . % * . + % % - 0 1 % 2 3 2 3 % . . ( 2 . . & - & ( ' 2 4 ' & ) * + pin name i/o options description osc1 osc2 i o crystal or rc osc1, osc2 are connected to an external 6mhz or 27mhz crystal/resonator for the internal system clock. vsslx i dc/dc lx gnd vss negative power supply, ground res i schmitt trigger reset input. active low vdd positive power supply absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3v no load, f sys = 27mhz 2 3.3 v i dd1 operating current (crystal osc) 3v no load, f sys = 27mhz adc disable 36ma i dd2 operating current (crystal osc) 3v no load, amp on, f sys = 27mhz 3.5 ma i stb standby current 3v no load, system halt wdt disable and lvr disable 20 a v il1 input low voltage for i/o (schmitt trigger) 0 0.3v dd v v ih1 input high voltage for i/o (schmitt trigger) 0.7v dd v dd v v il2 input low voltage (res ) 0 0.3v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvd low voltage detector voltage 2.1 2.2 2.3 v 1.9 2.0 2.1 v v lvr low voltage reset 2.4 v i ol1 pc6 sink current 3v v ol =0.1v dd 15 30 ma i ol2 other i/o pins sink current 3v v ol =0.1v dd 4 ma i oh1 pc6 source current 3v v oh =0.9v dd 3 6 ma i oh2 other i/o pins source current 3v v oh =0.9v dd 2.5 4.5 ma r ph1 pc6 internal pull-high resis - tance 3v 10 60 120 k r ph2 other pins internal pull-high re - sistance 3v 10 30 50 k HT82K73E rev. 1.00 3 april 16, 2008 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 27 mhz t rcsys watchdog osc with 6-stage prescaler period 3v 71 s t wdt1 watchdog time-out period (rc) 3v wdts=1 4.57 ms t res external reset low pulse width 1 ms t configure watchdog time-out period (system clock) 1024 t rcsys t ost oscillation start-up timer period 512 1/f sys t lvd low voltage detector voltage 200 s t lvr low voltage width to reset 1 ms f timer timer i/p frequency (tmr) 3v 0 4000 khz t oscsetup crystal setup 10 ms HT82K73E rev. 1.00 4 april 16, 2008 HT82K73E rev. 1.00 5 april 16, 2008 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction exe - cution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arith - metic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumula - tor and the alu. certain internal registers are imple - mented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. 5 # 6 7 8 . 9 6 7 8 5 # 6 7 : 8 . 9 6 7 8 5 # 6 7 : * 8 . 9 6 7 : 8 : : * 7 8 # # * # ) # & ! system clocking and pipelining 5 # 6 . 9 6 5 # 6 * 5 # ! * ) & ( . 2 ; < % = > * ? @ 2 2 . 2 ; 2 > * ? @ < < 1 . 9 6 * 5 # 6 ) 5 # 6 . 9 6 5 # 6 ' instruction fetching HT82K73E rev. 1.00 6 april 16, 2008 when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable regis - ter. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the con- tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in- struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper- ations may result in carry, borrow or other status changes, the status register will be correspondingly up- dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc mode program counter bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 00000000000 timer/event counter overflow 00000001000 skip program counter + 2 loading pcl pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc10~pc8: current program counter bits @7~@0: pcl bits #10~#0: instruction code address bits s10~s0: stack register bits 2 a 2 a * 2 a ) 2 a & ! b - b HT82K73E rev. 1.00 7 april 16, 2008 increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applica - tions which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. structure the program memory has a capacity of 2k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execu - tion. location 004h this vector is used by serial interface. when 8-bits of data have been received or transmitted success-fully from serial interface. the program will jump to this lo - cation and begin execution if the interrupt is enable and the stack is not full. location 008h this vector is used by the timer/event counter. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. table location any location in the program memory can be used as look-up tables. there are three method to read the rom data by two table read instructions: tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows: the in - structions tabrdc [m] (the current page, one page=256words), where the table locations is de - fined by tblp (07h) in the current page. and the rom code option tbhp is disabled (default). the instructions tabrdc [m] , where the table lo - cations is defined by registers tblp (07h) and tbhp (01fh). and the rom code option tbhp is enabled. the instructions tabrdl [m] , where the table lo - cations is defined by registers tblp (07h) in the last page (700h~7ffh). only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the re- maining 1-bit words are read as 0. the table higher-order byte register (tblh) is read only. the ta- ble pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before ac- cessing the table, the location must be placed in the tblp and tbhp (if the otp option tbhp is disabled, the value in tbhp has no effect). the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou - tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the require - ments. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the rom code option tbhp is dis - abled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. tbhp register bit0~bit2 when tbhp is enable. ( 5 5 ? . a ! 2 ! 7 * ( c $ 8 2 ! 7 * ( c $ 8 ' 5 5 ? + + + ? + + ? + + ? a d + + & ? ! program memory structure HT82K73E rev. 1.00 8 april 16, 2008 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 706h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 705h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 700h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m]pc10pc9pc8@7@6@5@4@3@2@1@0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc10~pc8: current program counter bits when tbhp is disable. tbhp register bit2~bit0 when tbhp is enabled @7~@0: table pointer tblp bits table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 2k program memory of device. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data ta - ble will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad - dress of the present page if the tabrdc [m] instruc - tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] in - struction is executed. HT82K73E rev. 1.00 9 april 16, 2008 data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the two sections of data memory, the special purpose and general purpose data memory are located at con - secutive locations. all are implemented in ram and are 8 bits wide. the start address of the data memory for all devices is the address 00h . registers which are com - mon to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . e ! ! ! + + ? * + ? , 5 ? 5 ? data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer register, mp. ! ! + + ? + ? + * ? + ) ? + & ? + ( ? + ? + ' ? + ? + , ? + ? + - ? + ? + ? + . ? + 5 ? + ? ? * ? ) ? & ? ( ? ? ' ? ? , ? ? - ? ? ? . ? 5 ? < f $ = $ g + + g , 5 ? e ! 7 * - 8 $ $ $ + 2 - 2 - 2 ? " " ! f 1 ? 2 $ - - - - . . " ! " 7 5 8 2 7 5 8 - ? * + ? special purpose data memory structure HT82K73E rev. 1.00 10 april 16, 2008 special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h. any unused data memory lo - cations between these special function registers and the point where the general purpose memory begins is re - served and attempting to read data from these locations will return a value of 00h. indirect addressing registers iar the iar register, located at data memory address 00h , is not physically implemented. this special regis - ter allows what is known as indirect addressing, which permits data manipulation using a memory pointer in - stead of the usual direct memory addressing method where the actual memory address is defined. any ac - tions on the iar register will result in corresponding read/write operations to the memory location specified by the memory pointer mp. reading the iar register in - directly will return a result of 00h and writing to the register indirectly will result in no operation. memory pointer mp one memory pointer, known as mp, is physically imple - mented in the data memory. the memory pointer can be written to and manipulated in the same way as nor - mal registers providing an easy way of addressing and tracking data. when using any operation on the indirect addressing register iar, it is actually the address speci - fied by the memory pointer that the microcontroller will be directed to. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1; accumulator loaded with first ram address mov mp,a ; setup memory pointer with first ram address loop: clr iar ; clear the data at address defined by mp inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory ad - dresses. HT82K73E rev. 1.00 11 april 16, 2008 accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh, tbhp these two special function registers are used to control operation of the look-up table which is stored in the pro- gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the rom code option tbhp is disabled, the instruction tabrdc [m] reads the rom data as de - fined by tblp and the current program counter bits. tbhp register bit0~bit2 when tbhp is enable. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place dur- ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 5 % / ! " b 9 b / b a b c b # $ ! " c $ c b " # $ b 1 ! $ = $ g + g ' + status register HT82K73E rev. 1.00 12 april 16, 2008 in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt rou - tine can change the status register, precautions must be taken to correctly save it. interrupt control registers intc the microcontroller provides an internal timer/event counter overflow interrupt. by setting various bits within this register using standard bit manipulation instruc - tions, the enable/disable function of each interrupt can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/dis - able and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is en - tered to disable further interrupt and is set by executing the reti instruction. timer/event counter registers tmrh, tmrl, tmrc all devices possess a single internal 16-bit count-up timer. an associated register pair known as tmrl/tmrh is the location where the timer 16-bit value is located. this register can also be preloaded with fixed data to allow different time intervals to be setup. an as- sociated control register, known as tmrc, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. watchdog timer register wdts the watchdog function in the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows.to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. input/output ports and control registers within the area of special function registers, the i/o registers and and their associated control registers play a prominent role. all i/o ports have a designated regis - ter correspondingly labeled as pa, pb, pc, pd and pe0~pe6. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc, pdc and pec0~pec6, also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program in - itialisation, it is important to first setup the control regis - ters to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating spe - cific bits of the i/o control registers during normal pro - gram operation is a useful feature of these devices. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the microcontroller provides 39 bidirectional input/out - put lines labeled with port names pa, pb, pc, pd and pe0~pe6. these i/o ports are mapped to the data memory with addresses as shown in the special pur- pose data memory table. all of these i/o lines can be used for input and output operations and one line as an input only. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, i/o pins, when configured as an input have the capability of being connected to an internal pull-high re - sistor. the pull-high resistors are selectable via configu - ration options and are implemented using weak pmos transistors. each pin on all of i/o can be selected indi - vidually to have this pull-high resistors feature and each nibble on each of the other ports. port pin wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. after a halt instruction HT82K73E rev. 1.00 13 april 16, 2008 forces the microcontroller into entering the power down mode, the processor will remain in a low-power state un - til the logic condition of the selected wake-up pin on the port pin changes from high to low. this function is espe - cially suitable for applications that can be woken up via external switches. each pin on pa , pb, pc, pd, pe0~pe6 has the capability to wake-up (by nibble) the device by falling edge and pe0~pe6 have both falling and rising wake-up function. all i/o except pa , pb, pc, pd, pe0~pe6 are configured as low to high nibble wake-up. it means once there are one pin is in low level, the i/o cannot wake-up the mcu. i/o port control registers each i/o port has its own control register pac, pbc, pcc, pdc and pec0~pec6, to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor struc - tures can be reconfigured dynamically under software control. each of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be di - rectly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the pro - gram will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro- gram control. external timer clock input the external timer pin tmr is pin-shared with the i/o pin pa2. to configure this pin to operate as timer input, the corresponding control bits in the timer control reg- ister must be correctly set. for applications that do not require an external timer input, this pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. the v1/v2 is for v-axis function the v1/v2 pins are pin shared with the pe0/pe1 pins, pe0, pe1 has falling and rising edge wake-up func - tion, if it select can wake-up by otp option. in halt mode if pe0 wake-up the pf3 [1ch] will beset, if pe1 wake-up the pf4 [1ch] will be set, if user read pe0 or pe1, the bit will be clear. the z1/z is for z-axis function the z1/z2 pins are pin shared with the pe2/pe3 pins, pe2, pe3has falling and rising edge wake-up func - tion, if it select can wake-up by otp option. in halt mode if pe2 wake-up the pf6 [1ch] will beset, if pe3 wake-up the pf7 [1ch] will be set, if user read pe2 or pe3, the bit will be clear. if user read pf6 or pf7, the bit will be clear. % f 3 - - " # ! $ " - h 4 h h 4 h + i * ) i ' - + i - ' + i ( ' 2 4 + i ' . + % . % * . * / . ) / * . & . ( 2 . " ! b ! $ " ! ! b ! ? # ! " ! 2 c * ! b input/output ports HT82K73E rev. 1.00 14 april 16, 2008 i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the pac, pbc, pcc, pdc and pec0~pec6 port control register, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated pa, pb, pc, pd and pe0~pe6 port data registers are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re- write this data back to the output ports. all pins have the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the selected wake-up pins. timer/event counters the provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. the device contains an inter - nal 16-bit count-up timer which has three operating modes. the timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. the provision of an internal 16-stage prescaler to the timer clock circuitry gives added range to the timer. there are three registers related to the timer/event counter, tmrl, tmrh and tmrc. the tmrl/tmrh register pair are the registers that contains the actual timing value. writing to this register pair places an initial starting value in the timer/event counter preload regis - ter while reading retrieves the contents of the timer/event counter. the tmrc register is a timer/event counter control register, which defines the timer options, and determines how the timer is to be used. the timer clock source can be configured to come from the internal system clock source or from an exter - nal clock on shared pin pa2/tmr. note: the timer overflow can t wake-up in halt mode. configuring the timer/event counter input clock source the internal timer clock source can originate from either the system clock or from an external clock source. the system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. an external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin pa2/tmr. depending upon the condition of the te bit, each high to low, or low to high transition on the pa2/tmr pin will increment the counter by one. . - $ - $ a b c ! 2 c - - b b ? # - 2 c - - . a 1 . a $ + f 3 b ; & ! 16-bit timer/event counter structure * ) & * ) & " $ b read/write timing HT82K73E rev. 1.00 15 april 16, 2008 timer registers tmrh, tmrl the tmrh and tmrl registers are two 8-bit special function register locations within the special purpose data memory where the actual timer value is stored. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the pa2/tmr pin. the timer will count from the initial value loaded by the preload regis - ter to the full count value of ffffh at which point the timer overflows and an internal interrupt signal gener - ated. the timer value will then be reset with the initial preload register value and continue counting. for a maximum full range count of 00h to ffffh the preload registers must first be cleared to 00h. it should be noted that after power-on the preload registers will be in an un - known condition. note that if the timer/event counter is not running and data is written to its preload registers, this data will be immediately written into the actual coun - ter. however, if the counter is enabled and counting, any new data written into the preload registers during this period will remain in the preload registers and will only be written into the actual counter the next time an over - flow occurs. accessing these registers is carried out in a specific way. it must be noted that when using instructions to preload data into the low byte register, namely tmrl, the data will only be placed in a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely tmrh, is executed. on the other hand, using instruc- tions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte register. after this has been done, the low byte register can be read in the normal way. note that reading the low byte timer register di - rectly will only result in reading the previously latched contents of the low byte buffer and not the actual con - tents of the low byte timer register. timer control register tmrc the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of the timer control register tmrc. to - gether with the tmrl and tmrh registers, these three registers control the full operation of the timer/event counter. before the timer can be used, it is essential that the tmrc register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, the timer mode, the event counting mode or the pulse width measurement mode, bits tm0 and tm1 must be set to the required logic levels. the timer-on bit ton or bit 4 of the tmrc register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. if the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the te or bit 3 of the tmrc register. % & ' & " ' . 1 + + $ < + < $ ! $ + + + + + $ a a $ 7 9 8 $ 7 8 ! c $ # $ $ b # a $ b ! ! < a # # c + < a c # # 1 ! $ = $ g + g 1 ! $ = $ g + g timer/event counter control register HT82K73E rev. 1.00 16 april 16, 2008 configuring the timer mode in this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. to operate in this mode, bits tm1 and tm0 of the tmrc register must be set to 1 and 0 respectively. in this mode, the internal clock is used as the timer clock. the timer-on bit, ton, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overflows, the timer will be reset to the value already loaded into the preload reg - ister and continue counting. if the timer interrupt is en - abled, an interrupt signal will also be generated. the timer interrupt can be disabled by ensuring that the eti bit in the intc register is cleared to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on external pin pa2/tmr, can be re - corded by the internal timer. for the timer to operate in the event counting mode, bits tm1 and tm0 of the tmrc register must be set to 0 and 1 respectively. the timer-on bit, ton must be set high to enable the timer to count. with te low, the counter will increment each time the pa2/tmr pin receives a low to high transition. if the te bit is high, the counter will increment each time pa2/tmr receives a high to low transition. as in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value al- ready loaded into the preload register and continue counting. if the timer interrupt is enabled, an interrupt signal will also be generated. the timer interrupt can be disabled by ensuring that the eti bit in the intc register is cleared to zero. to ensure that the external pin pa2/tmr is configured to operate as an event counter input pin, two things have to happen. the first is to en - sure that the tm0 and tm1 bits place the timer/event counter in the event counting mode, the second is to en - sure that the port control register configures the pin as an input. it should be noted that a timer overflow. in the event counting mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows and if the interrupts are enabled also generate a timer interrupt signal. configuring the pulse width measurement mode in this mode, the width of external pulses applied to the pin-shared external pin pa2/tmr can be measured. in the pulse width measurement mode, the timer clock source is supplied by the internal clock. for the timer to operate in this mode, bits tm0 and tm1 must both be set high. if the te bit is low, once a high to low transition has been received on the pa2/tmr pin, the timer will start counting until the pa2/tmr pin returns to its origi - nal high level. at this point the ton bit will be automati - cally reset to zero and the timer will stop counting. if the te bit is high, the timer will begin counting counting once a low to high transition has been received on the pa2/tmr pin and stop counting when the pa2/tmr pin returns to its original low level. as before, the ton bit will be automatically reset to zero and the timer will stop : * . 9 . a : ) : event counter mode timing chart : : * : ) : & . 9 ! + 1 1 7 c # + . . j + 8 ! ! ! $ a b $ b 6 pulse width measure mode timing chart ! : : * : 1 : 1 : timer mode timing chart HT82K73E rev. 1.00 17 april 16, 2008 counting. it is important to note that in the pulse width measurement mode, the ton bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the ton bit can only be reset to zero under program control. the residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin pa2/tmr. as the ton bit has now been reset any further transitions on the pa2/tmr pin will be ignored. not until the ton bit is again set high by the program can the timer begin fur - ther pulse width measurements. in this way single shot pulse measurements can be easily made. it should be noted that in this mode the counter is controlled by logi - cal transitions on the pa2/tmr pin and not by the logic level. as in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. if the timer in - terrupt is enabled, an interrupt signal will also be gener - ated. to ensure that the external pin pa2/tmr is configured to operate as a pulse width measuring input pin to ensure that the tm0 and tm1 bits place the timer/event counter in the pulse width measuring mode. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re- quire the use of the external pa2 pin for correct opera- tion. as this pin is a shared pin it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is imple- mented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. addi - tionally the port control register pac bit 2 must be set high to ensure that the pin is setup as an input. any pull-high resistor configuration option on this pin will re - main valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an inter - nal interrupt signal directing the program flow to the re - spective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn - chronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring pro - grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are prop - erly initialised before using them for the first time. the associated timer enable bits in the interrupt control reg - ister must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control regis- ter. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. but the timer overflow can t wake-up if mcu is in a power down con - dition. HT82K73E rev. 1.00 18 april 16, 2008 timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are en - abled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h reti org 08h ; timer/event counter interrupt vector jmp tmrint ; jump here when timer overflows : org 20h ; main program ;internal timer/event counter interrupt routine tmrint: : ; timer/event counter main program placed here : reti : : begin: ;setup timer registers mov a,09bh ; setup timer low register mov tmrl,a; ; load low register first mov a, 0aah ; setup timer high register mov tmrh,a mov a,081h ; setup timer control register mov tmrc,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start timer/event counter - note mode bits must be previously setup interrupts interrupts are an important part of any microcontroller system. when an internal function such as a timer/event counter overflow, their corresponding in- terrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. this device contains a single internal timer/event counter interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single inter - rupt control register, which is located in the data mem - ory. by controlling the appropriate enable bits in this register the interrupt can be enabled or disabled. also when an interrupt occurs, the request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer/event counter overflow, will generate an inter - rupt request by setting its corresponding request flag, if its interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond - ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruc- tion at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. once an interrupt subroutine is serviced, other inter - rupts will be blocked, as the emi bit will be cleared auto - matically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. HT82K73E rev. 1.00 19 april 16, 2008 timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and its corresponding timer in - terrupt enable bit, et0i, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, tf, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 08h, will take place. when the interrupt is serviced, the timer interrupt request flag, tf, will be automatically reset and the emi bit will be automatically cleared to disable other inter - rupts. programming considerations by disabling the interrupt enable bit, the requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the accumulator or status register are al - tered by the interrupt service program, which may cor - rupt the desired control sequence, then the contents should be saved in advance. $ $ b c . a a b c ! k 5 5 . . + ! ? # 2 c $ . $ b ! k 5 5 interrupt structure ( ) & ! e . < + < $ 1 ! $ = $ g + g ' + . + . . a ! . < + < $ . a ! k 5 < a + < a 5 1 ! $ = $ g + g . 5 b ! < + < $ b ! k 5 < a + < a interrupt control register HT82K73E rev. 1.00 20 april 16, 2008 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. . % + 6 , % power-on reset timing chart . + 6 5 + + % % + 6 + 5 + enhanced reset circuit . + 6 , % + 6 & % res reset timing chart . % % + 6 5 + + basic reset circuit HT82K73E rev. 1.00 21 april 16, 2008 low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se - lected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 00res reset during power-on 00res wake-up halt uures or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. 2 % low voltage reset timing chart " wdt time-out reset during normal operation timing chart " wdt time-out reset during power down timing chart HT82K73E rev. 1.00 22 april 16, 2008 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* pcl 000h 000h 000h 000h 000h mp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --00 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmrl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu wake-up status register (pf) xxxx x--- xxxx x--- xxxx x--- xxxx x--- uuuu u--- control register ctlr ( pfc ) -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tbhp 0000 0000 0000 0uuu 0000 0uuu 0000 0uuu 0000 0uuu sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu sbdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu period timer register 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: * means warm reset - not implemented u means unchanged x means unknown HT82K73E rev. 1.00 23 april 16, 2008 oscillator there are two oscillator circuits contained within the de - vice. the first is the system oscillator which utilises an external crystal and the second is the watchdog timer oscillator which is fully integrated and requires no exter - nal components. system clock configurations there are two oscillator mode crystal and rc. for crys - tal mode no built-in capacitor between osc1, osc2 and gnd. the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and fre - quencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ce - ramic resonator will usually require two small value ca - pacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specification. in most applications, re - sistor r1 is not required, however for those applications where the lvr function is not used, r1 may be neces - sary to ensure the oscillator stops running when vdd falls below its operating range. for rc mode use pull-high ip (the application add r be- tween osc1 and v dd ). more information regarding the oscillator is located in application note ha0075e on the holtek website. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an ex - tremely low standby current level. this occurs because when the device enters the power down mode, the sys - tem oscillator is stopped which reduces the power con - sumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in applica - tion areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli- cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi- nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de - signer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be con - nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or con - nected only to external circuits that do not draw current, such as other cmos inputs. crystal/ceramic oscillator rc oscillator HT82K73E rev. 1.00 24 april 16, 2008 if the configuration options have enabled the watchdog timer internal oscillator then this will continue to run when in the power down mode and will thus consume some power. for power sensitive applications it may be therefore preferable to use the system clock source for the watchdog timer. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on any of the i/o pins a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a or any nibble on the other ports can be setup via configuration options to permit a negative transition on the pin to wake-up the system. when a port pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possi- ble situations may occur. the first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situa - tion, the interrupt will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular inter - rupt response takes place. if an interrupt request flag is set to 212 before entering the power down mode, the wake-up function of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by its own internal dedicated internal wdt oscillator. note that if the wdt configuration op - tion has been disabled, then any instruction relating to its operation will result in no operation. all watchdog timer options, such as enable/disable, wdt clock source and clear instruction type all selected through configuration options. there are no internal reg - isters associated with the wdt in this device. however, it should be noted that this specified internal clock pe - riod can vary with vdd, temperature and process varia - tions. whether the wdt clock source is its own internal wdt oscillator, it is further divided by an internal 6-bit counter and a clearable single bit counter to give longer watchdog time-outs. as the clear instruction only resets the last stage of the divider chain, for this reason the ac - tual division ratio and corresponding watchdog timer time-out can vary by a factor of two. the exact division ratio depends upon the residual value in the watchdog timer counter before the clear instruc- tion is executed. it is important to realise that as there are no independent internal registers or configuration options associated with the length of the watchdog timer time-out, it is completely dependent upon the fre- quency the internal wdt oscillator. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how- ever, if the system is in the power down mode, when a wdt time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instruc - tions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2. for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watch - dog timer. HT82K73E rev. 1.00 25 april 16, 2008 ' f 3 " " + i " * " b ! " ! b ! 2 " 5 2 " * 5 * 2 2 " watchdog timer " * * + ' + " * + + + + " + + + + " + + + + + c ! & 6 ( ' 9 9 & ) 9 ' ) 9 & 9 ) * * , * 9 & ( & 9 * 1 $ " " + watchdog timer register ' + ' ( & ) * + e port a (12h) pa note: has option to configure whether there are pull-high and wake-up function. , ' + - ' - - ( - & - ) - * - - + e port b (14h) pb note: has option to configure whether there are pull-high and wake-up function. & ' + ' ( & ) * + e e = # b e = # b e e = # 2 4 b internal register port c port (16h) pc HT82K73E rev. 1.00 26 april 16, 2008 + ' + + e * ) & ( ' port d (18h) pd note: has option to configure whether there are pull-high and wake-up function. ! ' + 5 ' 5 5 ( 5 & 5 ) 5 * 5 5 + a $ < % # b % * 7 . + 8 + < $ b < % * # b % 7 . 8 + < $ b < f c ! ! $ a b c 7 $ 8 + < f " ! ! $ < / # b / * 7 . * 8 + < $ b < / * # b / 7 . ) 8 + < $ b note: the internal register data will clear to zero after f/w read the register. internal register port c port (1ch) pf ! & ' + 5 ' 5 5 ( 5 & 5 ) 5 * 5 5 + # $ $ $ c # # # ! + < 0 ! < $ 0 ! 7 $ b 8 # # # 2 % a j $ 2 % + j b b 7 $ b 8 5 b * 6 * % c b 7 + 6 % 8 < a j l * 6 * * 6 + % + < a m * 6 * * 6 + % 7 $ b 2 % 0 $ 0 j + 8 # # $ c ( b 2 % 0 $ $ # $ * 6 * * 6 + 2 c + + < & n 7 $ b 8 6 ' ( ? d + < n ) 6 ) ? d + * < n 6 ? d + ) < b * 6 & e ? d ! ! # # # $ 1 $ j + 7 $ b 8 $ j $ " # # j = # # b c 6 b # ? $ c # $ # 6 a $ internal register port c port (1dh) pfc application circuits HT82K73E rev. 1.00 27 april 16, 2008 period timer register ptimer this register is used to define the period of the timer which always counts in the suspend mode. once the timer is reached, the mcu will be woken-up by the i/o method. once the mcu is woken-up by the period timer, the cnt_wk bit of the wake-up register is set to 1 . bit no. function name r/w description 0~7 period timer r/w the time interval, one seconds as a unit. when <7:0>=0h then the hardware motion detector will only wake-up the mcu when it detects mouse movement or when there is a button change for the mouse mode. for the i/o mode, mcu will only be woken up by a port i/o or an int when <7:0>=0h, otherwise the mcu can be woken up from the suspend mode by the following conditions: i/o port wake-up rc watchdog is reached when the mcu is configured as rc watchdog enable otp option int wake-up reset the period of the period timer register is reached. period timer register dc/dc section this circuit is used to generate a stable dc_out (2.8, 3.1, 3.4, 3.8, 4.1, 4.6v use otp option error 5%) power voltage for whole ic and output to the irpt. the clock of dc/dc is 140khz. also it can detector the battery volt- age. if the battery voltage down to 2.2v or 2.0v lvd (er- ror 0.1v), it output a low signal (2.2 or 2.0 low battery) to mcu. also there are 2.4v lvr (dc_out), the lvr is detect the dc_out voltage. when the dc_out down to 2.4v, the mcu will reset (there are one otp option to decide whether this function is on or off). also if dc_dc is disable by pg0=0, and mcu in halt mode, the lvr is no effect on mcu no matter the lvr option is enable or disable. dc/dc output current in normal state= 100ma for 2.2v make sure the battery= 2.2v or 2.0 v, the dc/dc is work properly. for battery-in is 2.2v, the output driving current has mini. 50ma. HT82K73E rev. 1.00 28 april 16, 2008 spi serial interface the device includes two spi serial interfaces. the spi interface is a full duplex serial data link, originally de - signed by motorola, which allows multiple devices con - nected to the same spi bus to communicate with each other. the devices communicate using a master/slave technique where only the single master device can initi - ate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for spi communication known as sdi - serial data input, sdo - serial data output, sck - serial clock and scs - slave select. note that the con - dition of the slave select line is conditioned by the csen bit in the sbcr control register. if the csen bit is high then the scs line is active while if the bit is low then the scs line will be in a floating condition. the following timing diagram depicts the basic timing protocol of the spi bus. spi registers there are two registers associated with the spi inter - face. these are the sbcr register which is the control register and the sbdr which is the data register. the ' ( & ) * + - 7 a $ 8 f 3 - b b f 3 2 - f 3 a - $ 4 * + - . 1 - 5 - . 1 " - " 2 5 5 $ = - . 1 . 1 1 " - " - . . 1 a . 1 - . 1 $ = $ = spi block diagram - . 5 f 2 - . 5 f 2 1 < g f g # $ 6 4 + - . 1 2 . 1 " 2 5 ' ( & ) * + + + + + + + ' ( & ) * + f f f f f f f f - < . 2 - f 1 2 . e . - < . 2 - f . e . ' + ( * & ) ) & * ( + ' ' + ( * & ) ) & * ( + ' 4 HT82K73E rev. 1.00 29 april 16, 2008 sbcr register is used to setup the required setup pa - rameters for the spi bus and also used to store associ - ated operating flags, while the sbdr register is used for data storage. after power on, the contents of the sbdr register will be in an unknown condition while the sbcr register will default to the condition below: cks m1 m0 sben mls csen wcol trf 01100000 note that data written to the sbdr register will only be written to the txrx buffer, whereas data read from the sbdr register will actual be read from the register. spi bus enable/disable to enable the spi bus and csen=1, the sck, sdi, sdo and scs lines should all be zero, then wait for data to be written to the sbdr (txrx bufffer) register. for the master mode, after data has been written to the sbdr (txrx buffer) register then transmission or re - ception will start automatically. when all the data has been transferred the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. to disable the spi bus sck, sdi, sdo, scs floating. spi operation all communication is carried out using the 4-line inter - face for both master or slave mode. the timing diagram shows the basic operation of the bus. the csen bit in the sbcr register controls the overall function of the spi interface. setting this bit high, will en - able the spi interface by allowing the scs line to be ac - , & ' + 4 + - . 1 2 . 1 " 2 5 a 5 + < 1 ! < ! ! " - + < b < $ $ . - + < b < . - 2 - 5 - + < 2 - # b b < - # b b - . - + < < . ! $ ! . 1 a - $ - = $ < b = $ < b & = $ < b a $ + + + + + - + < b j b ; & < b j b ; spi interface control register 4 ' + ( * & ) ) & * ( + ' ' + ( * & ) ) & * ( + ' - . 1 j . 1 j $ c $ - - . 1 j = . 1 j + $ c $ - 7 b ! # # $ 8 4 spi bus timing HT82K73E rev. 1.00 30 april 16, 2008 tive, which can then be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be in a floating condition and can therefore not be used for control of the spi interface. the sben bit in the sbcr register must also be high which will place the sdi line in a floating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity con - figuration option. if in slave mode the sck line will be in a floating condition. if sben is low then the bus will be disabled and scs, sdi, sdo and sck will all be in a floating condition. in the master mode the master will always generate the clock signal. the clock and data transmission will be ini - tiated after data has been written to the sbdr register. in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode: step 1. select the clock source using the cks bit in the sbcr control register step 2. setup the m0 and m1 bits in the sbcr control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the slave device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write the data to the sbdr register, which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. goto to step6.for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trf bit or wait for an sbi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf. step10. goto step 5. slave mode: step 1. the cks bit has a don t care value in the slave mode. step 2. setup the m0 and m1 bits to 00 to select the slave mode. the cks bit is don t care. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the master device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write data to the sbcr register, which will actually place the data into the txrx register, then wait for the master clock and scs signal. after this goto step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trf bit or wait for an sbi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf step10. goto step 5 spi configuration options several configuration options exist for the spi interface function which must be setup during device program - ming. one option is to enable the operation of the wcol, write collision bit, in the sbcr register. another option exists to select the clock polarity of the sck line. a configuration option also exists to disable or enable the operation of the csen bit in the sbcr register. if the configuration option disables the csen bit then this bit cannot be used to affect overall control of the spi inter- face. error detection the wcol bit in the sbcr register is provided to indi- cate errors during data transfer. the bit is set by the se - rial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the sbdr register takes place during a data transfer operation and will prevent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcol bit can be disabled or enabled by a configuration option. programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trf bit is used to generate an interrupt when the data has been transferred or received. HT82K73E rev. 1.00 31 april 16, 2008 configuration options configuration options refer to certain options within the mcu that are programmed into the otp program memory de - vice during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. no. options 1 pa0~pa7 pull-high by bit none-pull-high or pull-high 2 pa wake-up by bit: none-wake-up or wake-up 3 pb0~pb7 pull-high by nibble: none-pull-high or pull-high 4 pb0~pb7 wake-up by nibble: none-wake-up or wake-up 5 pc0~pc7 pull-high by nibble: none-pull-high or pull-high 6 pc0~pc7 wake-up by nibble: none-wake-up or wake-up 7 pd0~pd7 pull-high by nibble: none-pull-high or pull-high 8 pd0~pd7 wake-up by nibble: none-wake-up or wake-up 9 pe0~pe6 pull-high by nibble: none-pull-high or pull-high 10 pe4~pe6 wake-up by nibble: none-wake-up or wake-up 11 pe0~pe3 wake-up by bit: none-wake-up or wake-up 12 tbhp function: enable or disable 13 dc-dc output option: 2.8v, 3.1v, 3.4v, 3.8v, 4.1v, 4.6v 14 lvr function: enable or disable 15 lvd voltage: 2.0v or 2.2v 16 wdt function: enable or disable 17 osc: 27mhz or 4mhz 18 output type pe4: nmos or cmos 19 output type pc4: nmos or cmos 20 output type pc5: nmos or cmos 21 output type pc7: nmos or cmos 22 sio wcol: enable or disable 23 sio csen: enable or disable 24 sio cpol: falling edge or raising edge 25 i/o slew rate: 100ns or 200ns 26 osc mode: rc mode or xtal mode application circuits HT82K73E rev. 1.00 32 april 16, 2008 ! " # $ # % & ' ! HT82K73E rev. 1.00 33 april 16, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. HT82K73E rev. 1.00 34 april 16, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z HT82K73E rev. 1.00 35 april 16, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc + x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82K73E rev. 1.00 36 april 16, 2008 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82K73E rev. 1.00 37 april 16, 2008 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82K73E rev. 1.00 38 april 16, 2008 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m] + 1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82K73E rev. 1.00 39 april 16, 2008 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82K73E rev. 1.00 40 april 16, 2008 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82K73E rev. 1.00 41 april 16, 2008 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skipif[m]=0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skipifacc=0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82K73E rev. 1.00 42 april 16, 2008 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skipif[m]=0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skipifacc=0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82K73E rev. 1.00 43 april 16, 2008 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skipif[m]=0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82K73E rev. 1.00 44 april 16, 2008 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82K73E rev. 1.00 45 april 16, 2008 package information 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 HT82K73E rev. 1.00 46 april 16, 2008 & * ( * & - 5 o e ? . product tape and reel specifications reel dimensions ssop 48w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 100 0.1 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 HT82K73E rev. 1.00 47 april 16, 2008 - * carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32 0.3 p cavity pitch 16 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 12 0.1 b0 cavity width 16.2 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 HT82K73E rev. 1.00 48 april 16, 2008 + . 5 4 * - + + " 4 HT82K73E rev. 1.00 49 april 16, 2008 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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