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1 features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) medium-voltage and standard-voltage operation ?5.0(v cc =4.5vto5.5v) ?2.7(v cc =2.7vto5.5v) 3.0 mhz clock rate (5v) 32-byte page mode block write protection ? protect 1/4, 1/2, or entire array write protect (wp ) pin and write disable instructions for both hardware and software data protection self-timed write cycle (5 ms typical) high-reliability ? endurance: one million write cycles ? data retention: 100 years 8-pin pdip and 8-lead jedec soic packages description the at25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electri- cally-erasable programmable read only memory (eeprom) organized as 1024/2048/4096/8192 words of 8 bits each. the device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. the at25080/160/320/640 is available in space saving 8-pin pdip and 8-lead jedec soic packages. the at25080/160/320/640 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. block write protection is enabled by programming the status register with one of four blocks of write protection. separate program enable and program disable instruc- tions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. spi serial automotive eeproms 8k (1024 x 8) 16k (2048 x 8) 32k (4096 x 8) 64k (8192 x 8) at25080 at25160 at25320 at25640 rev. 3260a?seepr?02/02 pin configuration pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input nc no connect dc don?t connect 8-pin pdip 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si
2 at25080/160/320/640 3260a ? seepr ? 02/02 block diagram absolute maximum ratings* operating temperature .................................. -55 cto+125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 cto+150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at25080/160/320/640 3260a ? seepr ? 02/02 pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. dc characteristics (1) note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a =25 c,f=1.0mhz,v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance (cs ,sck,si,wp ,hold )6pfv in =0v applicable over recommended operating range from: t a =-40 cto+125 c, v cc =+2.7vto+5.5v symbol parameter test condition min typ max units v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 1 mhz, so = open, read 3.0 ma i cc2 supply current v cc =5.0vat2mhz,so=open, read, write 5.0 ma i sb1 standby current v cc =2.7v,cs =v cc 0.2 2.0 a i sb2 standby current v cc =5.0v,cs =v cc 2.0 5.0 a i il input leakage v in =0vtov cc -3.0 a i ol output leakage v in =0vtov cc -3.0 3.0 a v il (1) input low-voltage -0.6 v cc x0.3 v v ih (1) input high-voltage v cc x0.7 v cc +0.5 v v ol1 output low-voltage 2.7v v cc 5.5v i ol =3.0ma 0.4 v v oh1 output high-voltage i oh =-1.6ma v cc -0.8 v
4 at25080/160/320/640 3260a ? seepr ? 02/02 note: 1. this parameter is characterized and is not 100% tested. ac characteristics applicable over recommended operating range from t a =-40 c to +125 c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter voltage min max units f sck sck clock frequency 4.5 - 5.5 2.7 - 5.5 0 0 3.0 2.1 mhz t ri input rise time 4.5 - 5.5 2.7 - 5.5 2 2 s t fi input fall time 4.5 - 5.5 2.7 - 5.5 2 2 s t wh sck high time 4.5 - 5.5 2.7 - 5.5 133 200 ns t wl sck low time 4.5 - 5.5 2.7 - 5.5 133 200 ns t cs cs high time 4.5 - 5.5 2.7 - 5.5 250 250 ns t css cs setup time 4.5 - 5.5 2.7 - 5.5 250 250 ns t csh cs hold time 4.5 - 5.5 2.7 - 5.5 250 250 ns t su data in setup time 4.5 - 5.5 2.7 - 5.5 50 50 ns t h data in hold time 4.5 - 5.5 2.7 - 5.5 50 50 ns t hd hold setup time 4.5 - 5.5 2.7 - 5.5 100 100 t cd hold hold time 4.5 - 5.5 2.7 - 5.5 200 200 ns t v output valid 4.5 - 5.5 2.7 - 5.5 0 0 133 200 ns t ho output hold time 4.5 - 5.5 2.7 - 5.5 0 0 ns t lz hold to output low z 4.5 - 5.5 2.7 - 5.5 0 0 100 100 ns t hz hold to output high z 4.5 - 5.5 2.7 - 5.5 100 100 ns t dis output disable time 4.5 - 5.5 2.7 - 5.5 250 250 ns t wc writecycletime 4.5-5.5 2.7 - 5.5 5 10 ms endurance (1) 5.0v, 25 c, page mode 1m write cycles
5 at25080/160/320/640 3260a ? seepr ? 02/02 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25080/160/320/640 always operates as a slave. transmitter/receiver: the at25080/160/320/640 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25080/160/320/640, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25080/160/320/640 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25080/160/320/640. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ? 1 ? , all write operations to the sta- tus register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is "0". this will allow the user to install the at25080/160/320/640 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ? 1 ? .
6 at25080/160/320/640 3260a ? seepr ? 02/02 spi serial interface
7 at25080/160/320/640 3260a ? seepr ? 02/02 functional description the at25080/160/320/640 is designed to interface directly with the synchronous serial periph- eral interface (spi) of the 6805 and 68hc11 series of microcontrollers. the at25080/160/320/640 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. writeenable(wren): the device will power-up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is independent of the sta- tus of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be deter- mined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table 1 . instruction set for the at25080/160/320/640 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 2 . status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy table 3 . read status register bit definition bit definition bit 0 (rdy ) bit0=0(rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1= 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 3. bit 3 (bp1) see table 3. bits 4 - 6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 7. bits 0 - 7 are 1s during an internal write cycle.
8 at25080/160/320/640 3260a ? seepr ? 02/02 writestatusregister(wrsr): the wrsr instruction allows the user to select one of four levels of protection. the at25080/160/320/640 is divided into four array segments. one quarter (1/4), one half (1/2), or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status register control bits are shown in table 4. the three bits, bp0, bp1, and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect (wp )pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ? 1 ? . hardware write protection is disabled when either the wp pin is high or the wpen bit is ? 0 ? . when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block- protected sections in the memory array are disabled. writes are only allowed to sections of the memory which are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ? 0 ? ,as long as the wp pin is held low. table 4 . block write protect bits level status register bits array addresses protected bp1 bp0 at25080 at25160 at25320 at25640 0 0 0 none none none none 1(1/4) 01 0300 -03ff 0600 -07ff 0c00 -0fff 1800 -1fff 2(1/2) 10 0200 -03ff 0400 -07ff 0800 -0fff 1000 -1fff 3(all) 11 0000 -03ff 0000 -07ff 0000 -0fff 0000 -1fff table 5 . wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
9 at25080/160/320/640 3260a ? seepr ? 02/02 read sequence (read): reading the at25080/160/320/640 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (a15 - a0, refer to table 6). upon completion, any data on the si line will be ignored. the data (d7 - d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be contin- ued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the at25080/160/320/640, two separate instructions must be executed. first, the device must be write enabled via the write enable (wren) instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address (a15 - a0) and the data (d7 - d0) to be programmed (refer to table 6). programming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low-time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read status register instruction is enabled during the write programming cycle. the at25080/160/320/640 is capable of a 32-byte page write operation. after each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the at25080/160/320/640 is automatically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. table 6 . address key address at25080 at25160 at25320 at25640 a n a 9 -a 0 a 10 -a 0 a 11 -a 0 a 12 -a 0 don't care bits a 15 -a 10 a 15 -a 11 a 15 -a 12 a 15 -a 13
10 at25080/160/320/640 3260a ? seepr ? 02/02 timing diagrams synchronous data timing (for mode 0) wren timing wrdi timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
11 at25080/160/320/640 3260a ? seepr ? 02/02 rdsr timing wrsr timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance high impedance instruction data in 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 9 10 11 12 13 14 15 cs sck si so
12 at25080/160/320/640 3260a ? seepr ? 02/02 read timing write timing hold timing cs sck si so 0 0 0 1 1 1 2 2 2 3 3 3 ... 4 4 5 5 6 6 7 7 8910 15 14 13 11 20 21 22 23 24 25 26 27 28 29 30 high impedance instruction byte address msb data out 0 0 0 1 1 1 2 2 2 3 3 3 ... 4 4 5 5 6 6 7 7 8910 15 14 13 11 20 21 22 23 24 25 26 27 28 29 30 31 high impedance cs sck si so instruction byte address data in so sck ho ld t cd t hd t hz t lz t cd t hd cs
13 at25080/160/320/640 3260a ? seepr ? 02/02 at25080 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 5 5000 2.0 3000 at25080-10pa-5.0c at25080n-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 3000 0.5 2100 at25080-10pa-2.7c at25080n-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-pin, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
14 at25080/160/320/640 3260a ? seepr ? 02/02 at25160 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 5 5000 2.0 3000 at25160-10pa-5.0c at25160n-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 3000 0.5 2100 at25160-10pa-2.7c at25160n-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-pin, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
15 at25080/160/320/640 3260a ? seepr ? 02/02 at25320 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 5 5000 2.0 3000 at25320-10pa-5.0c at25320n-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 3000 0.5 2100 at25320-10pa-2.7c at25320n-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-pin, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
16 at25080/160/320/640 3260a ? seepr ? 02/02 at25640 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 5 5000 2.0 3000 at25640-10pa-5.0c at25640n-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 3000 0.5 2100 at25640-10pa-2.7c at25640n-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-pin, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
17 at25080/160/320/640 3260a ? seepr ? 02/02 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
18 at25080/160/320/640 3260a ? seepr ? 02/02 8s1 ? jedec soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. note: 10/10/01 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 a common dimensions (unit of measure = mm) symbol min nom max note this drawing is for general information only. refer to jedec drawing ms-012 for proper dimensions, tolerances, datums, etc. h 1 2 n 3 top view c e end view a b l a2 e d side view a ? ? 1.75 b ? ? 0.51 c ? ? 0.25 d ? ? 5.00 e ? ? 4.00 e 1.27 bsc h ? ? 6.20 l ? ? 1.27
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