 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| agilent ACPM-7881 w-cdma power amplifier data sheet features ? ? ? ? ? operating frequency: 1920 - 1980 mhz ? ? ? ? ? 28.5 dbm linear output power @ 3.5v ? ? ? ? ? high efficiency 46% pae ? ? ? ? ? single bias, low quiescent current (50ma) ? ? ? ? ? internal 50 ohm matching networks for both rf input & output ? ? ? ? ? no regulated voltages required ? ? ? ? ? 3.2 - 4.5 v linear operation ? ? ? ? ? 4.0 x 4.0mm smt package ? ? ? ? ? low package profile, 1.1mm applications ? ? ? ? ? w-cdma handsets ? ? ? ? ? data cards ? ? ? ? ? pdas description the ACPM-7881 is a high performance w-cdma power amplifier module offered in a 4x4x1.1mm package. designed around agilent technologies gaas enhancement mode phemt process, the acpm- 7881 offers premium power added efficiency and linearity in a very small form factor. the pa is fully matched to 50 ohms on the input and output. functional block diagram the amplifier has excellent aclr and efficiency performance at max pout, 28.5dbm, and low quiescent current (50ma) with a single bias control voltage, vctrl = 2.0v. no regulated voltages are required to set the bias, vdd2 can be connected directly to the battery. designed in a surface mount rf package, the ACPM-7881 is very cost and size competitive. vdd3 (10) vdd1 (1) vdd2 (5) vctrl (4) rf in (2) rf out (8) gnd (3,6,7,9) bias control mmic module output match
2 pin description table package diagram pin number pin label description function 1 vdd1 supply bias 1 st and 2 nd stages drain bias, nominally 3.5v 2 rfin rf input w-cdma signal input, internally grounded through inductor. external dc block needed if dc voltage present on input trace. 3 n/c no internal connection recommend ground connection on pcb 4 vctrl control voltage output level control, nominally 2v 5 vdd2 supply bias bias circuit supply, > 2.5v; nominally 2.85v. does not require a regulated input and can be connected directly to the battery, if desired. 6gndground 7gndground 8 rfout rf output w-cdma signal, requires external dc block 9gndground 10 vdd3 supply bias 3 rd stage drain bias, nominally 3.5v agilent ACPM-7881 mlywwdd xxxx vdd1 (pin 1) rfin n/c (gnd) vctrl vdd2 (pin 5) gnd gnd gnd (pin 6) rfout vdd3 (pin 10) 4mm sq 1.175mm max bottom view package dimensions marking notes : row 3: ml = manufacturing location (pm = agilent technologies malaysia) y = year ww = work week dd = date code row 4: xxxx = trace code (agilent internal reference) 4.00 0.075mm 4.00 0.075mm 0.50mm 0.40mm 0.45mm 0.10mm 0.10mm 2.00mm 0.50mm 0.60mm 0.40mm 0.60mm 3.80mm viewed down through top of package 3 maximum ratings table notes: 1. operation of this device in excess of any of these limits may cause permanent damage. 2. avoid electrostatic discharge on i/o pins parameter min. max. supply voltage, vdd1 and vdd3 5.0 v supply voltage, vdd2 -1 v 5.0 v analog control voltage -1 v 3.0 v rf input power +5 dbm operating case temperature +90 c load vswr 12:1 storage temperature (case temperature) -30 c +100 c recommended operating conditions parameter min. typ. max. supply voltage, vdd1 and vdd3 1.0 v 3.5 v 4.5 v supply voltage, vdd2 2.6 v 2.85 v 4.5 v control voltage 1.9 v 2.0 v 2.1 v case temperature -20 c +85 c 4 electrical characteristics unless otherwise specified: f=1920-1980mhz, vdd1=vdd3=3.5v, vdd2=2.85v, vctrl=2.0v, pout=28.5dbm, ta=25c, zin/zout = 50 ? pa operation/shutdown logic: dc signals vctrl vdd2 operational mode 2.0v typ 2.6 ~ 3.5v ( 2.85v typ) shutdown < 0.2v 0 ~ 4.5 v parameter min. typ. max. units leakage current, idd1,2,3; vctrl=0 v, rf off 20 50 ua control current, ictrl; vctrl=2.0 v 75 110 145 ua bias current, idd2; vctrl=2 v, vdd2=2.85 v 6 10 ma quiescent current, idd1,3; rf off vctrl=2.0 v 50 80 ma at pout=28.5dbm supply current idd1+idd3 435 490 ma pae including vdd1,2,3 41 46 % gain 26.5 29 31.5 db input vswr 1.1 2.0:1 - aclr 5mhz offset -42 -38 dbc/3.84mhz 10mhz offset -54 -48 dbc/3.84mhz 2nd harmonic -50 -40 dbc/1mhz 3rd harmonic -60 -45 dbc/1mhz noise power in receive band, 2110 to 2170mhz pout = -50dbm to 28.5dbm -140 -138 dbm/hz noise figure 2.1 3.1 4.1 db stability, no spurious under conditions: vswr=4:1, all phases 3 6 figure 9. aclr2 vs pout figure 10. gain vs pout figure 11. pae vs pout figure 12. total idd vs pout figure 13. aclr1 vs pout figure 14. aclr2 vs pout figure 15. gain vs pout data measured at 1980mhz 20 21 22 23 24 25 26 27 28 29 30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) 0 10 20 30 40 50 60 -10 -5 0 5 10 15 20 25 30 pout (dbm) pae (%) 0 100 200 300 400 500 600 -10 -5 0 5 10 15 20 25 30 pout (dbm) idd (ma) 20 21 22 23 24 25 26 27 28 29 30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr (dbc) -60 -55 -50 -45 -40 -35 -30 -25 -20 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr (dbc) -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr (dbc) 7 esd sensitivity level human body model (eia/ jesd22-a114b): class 1a (250vmin, less than 500v) machine model (eia/jesd22- a115a): class a (50vmin, less than 200v) notes: esd sensitivity level for human body model and machine model necessitate the following handling precautions: 1. ensure faraday cage or conductive shield bag is used during transportation processes. 2. if the static charge at smt assemble station is above the device sensitivity level, place an ionizer near to the device for charge neutralization purposes. 3. personal grounding must be worn at all times when handling the devices. moisture sensitivity classification: class 3 preconditioning per jesd22- a113-d class 3 was performed on all devices prior to reliability testing. ACPM-7881 is a moisture sensitive component. its important that the parts are handled under precaution and a proper manner. the handling, baking and out-of- pack storage conditions of the moisture sensitive components are described in ipc/jedc s- std-033a. agilent recommends utilizing the standard precautions listed below. 1. calculated shelf life in sealed bag: 12 months at < 40c and < 90% relative humidity (rh) 2. peak package body temperature: 250c 3. after bag is opened, devices that will be subjected to reflow solder of other high temperature process must be: a. mounted within 168 hours of factory condition 30c / 60% rh b. stored at <10% rh if not used 4. devices require baking, before mounting if: a. humidity indicator card is > 10% when read at 23 5c immediately after moisture barrier bag is opened. b. items 3a or 3b is not met 5. if baking is required, please refer to j-std-033 standard for low temperature (40c) baking requirement in tape/ reel form. tape dimensions and orientation ? 1.55 0.05 ? 1.50 (min) 4.38 0.10 1.80 0.10 4.38 0.10 c l 8.00 0.10 4.38 0.10 2.00 0.05 [1] 4.00 0.10 [2] 5.50 0.05 [3] 12.00 0.30 1.75 0.10 0.30 0.05 notes: 1. measured from centerline of sprocket hole to centerline of pocket 2. cumulative tolerance of 10 sprocket holes is 0.2 mm 3. all dimensions in millimeters unless otherwise stated. agilent ACPM-7881 mlywwdd xxxx 8 order information reel dimensions and orientation part number no. of devices container ACPM-7881-blk 100 bulk ACPM-7881-tr1 1000 7" tape and reel notes: 1. reel shall be labeled with the following information (as a minimum). 2. a certificate of compliance shall be issued and accompany each shipment of product. 3. reel must not be made with or contain ozone depleting materials. 4. all dimensions in millimeters (mm). a. manufacturers name or symbol b. agilent technologies part number c. purchase order number d. date code e. quantity of units 50 min. 12.4 +2.0 -0.0 18.4 max. 25 min wide (ref) slot for carrier tape insertion for attachment to reel hub (2 places 180 apart) back view front view 178 shading indicates thru slots +0.4 -0.2 21.0 0.8 13.0 0.2 1.5 min. user feed direction cover tape carrier tape reel 9 suggested board implementation notes: 1. all decoupling capacitors should be placed as close to the power module as possible. 2. rfin (pin 2) has a grounded inductor inside package as a matching element. an external series capacitor is needed if a dc vo ltage is present. 3. an additional battery bypass capacitor should be placed on bias line before the battery terminal, but does not need to be imm ediately adjacent to the pa module. the bypass capacitor should be a large value, nominally between 2.2uf and 4.7uf. 4. trace impedance on rf lines should be 50 ? . c5 (10,000pf) c1 (4700pf) c2 (4700pf) c4 (33pf) c3 (33pf) gnd 10 lead free reflow profile general guidelines i. ramp 1 ramp to 100c. maximum slope for this zone is limited to 2c/sec. faster heating with ramp higher than 2c may result in excessive solder balling and slump. ii. preheat preheat setting should range from 100 to 150c over a period of 60 to 120 seconds depending on the characteristics of the pcb components and the thermal characteristics of the oven. if possible, do not prolong preheat as it will cause excessive oxidation to occur to the solder powder surface. iii. ramp 2 the time in this zone should be kept below 35 seconds to reduce the risk of flux exhaustion. the ramp up rate should be 2c/sec from 150c to re-flow at 217c. it is important that the flux medium retains its activity during this phase to ensure the complete coalescence of the solder particles during re- flow. iv. reflow the peak reflow temperature is calculated by adding ~32c to the melting point of the alloy. lead free solder paste melts at 218c and peak reflow temperature is 218c + 32c = 250c (5c). note that total time over 218c is critical and should typically be 60 C 150 seconds. this period determines the appearance of the solder joints. excessive time above reflow may cause a dull finish and charred of flux residues. insufficient time above reflow may lead to poor wetting and improperly fused (cloudy) flux residues. v. cooling maximum slope for cooling is limited to 3c/sec. more rapid cooling may cause solder joints crack while cooling at a slower rate will increase the likelihood of a crystalline appearance on the solder joints (dull finish). solder reflow profile the most commonly used solder reflow method is accomplished in a belt furnace using convection heat transfer. this profile is designed to ensure reliable finished joints. however, the profile indicated will vary among different solder pastes from different manufacturers and is shown here for reference only. other factors that can affect the profile include the density and types of components on the board, type of solder used and type of board or substrate material being used. the profile shows the actual temperature that should occur on the surface of a test board at or near the central of the solder joint. for this type of reflow soldering, the circuit board and solder joints are first to get heated up. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs thermal energy efficiently and distributes this heat to the components. reflow temperature profiles designed for tin/lead alloys will need to be revised accordingly to cater for the melting point of the lead free solder being 34c (54f) higher than that of tin/lead eutectic or near-eutectic alloys. in addition, the surface tension of molten lead free solder alloys is significantly higher than the surface tension for tin/lead alloys and this can reduce the spread of lead free solder during reflow. 250 200 150 100 melting point = 218?c suggested lead free reflow profile for snagcu solder paste 0 50 100 150 200 250 seconds ramp 1 preheat ramp 2 reflow cooling 50 peak = 250 5?c 11 pcb design guidelines the recommended ACPM-7881 pcb land pattern is shown in figure 16. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding / bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown in figure 17. the stencil has a solder paste deposition opening that is approximately 80% of the pcb pad. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm (4 mils) or 0.127mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. the combined pcb and stencil layout is shown in figure 18. figure 16. pcb land pattern (dimensions in mm) figure 17. stencil outline drawing (dimensions in mm) figure 18. combined pcb and stencil layouts (dimensions in mm) 2.1 0.85 (pitch) 0.375 0.55 3.9 0.3 0.55 0.375 1.68 0.44 0.64 0.64 0.44 0.85 3.12 0.41 2.1 1.68 3.9 0.55 stencil opening 0.44 3.12 0.55 0.44 www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/inter- national), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2004 agilent technologies, inc. novermber 4, 2004 5989-1894en solder paste recommendation the ACPM-7881 package is a lead free package that was proven to pass msl3 when reflowed under lead free solder reflow profile. the recommended lead free solder for smt reflow is sn-ag-cu (95.5% tin, 3.8% silver, 0.7% copper) or other similar sn- ag-cu solders. this lead free solder paste has a melting point of 218c (423f), the ternary eutectic of sn-ag-cu system, giving it the advantage of being the lowest melting lead free alternative. this temperature is still low enough to protect from damaging the internal circuitry during solder reflow operations provided the exposure time at peak reflow temperatures is not too excessive. in certain situations, the designer may use leaded solder paste for reflow. the recommended solder for mounting ACPM-7881 package is sn63 (63% sn, 37% pb). it is a eutectic compound with a typical melting point of 183c. |
Price & Availability of ACPM-7881
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |