ds 208 (v.1.2) june 28, 2002 www.xilinx.com 1 data sheet, v3.0.99 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to change without notice. notice of disclaimer: xilinx is providing this design, code, or information "as is." by providing the design, code, or information as one possible imp lementation of this fea- ture, application, or standard, xilinx makes no representation that this implementation is free from any claims of infringement. you are responsibl e for obtaining any rights you may require for your implementation. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran- ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a p articular purpose. introduction with the xilinx logicore pci-x interface, a designer can build a customized pci-x 1.0a-compliant core with high sustained performance, 800 mbytes/sec. features ? fully pci-x 1.0a-compliant core, 64-bit, 100/66/33 mhz interface with 3.3 v operation customizable, programmable, single-chip solution predefined implementation for predictable timing incorporates xilinx smart-ip technology fully verified design tested with xilinx proprietary test- bench and hardware available for configuration and download on the web: - web-based configuration and download tool - web-based user constraint file generator tool instant access to new releases integrated extended capabilities: - pci-x capability item - power management capability item - message signalled interrupt capability item supported pci-x only functions: - split completion - memory read dword - memory read block - memory write block supported pci only functions: - memory read - memory read multiple - memory read line - memory write and invalidate 0 logicore pci interface v3.0 ds 208 (v.1.2) june 28, 2002 00 data sheet, v3.0.99 logicore facts pci-x64 / pci64 resource utilization 1 slice four input luts 2646 slice flip flops 1605 iob flip flops 257 iobs 90 bufgs / dcms 2 / 1 pci-x64 mode only resource utilization 1 slice four input luts 2126 slice flip flops 1461 iob flip flops 257 iobs 90 bufgs / dcms 1 / 1 pci64 mode only resource utilization 1 slice four input luts 1915 slice flip flops 1350 iob flip flops 253 iobs 90 bufgs / dcms 1 / 0 provided with core documentation pci-x design guide pci-x implementation guide design file formats verilog/vhdl simulation model ngo netlist constraint files user constraint files (ucf) example design verilog/vhdl example design design tool requirements xilinx tools v4.2i, service pack 3 tested entry and verification tools 2 synplicity synplify synopsys fpga express exemplar leonardo spectrum xilinx xst 3 cadence verilog xl model technology modelsim 1. the resource utilization depends on configuration of the interface and the user design. unused resources are trimmed by the xilinx technology mapper. the uti- lization figures reported in this table are representative of a maximum configura- tion. 2. see the implementation guide or product release notes for current supported ver- sions. 3. xst is command line option only. see implementation guide for details.
logicore pci interface v3.0 2 www.xilinx.com ds 208 (v.1.2) june 28, 2002 1-800-255-7778 data sheet, v3.0.99 more features supported pci and pci-x functions: -memorywrite - i/o read -i/owrite - configuration read - configuration write - interrupt acknowledge -busparking - type 0 configuration space header - full 64-bit addressing support - upto6baseaddressregisters - expansion rom base address register - instant-on base address registers - parity generation, parity error detection - full command/status registers applications embedded applications in networking, industrial, and telecommunication systems pci-x add-in boards such as frame buffers, network adapters, and data acquisition boards hot swap compactpci-x boards any applications that need a pci-x interface general description the logicore pci-x interface is a preimplemented and fully tested module for xilinx fpgas. critical paths are con- trolled by constraint and guide files to ensure predictable timing. this significantly reduces the engineering time required to implement the pci-x portion of your design. resources can instead be focused on your unique user application logic in the fpga and on the system level design. as a result, logicore pci-x products minimize your product development time. the core meets the setup, hold, and clock to timing require- ments as specified in the pci-x specification. the interface is verified through extensive simulation. other features that enable efficient implementation of a pci-x system include: block selectram? memory. blocks of on-chip ultra-fast ram with synchronous write and dual-port ram capabilities. used in pci-x designs to implement fifos. selectram memory. distributed on-chip ultra-fast ram with synchronous write option and dual-port ram capabilities. used in pci-x designs to implement fifos. the interface is carefully optimized for best possible perfor- mance and utilization in xilinx fpga devices. smart-ip technology drawing on the architectural advantages of xilinx fpgas, xilinx smart-ip technology ensures the highest perfor- mance, predictability, repeatability, and flexibility in pci-x designs. the smart-ip technology is incorporated in every logicore pci-x interface. xilinx smart-ip technology leverages the xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. this technology provides the best physical layout, predictability, and performance. addition- ally, these features allow for significantly reduced compile times over competing architectures. to guarantee the critical setup, hold, minimum clock to out, and maximum clock to out timing, the pci-x interface is delivered with smart-ip constraint files that are unique for a device and package combination. these constraint files guide the implementation tools so that the critical paths always are within specification. xilinx provides smart-ip constraint files for many device and package combinations. constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. functional description the logicore pci-x interface is partitioned into six major blocks and a user application as shown in figure 1 . datapath there are four datapaths, in and out for both target and ini- tiator. to improve timing and ease of design, the four unidi- rectional datapaths are multiplexed inside the interface. all data transfers are register-to-register. since fewer registers are on each datapath, loading is reduced and false timing paths are eliminated. logicore facts (cont) pci-x 64 supported devices pci64/33 only virtex-e v300ebg432-8c virtex-ii 2v1000fg456-5c 3.3v only 3.3v only pci-x64/66 only virtex-e v300ebg432-8c virtex-ii 2v1000fg456-5c 3.3v only 3.3v only pci-x64/100 only virtex-ii 2v1000fg456-5c 3.3v only pci-x64/66 pci64/33 virtex-ii 2v1000fg456-5c 3.3v only xilinx provides technical support for this logicore product when used as described in the design guide and the implementation guide. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if custom- ized beyond that allowed in the product documentation. note: fully compliant designs over 66 mhz require two bitstreams. note: universal card implementations not supported. note: commercial devices only; 0 c < t j <85c.
logicore pci interface v3.0 ds 208 (v.1.2) june 28, 2002 www.xilinx.com 3 data sheet, v3.0.99 1-800-255-7778 decode when an address is broadcast on the bus, the decode mod- ule compares it to the base address registers for a match. if one occurs, the target state machine is activated. pci-x configuration space this block provides the first 64 bytes of type 0, version 2.3 configuration space header, and an additional 64 bytes reserved for extended capabilities, as shown in ta b le 1 .the remaining 128 bytes of configuration space are available to the user for application specific registers. together, these support software-driven ?plug-and play? initialization and configuration. this includes information for command, sta- tus, base address registers, and the extended capabilities required for pci-x. three extended capabilities are provided in the interface: pci-x capability item power management capability item message signalled interrupt capability item these capability items may be linked or delinked from the capabilities list as required, and user functions can be inte- grated into the capabilities list. table 1: pci-x configuration space header watchdog the watchdog monitors various system conditions, includ- ing bus mode and bus width. this module also indicates if run-time reconfiguration is required for loading different bit- streams. target state machine this block controls the pci-x and pci interface for target functions. the controller is a high-performance state machine using one-hot encoding for maximum perfor- mance. figure 1: logicore pci-x interface block diagram data path mux targ init initiator status initiator control target control target status initiator datapath out initiator datapath in target datapath out target datapath in initiator state machine target state machine config space decode watchdog data path mux data path mux data path mux target hit 31 16 15 0 device id vendor id 00h status command 04h class code rev id 08h bist header type latency tim- er cache line size 0ch base address register 0 (bar0) 10h base address register 1 (bar1) 14h base address register 2 (bar2) 18h base address register 3 (bar3) 1ch base address register 4 (bar5) 20h base address register 5 (bar5) 24h cardbus cis pointer 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved capptr 34h reserved 38h max lat min gnt interrupt pin interrupt line 3ch power management capa- bility nxtcap pm cap 40h data pmcsr bse pmcsr 44h message control nxtcap msi cap 48h message address 4ch message upper address 50h reserved message data 54h pci-x command nxtcap pci-x cap 58h pci-x status 5ch reserved 60h-7fh available user configuration space 80h-ffh note: shaded areas are not implemented and return zero.
logicore pci interface v3.0 4 www.xilinx.com ds 208 (v.1.2) june 28, 2002 1-800-255-7778 data sheet, v3.0.99 initiator state machine this block controls the pci-x and pci interface for initiator functions. the initiator control logic also uses one-hot encoding for maximum performance. user interface the pci-x interface provides a simplified user application interface which allows a user to create one design that han- dles both pci-x and pci transactions without design changes, and both 32-bit and 64-bit data transfers without external data width conversion. this eliminates the need for multiple designs to support pci-x and pci and varying bus widths. this streamlined interface also simplifies the amount of work needed to create a user application. the user inter- face can be designed as either a 32-bit or 64-bit interface and the pci-x interface will automatically handle data con- versions regardless of the width of the pci-x or pci bus. interface configuration the logicore pci-x interface can easily be configured to fit unique system requirements by using the xilinx web-based configuration and download tool or by chang- ing the hdl configuration file. the following customization options, among many others, are supported by the interface and are described in the product design guide. base address registers (number, size, and mode) expansion rom bar cardbus cis pointer configuration space header rom interrupt connectivity extended command use capability configuration burst transfer the pci-x bus derives its performance from its ability to support burst transfers. the performance of any pci-x application depends largely on the size of the burst transfer. buffers to support pci-x burst transfer can efficiently be implemented using on-chip ram resources. supported pci commands table 2 lists the pci bus commands supported by the logi- core pci-x interface, and table 3 lists the supported pci-x bus commands. table 2: pci bus commands table 3: pci-x bus commands bandwidth the logicore pci-x interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. this interface supports a sustained band- width of up to 800 mbytes/sec. the design can be config- ured to take advantage of the ability of the logicore pci-x interface to do very long bursts. the flexible user application interface, combined with sup- port for many different pci-x features, gives users a solu- tion that lends itself to use in many high-performance applications. the user is not locked into one dma engine, hence, an optimized design that fits a specific application can be designed. cbe [3:0] command initiator target 0000 interrupt acknowledge yes yes 0001 special cycle yes no 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved ignore ignore 0101 reserved ignore ignore 0110 memory read 1 yes yes 0111 memory write yes yes 1000 reserved ignore ignore 1001 reserved ignore ignore 1010 configuration read yes yes 1011 configuration write yes yes 1100 memory read multiple 2 yes yes 1101 dual address cycle yes yes 1110 memory read line 2 yes yes 1111 memory write invalidate 2 yes yes 1. this command can only be used for a single dword transfer. 2. these commands have fixed byte enables of 0h . cbe [3:0] command initiator target 0000 interrupt acknowledge yes yes 0001 special cycle yes no 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved ignore ignore 0101 reserved ignore ignore 0110 memory read dword yes yes 0111 memory write yes yes 1000 alias to memory read block yes yes 1001 alias to memory write block yes yes 1010 configuration read yes yes 1011 configuration write yes yes 1100 split completion yes yes 1101 dual address cycle yes yes 1110 memory read block yes yes 1111 memory write block yes yes
logicore pci interface v3.0 ds 208 (v.1.2) june 28, 2002 www.xilinx.com 5 data sheet, v3.0.99 1-800-255-7778 recommended design experience the logicore pci-x interface is pre-implemented allow- ing engineering focus on the unique user application func- tions of a pci-x design. regardless, pci-x is a high-performance design that is challenging to implement in any technology. therefore, previous experience with build- ing high-performance, pipelined fpga designs using xilinx implementation software, constraint files, and guide files is recommended. the challenge to implement a complete pci-x design including user application functions varies depending on configuration and functionality of your appli- cation. contact your local xilinx representative for a closer review and estimation for your specific requirements. timing specifications the maximum speed at which your user design is capable of running can be affected by the size and quality of the design. the following tables show the key timing parame- ters for the logicore pci-x interface. timing parameters in the 66mhz pci-x are listed in ta b l e 4 . timing parameters in the 33mhz pci are listed in table 5 . ordering information this core may be downloaded from the xilinx ip center for use with the xilinx core generator system v4.1 and later. the xilinx core generator system tool is bundled with all alliance and foundation series software packages, at no additional charge. part numbers do-di-pcix64-ve -pci-x 64-bit 66/100 mhz ip only core DX-DI-64IP-XVE - upgrade from do-di-pci64/do-di-pci-al/do-di-pci64dk to do-di-pcix64-ve to order xilinx?s pci core, please visit the xilinx silicon xpresso cafe or contact your local xilinx sales representa- tive . information on additional xilinx logicore modules is avail- able on the xilinx ip center . table 4: timing parameters, 66mhz pci-x table 5: timing parameters, 33mhz pci revision history the following table shows the revision history for this document. symbol parameter min max t cyc clk cycle time 15 1 20 t high clk high time 6 - t low clk low time 6 - t val clk to signal valid delay (bussed signals) 0.7 2 3.8 2 t val clk to signal valid delay (point to point signals) 0.7 2 3.8 2 t on float to active delay 0 2 - t off active to float delay - 7 2 t su input setup time to clk (bussed signals) 1.7 2 - t su input setup time to clk (point to point signals) 1.7 2 - t h input hold time from clk 0.5 2 - t rstoff reset active to output float - 40 notes: 1. controlled by timespec constraints, included in product. 2. controlled by selectio configured for pcix. 3. operation at 100 mhz requires t su of 1.2 and t cyc of 10. symbol parameter min max t cyc clk cycle time 30 1 - t high clk high time 11 - t low clk low time 11 - t val clk to signal valid delay (bussed signals) 2 2 11 2 t val clk to signal valid delay (point to point signals) 2 2 11 2 t on floattoactivedelay 2 2 - t off active to float delay - 28 1 t su input setup time to clk (bussed signals) 7 2 - t su input setup time to clk (point to point signals) 10 2 - t h input hold time from clk 0 2 - t rstoff reset active to output float - 40 notes: 1. controlled by timespec constraints, included in product. 2. controlled by selectio configured for pci33_3 or pcix. date version revision 06/28/02 1.0 new template
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