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international: connect one ltd. 2 hanagar street kfar saba 44425, israel tel: +972-9-766-0456 fax: +972-9-766-0461 e-mail: info@connectone.com http://www.c onnectone.com usa: connect one semiconductors, inc. 4677 old ironsides drive, suite 280 santa clara, ca 95054 tel: 408-986-9602 fax: 408-986-9604 e-mail: info@connectone.com http://www.c onnectone.com pub. no. 11-3100-06, march 28, 2001 ichip co561ad-s ichip co561ad-c ichip lan co561ad-l datasheet
ichip & ichip lan datasheet ii information provided by connect one ltd. is believed to be accurate and reliable. however, no responsibility is assumed by connect one for its use, nor any infringement of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent rights of connect one other than for circuitry embodied in connect one?s products. connect one reserves the right to change circuitry at any time without notice. this document is subject to change without notice. the software described in this document is furnished under a license agreement and may be used or copied only in accordance with the terms of such a license agreement. it is forbidden by law to copy the software on any medium except as specifically allowed in the license agreement. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including but not limited to photocopying, recording, transmitting via fax and/or modem devices, scanning, and/or information storage and retrieval systems for any purpose without the express written consent of connect one. ichip, ichip lan, socket ichip, embedded imodem, internet controller, ilan, imodem, fax messenger, at+i, iware, and connect one are trademarks of connect one ltd. copyright ? 2000 - 2001 connect one ltd. all rights reserved.
revision history ichip & ichip lan datasheet iii revision history 11-3100-06 version date description 1.0 november 1999 original release for ichip co561ad-s. author amit resh 4.0 november 2000 updated with ichip lan co561ad-l. author jakob apelblat 5.0 february 2001 parallel modem obsolete. figure 4-1 ichip pin names changed for pin #14, 21, 40, 61 - 66. figure 4-2 ichip pin names changed for pin #14, 21, 28 ? 30, 40, 61 ? 63, 65. removed components for debugging from reference designs. author jakob apelblat 5.1 march 2001 chapter 2 ?ordering information? is new. figure 6-3, pin 61 of u2 connected to vcc, 56 no pin, 55, 54 changed, pin 40 of u1 connected via pull up to vcc, u3a changed to u4. figure 6-4, pin 40 of u1 connected via pull up to vcc. figure 7-1, pin 53, 56 changed. figure 7-3, 55, 54 changed. table 6-1, #27 p/n changed, #23, r10 added, #17, #28, #29, #32 updated. table 6-2, #14, r19 added, #11, #22, #24, #25, #27 updated. ?2.1 overview? updated. ?2.2.6 local bus connection to ethernet controller? updated. ?4.3.3 ichip serial modem signals? mmsel updated. chapter ?6.3 mechanical dimensions? has been updated. chapter 7.6 ?pld equations? reset removed. author jakob apelblat
contents ichip & ichip lan datasheet iv contents 1 introduction .............................................................................................................1-1 2 ordering information .............................................................................................2-1 2.1 ichip serial / lan / dual ............................................................................2-1 2.2 socket ichip .................................................................................................2-2 3 functional description ............................................................................................3-1 3.1 overview ......................................................................................................3-1 3.2 technical specifications ..............................................................................3-1 3.2.1 general .........................................................................................................3-1 3.2.2 data rates ....................................................................................................3-1 3.2.3 operation ......................................................................................................3-2 3.2.4 host serial connection.................................................................................3-2 3.2.5 serial connection to dial-up modem ..........................................................3-2 3.2.6 local bus connection to ethernet controller ..............................................3-3 3.2.7 hardware and software flow control .........................................................3-3 4 hardware interface .................................................................................................4-1 4.1 host interface ...............................................................................................4-1 4.2 serial modem interface................................................................................4-2 3.3 ethernet controller interface..................................................................................4-3 5 pin descriptions .......................................................................................................5-1 5.1 ichip co561ad-s pin assignments ...........................................................5-1 5.2 ichip lan pin assignments........................................................................5-2 5.3 ichip pin functional descriptions ...............................................................5-3 5.3.1 local bus signals.........................................................................................5-3 5.3.2 host interface signals ..................................................................................5-7 5.3.3 ichip serial modem signals ........................................................................5-8 5.4 ichip lan signals .......................................................................................5-9 6 electrical/mechanical specifications .....................................................................6-1 6.1 environmental specifications ......................................................................6-1 6.1.1 absolute maximum ratings.........................................................................6-1 6.1.2 dc operating characteristics.......................................................................6-2 6.2 interface timing and waveforms ................................................................6-3 6.2.1 local bus read cycle ..................................................................................6-3 6.2.2 local bus write cycle .................................................................................6-4 6.3 mechanical dimensions ...............................................................................6-5 7 ichip designs............................................................................................................7-1 7.1 general hardware architecture ...................................................................7-1 7.1.1 serial modem environment .........................................................................7-1
contents ichip & ichip lan datasheet v 7.1.2 ethernet controller environment .................................................................7-1 7.2 reference design for embedded imodem using co561ad-s...................7-2 7.3 bill of materials for co561ad-s reference design ..................................7-3 7.4 reference design for embedded ilan using co561ad-l.......................7-4 7.5 bill of materials for co561ad-l reference design ..................................7-5 7.6 pld equations .............................................................................................7-1 8 socket ichip tm carrier board ...............................................................................8-2 8.1 pin assignments...........................................................................................8-2 8.2 pin functional descriptions .........................................................................8-3 8.2.1 socket modem interface signals..................................................................8-3 8.2.2 host interface signals ..................................................................................8-4 8.3 socket ichip? package dimensions...........................................................8-6 8.4 reference design for co561ad-c based modem .....................................8-7 8.5 bill of materials for co561ad-c reference design ..................................8-8 9 pcb design and layout considerations ...............................................................9-1 9.1 design consideration ...................................................................................9-1 9.2 pc board layout guidelines........................................................................9-1 9.2.1 electromagnetic interference (emi) considerations ...................................9-2 9.2.2 other considerations in a modem design ...................................................9-3 10 protocol compliance ................................................................................10-1 11 list of terms and acronyms...................................................................11-1 12 index ..........................................................................................................12-1
figures ichip & ichip lan datasheet vi figures figure 1-1 ichip functional block diagram....................................................................1-2 figure 4-1 ichip co561ad-s with a serial modem interface .......................................4-2 figure 4-2 ichip lan with an ethernet controller interface ..........................................4-3 figure 5-1 plcc68 package for ichip co561ad-s serial version ..............................5-1 figure 5-2 plcc68 package for ichip lan co561ad-l serial version .....................5-2 figure 5-3 selecting a crystal ..........................................................................................5-5 figure 6-1 local bus read cycle ....................................................................................6-3 figure 6-2 local bus write cycle ...................................................................................6-4 figure 6-3 mechanical dimensions .................................................................................6-5 figure 7-1 serial modem environment ...........................................................................7-1 figure 7-2 ethernet controller environment ...................................................................7-1 figure 7-3 reference design for embedded imodem using co561ad-s.....................7-2 figure 7-4 reference design for embedded ilan using co561ad-l.........................7-4 figure 8-1 carrier board co561ad-c pinout ................................................................8-2 figure 8-2 socket ichip package dimensions .................................................................8-6 figure 8-3 reference design for co561ad-c based modem .......................................8-7
tables ichip & ichip lan datasheet vii tables table 4-1 host data format.............................................................................................4-1 table 5-1 data byte encoding .........................................................................................5-3 table 6-1 environmental specifications 3.3v version ...................................................6-1 table 6-2 environmental specifications 5v version ......................................................6-1 table 6-3 dc operating characteristics 3.3v version....................................................6-2 table 6-4 dc operating characteristics 5v version.......................................................6-2 table 7-1 bill of materials for co561ad-s reference design ......................................7-3 table 7-2 bill of materials for co561ad-l reference design......................................7-5 table 7-1 bill of materials for co561ad-c reference design .....................................8-8 table 10-1 internet protocol compliance ......................................................................10-1 table 11-1 terms and acronyms...................................................................................11-2
introduction ichip & ichip lan datasheet 1 - 1 1 introduction description the ichip? internet controller? is a family of low-cost intelligent peripheral device that provide internet connectivity solutions to a myriad of embedded devices. two firmware versions are available: ichip co561ad-s for dial-up and wireless internet connectivity, and ichip lan? co561ad-l for 10baset ethernet lan internet connectivity. for the sake of consistency, the name ?ichip? is used herein when referring to both ichip co561ad-s and ichip lan. otherwise, the specific product name is used. the socket ichip? internet controller, co561ad-c, is the ichip co561ad-s on a carrier board that is pin-compatible with conexant socketmodem?. as an embedded, self-contained internet engine, ichip acts as mediator device between a host processor and an internet communications platform. by completely offloading internet connectivity and standard protocols, it relieves the host from the burden of handling internet communications. from the perspective of a host device, the complexity of establishing and maintaining internet-related sessions are reduced to simple, straightforward commands that are entirely dealt with within ichip?s domain. a serial bus interfaces ichip co561ad-s to a device?s host processor via an on-chip uart. an optional 8/16-bit parallel interface to a host processor is supported as well by adding an external uart for low- bandwidth applications or a dual-port-ram for high bandwidth applications. ichip co561ad-s also directly interfaces a serial data modem, through which it supports independent communications on the internet via a dial-up isp connection. in addition to supporting dial-up modems, ichip co561ad-s also supports gsm modems. through its host application programming interface (api), ichip accepts commands formatted in connect one's at+i? extension to the renowned hayes at command set. commands are available to store and manipulate functional and internet-related non-volatile parameter data; transmit and receive textual email messages; transmit and receive binary (mime encoded) email messages; fetch html web pages; and download parameter and firmware updates for the host device or ichip itself. send command variants exist for immediate communications or scheduled "store- and-forward?. ichip supports several levels of status reporting to the host. when the host cpu issues standard at commands, ichip co561ad- s gains direct access to the modem, and automatically operates in transparent mode, emulating a direct host-to-modem environment. ichip lan? supports 10baset ethernet lans with the addition of an external 16-bit cirrus logic crystal lan cs8900a ethernet controller. at commands enable ichip lan to send and receive internet commands through the lan. upon receiving an at+i command, ichip operates in internet mode, controls the modem or ethernet controller, and independently manages standard internet protocols to transmit and receive messages. ichip provides all the necessary procedures to log onto an isp, authenticate the user and establish an internet session.
introduction ichip & ichip lan datasheet 1-2 functional block diagram pin diagram plcc68 figure 1-1 ichip functional block diagram general features microprocessor-controllable through a standard serial connection or optional parallel bus. supports remote firmware update by host, email, or direct modem-to- modem communications. includes onboard 128kb sram and 256kb or 512kb flash memory. supports up to 1mb of external memory. driven by connect one?s ?at+i" extension to the at command set. stand-alone internet communication capabilities. binary base64 encoding and mime. opens up to 5 tcp or udp sockets. power save mode reduces power consumption. 3.3 and 5v versions available, cmos technology. onboard non-volatile memory stores all functional and internet- related parameters. supports several layers of status reports. internal self-test procedures. internal "watch-dog" guard circuit. auto baud rate detection. includes hardware and software flow control. plcc68 package. dial-up features supports following internet protocols and formats: ppp, lcp, ipcp, ip, tcp, udp, dns, smtp, pop3, http and pap, chap, or script authentication. supports data modems up to 56 kbps throughput. supports gsm modems. stay-on-line feature for multiple send/receive. lan features supports following internet protocols and formats: arp, ip, icmp, tcp, udp, dns, dhcp, smtp, pop3, mime, and http. provides 10baset ethernet lan connectivity via crystal lan cs8900a ethernet controller supports up to 230 kbps throughput. host serial interface local parallel/serial interface ichip rx,tx,cts,rts,dtr reset l d0-d15 l a0-a19 rx,tx,cts,rts,dtr x1 x2 cs modem lnint ~w r ~rd crystal cpu core sram 128 kb flash 256 kb -or- 512 kb co561ad-s/l 50-3150-01 0032 ?connect one ?00
ordering information ichip & ichip lan datasheet 2 - 1 2 ordering information 2.1 ichip / ichip lan order number connect one?s standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. co561ad -s /20 p c ? 5 product code version: s = serial l = lan clock: 20 = mhz package: p = plcc 68 pin temperature range: c = commercial (0-70) voltage: 5 = 5v 3 = 3.3v
ordering information ichip & ichip lan datasheet 2-2 2.2 socket ichip order number connect one?s standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. co561ad -c /20 d c ? 5 product code version: c = socket clock: 20 = mhz package: d = dip 64 pin temperature range: c = commercial (0-70) voltage: 5 = 5v 3 = 3.3v
functional description ichip & ichip lan datasheet 3-1 3 functional description 3.1 overview connect one?s ichip internet controller is an integrated, firmware-driven, self-contained internet engine that is available in a 68-pin plcc package. ichip accepts simple ascii commands from a host cpu via a serial communication bus and manages an internet communication session to send and receive email and web pages, and to open and close sockets through a linked modem or ethernet communications platform. for dial-up and gsm cellular modem configurations, ichip co561ad-s is available in two forms: co561ad-s interfaces a serial modem. co561ad-s is also available mounted on a carrier board, co561ad-c that is pin-compatible with conexant?s socketmodem. for 10baset ethernet applications, ichip lan co561ad-l includes the firmware and pin-out necessary to drive an external crystal lan cs8900a 10baset ethernet controller. ichip co561ad-s and ichip lan contain non-volatile flash memory to store their firmware and internet-related operational parameters. remote firmware and parameter updates are supported through the host link, by email or directly through the communications platform. 3.2 technical specifications 3.2.1 general ichip constitutes a complete internet messaging solution for non-pc embedded devices. it acts as a mediator device to completely offload the host processor of internet-related software and activities. an industry-standard asynchronous serial link connects ichip to the host processor. programming, monitoring and control are fully supported using connect one?s at+i extension to the standard at command set. an additional industry-standard asynchronous serial link connects ichip co561ad-s to a standard serial modem ,while ichip lan co561ad-l connects to an ethernet mac for internet access. in serial modem configurations, ichip supports direct host-to-modem operations using the standard at command set. 3.2.2 data rates ichip supports standard baud rate configurations from 2,400 bps up to 57,600 bps, while ichip lan supports bandwidth up to 230,000 bps on the host asynchronous serial communications bus. for safety reasons, ichip is shipped with a default zero connection rate. the default baud rate may be changed permanently by using the at+ibdr command.
functional description ichip & ichip lan datasheet 3-2 3.2.3 operation all ichip internet and parameter operations are controlled by at+i commands. 3.2.3.1 transparent mode in modem configurations, ichip co561ad-s defaults to transparent mode, allowing the host to control the modem device directly. control is implemented by the host issuing standard at commands to ichip. in this mode, ichip co561ad-s transparently echoes the at commands to the modem, as well as echoing the modem responses back to the host. in addition, hardware flow control signals are emulated on the host side to reflect the levels set by the modem and vice-versa. ichip co561ad-s supports interlacing at+i and at commands, while the modem is in command mode. when the modem is put into data mode, by issuing a dial command, transparent mode is sustained throughout the data-mode session. 3.2.3.2 command mode ichip commands are implemented using the at+i command set. command flow exists only on the host serial bus between the host and ichip. 3.2.3.3 internet mode ichip enters internet mode after being issued an internet messaging command to send or receive an email message. ichip attempts to establish an internet connection and carry out the required activity through the communication platform link. while in this mode, at+i commands are supported to monitor and control the process when needed. all other at+i commands return with an i/busy response. 3.2.3.4 direct modem firmware update mode in a modem configuration, issuing an at+ifu command enters this mode. ichip co561ad-s monitors the modem for an incoming call by detecting the ?ring? response. when called, ichip co561ad-s instructs the modem to answer the call and assumes a ymodem session to receive a file containing a firmware update. the incoming file contents are downloaded and authenticated. if the new firmware image checks out the existing firmware is replaced in the on-chip flash memory and ichip co561ad-s is reinitialized. 3.2.4 host serial connection ichip supports a full-duplex, ttl-level serial communications link with the host processor. full eia-232-d hardware flow control, including tx, rx, cts, rts, and dtr lines, is supported. 3.2.5 serial connection to dial-up modem ichip co561ad-s supports a full-duplex, ttl-level serial communications link with the modem device. full eia-232-d hardware flow control, including tx, rx, cts, rts, and dtr lines, is supported.
functional description ichip & ichip lan datasheet 3-3 3.2.6 local bus connection to ethernet controller ichip lan co561ad-l directly supports a crystal lan cs8900a ieee 802.3 ethernet controller in 16-bit memory mode. interrupt and dma request are directly connected to dedicated inputs. a small pld or discrete logic is required to generate the memrd#/memwe# and iord#/iowr# signals that form ichip?s rd# and wr# signals to simulate memory, io and dma accesses. see section "6.4 reference design for embedded lan using ichip lan co561ad-l". 3.2.7 hardware and software flow control hardware flow control is supported between the host cpu and ichip. hardware flow control is also provided between the ichip co561ad-s and the modem. flow control is programmed via the at+iflw command. the default flow control methods are set to wait/continue software flow control between ichip and host, and no flow control between ichip and modem. the hardware flow control method frees the host cpu from monitoring and handling the software flow control. the host can program ichip to either use hardware flow control or to use wait/continue software flow control between the ichip and the host cpu. the flow control mechanism is based on the rts/cts signals. flow control between ichip and the modem can be individually programmed to hardware flow control or no flow control. the crystal ethernet controller cs8900a provides sufficient buffers to support the packet flow control on tcp/ip level between ichip lan and the ethernet lan.
hardware interface ichip & ichip lan datasheet 4-1 4 hardware interface ichip co561ad-s interfaces between a host cpu and a modem. 4.1 host interface the host interface is a serial dte interface. ichip can change the rate and format of the data sent and received from the host cpu. speeds of 2400, 4800, 7200, 9600, 19200, 38400, and 57600 bps (ichip lan up to 230,000 bps) are supported in the following data formats: parity data length (no. of bits) no. of stop bits character length (no. of bits) none 8 1 10 table 4-1 host data format
hardware interface ichip & ichip lan datasheet 4-2 4.2 serial modem interface figure 4-1 ichip co561ad-s with a serial modem interface in addition to a serial modem interface, ichip supports a memory expansion option, which is used to increase the store-and-forward buffer. ichip co561ad-s serial version rx,tx, cts,rts,dtr,dsr, ri,cd rx,tx, cts,rts,dtr,dsr, cd uart with auto baud rate uart local addr bus 20-bit data bus 16-bit local bus interface unit cpu core three 16-bit timers interrupt controller wr rd internal flash 256 kb or 512 kb internal ram 128 kb wdt ram expansion cs dma controller host serial modem
hardware interface ichip & ichip lan datasheet 4-3 3.3 ethernet controller interface ichip lan co561ad-l figure 4-2 ichip lan with an ethernet controller interface ichip and ichip lan support a memory expansion option, which is used to increase the store-and-forward buffer.
pin descriptions ichip & ichip lan datasheet 5-1 5 pin descriptions 5.1 ichip co561ad-s pin assignments figure 5-1 plcc68 package for ichip co561ad-s serial version ~ctsm ~dtrm vcc ad5 ad4 ad3 ad2 ad1 ad0 a17 ad7 ad14 ad13 ~res ad11 -flcs ~dsrh ad10 ad9 a 16 a 13 a 19 a 15 a 12 a 14 a 5 clko x2 x1 a le urtint a 18 a 8 a 7 a 4 a 3 a 11 a 9 gnd a10 a0 ~cdh hold ~rih mmsel ~dsrm ~cdm gnd ~rd a2 a6 ~rtsm rxdh txdm rxdm txdh ad15 ad6 ad12 ad8 ~lcs ~dtrh a1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 53 5 4 55 56 57 58 59 60 61 62 63 64 65 66 67 68 52 ~wr ~bhe 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 34 ~rtsh ~ctsh hlda co561ad-s
pin descriptions ichip & ichip lan datasheet 5-2 5.2 ichip lan pin assignments figure 5-2 plcc68 package for ichip lan co561ad-l serial version nc landr q vcc ad5 ad4 ad3 ad2 ad1 ad0 a17 ad7 ad14 ad13 ~res ad11 ~ucs ~dsrh ad10 ad9 a 16 a 13 a 19 a 15 a 12 a 14 a 5 clko x2 x1 a le urtint a 18 a 8 a 7 a 4 a 3 a 11 a 9 gnd a10 a0 ~cdh hold ~rih lanint ~lmsel nc gnd ~rd a2 a6 nc rxdh nc nc txdh ad15 ad6 ad12 ad8 ~lcs ~dtrh a1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 53 5 4 55 56 57 58 59 60 61 62 63 64 65 66 67 68 52 ~wr ~bhe 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 34 ~rtsh ~ctsh hlda co561ad-l
pin descriptions ichip & ichip lan datasheet 5-3 5.3 ichip pin functional descriptions 5.3.1 local bus signals a19?a0 address bus (output, three-state, synchronous) these pins supply non-multiplexed memory or i/o addresses to the system one half of a clko period earlier than the multiplexed address and data bus ad15?ad0. during a bus hold or reset condition, the address bus is in a high-impedance state. ad15?ad0 address and data bus (input/output, three-state, synchronous, level-sensitive) ad15?ad0 ?these time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an address to the system during the first period of a bus cycle. it supplies data to the system during the remaining periods of that cycle. when ~wr is deasserted, these pins are three-stated. ale address latch enable (output, synchronous) this pin indicates to the system that an address appears on the address and data bus (ad15?ad0). the address is guaranteed to be valid on the trailing edge of ale. this pin is not three-stated during a bus hold or reset. ~ bhe bus high enable (three-state, output, synchronous) during a memory access, this pin and the least-significant address bit (ad0 or a0) indicate to the system, which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the ~bhe and ad0 pins are encoded as shown in the table below. ~bhe ad0 type of bus cycle 0 0 word transfer 1 0 even byte transfer 0 1 odd byte transfer 1 1 n/a table 5-1 data byte encoding bhe floats during bus hold and reset. during refresh cycles, the a bus and the ad bus are not guaranteed to provide the same address during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. clko clock output. this pin supplies the internal clock to the system. clko remains active during reset.
pin descriptions ichip & ichip lan datasheet 5-4 ~ucs upper chip select (output, synchronous) this pin indicates to the system that that a memory access is in progress to the flash memory. normally this pin should be open. hold bus hold request (input, synchronous, level sensitive) this pin indicates to the ichip that an external bus master needs control of the local bus . normally this pin should connect to gnd. hlda bus hold acknowledge (output , synchronous, level sensitive) this pin asserted high to indicate to an external bus master that the ichip has release control of local bus. normally this pin should be open. ~lcs low memory ram chip select (output, synchronous) this pin indicates to the system that that a memory access is in progress to the static ram memory. normally this pin should be open. ~rd read strobe (output, synchronous, three-state) this pin indicates to the system that the ichip is performing a memory or i/o read cycle. ~rd is guaranteed to not be asserted before the address and data bus is floated during the address-to-data transition. ~rd floats during a bus hold condition. ~ res reset (input, asynchronous, level-sensitive) this pin requires the ichip to perform a reset. when ~res is asserted, the ichip immediately terminates its present activity and clears its internal logic. ~res must be held low for at least 1 ms. ~res can be asserted asynchronously to clko because ~res is synchronized internally. for proper initialization, vcc must be within specifications, and clko must be stable for more than four clko periods during which res is asserted. the ichip begins fetching instructions approximately 6.5 clko periods after ~res is de-asserted. this input is provided with a schmidt trigger to facilitate power-on res generation via an rc network. urtint uart interrupt (input , asynchronous) this pin for debugging only . it must be pull up to vcc with resistor of 4.7k.
pin descriptions ichip & ichip lan datasheet 5-5 ~wr write strobe (output, synchronous) this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. ~wr floats during reset condition. x1 crystal input (input) this pin and the x2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the ichip with an external clock source, connect the source to the x1 pin and leave the x2 pin unconnected. x2 crystal output (output) this pin and the x1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. to provide the ichip with an external clock source, leave the x2 pin unconnected and connect the source to the x1 pin. selecting a crystal figure 5-3 selecting a crystal the characteristics of the built-in inverting amplifier set limits on the following parameters for crystals: crystal first overtone frequency .................. 18.432 mhz esr (equivalent series resistance) ............ 40 ? max drive level ............................................?.. 1 mw max the recommended range of values for c 1 and c 2 are as follows: c 1 ............................................................... 15 pf 20% c 2 ............................................................... 22 pf 20% the specific values for c1 and c2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. gnd ground ground pins connect the ichip to the system ground. x1 x2 c1 c2 crystal
pin descriptions ichip & ichip lan datasheet 5-6 vcc power supply (input) these pins supply power (+5 v) to the ichip.
pin descriptions ichip & ichip lan datasheet 5-7 5.3.2 host interface signals txdh transmit data host (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port. rxdh receive data host (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port. ~ctsh clear-to-send host (input, asynchronous) this pin provides the clear to send signal for asynchronous serial port when the hardware flow control is enabled for the port. the ~ctsh signal gates the transmission of data from the associated serial port transmit register. when ~ctsh is asserted, the transmitter begins transmission of a frame of data, if any is available. if ~ctsh is de- asserted, the transmitter holds the data in the serial port transmit register. the value of ~ctsh is checked only at the beginning of the transmission of the frame. ~rtsh ready-to-send host (output, asynchronous) this pin provides the ready to send signal for asynchronous serial port when the hardware flow control is enabled for the port. the ~rtsh signal is asserted when the associated serial port transmit register contains data which has not been transmitted. ~dsrh data set ready host (input, synchronous) when flow control is enabled, this pin is data set ready input. ~ dtrh data terminal ready host (output, synchronous) when flow control is enabled, this pin operates as data terminal ready output. ~cdh carrier detect host (output, synchronous) this pin indicates to the system that a carrier was detected by the communication device (modem). ~rih ring indicator host (output, synchronous) this pin indicates to the system that a ring signal was detected by communication device (modem).
pin descriptions ichip & ichip lan datasheet 5-8 5.3.3 ichip serial modem signals rxdm receive data modem (input, asynchronous) this pin supplies asynchronous serial receive data from modem to asynchronous serial port. txdm transmit data modem (output, asynchronous) this pin supplies asynchronous serial transmit data to modem from serial port. ~cdm carrier detect modem (input, asynchronous, internal pull-up) when configured in serial-to-serial mode, this pin is carrier detect input. ~dsrm data set ready modem (input, asynchronous). when flow control is enabled, this pin is data set ready input. ~rtsm ready-to-send modem (output, asynchronous) this pin provides the ready to send signal for asynchronous serial port when the hardware flow control is enabled for the port. the ~rtsm signal is asserted when the associated serial port transmit register contains data that has not been transmitted. ~ctsm clear-to-send modem (input, asynchronous) enable-receiver-request m (input, asynchronous) this pin provides the clear to send signal for asynchronous serial port when flow control option is enabled. the ~ctsm signal gates the transmission of data from the associated serial port transmit register. when ~ctsm is asserted, the transmitter begins transmission of a frame of data, if any is available. if ~ctsm is de-asserted, the transmitter holds the data in the serial port transmit register. the value of ~ctsm is checked only at the beginning of the transmission of the frame. ~dtrm data terminal ready modem(output, asynchronous) when flow control is enabled, this pin is channel data terminal ready output. mmsel modem mode input (input, asynchronous ) (for modem application only ) when this pin is held low during power up, for at least 5 seconds, the ichip will automatically enter firmware update mode. during a firmware update procedure, when an external modem dials to the ichip, pulling this pin down to low will cause the ichip to immediately answer the call and begin the update session. when this pin is held low during power up for less than 5 seconds, it forces the ichip into auto baud rate detection.
pin descriptions ichip & ichip lan datasheet 5-9 5.4 ichip lan signals lanint lan interrupt (active high input) this pin inputs the interrupt from the ethernet controller. landrq lan dma request (active high input) this pin inputs the dma request from the ethernet controller. lmsel lan mode input (input, asynchronous ) (for lan application only ) when this pin is held low during power up, for at least 5 seconds, the ichip will automatically enter firmware update mode.
electrical/mechanical specifications ichip & ichip lan datasheet 6-1 6 electrical/mechanical specifications 6.1 environmental specifications 6.1.1 absolute maximum ratings 6.1.1.1 3.3 volt version parameter rating voltage at any pin with respect to ground -1.0 to vcc + 0.5 volts operating temperature 0 c to 70 c (32 to 158 f) storage temperature -60 c to 120 c (?76 to 248 f) soldering temperature (max. 10 sec.) 220 c (428 f) package dissipation 1.5 watts table 6-1 environmental specifications 3.3v version 6.1.1.2 5 volt version parameter rating voltage at any pin with respect to ground -1.0 to +7.0 volts operating temperature 0 c to 70 c (32 to 158 f) storage temperature -60 c to 120 c (?76 to 248 f) soldering temperature (max. 10 sec.) 220 c (428 f) package dissipation 1.5 watts table 6-2 environmental specifications 5v version
electrical/mechanical specifications ichip & ichip lan datasheet 6-2 6.1.2 dc operating characteristics 6.1.2.1 3.3 volt version parameter min typical max units dc supply 3.0 3.3 3.6 volts high-level input 2.0 vcc+0.5 volts low-level input -0.5 0.8 volts high-level output 1 2.4 vcc volts low-level output 0.45 volts input leakage current +/- 10 a power supply current (operating mode) 2 30 60 ma power supply current (power save mode) 0.25 0.5 ma input capacitance 20 pf notes: 1 i ol = 2ma 2 20 mhz clock table 6-3 dc operating characteristics 3.3v version 6.1.2.2 5 volt version parameter min typical max units dc supply 4.75 5.0 5.25 volts high-level input 2.0 vcc+0.5 volts low-level input -0.5 0.8 volts high-level output 1 2.4 vcc volts low-level output 0.45 volts input leakage current +/- 10 a power supply current (operating mode) 2 160 250 ma power supply current (power save mode) 10 ma input capacitance 20 pf notes: 1 i ol = 2ma 2 20 mhz clock table 6-4 dc operating characteristics 5v version
electrical/mechanical specifications ichip & ichip lan datasheet 6-3 6.2 interface timing and waveforms 6.2.1 local bus read cycle figure 6-1 local bus read cycle a19-a0 address ad15-ad0 (read) ale clko tclk-3 tclk 10 ucs lcs ~rd ~bhe 2tclk-15 ~bhe 0-25 0-25 data 3 25 25
electrical/mechanical specifications ichip & ichip lan datasheet 6-4 6.2.2 local bus write cycle figure 6-2 local bus write cycle a19-a0 address ad15-ad0 (read) ale clko tclk-3 tclk ucs lcs ~wr ~bhe 2tclk-10 ~bhe 0-25 0-20 data 0 25 25 15
electrical/mechanical specifications ichip & ichip lan datasheet 6-5 6.3 mechanical dimensions figure 6-3 mechanical dimensions 1.27 mm/ 0.050? 2.69 mm/ 0.106? co561ad-s//l ichip tm /ichip lan tm 25.2 mm/ 0.995? 1.78 mm/0.070? 4.9 mm/ 0.193? 0.5 mm/ 0.020? 24.5mm/ 0.965?
ichip designs ichip & ichip lan datasheet 7-1 7 ichip designs 7.1 general hardware architecture 7.1.1 serial modem environment figure 7-1 serial modem environment 7.1.2 ethernet controller environment figure 7-2 ethernet controller environment data modem seria l ichip embedded cpu (host) phone seria l ethernet controller ichip lan embedded cpu (host) lan serial d0-15 a0-19 rd w r ir q cs aen memwr memrd iowr iord pld
ichip designs ichip & ichip lan datasheet 7-2 7.2 reference design for embedded imodem using co561ad-s figure 7-3 reference design for embedded imodem using co561ad-s
ichip designs ichip & ichip lan datasheet 7-3 7.3 bill of materials for co561ad-s reference design # qty reference designator p/n, description manufacturer 1. 4 c1,c2,c3,c4 1uf/16v, tantalum 2. 4 c5,c8,c14,c16 0.1uf, ceramic 3. 1 c6 0.047uf ceramic 4. 2 c7,c13 10uf/6.3v 5. 1 c9 33pf, ceramic 6. 1 c10 22pf, ceramic 7. 2 c11,c12 1nf/3kv 8. 1 c15 1000uf/25v 9. 16 c17,c18,c19,c20,c21,c22, 56pf, ceramic 10. c23,c24,c25,c26,c27,c28, 11. c29,c30,c31,c32 12. 2 c33,c34 10uf/16v 13. 5 d1,d2,d3,d4,d5 led, 10ma 14. 1 j1 dc-jack-male 15. 1 j2 db-9/female 16. 1 j3 rj11 17. 1 ls1 hpe-1206, speaker 50 ? 18. 8 l1,l2,l3,l4,l5,l6,l7,l8 bk2125hs601 taiyoyuden co. ltd. 19. 2 l9,l10 2961666681 fair rite inc. 20. 1 rv1 1.5ke220a 21. 1 r1 10, 0.125w 22. 2 r2,r3 18r, 0.75w 23. 3 r7,r9,r10 4.7k, 0.125w 24. 2 r4,r8 470, 0.125w 25. 1 s1 pb switch 26. 1 u1 co561ad-s connect one ltd. 27. 1 u2 sf336d/sp-h1-d5 conexant 28. 1 u3 7805 29. 1 u4 mc34164p on semiconductor 30. 1 u5 max237cwg maxim integrated products 31. 1 u6 lm386d national semiconductor 32. 1 y1 18.432mhz, parallel resonance, 100ppm table 7-1 bill of materials for co561ad-s reference design item #27 sf xx d/sp-h1- yy , conexant socket modem, can be ordered in the following configurations: xx = 56 (56,000 bps), 336 (33,600 bps), 144 (14,400 bps) yy = d5: (u.s), df (france), dg (germany), dt (italy), de (spain), dj (japan), dc (ctr21: ctr21 countries include austria, belgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, norway, portugal, spain, sweden, switzerland, the netherlands, and uk. the country is selected by issuing the at*nc70 command.)
ichip designs ichip & ichip lan datasheet 7-4 7.4 reference design for embedded ilan using co561ad-l figure 7-4 reference design for embedded ilan using co561ad-l
ichip designs ichip & ichip lan datasheet 7-5 7.5 bill of materials for co561ad-l reference design # qty reference designator p/n, description manufacturer 1 1 c10 68pf 2 13 c1,c2,c3,c4,c5,c6,c7,c11, 0.1uf c12,c13,c16,c22,c24 3 6 c14,c15,c17,c18,c19,c20 1uf/16v-a 4 1 c21 100uf/16v 5 1 c23 10uf/16v-b 6 2 c8,c9 22pf 7 5 d1,d2,d3,d4,d5 led 8 1 jp1 rj-725 transpower 9 1 j2 dc-jack-male 10 1 j3 db-9/female 11 8 l1,l2,l3,l4,l5,l6,l7,l8 knh21471 avx corporation 12 1 l9 2961666681 fair rite 13 1 r1 100/1% 14 3 r2,r3,r19 4.7k 15 2 r4,r7 24.3/1% 16 1 r5 100k 17 1 r6 0 18 6 r8,r9,r10,r11,r13,r17 470 19 1 r12 4.99k/1% 20 2 r15,r14 10k 21 1 s1 pb sw 22 1 u1 co561ad-l connect one ltd. 23 1 u2 cs8900a crystal 24 1 u3 tl7705acd texas instruments 25 1 u5 pal16v8 26 1 u7 max237cwg maxim integrated products 27 1 u8 7805 28 1 y1 18.432mhz, parallel resonance, 100ppm 29 1 y2 20mhz, parallel resonance, 50ppm table 7-2 bill of materials for co561ad-l reference design
socket ichip carrier board ichip & ichip lan datasheet 7-1 7.6 pld equations ------------------------------------------------------------------ -- file name: imdlnref.vhd -- designed by: leonid epstein -- purpose: ilan board control logic. -- the board memory map: -- 0x00000 - 0x1ffff - system sram -- 0x20000 - 0x27fff - lan io space (32kb) -- (default io 0x300 so the first access s.b. to 0x20300) -- 0x28000 - 0x2ffff - lan dma access (32kb) -- 0x38000 - 0x3ffff - lan memory space (32kb) -- 0x80000 - 0xfffff - system flash ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity imdlnref is port ( a : in std_logic_vector(19 downto 15); wr_n : in std_logic; rd_n : in std_logic; memwr_n : out std_logic; memrd_n : out std_logic; iowr_n : out std_logic; iord_n : out std_logic; aen : out std_logic ); attribute loc : string ; attribute loc of wr_n : signal is "p2" ; attribute loc of rd_n : signal is "p3" ; attribute loc of a15 : signal is "p4" ; attribute loc of a16 : signal is "p5" ; attribute loc of a17 : signal is "p6" ; attribute loc of a18 : signal is "p7" ; attribute loc of a19 : signal is "p8" ; attribute loc of memwr_n : signal is "p13" ; attribute loc of memrd_n : signal is "p14" ; attribute loc of iowr_n : signal is "p15" ; attribute loc of iord_n : signal is "p16" ; attribute loc of aen : signal is "p17" ; end imdlnref; architecture behavioral of imdlnref is signal mem_access: std_logic; signal io_access: std_logic; signal dma_access: std_logic; begin mem_access <= '1' when a(19 downto 16) = "0011" and a(15) = '1' else '0'; -- 0x38000 - 0x3ffff ; io_access <= '1' when a(19 downto 16) = "0010" and a(15) = '0' else '0'; -- 0x20000 - 0x27fff ; dma_access <= '1' when a(19 downto 16) = "0010" and a(15) = '1' else '0'; -- 0x28000 - 0x2ffff ; memwr_n <= wr_n when mem_access = '1' else '1'; memrd_n <= rd_n when mem_access = '1' else '1'; iowr_n <= wr_n when io_access = '1' or dma_access = '1' else '1'; iord_n <= rd_n when io_access = '1' or dma_access = '1' else '1'; aen <= '1' when dma_access = '1' else '0' ; end behavioral;
socket ichip carrier board ichip & ichip lan datasheet 8-2 8 socket ichip tm carrier board the socket ichip? internet controller, co561ad-c, is the ichip co561ad-s on a carrier board that is pin-compatible with conexant socketmodem?. 8.1 pin assignments figure 8-1 carrier board co561ad-c pinout component side sqt--111-03--l-s-mw sqt--109-03--l-s-mw sqt--109-03--l-s-mw mms-109-02-l-sv-k pt64(spkr) pt54(~vc) pt53(~voice) pt56 (nc) t pt57(lcs) pt58(telou) pt59(telin) pt60(micm) vcc pt62(micv) gnd 64 56 57 58 59 60 61 62 54 63 55 9 8 7 6 5 4 3 2 1 pt1(tip) pt2(ring) pt5(acout1) pt6(acout2) pt7(xfmr1) pt8(xfmr2) pt9(rdet/cid) pt3(rdetin1) pt4(rdetin2) 32 31 30 29 28 27 26 24 25 dgnd pt24(~reset) pt25(nc) pt27(~rdl) pt29(dcdin) pt30(rxind) pt31(dtrind) pt32(txind) pt28(~pulse) tmm-109-01-l-s-sm ~dsrh ~dcdh ~dtrh gnd ~rtsh ~rih ~ctsh txdh rxdh 35b 41b 40b 39b 38b 37b 36b 34b 33b 35b print side connector txdm ~dsrm ~cdm ~dtrm ~ctsm ~rtsm rxdm ~rim gnd 41t 40t 39t 38t 37t 36t 35t 34t 33t
socket ichip carrier board ichip & ichip lan datasheet 8-3 8.2 pin functional descriptions 8.2.1 socket modem interface signals ptx pass-through connections. the board provides pass-through connection between a motherboard and a socket modem mounted on top of the co561ad-ct/r. pins pt1 .. pt9 are dedicated for tnv signals. the co561ad-ct/r board layout meets en 60950:1992 +a1/a2:1993 +a3:1995 requirements for creepage distance and clearance. signal names in brackets correspond to conexant?s? socket modem data sheet. vcc +5vdc dgnd digital ground. connect to digital ground on the interface circuit. ~reset modem and ichip reset. the active low ~reset input resets both the ichip and a socketmodem logic and returns the at command set to the original factory default values and to "stored values" in nvram. agnd analog ground. connect to analog ground on the interface circuit. note that agnd is connected to dgnd on the socketmodem. rxdm, received data (ttl active low, eia-232 active high), input. this pin supplies asynchronous serial receive data from socket modem to asynchronous serial port . txdm, transmitted data modem (ttl active low, eia-232 active high), output . this pin supplies asynchronous serial transmit data to socket modem from serial port . ~ctsm, clear to send modem (ttl active low, eia-232 active high), input this pin provides the clear to send signal for asynchronous serial port when flow control option is enabled. the ~ctsm signal gates the transmission of data from the associated serial port transmit register. when ~ctsm is asserted, the transmitter begins transmission of a frame of data, if any is available. if ~ctsm is de-asserted, the
socket ichip carrier board ichip & ichip lan datasheet 8-4 transmitter holds the data in the serial port transmit register. the value of ~ctsm is checked only at the beginning of the transmission of the frame. ~rtsm, ready to send modem (ttl active low, eia-232 active high),output this pin provides the ready to send signal for asynchronous serial port when the hardware flow control is enabled for the port. the ~rtsm signal is asserted when the associated serial port transmit register contains data that has not been transmitted. ~dtrm, data terminal ready modem (ttl active low, eia-232 active high), output. when flow control is enabled, this pin is channel data terminal ready output. ~dsrm, data set ready modem (ttl active low, eia-232 active high), input. when flow control is enabled, this pin is data set ready input. ~rim, ring indicate modem (ttl active low, eia-232 active high), input. ~rim input on (low) indicates the presence of an on segment of a ring signal on the telephone line (this signal is ignored by the socket ichip). ~cdm, carrier detect modem (ttl active low, eia-232 active high), input. this pin is the carrier detect input from the modem. 8.2.2 host interface signals co561ad-ct/r interfaces to a host cpu via asynchronous serial interface with ttl (t) or eia-232 (r) signal levels. ~ txdh/txd232 transmit data host (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from serial port. ~rxdh/rxd232 receive data host (input, asynchronous) this pin supplies asynchronous serial receive data from the system to asynchronous serial port. ~ctsh/cts232 clear-to-send host (input, asynchronous) this pin provides the clear to send signal for asynchronous serial port 1 when the hardware flow control is enabled for the port. the ~ctsh signal gates the transmission of data from the associated serial port transmit register. when ~ctsh is asserted, the transmitter begins transmission of a frame of data, if any is available. if ~ctsh is de- asserted, the transmitter holds the data in the serial port transmit register. the value of ~ctsh is checked only at the beginning of the transmission of the frame.
socket ichip carrier board ichip & ichip lan datasheet 8-5 ~rtsh/rts232 ready-to-send host (output, asynchronous) this pin provides the ready to send signal for asynchronous serial port when the hardware flow control is enabled for the port. the ~rtsh signal is asserted when the associated serial port transmit register contains data which has not been transmitted. ~dsrh/dsr232 data set ready host (input, synchronous) when flow control is enabled, this pin is data set ready input ~dtrh/dtr232 data terminal ready host (input, synchronous) when flow control is enabled, this pin operates as data terminal ready output ~cdh/cd232 carrier detect host (output, synchronous) this pin indicates to the system that carrier was detected by communication device (modem). ~rih/ri232 ring indicator host (output, synchronous) this pin indicates to the system that ring signal was detected by communication device (modem).
socket ichip carrier board ichip & ichip lan datasheet 8-6 8.3 socket ichip? package dimensions figure 8-2 socket ichip package dimensions
socket ichip carrier board ichip & ichip lan datasheet 8-7 8.4 reference design for co561ad-c based modem figure 8-3 reference design for co561ad-c based modem
socket ichip carrier board ichip & ichip lan datasheet 8-8 8.5 bill of materials for co561ad-c reference design # qty reference designator p/n, description manufacturer 1. 4 c1,c2,c3,c4 1uf/16v, tantalum 2. 1 c8 0.047uf 3. 4 c6,c10,c18,c5 0.1uf, ceramic 4. 2 c19,c13,c7 10uf/16v 5. 2 c15,c16 1nf/3kv 6. 1 c11 100uf/16v 7. 16 c21,c22,c23,c24,c25 56pf, ceramic 8. ,c26,c27,c28,c29,c30 9. ,c31,c32,c33,c34,c35,c36 10. 2 c37,c39 0.47uf ceramic 11. 5 d1,d2,d3,d4,d5 led 12. 1 j12 dc-jack-male 13. 1 j11 db-9/female 14. 1 j9 rj11 15. 2 l2,l3 2961666681 fair rite inc. 16. 8 l4,l5,l6,l7,l8,l9,l10,l11 bk2125hs601 taiyoyuden co. ltd. 17. 1 rv1 1.5ke220a 18. 2 r22,r23 18r,1w 19. 1 r24 10r 20. 2 r2,r3 4.7k 21. 2 r35 470 22. 1 s1 pb switch 23. 1 u1 lm386 national semiconductor 24. 1 u2 co561ad-c connect one ltd. 25. 1 u5 7805 26. 1 u8 tl7705acd texas instruments 27. 1 u6 max237cwg maxim integrated products 28. 1 ls1 hpe-1206, speaker 50 ? table 7-1 bill of materials for co561ad-c reference design
pcb design and layout considerations ichip & ichip lan datasheet 9-1 9 pcb design and layout considerations 9.1 design consideration good engineering practices must be adhered to when designing a printed circuit board (pcb) containing the socketmodem module. suppression of noise is essential to the proper operation and performance of the modem itself and for surrounding equipment. two aspects of noise in an oem board design containing the conexant socketmodem module must be considered: on-board/off-board generated noise that can affect analog signal levels and analog-to-digital conversion (adc)/digital-to-analog conversion (dac), and on-board generated noise that can radiate off-board. both on-board and off-board generated noise that is coupled on-board can affect interfacing signal levels and quality, especially in low level analog signals. of particular concern is noise in frequency ranges affecting modem performance. on-board generated electromagnetic interference (emi) noise that can be radiated or conducted off-board is a separate, but equally important, concern. this noise can affect the operation of surrounding equipment. most local governing agencies have stringent certification requirements that must be met for use in specific environments. proper pc board layout (component placement, signal routing, trace thickness and geometry, etc.), component selection (composition, value, and tolerance), interface connections, and shielding are required for the board design to achieve desired modem performance and to attain emi certification. 9.2 pc board layout guidelines 1. in a 2-layer design, all unused space around and under components should be filled with copper connected to the board ground on both sides of the board, and connected in such a manner as to avoid small islands. isolated islands should be avoided by connecting all grounds on the same side at several points and to the ground plane on the opposite side through the board at several points. in a modem design, connect the socketmodem dgnd and agnd pins to the ground plane. 2. in a 4-layer design, provide an adequate ground plane covering the entire board. in a modem design, socketmodem dgnd and agnd pins are tied together on the socketmodem. do not split analog and digital ground planes. 3. as a general rule, route digital signals on the component side of the pcb and the analog signals on the solder side. the sides may be reversed to match particular oem requirements. route the digital traces perpendicular to the analog traces to minimize signals cross coupling. 4. route the modem signals to provide maximum isolation between noise sources and noise sensitive inputs. when layout requirements necessitate routing these
pcb design and layout considerations ichip & ichip lan datasheet 9-2 signals together, they should be separated by neutral signals. for the ichip lan version, void power/ground plane as well as other digital signals between the cs8900a and the rj45 module. 5. all power and ground traces should be at least 0.05 in. wide. 6. 0.1 uf ceramic capacitors should be placed as close as possible to the power pins. when internal power plane is used, the traces connecting between the power pins of the components and the vias should be kept short and to have bypass capacitor between the via and the pin. 7. in a modem design, tip and ring signal traces are to be no closer than 0.062" from any other traces for u.s. applications. tip and ring signal traces are to be no closer than 2.5mm (0.1?) from any other traces for european applications. 2.5mm spacing must be used if the host board is to support both u.s. and european socket modems. in multi layer design, power and ground planes should be cleared underneath the traces, which belong to the primary (tip and ring) circuit. for an ethernet design, route differential signals (rxd, txd) close together as pairs. try to avoid vias. 8. in a modem design, if the socketmodem is mounted flush with the host pcb, the host pcb should be clear of all traces directly underneath the socketmodem oscillator section. it is strongly suggested that the socketmodem be mounted at least 0.130 inch above the host board. 9.2.1 electromagnetic interference (emi) considerations in a modem design, the following guidelines are offered to specifically help minimize emi generation. some of these guidelines are the same as, or similar to, the general guidelines but are mentioned again to reinforce their importance. in order to minimize the contribution of the socketmodem-based design to emi, the designer must understand the major sources of emi and how to reduce them to acceptable levels. 1. keep traces carrying high frequency signals as short as possible. 2. decouple power from ground with decoupling capacitors as close to the active components? power pins as possible. 3. eliminate ground loops, which are unexpected current return paths to the power source and ground. 4. decouple the telephone line cables at the telephone line jacks. typically, use common mode chokes and shunt capacitors. methods to decouple telephone lines are similar to decoupling power lines, however, telephone line decoupling may be more difficult and deserves additional attention. a commonly used design aid is to place footprints for these components and populate as necessary during performance/emi testing and certification.
pcb design and layout considerations ichip & ichip lan datasheet 9-3 5. decouple the power cord at the power cord interface with decoupling capacitors. methods to decouple power lines are similar to decoupling telephone lines. 6. locate cables and connectors so as to avoid coupling from high frequency circuits. 7. avoid right angle turns on high frequency traces. forty-five degree corners are good, however, radius turns are better. 9.2.2 other considerations in a modem design the pins of all socketmodems are grouped according to function. the daa interface, host interface, and led interface pins are all conveniently arranged, easing the host board layout design. conexant has tested each of the w.class socketmodems for compliance with their respective country?s ptt requirements and has received ptt certificates that cover, without additional expense to the user, all applications that use these socketmodems in their respective countries. the certificates apply only to designs that route tip and ring (pins 1 and 2) directly to the telco jack. only specified emi filtering components are allowed on these two signals.
protocol compliance ichip & ichip lan datasheet 10- 1 10 protocol compliance ichip complies with the following internet standards: rfc 768 user datagram protocol (udp) rfc 791 internet protocol (ip) rfc 792 internet control message protocol rfc 793 transmission control protocol (tcp) rfc 821 simple mail transfer protocol (smtp) rfc 826 ethernet address resolution protocol (ichip lan) rfc 951 bootstrap protocol (ichip lan) rfc 822 standard for the format of arpa internet text messages rfc 1331 point-to-point protocol (ppp) (ichip co561ad-s/p ) rfc 1332 ppp internet protocol control protocol (ipcp) (ichip co561ad-s/p) rfc 1334 ppp authentication protocols (pap) (ichip co561ad-s/p) rfc 1661 point-to-point protocol (ppp) (ichip co561ad-s/p) rfc 1939 post office protocol - version 3 (pop3) rfc 1957 some observations on the implementations of the post office protocol (pop3) rfc 2045 multipurpose internet mail extensions (mime) part one: format of internet message bodies rfc 2046 multipurpose internet mail extensions (mime) part two: media types rfc 2047 mime (multipurpose internet mail extensions) part three: message header extensions for non-ascii text rfc 2048 multipurpose internet mail extensions (mime) part four: registration procedures rfc 2049 multipurpose internet mail extensions (mime) part five: conformance criteria and examples rfc 2068 hypertext transfer protocol http/1.1 rfc 2131 dynamic host configuration protocol (ichip lan) rfc 2132 dhcp options and bootp vendor extensions (ichip lan) table 10-1 internet protocol compliance
list of terms and acronyms ichip & ichip lan datasheet 11-1 11 list of terms and acronyms 10baset 10-mbps baseband ethernet specification using two pairs of twisted-pair cabling (category 3, 4, or 5): one pair for transmitting data and the other for receiving data. arp address resolution protocol . internet protocol used to map an ip address to a mac address. at+i tm connect one's internet extension to the industry-standard hayes at command set. supports simplified internet connectivity commands in the spirit of the at syntax. base64 encoding scheme , which converts arbitrary binary data into a 64-character subset of us ascii. the encoded data is 33% larger than the original data. chap challenge authentication protocol. extends the pap procedure by introducing advanced elements of security. dhcp dynamic host configuration protocol. provides a mechanism for allocating ip addresses dynamically so that addresses can be reused when hosts no longer need them. dns domain name system . defines the structure of internet names and their association with ip addresses. ichip tm connect one?s internet controller for embedded internet connectivity. icmp internet control message protocol . network layer internet protocol that reports errors and provides other information relevant to ip packet processing. ip internet protocol . provides for transmitting blocks of data, called datagrams, from sources to destinations, which are hosts identified by fixed length addresses. also provides for fragmentation and reassemble of long datagrams, if necessary. ipcp internet protocol control protocol . establishes and configures the internet protocol over ppp. also negotiates van jacobson tcp/ip header compression with ppp. isp internet service provider . commercial company that provides internet access to end (mostly pc) users through a dial-up connection. lan local area network . high-speed, low-error data network covering a relatively small geographic area (up to a few thousand meters). lcp link control protocol . negotiates data link characteristics and tests the integrity of the link. mac media access control. lower of the two sublayers of the data link layer defined by the ieee. the mac sublayer handles access to shared media, such as whether token passing or contention will be used. mac address standardized data link layer address that is required for every port or device that connects to a lan. other devices in the network use these addresses to locate specific ports in the network and to create and update routing tables and data structures. mac addresses are 6 bytes long and are controlled by the ieee. it is represented as a 12-digit hexadecimal integer, where the first (left- most) six digits are the connect one company identification ?000394?.
list of terms and acronyms ichip & ichip lan datasheet 11-2 mime multipurpose internet mail extensions . extends the format of mail message bodies to allow multi-part textual and non-textual data to be represented and exchanged between internet mail servers. pap password authentication protocol . used optionally by the ppp protocol to identify the user to the isp. ping packet internet groper . icmp echo message and its reply. often used in ip networks to test the reachability of a network device. pop3 post office protocol version 3 . allows a workstation/pc to dynamically retrieve mail from a mailbox kept on a remote server. ppp point-to-point protocol . communications protocol used to send data across serial communication links, such as modems. rfc request for comments . collections of standards that define the way remote computers communicate over the internet. smtp simple mail transfer protocol . provides for transferring mail reliably and efficiently over the internet. tcp transmission control protocol . provides reliable stream-oriented connections over the internet. works in conjunction with its underlying ip protocol. "leave on server" an option designating whether retrieved email messages are to be left intact on the server for subsequent downloads or are to be deleted from the server after a successful download. table 11-1 terms and acronyms
index ichip & ichip lan datasheet 12-1 12 index 2 ichip lan with an ethernet controller interface ........................4-3 3.3 volt version .................................6-1 5 volt version ....................................6-2 absolute maximum ratings...............6-1 bill of materials for co561ad-c reference design ...........................8-8 bill of materials for co561ad-l reference design ...........................7-5 bill of materials for co561ad-s reference design ...........................7-3 carrier board co561ad-c pinout ....8-2 command mode.................................3-2 data byte encoding ...........................5-3 data rates ..........................................3-1 dc operating characteristics 3.3v version ...........................................6-2 dc operating characteristics 5v version ...........................................6-2 dc operation characteristics.............6-2 designs considerations ......................9-1 direct modem firmware update mode ........................................................3-2 electrical/mechanical specifications .6-1 electromagnetic interference (emi) considerations................................9-2 environmental specifications ............6-1 environmental specifications 3.3v version ...........................................6-1 environmental specifications 5v version ...........................................6-1 ethernet controller environment .......7-1 ethernet controller interface..............4-3 functional description .......................3-1 general ...............................................3-1 general hardware architecture .........7-1 hardware and software flow control3-3 hardware interface .............................4-1 host data format ...............................4-1 host interface .....................................4-1 host interface signals ................ 5-7, 8-4 host serial connection.......................3-2 ichip co561ad-s with a serial modem interface..........................................4-2 ichip co561ad-s/p pin assignments 5- 1 ichip designs .....................................7-1 ichip functional block diagram .......1-2 ichip lan pin assignments..............5-2 ichip lan signals .............................5-9 ichip pin functional descriptions .....5-3 ichip version specific signals ..........5-8 index.................................................12-1 interface timing and waveforms ......6-3 internet mode .....................................3-2 internet protocol compliance...........10-1 introduction ........................................1-1 local bus connection to ethernet controller .......................................3-3 local bus read cycle ........................6-3 local bus signals...............................5-3 local bus write cycle .......................6-4 mechanical dimensions .....................6-5 modem interface ................................4-2 operation............................................3-2 ordering information .........................2-1 other considerations in a modem design.............................................9-3 overview ............................................3-1 parallel modem environment ............7-1 pc board layout guidelines..............9-1 pcb design and layout considerations ........................................................9-1 pin assignments.................................8-2 pin descriptions .................................5-1 pin functional descriptions ...............8-3 plcc68 package for ichip co561ad-s serial version.................................5-1 plcc68 package for ichip lan co561ad-l serial version...........5-2 pld equations ...................................7-1 protocol compliance ........................10-1
index ichip & ichip lan datasheet 12-2 reference design for co561ad-c based modem.................................8-7 reference design for embedded imodem using co561ad-s..........7-2 reference design for embedded lan using co561ad-l ........................7-4 selecting a crystal..............................5-5 serial connection to dial-up modem 3-2 serial modem environment ...............7-1 serial version.....................................5-1 socket ichip package dimensions.....8-6 socket ichip tm carrier board ............8-2 socket modem interface signals .......8-3 technical specifications ....................3-1 terms and acronyms .......................11-2 transparent mode ..............................3-2 volt version ............................... 6-1, 6-2

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