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  users manual m m m m pd789046 m m m m pd78f9046 m m m m pd789046 subseries 8-bit single-chip microcontrollers printed in japan document no. u13600ej2v0umj1 (2nd edition) date published october 2000 n cp(k) ? 1998, 1999
user's manual u13600ej2v0um00 2 [memo]
user's manual u13600ej2v0um00 3 summary of contents chapter 1 general ............................................................................................................. .......................23 chapter 2 pin functions....................................................................................................... ...................29 chapter 3 cpu architecture.................................................................................................... .............37 chapter 4 port functions...................................................................................................... ................59 chapter 5 clock generation circuit ............................................................................................ ....75 chapter 6 16-bit timer ........................................................................................................ ......................85 chapter 7 8-bit timer/event counter........................................................................................... ....101 chapter 8 watch timer ......................................................................................................... .................113 chapter 9 watchdog timer ...................................................................................................... ............119 chapter 10 serial interface 20................................................................................................ ............125 chapter 11 interrupt functions ................................................................................................ .........159 chapter 12 standby function................................................................................................... ............175 chapter 13 reset function ..................................................................................................... ...............183 chapter 14 m m m m pd78f9046 ...................................................................................................................... ........187 chapter 15 instruction set .................................................................................................... ...............193 appendix a development tools .................................................................................................. .........203 appendix b embedded software.................................................................................................. ........211 appendix c register index ..................................................................................................... ................213 appendix d revision history ................................................................................................... ...............217
user's manual u13600ej2v0um00 4 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom is a trademark of nec corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun-microsystems, inc. osf/motif is a trademark of open software foundation, inc. news and news-os are trademarks of sony corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron.
user's manual u13600ej2v0um00 5 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd78f9046 the customer must judge the need for license: m pd789046 m8e 00. 4 the information in this document is current as of october, 1999. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).
user's manual u13600ej2v0um00 6 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
user's manual u13600ej2v0um00 7 major revision in this edition page description throughout completion of development of m pd789046 and m pd78f9046 p.34 change of recommended connection of unused pins in table 2-1 p.86 correction of figure 6-1 p.92 addition of cautions on rewriting cr90 to section 6.4.1 p.98 addition of cautions on 16-bit timer to section 6.5 p.102 addition of cautions on rewriting cr80 to section 7.2 (1) p.105 addition of description of operation to section 7.4.1 p.107 addition of description of operation to section 7.4.2 p.108 addition of description of operation to section 7.4.3 p.110 addition of description of operation to section 7.4.4 p.188 correction of pins used in pseudo 3-wire mode in table 14-2 p.190 change of connection of p01 and p02 pins in figure 14-4 p.191 addition of setting example to section 14.1.4 correction of product name of flash memory writing adapter in section a.2 p.206 addition of np-44gb-tq as emulation probe to section a.3.1 p.210 addition of package drawing to section a.5 p.211 addition of part number of mx78k0s to appendix b the mark shows the major revised points.
user's manual u13600ej2v0um00 8 [memo]
user's manual u13600ej2v0um00 9 introduction readers this manual is intended for user engineers who understand the functions of the m pd789046 subseries to design and develop its application systems and programs. target products: m pd789046 subseries: m pd789046 and m pd78f9046 purpose this manual is intended for users to understand the functions described in the organization below. organization two manuals are available for the m pd789046 subseries: this manual and instruction manual (common to the 78k/0s series). m pd789046 subseries user's manual 78k/0s series user's manual ? instruction pin functions internal block functions interrupt other internal peripheral functions cpu function instruction set instruction description how to read this manual it is assumed that the readers of this manual have general knowledge on electric engineering, logic circuits, and microcontrollers. to understand the overall functions of the m pd789046 subseries ? read this manual in the order of the table of contents . how to read register formats ? the name of a bit whose number is enclosed with <> is reserved for the assembler and is defined for the c compiler by the header file sfrbit.h . to learn the detailed functions of a register whose register name is known ? see appendix c . to learn the details of the instruction functions of the 78k/0s series ? refer to 78k/0s series user's manual ? ? ? ? instruction (u11047e) separately available. legend data significance : left: higher digit, right: lower digit active low : (top bar over pin or signal name) note : footnote caution : important information remark : supplement numerical representation : binary ... or b decimal ... hexadecimal ... h
user's manual u13600ej2v0um00 10 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document no. document name english japanese m pd789046 data sheet u13380e u13380j m pd78f9046 preliminary product information u13546e u13546j m pd789046 subseries user's manual this manual u13600j 78k/0s series user's manual ? instruction u11047e u11047j documents related to development tools (user's manual) document no. document name english japanese operation u11622e u11622j assembly language u11599e u11599j ra78k0s assembler package structured assembly language u11623e u11623j operation u11816e u11816j cc78k0s c compiler language u11817e u11817j sm78k0s system simulator windows tm based reference u11489e u11489j sm78k series system simulator external parts user open interface specifications u10092e u10092j id78k0s-ns integrated debugger windows based reference u12901e u12901j documents for embedded software (user's manual) document no. document name english japanese 78k/0s series os mx78k0s basics u12938e u12938j caution the related documents listed above are subject to change without notice. be sure to use the latest documents for designing, etc.
user's manual u13600ej2v0um00 11 other related documents document no. document name english japanese semiconductors selection guide products & package x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor device c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j semiconductor device quality control/reliability handbook - c12769j guide for products related to micro-computer: other companies - u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest documents for designing, etc.
user's manual u13600ej2v0um00 12 [memo]
user's manual u13600ej2v0um00 13 table of contents chapter 1 general............................................................................................................. ................23 1.1 features .................................................................................................................. ....................23 1.2 applications.............................................................................................................. ..................23 1.3 ordering information ...................................................................................................... ...........23 1.4 pin configuration (top view).............................................................................................. ......24 1.5 78k/0s series development ................................................................................................. .....25 1.6 block diagram ............................................................................................................. ...............27 1.7 functions ................................................................................................................. ...................28 chapter 2 pin functions ....................................................................................................... ...........29 2.1 pin function list ......................................................................................................... ...............29 2.2 description of pin functions .............................................................................................. ......31 2.2.1 p00 to p07 (port 0)..................................................................................................... .................31 2.2.2 p10 to p17 (port 1)..................................................................................................... .................31 2.2.3 p20 to p27 (port 2)..................................................................................................... .................31 2.2.4 p30, p31 (port 3)....................................................................................................... ..................32 2.2.5 p40 to p47 (port 4)..................................................................................................... .................32 2.2.6 reset................................................................................................................... ......................33 2.2.7 x1, x2.................................................................................................................. ........................33 2.2.8 xt1, xt2 ................................................................................................................ .....................33 2.2.9 v dd0 , v dd1 ............................................................................................................................... .....33 2.2.10 v ss0 , v ss1 ............................................................................................................................... ......33 2.2.11 v pp ( m pd78f9046 only)...............................................................................................................3 3 2.2.12 ic0 (masked rom version only) .......................................................................................... .......33 2.3 pin input/output circuits and handling of unused pins .......................................................34 chapter 3 cpu architecture .................................................................................................... .....37 3.1 memory space .............................................................................................................. ..............37 3.1.1 internal program memory space........................................................................................... .......39 3.1.2 internal data memory (internal high-speed ram) space .............................................................39 3.1.3 special function register (sfr) area .................................................................................... .......39 3.1.4 data memory addressing .................................................................................................. ..........40 3.2 processor registers ....................................................................................................... ...........42 3.2.1 control registers ....................................................................................................... ...................42 3.2.2 general-purpose registers............................................................................................... ............45 3.2.3 special function register (sfr)......................................................................................... ...........46 3.3 instruction address addressing ............................................................................................ ..49 3.3.1 relative addressing ..................................................................................................... ................49 3.3.2 immediate addressing .................................................................................................... .............50
user's manual u13600ej2v0um00 14 3.3.3 table indirect addressing ............................................................................................... .............51 3.3.4 register addressing ..................................................................................................... ...............51 3.4 operand address addressing ................................................................................................ .. 52 3.4.1 direct addressing ....................................................................................................... .................52 3.4.2 short direct addressing ................................................................................................. ..............53 3.4.3 special function register (sfr) addressing.............................................................................. ...54 3.4.4 register addressing ..................................................................................................... ...............55 3.4.5 register indirect addressing............................................................................................ ............56 3.4.6 based addressing........................................................................................................ ................57 3.4.7 stack addressing........................................................................................................ .................57 chapter 4 port functions ...................................................................................................... ........ 59 4.1 port functions............................................................................................................ ................ 59 4.2 port configuration ........................................................................................................ ............. 61 4.2.1 port 0.................................................................................................................. .........................61 4.2.2 port 1.................................................................................................................. .........................62 4.2.3 port 2.................................................................................................................. .........................63 4.2.4 port 3.................................................................................................................. .........................68 4.2.5 port 4.................................................................................................................. .........................69 4.3 port function control registers ........................................................................................... ... 70 4.4 operation of port functions ............................................................................................... ...... 73 4.4.1 writing to i/o port ..................................................................................................... ...................73 4.4.2 reading from i/o port ................................................................................................... ...............73 4.4.3 arithmetic operation of i/o port........................................................................................ ............73 chapter 5 clock generation circuit......................................................................................... 75 5.1 clock generation circuit functions........................................................................................ .75 5.2 clock generation circuit configuration .................................................................................. 75 5.3 registers controlling clock generation circuit ..................................................................... 77 5.4 system clock oscillators .................................................................................................. ........ 79 5.4.1 main system clock oscillator............................................................................................ ............79 5.4.2 subsystem clock oscillator .............................................................................................. ............79 5.4.3 scaler .................................................................................................................. ........................81 5.4.4 when no subsystem clocks are used....................................................................................... ...81 5.5 clock generation circuit operation ........................................................................................ .82 5.6 changing setting of system clock and cpu clock ............................................................... 83 5.6.1 time required for switching between system clock and cpu clock ............................................83 5.6.2 switching between system clock and cpu clock ........................................................................84 chapter 6 16-bit timer ........................................................................................................ ............... 85 6.1 16-bit timer functions .................................................................................................... .......... 85 6.2 16-bit timer configuration................................................................................................ ........ 85 6.3 registers controlling 16-bit timer........................................................................................ ... 88 6.4 16-bit timer operation .................................................................................................... .......... 92
user's manual u13600ej2v0um00 15 6.4.1 operation as timer interrupt............................................................................................ .............92 6.4.2 operation as timer output ............................................................................................... .............94 6.4.3 capture operation....................................................................................................... .................95 6.4.4 16-bit timer counter 90 readout ......................................................................................... ..........96 6.4.5 buzzer output operation ................................................................................................. .............97 6.5 notes on 16-bit timer ..................................................................................................... ...........98 chapter 7 8-bit timer/event counter .......................................................................................101 7.1 functions of 8-bit timer/event counter ................................................................................101 7.2 8-bit timer/event counter configuration ..............................................................................102 7.3 8-bit timer/event counter control registers........................................................................103 7.4 operation of 8-bit timer/event counter ................................................................................105 7.4.1 operation as interval timer ............................................................................................. ...........105 7.4.2 operation as external event counter ..................................................................................... ....107 7.4.3 operation as square wave output......................................................................................... .....108 7.4.4 pwm output operation.................................................................................................... ...........110 7.5 notes on using 8-bit timer/event counter ...........................................................................111 chapter 8 watch timer......................................................................................................... ..........113 8.1 watch timer functions ..................................................................................................... ......113 8.2 watch timer configuration ................................................................................................. ....114 8.3 watch timer control register .............................................................................................. ..115 8.4 watch timer operation..................................................................................................... .......116 8.4.1 operation as watch timer................................................................................................ ...........116 8.4.2 operation as interval timer ............................................................................................. ...........116 chapter 9 watchdog timer...................................................................................................... .....119 9.1 watchdog timer functions.................................................................................................. ...119 9.2 watchdog timer configuration .............................................................................................. 120 9.3 watchdog timer control registers........................................................................................12 1 9.4 watchdog timer operation .................................................................................................. ...123 9.4.1 operation as watchdog timer............................................................................................. ........123 9.4.2 operation as interval timer ............................................................................................. ...........124 chapter 10 serial interface 20................................................................................................ ...125 10.1 serial interface 20 functions ............................................................................................ ......125 10.2 serial interface 20 configuration ........................................................................................ ....125 10.3 serial interface 20 control registers .................................................................................... .129 10.4 serial interface 20 operation............................................................................................ .......136 10.4.1 operation stop mode .................................................................................................... .............136 10.4.2 asynchronous serial interface (uart) mode ............................................................................13 7 10.4.3 3-wire serial i/o mode ................................................................................................. ..............149 chapter 11 interrupt functions................................................................................................ 159
user's manual u13600ej2v0um00 16 11.1 interrupt function types................................................................................................. ........ 159 11.2 interrupt sources and configuration ..................................................................................... 1 59 11.3 interrupt function control registers..................................................................................... 162 11.4 interrupt processing operation ........................................................................................... ... 168 11.4.1 non-maskable interrupt request acceptance operation.............................................................168 11.4.2 maskable interrupt request acceptance operation ....................................................................170 11.4.3 multiplexed interrupt processing....................................................................................... .........172 11.4.4 interrupt request reserve .............................................................................................. .............174 chapter 12 standby function ................................................................................................... .. 175 12.1 standby function and configuration..................................................................................... 17 5 12.1.1 standby function....................................................................................................... .................175 12.1.2 standby function control register...................................................................................... .........176 12.2 operation of standby function ............................................................................................ .. 177 12.2.1 halt mode .............................................................................................................. .................177 12.2.2 stop mode.............................................................................................................. .................180 chapter 13 reset function..................................................................................................... ...... 183 chapter 14 m m m m pd78f9046 ..................................................................................................................... 1 87 14.1 flash memory programming................................................................................................. .. 188 14.1.1 selecting communication mode........................................................................................... ......188 14.1.2 function of flash memory programming ................................................................................... .189 14.1.3 flashpro iii connection ................................................................................................ ..............189 14.1.4 setting example with flashpro iii (pg-fp3)............................................................................. .191 chapter 15 instruction set.................................................................................................... ...... 193 15.1 operation ................................................................................................................ .................. 193 15.1.1 operand identifiers and description methods............................................................................ 193 15.1.2 description of "operation" column...................................................................................... .......194 15.1.3 description of "flag" column ........................................................................................... ..........194 15.2 operation list........................................................................................................... ................ 195 15.3 instructions listed by addressing type ............................................................................... 200 appendix a development tools.................................................................................................. 203 a.1 language processing software.............................................................................................. 205 a.2 flash memory writing tools ................................................................................................ ... 206 a.3 debugging tools........................................................................................................... ........... 206 a.3.1 hardware ................................................................................................................ ...................206 a.3.2 software ................................................................................................................ ....................207 a.4 conversion socket (ev-9200g-44) drawing and recommended footprint....................... 208 a.5 conversion adapter (tgb-044sap) drawing........................................................................ 210
user's manual u13600ej2v0um00 17 appendix b embedded software.................................................................................................2 11 appendix c register index ..................................................................................................... .......213 c.1 register name index (alphabetic order) ...............................................................................213 c.2 register symbol index (alphabetic order)............................................................................215 appendix d revision history................................................................................................... ......217
user's manual u13600ej2v0um00 18 list of figures (1/3) figure no. title page 2-1 pin input/output circuits ................................................................................................. ...........................35 3-1 memory map ( m pd789046)...................................................................................................................... ..37 3-2 memory map ( m pd78f9046)..................................................................................................................... .38 3-3 data memory addressing modes ( m pd789046) ........................................................................................40 3-4 data memory addressing modes ( m pd78f9046) ......................................................................................41 3-5 program counter configuration ............................................................................................. ....................42 3-6 program status word configuration ......................................................................................... .................42 3-7 stack pointer configuration ............................................................................................... ........................44 3-8 data to be saved to stack memory .......................................................................................... .................44 3-9 data to be restored from stack memory..................................................................................... ..............44 3-10 general-purpose register configuration ................................................................................... ................45 4-1 port types................................................................................................................ ..................................59 4-2 block diagram of p00 to p07 ............................................................................................... ......................61 4-3 block diagram of p10 to p17 ............................................................................................... ......................62 4-4 block diagram of p20 ...................................................................................................... ..........................63 4-5 block diagram of p21 ...................................................................................................... ..........................64 4-6 block diagram of p22 and p24 to p26....................................................................................... ................65 4-7 block diagram of p23 ...................................................................................................... ..........................66 4-8 block diagram of p27 ...................................................................................................... ..........................67 4-9 block diagram of p30 and p31 .............................................................................................. ....................68 4-10 block diagram of p40 to p47 .............................................................................................. .......................69 4-11 format of port mode register............................................................................................. .......................71 4-12 format of pull-up resistor option register 0............................................................................. ...............71 4-13 format of pull-up resistor option register b2 ............................................................................ .............72 5-1 block diagram of clock generation circuit................................................................................. ...............76 5-2 format of processor clock control register................................................................................ ..............77 5-3 format of suboscillation mode register .................................................................................... ................78 5-4 format of subclock control register ....................................................................................... ..................78 5-5 external circuit of main system clock oscillator .......................................................................... .............79 5-6 external circuit of subsystem clock oscillator ............................................................................ ..............79 5-7 unacceptable resonator connections ........................................................................................ ..............80 5-8 switching between system clock and cpu clock.............................................................................. .......84 6-1 block diagram of 16-bit timer ............................................................................................. ......................86 6-2 format of 16-bit timer mode control register 90 ........................................................................... ..........89 6-3 format of buzzer output control register 90............................................................................... .............90 6-4 format of port mode register 3............................................................................................ .....................91 6-5 settings of 16-bit timer mode control register 90 for timer interrupt operation .....................................92 6-6 timing of timer interrupt operation ....................................................................................... ....................93
user's manual u13600ej2v0um00 19 list of figures (2/3) figure no. title page 6-7 settings of 16-bit timer mode control register 90 for timer output operation....................................... 94 6-8 timer output timing ....................................................................................................... .......................... 94 6-9 settings of 16-bit timer mode control register 90 for capture operation ............................................... 95 6-10 capture operation timing (both edges of cpt90 pin are specified) ...................................................... 95 6-11 16-bit timer counter 90 readout timing................................................................................... ............... 96 6-12 settings of buzzer output control register 90 for buzzer output operation ........................................... 97 7-1 block diagram of 8-bit timer/event counter ................................................................................. ......... 102 7-2 format of 8-bit timer mode control register 80 ............................................................................ ........ 103 7-3 format of port mode register 2 ............................................................................................ .................. 104 7-4 interval timer operation timing........................................................................................... ................... 106 7-5 external event counter operation timing (with rising edge specified)................................................. 107 7-6 square wave output timing................................................................................................. .................. 109 7-7 pwm output timing ......................................................................................................... ....................... 110 7-8 start timing of 8-bit timer counter 80.................................................................................... ................ 111 7-9 external event counter operation timing ................................................................................... ........... 111 8-1 block diagram of watch timer .............................................................................................. ................. 113 8-2 format of watch timer mode control register............................................................................... ........ 115 8-3 watch timer/interval timer operation timing ............................................................................... ......... 117 9-1 block diagram of watchdog timer ........................................................................................... .............. 120 9-2 format of timer clock selection register 2 ................................................................................ ........... 121 9-3 format of watchdog timer mode register .................................................................................... ......... 122 10-1 block diagram of serial interface 20....................................................................................... ................ 126 10-2 block diagram of baud rate generator 20.................................................................................... ......... 127 10-3 format of serial operation mode register 20.............................................................................. ........... 129 10-4 format of asynchronous serial interface mode register 20 ................................................................. . 130 10-5 format of asynchronous serial interface status register 20 ............................................................... .. 132 10-6 format of baud rate generator control register 20........................................................................ ...... 133 10-7 asynchronous serial interface transmit/receive data format .............................................................. 1 43 10-8 asynchronous serial interface transmission completion interrupt timing ............................................ 145 10-9 asynchronous serial interface reception completion interrupt timing.................................................. 146 10-10 receive error timing .................................................................................................... .......................... 147 10-11 3-wire serial i/o mode timing ........................................................................................... ..................... 152 11-1 basic configuration of interrupt function................................................................................ ................ 161 11-2 format of interrupt request flag register................................................................................ .............. 163 11-3 format of interrupt mask flag register ................................................................................... ............... 164 11-4 format of external interrupt mode register 0 ............................................................................. ............ 165 11-5 program status word configuration ........................................................................................ ............... 166
user's manual u13600ej2v0um00 20 list of figures (3/3) figure no. title page 11-6 format of key return mode register 00 .................................................................................... .............167 11-7 block diagram of falling edge detection circuit .......................................................................... ...........167 11-8 flowchart from non-maskable interrupt request generation to acceptance..........................................169 11-9 timing of non-maskable interrupt request acceptance...................................................................... ....169 11-10 accepting non-maskable interrupt request ................................................................................ ............169 11-11 interrupt request acceptance processing algorithm....................................................................... ........171 11-12 interrupt request acceptance timing (example of mov a,r)................................................................ ..172 11-13 interrupt request acceptance timing (when interrupt request flag is set at the last clock during instruction execution).............................172 11-14 example of multiple interrupt ........................................................................................... ........................173 12-1 format of oscillation settling time selection register ................................................................... .........176 12-2 releasing halt mode by interrupt......................................................................................... .................178 12-3 releasing halt mode by reset input ....................................................................................... ...........179 12-4 releasing stop mode by interrupt ......................................................................................... ................181 12-5 releasing stop mode by reset input....................................................................................... ...........181 13-1 block diagram of reset function.......................................................................................... ...................183 13-2 reset timing by reset input .............................................................................................. ...................184 13-3 reset timing by overflow in watchdog timer............................................................................... ..........184 13-4 reset timing by reset input in stop mode................................................................................. ........184 14-1 format of communication mode selection ................................................................................... ...........188 14-2 flashpro iii connection example in 3-wire serial i/o mode................................................................ ....189 14-3 flashpro iii connection example in uart mode ............................................................................. .......190 14-4 flashpro iii connection example in pseudo 3-wire mode (when p0 is used) .......................................190 a-1 development tools ......................................................................................................... .........................204 a-2 ev-9200g-44 package drawing (reference) (unit: mm) ....................................................................... .208 a-3 ev-9200g-44 footprints (reference) (unit: mm) ............................................................................ ........209 a-4 tgb-044sap package drawing (reference) (unit: mm) ........................................................................ 210
user's manual u13600ej2v0um00 21 list of tables (1/2) table no. title page 2-1 type of input/output circuit for each pin and handling of unused pins .................................................. 34 3-1 internal rom capacity..................................................................................................... ......................... 39 3-2 vector table.............................................................................................................. ................................ 39 3-3 special function registers ................................................................................................ ....................... 47 4-1 port functions ............................................................................................................ ............................... 60 4-2 configuration of port ..................................................................................................... ............................ 61 4-3 port mode register and output latch settings for using alternate functions ......................................... 70 5-1 configuration of clock generation circuit................................................................................. ................ 75 5-2 maximum time required for switching cpu clock ............................................................................. ..... 83 6-1 configuration of 16-bit timer ............................................................................................. ....................... 85 6-2 interval time of 16-bit timer............................................................................................. ........................ 92 6-3 settings of capture edge .................................................................................................. ........................ 95 6-4 buzzer frequency of 16-bit timer .......................................................................................... .................. 97 6-5 operating status of 16-bit timer under each condition ..................................................................... ...... 98 7-1 interval time of 8-bit timer/event counter ................................................................................ ............. 101 7-2 square wave output range of 8-bit timer/event counter..................................................................... 101 7-3 8-bit timer/event counter configuration ................................................................................... ............. 102 7-4 interval time of 8-bit timer/event counter ................................................................................ ............. 105 7-5 square wave output range of 8-bit timer/event counter..................................................................... 108 8-1 interval generated using interval timer ................................................................................... .............. 114 8-2 watch timer configuration ................................................................................................. .................... 114 8-3 interval generated using interval timer ................................................................................... .............. 116 9-1 inadvertent loop detection time of watchdog timer......................................................................... .... 119 9-2 interval time ............................................................................................................. .............................. 119 9-3 configuration of watchdog timer ........................................................................................... ................ 120 9-4 inadvertent loop detection time of watchdog timer......................................................................... .... 123 9-5 interval generated using interval timer ................................................................................... .............. 124 10-1 configuration of serial interface 20..................................................................................... .................... 125 10-2 serial interface 20 operating mode settings .............................................................................. ............ 131 10-3 example of relationships between system clock and baud rate ......................................................... 134 10-4 relationships between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) .................................................................................................... ........... 135 10-5 example of relationships between system clock and baud rate ......................................................... 142
user's manual u13600ej2v0um00 22 list of tables (2/2) table no. title page 10-6 relationships between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) .................................................................................................... ............142 10-7 receive error causes ..................................................................................................... .........................147 11-1 interrupt sources ........................................................................................................ .............................160 11-2 interrupt request signals and corresponding flags ........................................................................ .......162 11-3 time from generation of maskable interrupt request to processing ......................................................170 12-1 operation statuses in halt mode .......................................................................................... ................177 12-2 operation after release of halt mode..................................................................................... ..............179 12-3 operation statuses in stop mode.......................................................................................... ................180 12-4 operation after release of stop mode ..................................................................................... .............181 13-1 state of the hardware after a reset...................................................................................... ...................185 14-1 differences between flash memory and masked rom versions............................................................187 14-2 communication mode ....................................................................................................... .......................188 14-3 major functions of flash memory programming .............................................................................. .......189 14-4 setting example with pg-fp3.............................................................................................. ....................191 15-1 operand identifiers and description methods.............................................................................. ............193
user's manual u13600ej2v0um00 23 chapter 1 general 1.1 features ? rom and ram capacity item product name program memory data memory (internal high-speed ram) m pd789046 masked rom 16 kbytes m pd78f9046 flash memory 16 kbytes 512 bytes ? minimum instruction execution time changeable from high-speed (0.4 m s: main system clock 5.0-mhz operation) to ultra-low speed (122 m s: subsystem clock 32.768-khz operation) ? i/o port: 34 lines ? serial interface: 1 channel 3-wire serial i/o mode/uart mode selectable ? timer: 4 channels ? 16-bit timer counter : 1 channel ? 8-bit timer/event counter : 1 channel ? watch timer : 1 channel ? watchdog timer : 1 channel ? vectored interrupt source: 12 ? supply voltage: v dd = 1.8 to 5.5 v ? operating ambient temperature: t a = -40 c to +85 c 1.2 applications cordless telephones, etc. 1.3 ordering information part number package internal rom m pd789046gb- -8es 44-pin plastic lqfp (10 10 mm) mask rom m pd78f9046gb-8es 44-pin plastic lqfp (10 10 mm) flash memory remark indicates rom code suffix.
chapter 1 general user's manual u13600ej2v0um00 24 1.4 pin configuration (top view) ? 44-pin plastic lqfp (10 10 mm) m pd789046gb- -8es m pd78f9046gb-8es 1 2 3 4 5 6 7 8 9 10 11 p12 p11 p10 p47/kr07 p46/kr06 p45/kr05 p44/kr04 p43/kr03 p42/kr02 p41/kr01 p40/kr00 p13 p14 p15 p16 p17 v ss1 v dd1 p00 p01 p02 p03 33 32 31 30 29 28 27 26 25 24 23 p04 p05 p06 p07 p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/ss20 p24/intp0 p25/intp1 p26/intp2/cpt90 p31/bzo90 ic0 (v pp ) x2 x1 v ss0 v dd0 xt2 xt1 reset p30/to90 p27/ti80/to80 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 caution connect the ic0 (internally connected) pin directly to the v ss0 or v ss1 pin. remark pin connections in parentheses are intended for the m pd78f9046. asck20 : asynchronous serial input rxd20 : receive data bzo90 : buzzer output sck20 : serial clock cpt90 : capture trigger input si20 : serial input ic0 : internally connected so20 : serial output intp0 to intp2 : interrupt from peripherals ss20 : chip select input kr00 to kr07 : key return ti80 : timer input p00 to p07 : port 0 to80, to90 : timer output p10 to p17 : port 1 txd20 : transmit data p20 to p27 : port 2 v dd0 , v dd1 : power supply p30, p31 : port 3 v pp : programming power supply p40 to p47 : port 4 v ss0 , v ss1 : ground reset : reset x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock)
chapter 1 general user's manual u13600ej2v0um00 25 1.5 78k/0s series development the 78k/0s series products are shown below. subseries names are indicated in frames. under development in production pd789014 42/44-pin device developed by enhancing the timers of the pd789014 and expanding rom and ram for small-scale, general- purpose applicationns for small-scale, general-purpose applications and a/d function for inverter control for lcd driving for assp for ic card pd789146 pd789156 44-pin rc oscillator version ot the pd789197ay with built-in eeprom tm and smb in the pd789177 78k/0s series 44/48-pin 44/48-pin 28-pin 44-pin device developed by enhancing the a/d function of the pd789167 device developed by enhancing the timers of the pd789104a device developed by enhancing the a/d function of the pd789124a rc oscillator version of the pd789104a device developed by enhancing the a/d function of the pd789104a device developed by adding the a/d function and multiplier to the pd789026 with built-in uart bus and capable of low-voltage (1.8 v) operation pd789026 44-pin pd789046 device developed by adding the subsystem clock to the pd789026 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789 217ay pd789 197ay pd789177 pd789167 30-pin 30-pin pd789104a pd789114a with built-in eeprom in the pd789104a device developed by enhancing the a/d function of the pd789146 device developed by enhancing the a/d funciton of the pd789427 with built-in uart bus and dot lcd 80-pin 80-pin 88-pin device developed by enhancing the a/d function of the pd789447 44-pin pd789842 with built-in inverter control circuit and uart bus with built-in eeprom and security circuit 5-pin pd789810 device for a keyless entry, with built-in poc and key return circuit 20-pin pd789860 pd789840 device for a keypad, with a built-in poc 44-pin device for a pc keyboard, with a built-in usb function 44-pin pd789800 20-pin pd789861 rc oscillator version of the pd789860 device developed by enhancing the i/o of the pd789457 rc oscillator version of the pd789427 pd789447 pd789457 pd789437 device developed by enhancing the a/d function of the pd789407a pd789417a pd789830 pd789407a pd789427 pd789306 pd789316 device developed by adding the a/d function of the pd789306 rc oscillator version of the pd789306 basic subseries for lcd driving 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m
chapter 1 general user's manual u13600ej2v0um00 26 the following table lists the major differences in functions between the subseries. timer function subseries rom size 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o minimum v dd value remarks m pd789046 16 k 1 ch m pd789026 4 k to 16 k 1 ch 1 ch 34 pins small-scale, general- purpose applications m pd789014 2 k to 4 k 2 ch - - 1 ch -- 1 ch (uart: 1 ch) 22 pins 1.8 v - m pd789217ay rc-oscillator version, on-chip eeprom m pd789197ay 2 ch uart : 1 ch smb : 1 ch on-chip eeprom m pd789177 - 8 ch m pd789167 16 k to 24 k 3 ch 1 ch 8 ch - 31 pins - m pd789156 - 4 ch m pd789146 8 k to 16 k 4 ch - on-chip eeprom m pd789134a - 4 ch m pd789124a 4 ch - rc-oscillator version m pd789114a - 4 ch small-scale, general- purpose applications and a/d function m pd789104a 2 k to 8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 pins 1.8 v - inverter control m pd789842 8 k to 16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 pins 4.0 v - m pd789830 24 k 1 ch - 30 pins 2.7 v m pd789417a - 7 ch 43 pins m pd789407a 12 k to 24 k 3 ch 7 ch - 1 ch (uart: 1 ch) - m pd789457 - 4 ch m pd789447 4 ch - rc-oscillator version m pd789437 - 4 ch m pd789427 16 k to 24 k 4 ch 25 pins - m pd789316 rc-oscillator version lcd driving m pd789306 8 k to 16 k 2 ch 1 ch 1 ch 1 ch - - 2 ch (uart: 1 ch) 23 pins 1.8 v - m pd789800 - 2 ch (usb: 1 ch) 31 pins 4.0 v m pd789840 8 k 1 ch 4 ch 1 ch 29 pins 2.8 v - m pd789861 rc-oscillator version assp m pd789860 4 k 2 ch - - 1 ch - - - 14 pins 1.8 v - ic card m pd789810 6 k -- - 1 ch -- - 1 pin 2.7 v on-chip eeprom
chapter 1 general user's manual u13600ej2v0um00 27 1.6 block diagram 78k/0s cpu core rom ram v dd0 v ss0 v dd1 v ss1 (v pp ) ic0 ti80/to80/p27 8-bit timer80 p00 to p07 port 0 p10 to p17 port 1 p20 to p27 port 2 p30, p31 port 3 p40 to p47 port 4 system control cpt90/intp2/p26 to90/p30 bzo90/p31 sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 ss20/p23 16-bit timer90 watch timer watchdog timer reset x1 x2 xt1 xt2 sio20 interrupt control intp0/p24 intp1/p25 intp2/cpt90/p26 kr00/p40 to kr07/p47 remark pin connections in parentheses are intended for the m pd78f9046.
chapter 1 general user's manual u13600ej2v0um00 28 1.7 functions product item m pd789046 m pd78f9046 rom structure masked rom flash memory rom capacity 16 kbytes internal memory high-speed ram 512 bytes minimum instruction execution time ? 0.4/1.6 m s (operation with main system clock r unning at 5.0 mhz) ? 122 m s (operation with sub system clock r unning at 32.768 khz) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) i/o ports 34 cmos input/output pins serial interface switchable between three-wire serial i/o and uart modes timers ? 16-bit timer : 1 channel ? 8-bit timer/event counter : 1 channel ? clock timer : 1 channel ? watchdog timer : 1 channel timer output two outputs maskable seven internal and four external interrupts vectored interrupt sources nonmaskable one internal interrupt power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40c to + 85c package 44-pin plastic lqfp (10 10 mm) the outline of the timer is as follows. 16-bit timer 8-bit timer/event counter watch timer watchdog timer interval timer - 1 channel 1 channel note 1 1 channel note 2 operating mode external event counter - 1 channel -- timer output 1 output 1 output -- pwm output - 1 output -- square-wave output - 1 output -- buzzer output 1 output --- capture 1 input --- function interrupt source 1 1 1 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer provides the watchdog timer function and interval timer function. use either of the functions.
user's manual u13600ej2v0um00 29 chapter 2 pin functions 2.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input - p10 to p17 i/o port 1 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input - p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ss20 p24 intp0 p25 intp1 p26 intp2/cpt90 p27 i/o port 2 8-bit input/output port can be set to either input or output in 1-bit units whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register b2 (pub2). input ti80/to80 p30 to90 p31 i/o port 3 2-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input bzo90 p40 to p47 i/o port 4 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input kr00 to kr07
chapter 2 pin functions user's manual u13600ej2v0um00 30 (2) non-port pins pin name i/o function after reset alternate function intp0 p24 intp1 p25 intp2 input external interrupt input for which effective edges (rising and/or falling edges) can be set input p26/cpt90 kr00 to kr07 input detection of key return signal input p40 to p47 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock input to serial interface input p20/asck20 ss20 input chip select i nput to serial interface input p23 asck20 input serial clock input to asynchronous serial interface input p20/sck20 rxd20 input serial data input to asynchronous serial interface input p22/si20 txd20 output serial data output from asynchronous serial interface input p21/so20 ti80 input external count clock input to 8-bit timer (tm80) input p27/to80 to80 output 8-bit timer (tm80) output input p27/ti80 to90 output 16-bit timer (tm90) output input p30 bzo90 output 16-bit timer (tm90) buzzer output input p31 cpt90 input capture edge input input p26/intp2 x1 input -- x2 - connected to crystal for main system clock oscillation -- xt1 input -- xt2 - connected to crystal for sub system clock oscillation -- reset input system reset input input - v dd0 - positive supply voltage for ports -- v dd1 - positive supply voltage (for circuits other than ports) -- v ss0 - ground potential for ports -- v ss1 - ground potential (for circuits other than ports) -- ic0 - this pin is internally connected. connect this pin directly to the v ss0 or v ss1 pin. -- v pp - this pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified. in normal operation mode, connect this pin directly to the v ss0 or v ss1 pin. --
chapter 2 pin functions user's manual u13600ej2v0um00 31 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these pins constitute an 8-bit i/o port and can be set to input or output port mode in 1-bit units by using port mode register 0 (pm0). when these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). 2.2.2 p10 to p17 (port 1) these pins constitute an 8-bit i/o port. can be set to input or output port mode in 1-bit units by using port mode register 1 (pm1). when these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull- up resistor option register 0 (pu0). 2.2.3 p20 to p27 (port 2) these pins constitute an 8-bit i/o port. in addition, these pins provide a function to perform input/output to/from the timer, to input/output the data and clock of the serial interface, and to input the external interrupt. port 2 can be set to the following operation modes bit-wise. (1) port mode in port mode, p20 to p27 function as an 8-bit i/o port. port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for p20 to p27, whether to use on-chip pull-up resistors can be specified in 1-bit units by using pull-up resistor option register b2 (pub2), regardless of the setting of port mode register 2 (pm2). (2) control mode in this mode, p20 to p27 function as the timer input/output, the data input/output and the clock input/output of the serial interface, and the external interrupt input. (a) ti80 this is the external clock input pin for the 8-bit timer/event counter. (b) to80 this is the timer output pin of the 8-bit timer/event counter. (c) si20, so20 this is the serial data i/o pin of the serial interface. (d) sck20 this is the serial clock i/o pin of the serial interface. (e) ss20 this is the chip select input pin of the serial interface. (f) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 2 pin functions user's manual u13600ej2v0um00 32 (g) asck20 this is the serial clock input pin of the asynchronous serial interface. (h) cpt90 this is the capture edge input pin of the 16-bit timer counter. (i) intp0 to intp2 these are external interrupt input pins for which the valid edge (rising edge, falling edge, and both the rising and falling edges) can be specified. caution when using p20 to p27 as serial interface pins, the input/output mode and output latch must be set according to the functions to be used. for details of the setting, see table 10-2. 2.2.4 p30, p31 (port 3) these pins constitute a 2-bit i/o port. in addition, these pins function as the timer output and the buzzer output. port 3 can be set to the following operation modes bit-wise. (1) port mode in port mode, p30 and p31 function as a 2-bit i/o port. port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (pm3). when this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, p30 and p31 function as the timer output and the buzzer output. (a) to90 this is the output pin of the 16-bit timer counter. (b) bzo90 this is the buzzer output pin of the 16-bit timer counter. 2.2.5 p40 to p47 (port 4) these pins constitute an 8-bit i/o port. in addition, they also function as key return signal detection pins. port 4 can be set to the following operation modes bit-wise. (1) port mode in port mode, p40 to p47 function as an 8-bit i/o port. port 4 can be set to input or output mode in 1-bit units by using port mode register 4 (pm4). when this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, p40 to p47 function as key return signal detection pins (kr00 to kr07).
chapter 2 pin functions user's manual u13600ej2v0um00 33 2.2.6 reset an active-low system reset signal is input to this pin. 2.2.7 x1, x2 these pins are used to connect a crystal resonator for main system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 2.2.8 xt1, xt2 these pins are used to connect a crystal resonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 2.2.9 v dd0 , v dd1 v dd0 supplies positive power to the ports. v dd1 supplies positive power to circuits other than those of the ports. 2.2.10 v ss0 , v ss1 v ss0 is the ground pin for the ports. v ss1 is the ground pin for circuits other than those of the ports. 2.2.11 v pp ( m m m m pd78f9046 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. directly connect this pin to v ss0 or v ss1 in normal operation mode. 2.2.12 ic0 (masked rom version only) the ic0 (internally connected) pin is used to set the m pd789046 to test mode before shipment. in normal operation mode, directly connect this pin to the v ss0 or v ss1 pin with as short a wiring length as possible. if a potential difference is generated between the ic0 pin and v ss0 or v ss1 pin due to a long wiring length between the ic0 pin and v ss0 or v ss1 pin or an external noise superimposed on the ic0 pin, a user program may not run correctly. directly connect the ic0 pin to the v ss0 or v ss1 pin. v ss0 , v ss1 ic0 keep short
chapter 2 pin functions user's manual u13600ej2v0um00 34 2.3 pin input/output circuits and handling of unused pins table 2-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 2-1 shows the configuration of each type of input/output circuit. table 2-1. type of input/output circuit for each pin and handling of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00 to p07 p10 to p17 5-h p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/ss20 p24/intp0 p25/intp1 p26/intp2/cpt90 p27/ti80/to80 8-c p30/to90 p31/bzo90 5-h p40/kr00 to p47/kr07 8-c i/o input: connect these pins to the v dd0 , v dd1 , v ss0 , or v ss1 pin via respective resistors. output: leave these pins open. xt1 input connect this pin to the v ss0 or v ss1 pin. xt2 - - leave this pin open. reset 2 input - ic0 (masked rom version) v pp (flash memory version) -- connect these pins directly to the v ss0 or v ss1 pin.
chapter 2 pin functions user's manual u13600ej2v0um00 35 figure 2-1. pin input/output circuits schmitt trigger input with hysteresis type 2 in type 5-h pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 8-c
user's manual u13600ej2v0um00 36 [memo]
user's manual u13600ej2v0um00 37 chapter 3 cpu architecture 3.1 memory space the m pd789046 subseries can each access up to 64 kbytes of memory space. figures 3-1 and 3-2 show the memory maps. figure 3-1. memory map ( m m m m pd789046) special function register 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area unusable vector table area internal rom 16,384 8 bits ffffh ff00h feffh fd00h fcffh 3fffh 0080h 007fh 0040h 003fh 001ah 0019h 0000h 0000h 4000h 3fffh
chapter 3 cpu architecture user's manual u13600ej2v0um00 38 figure 3-2. memory map ( m m m m pd78f9046) special function register 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area unusable vector table area flash memory 16,384 8 bits ffffh ff00h feffh fd00h fcffh 3fffh 0080h 007fh 0040h 003fh 001ah 0019h 0000h 0000h 4000h 3fffh
chapter 3 cpu architecture user's manual u13600ej2v0um00 39 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the m pd789046 subseries provide the following internal roms (or flash memory) containing the following capacities. table 3-1. internal rom capacity internal rom part number structure capacity m pd789046 masked rom 16,384 8 bits m pd78f9046 flash memory 16,384 8 bits the following areas are allocated to the internal program memory space: (1) vector table area a 26-byte area of addresses 0000h to 0019h is reserved as a vector table area. this area stores program start addresses to be used when branching by the reset input or an interrupt request generation. of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 000eh intst20 0004h intwdt 0010h intwt 0006h intp0 0012h intwti 0008h intp1 0014h inttm80 000ah intp2 0016h inttm90 000ch intsr20/intcsi20 0018h intkr00 (2) callt instruction table area in a 64-byte area of addresses 0040h to 007fh, the subroutine entry address of a 1-byte call instruction (callt) can be stored. 3.1.2 internal data memory (internal high-speed ram) space the m pd789046 subseries provide 512-byte internal high-speed ram. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocated to an area of ff00h to ffffh (see table 3-3 ).
chapter 3 cpu architecture user's manual u13600ej2v0um00 40 3.1.4 data memory addressing each of the m pd789046 subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. a data memory area (fd00h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special function register (sfr). figures 3-3 and 3-4 illustrate the data memory addressing modes. figure 3-3. data memory addressing modes ( m m m m pd789046) special function register (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 16,384 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing unusable ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh 4000h 3fffh 0000h
chapter 3 cpu architecture user's manual u13600ej2v0um00 41 figure 3-4. data memory addressing modes ( m m m m pd78f9046) special function register (sfr) 256 8 bits internal high-speed ram 512 8 bits flash memory 16,384 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing unusable ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh 4000h 3fffh 0000h
chapter 3 cpu architecture user's manual u13600ej2v0um00 42 3.2 processor registers the m pd789046 subseries provide the following on-chip processor registers: 3.2.1 control registers the control registers have special functions to control the program sequence statuses and stack memory. the control registers include a program counter, a program status word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-5. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-6. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 3 cpu architecture user's manual u13600ej2v0um00 43 (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of the cpu. when ie = 0, the interrupt disabled (di) status is set. all interrupt requests except non-maskable interrupt are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. this flag is reset to 0 upon di instruction execution or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. (d) carry flag (cy) this flag stores overflow and underflow that have occurred upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
chapter 3 cpu architecture user's manual u13600ej2v0um00 44 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-7. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores data as shown in figures 3-8 and 3-9. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-8. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs figure 3-9. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs ret instruction pop rp instruction sp pc7 to pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 3 cpu architecture user's manual u13600ej2v0um00 45 3.2.2 general-purpose registers a general-purpose register consists of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). they can be described in terms of functional names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 3-10. general-purpose register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) functional names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 3 cpu architecture user's manual u13600ej2v0um00 46 3.2.3 special function register (sfr) unlike a general-purpose register, each special function register has a special function. it is allocated in the 256-byte area ff00h to ffffh. the special function register can be manipulated, like the general-purpose register, with the operation, transfer, and bit manipulation instructions. manipulatable bit units (1, 8, and 16) differ depending on the special function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describes a symbol reserved with assembler for the 16-bit manipulation instruction operand. when specifying an address, describe an even address. table 3-3 lists the special function registers. the meanings of the symbols in this table are as follows: symbol indicates the addresses of the implemented special function registers. the symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of c compiler. therefore, these symbols can be used as instruction operands if assembler or integrated debugger is used. r/w indicates whether the special function register can be read or written. r/w : read/write r : read only w : write only number of bits manipulated simultaneously indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. after reset indicates the status of the special function register when the reset signal is input.
chapter 3 cpu architecture user's manual u13600ej2v0um00 47 table 3-3. special function registers (1/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 oo- ff01h port 1 p1 oo- ff02h port 2 p2 oo- ff03h port 3 p3 oo- ff04h port 4 p4 r/w oo- 00h ff16h ff17h 16-bit compare register 90 cr90 w - o note 1 o note 2 ffffh ff18h ff19h 16-bit timer counter 90 tm90 - o note 1 o note 2 0000h ff1ah ff1bh 16-bit capture register 90 tcp90 r - o note 1 o note 2 undefined ff20h port mode register 0 pm0 oo- ff21h port mode register 1 pm1 oo- ff22h port mode register 2 pm2 oo- ff23h port mode register 3 pm3 oo- ff24h port mode register 4 pm4 oo- ffh ff32h pull-up resistor option register b2 pub2 oo- ff42h timer clock selection register 2 tcl2 -o- ff48h 16-bit timer mode control register 90 tmc90 oo- ff49h buzzer output control register 90 bzc90 oo- ff4ah watch timer mode control register wtm r/w oo- 00h ff50h 8-bit compare register 80 cr80 w -o- undefined ff51h 8-bit timer counter 80 tm80 r -o- ff53h 8-bit timer mode control register 80 tmc80 oo- ff70h asynchronous serial interface mode register 20 asim20 r/w oo- ff71h asynchronous serial interface status register 20 asis20 r oo- ff72h serial operation mode register 20 csim20 oo- ff73h baud rate generator control register 20 brgc20 r/w -o- 00h notes 1. cr90, tm90, and tcp90 are designed only for 16-bit access. in direct addressing, however, 8-bit access can also be performed. 2. 16-bit access is allowed only in short direct addressing.
chapter 3 cpu architecture user's manual u13600ej2v0um00 48 table 3-3. special function registers (2/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset transmission shift register 20 txs20 w -o- ffh ff74h reception buffer register 20 rxb20 sio20 r -o- undefined ffe0h interrupt request flag register 0 if0 oo- ffe1h interrupt request flag register 1 if1 oo- 00h ffe4h interrupt mask flag register 0 mk0 oo- ffe5h interrupt mask flag register 1 mk1 oo- ffh ffech external interrupt mode register 0 intm0 -o- fff0h suboscillation mode register sckm oo- fff2h subclock control register css oo- fff5h key return mode register 00 krm00 oo- fff7h pull-up resistor option register 0 pu0 oo- fff9h watchdog timer mode register wdtm oo- 00h fffah oscillation settling time selection register osts -o- 04h fffbh processor clock control register pcc r/w oo- 02h
chapter 3 cpu architecture user's manual u13600ej2v0um00 49 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents. pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination address information is set to the pc to branch by the following addressing (for details of each instruction, refer to 78k/0s series user's manual ? ? ? ? instruction (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) to branch. the displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 a jdisp8 when s = 0, a indicates all bits "0". ... pc is the start address of the next instruction of a br instruction. when s = 1, a indicates all bits "1".
chapter 3 cpu architecture user's manual u13600ej2v0um00 50 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) to branch. this function is carried out when the call !addr16 and br !addr16 instructions are executed. call !addr16 and br !addr16 instructions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 3 cpu architecture user's manual u13600ej2v0um00 51 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) to branch. table indirect addressing is carried out when the callt [addr5] instruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4? instruction code 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) to branch. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture user's manual u13600ej2v0um00 52 3.4 operand address addressing the following methods (addressing) are available to specify the register and memory which undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code00101001op code 0000000000h 11111110feh [illustration] 70 op code addr16 (low) addr16 (high) memory
chapter 3 cpu architecture user's manual u13600ej2v0um00 53 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space where this addressing is applied is the 256-byte space fe20h to ff1fh. an internal high- speed ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of all sfr areas. in this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset a when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1. a a
chapter 3 cpu architecture user's manual u13600ej2v0um00 54 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture user's manual u13600ej2v0um00 55 3.4.4 register addressing [function] the general-purpose register is accessed as an operand. the general-purpose register to be accessed is specified with register specify code and functional name in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 'r' and 'rp' can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 00100101 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code
chapter 3 cpu architecture user's manual u13600ej2v0um00 56 3.4.5 register indirect addressing [function] the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description - [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de
chapter 3 cpu architecture user's manual u13600ej2v0um00 57 3.4.6 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description - [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code00101101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing can be used to access the internal high-speed ram area only. [description example] in the case of push de instruction code10101010
user's manual u13600ej2v0um00 58 [memo]
user's manual u13600ej2v0um00 59 chapter 4 port functions 4.1 port functions the m pd789046 subseries is provided with the ports shown in figure 4-1. these ports are used to enable several types of control. table 4-1 lists the functions of each port. these ports, while originally designed as digital input/output ports, have alternate functions, as summarized in section 2.1 . figure 4-1. port types port 2 port 3 port 4 port 0 port 1 p20 p27 p30 p31 p40 p47 p00 p07 p10 p17
chapter 4 port functions user's manual u13600ej2v0um00 60 table 4-1. port functions pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input - p10 to p17 i/o port 1 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input - p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ss20 p24 intp0 p25 intp1 p26 intp2/cpt90 p27 i/o port 2 8-bit input/output port can be set to either input or output in 1-bit units whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register b2 (pub2). input ti80/to80 p30 to90 p31 i/o port 3 2-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input bzo90 p40 to p47 i/o port 4 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by pull-up resistor option register 0 (pu0). input kr00 to kr07
chapter 4 port functions user's manual u13600ej2v0um00 61 4.2 port configuration ports have the following hardware configuration. table 4-2. configuration of port parameter configuration control register port mode registers (pmm: m = 0 to 4) pull-up resistor option register 0 (pu0) pull-up resistor option register b2 (pub2) port total: 34 (cmos input/output: 34) pull-up resistor total: 34 (software control: 34) 4.2.1 port 0 this is an 8-bit i/o port with an output latch. port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (pm0). when pins p00 to p07 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (pu0). reset input sets port 0 to input mode. figure 4-2 shows a block diagram of port 0. figure 4-2. block diagram of p00 to p07 internal bus wr pu0 rd wr port wr pm pu00 output latch (p00 to p07) pm00 to pm07 v dd0 p-ch p00 to p07 selector pu0 : pull-up resistor option register 0 pm : port mode register rd : port 0 read signal wr : port 0 write signal
chapter 4 port functions user's manual u13600ej2v0um00 62 4.2.2 port 1 this is an 8-bit i/o port with an output latch. port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (pm1). when the p10 to p17 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (pu0). reset input sets port 1 to input mode. figure 4-3 shows a block diagram of port 1. figure 4-3. block diagram of p10 to p17 internal bus wr pu0 rd wr port wr pm pu01 output latch (p10 to p17) pm10 to pm17 v dd0 p-ch p10 to p17 selector pu0 : pull-up resistor option register 0 pm : port mode register rd : port 1 read signal wr : port 1 write signal
chapter 4 port functions user's manual u13600ej2v0um00 63 4.2.3 port 2 this is an 8-bit i/o port with output latches. port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for pins p20 to p27, on-chip pull-up resistors can be connected in 1-bit units by using pull- up resistor option register b2 (pub2). the port is also used as a data i/o and clock i/o to and from the serial interface, timer i/o, and external interrupt input. reset input sets port 2 to input mode. figures 4-4 through 4-8 show block diagrams of port 2. caution when using the pins of port 2 as the serial interface, the i/o and output latches must be set according to the function to be used. for details of the settings, see table 10-2. figure 4-4. block diagram of p20 internal bus v dd0 p-ch p20/asck20/ sck20 wr pub2 rd wr port wr pm pub20 alternate function output latch (p20) pm20 alternate function selector pub2 : pull-up resistor option register b2 pm : port mode register rd : port 2 read signal wr : port 2 write signal
chapter 4 port functions user's manual u13600ej2v0um00 64 figure 4-5. block diagram of p21 internal bus v dd0 p-ch p21/txd20/ so20 wr pub2 rd wr port wr pm pub21 output latch (p21) pm21 alternate function selector ss20 chip select input signal pub2 : pull-up resistor option register b2 pm : port mode register rd : port 2 read signal wr : port 2 write signal
chapter 4 port functions user's manual u13600ej2v0um00 65 figure 4-6. block diagram of p22 and p24 to p26 internal bus v dd0 p-ch p22/rxd20/si20 p24/intp0 p25/intp1 p26/intp2/cpt90 wr pub2 rd wr port wr pm pub22, pub24 to pub26 alternate function output latch (p22, p24 to p26) pm22, pm24 to pm26 selector pub2 : pull-up resistor option register b2 pm : port mode register rd : port 2 read signal wr : port 2 write signal
chapter 4 port functions user's manual u13600ej2v0um00 66 figure 4-7. block diagram of p23 internal bus v dd0 p-ch p23/ss20 wr pub2 rd wr port wr pm pub23 alternate function output latch (p23) pm23 selector pub2 : pull-up resistor option register b2 pm : port mode register rd : port 2 read signal wr : port 2 write signal
chapter 4 port functions user's manual u13600ej2v0um00 67 figure 4-8. block diagram of p27 internal bus v dd0 p-ch p27/to80/ti80 wr pub2 rd wr port wr pm pub27 output latch (p27) pm27 alternate function selector alternate function pub2 : pull-up resistor option register b2 pm : port mode register rd : port 2 read signal wr : port 2 write signal
chapter 4 port functions user's manual u13600ej2v0um00 68 4.2.4 port 3 this is a 2-bit i/o port with output latches. port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (pm3). when p30 and p31 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (pu0). the port is also used as timer output and buzzer output. reset input sets port 3 to input mode. figure 4-9 shows a block diagram of port 3. figure 4-9. block diagram of p30 and p31 internal bus wr pu0 rd wr port wr pm pu03 output latch (p30, p31) pm30, pm31 alternate function v dd0 p-ch p30/to90 p31/bzo90 selector pu0 : pull-up resistor option register 0 pm : port mode register rd : port 3 read signal wr : port 3 write signal
chapter 4 port functions user's manual u13600ej2v0um00 69 4.2.5 port 4 this is an 8-bit i/o port with output latches. port 4 can be set to input or output mode in 1-bit units by using port mode register 4 (pm4). when p40 to p47 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register 0 (pu0). the port is also used as the key return input. reset input sets port 4 to input mode. figure 4-10 shows a block diagram of port 4. caution when using port 4 for the key return function, it is necessary to set key return mode register 00 (krm00). for details of the settings, see section 11.3 (5). figure 4-10. block diagram of p40 to p47 internal bus wr pu0 rd wr port wr krm00 wr pm v dd0 p-ch p40/kr00 to p47/kr07 wr pu0 alternate function pm40 to pm47 output latch (p40 to p47) krm000 to krm007 pu04 selector krm00 : key return mode register 00 pu0 : pull-up resistor option register 0 pm : port mode register rd : port 4 read signal wr : port 4 write signal
chapter 4 port functions user's manual u13600ej2v0um00 70 4.3 port function control registers the following two types of registers are used to control the ports. ? port mode registers (pm0 to pm4) ? pull-up resistor option registers (pu0 and pub2) (1) port mode registers (pm0 to pm4) the port mode registers separately set each port bit to either input or output. each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. reset input writes ffh into the port mode registers. when port pins are used for alternate functions, the corresponding port mode register and output latch must be set or reset as described in table 4-3. caution when port 2 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance. table 4-3. port mode register and output latch settings for using alternate functions alternate function pin name name input/output pm p p24 intp0 input 1 p25 intp1 input 1 intp2 input 1 p26 cpt90 input 1 ti80 input 1 p27 to80 output 0 0 p30 to90 output 0 0 p31 bzo90 output 0 0 p40 to p47 note kr00 to kr07 input 1 note when an alternate function is used, set key return mode register 00 (krm00) to 1 (see section 11.3 (5) ). caution when using the pins of port 2 as the serial interface, the i/o or output latch must be set according to the function to be used. for details of the settings, see table 10-2. remark : don't care pm : port mode register p : port output latch
chapter 4 port functions user's manual u13600ej2v0um00 71 figure 4-11. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 pmn pin input/output mode selection m = 0 to 2, 4 : n = 0 to 7 m = 3 : n = 0, 1 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0 76 54 symbol address after reset r/w ff20h ffh r/w 3210 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1 ff21h ffh r/w pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 ff22h ffh r/w 1 1 1 1 1 1 pm31 pm30 pm3 ff23h ffh r/w pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm4 ff24h ffh r/w (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (pu0) sets whether an on-chip pull-up resistor on port 0, 1, 3, or 4 is used. on the port which is specified to use the on-chip pull-up resistor in pu0, the pull-up resistor can be internally used only for the bits set to input mode. no on-chip pull-up resistors can be used for the bits set to output mode regardless of the setting of pu0. on-chip pull-up resistors cannot be used even when the pins are used as the alternate-function output pins. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 4-12. format of pull-up resistor option register 0 pu0m 0 1 pm on-chip pull-up resistor selection (m = 0, 1, 3, 4) on-chip pull-up resistor not used on-chip pull-up resistor used 0 0 0 pu04 pu03 0 pu01 pu00 pu0 7 6 5 <4> symbol address after reset r/w fff7h 00h r/w <3> 2 <1> <0> caution bits 2 and 5 to 7 must all be set to 0.
chapter 4 port functions user's manual u13600ej2v0um00 72 (3) pull-up resistor option register b2 (pub2) this register specifies whether an on-chip pull-up resistor connected to each pin of port 2 is used. the pin for which use of an on-chip pull-up resistor is specified by pub2 can use a pull-up register internally, regardless of the setting of the port mode register. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 4-13. format of pull-up resistor option register b2 pub2n 0 1 p2n on-chip pull-up resistor selection (n = 0 to 7) on-chip pull-up resistor not used on-chip pull-up resistor used pub27 pub26 pub25 pub24 pub23 pub22 pub21 pub20 pub2 <7> <6> <5> <4> symbol address after reset r/w ff32h 00h r/w <3> <2> <1> <0>
chapter 4 port functions user's manual u13600ej2v0um00 73 4.4 operation of port functions the operation of a port differs depending on whether the port is set to input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. the data once written to the output latch is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. however, the status of the port pin is not changed because the output buffer is off. the data once written to the output latch is retained until new data is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the contents of the output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the result of the operation is written to the output latch. the contents of the output latch are output from the port pins. the data once written to the output latch is retained until new data is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
user's manual u13600ej2v0um00 74 [memo]
user's manual u13600ej2v0um00 75 chapter 5 clock generation circuit 5.1 clock generation circuit functions the clock generation circuit generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. main system clock oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by setting the subclock control register (css). 5.2 clock generation circuit configuration the clock generation circuit consists of the following items of hardware. table 5-1. configuration of clock generation circuit item configuration control register processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillator main system clock oscillator subsystem clock oscillator
chapter 5 clock generation circuit user's manual u13600ej2v0um00 76 figure 5-1. block diagram of clock generation circuit f xt f x prescaler f x 2 2 f xt 2 1/2 prescaler clock for peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc xt2 xt1 scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x2 x1 main system clock oscillator 16-bit timer 90 watch timer
chapter 5 clock generation circuit user's manual u13600ej2v0um00 77 5.3 registers controlling clock generation circuit the clock generation circuit is controlled by the following registers: processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) (1) processor clock control register (pcc) pcc selects the cpu clock and the ratio of division. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processor clock control register control of main system clock oscillator operation mcc 0 1 operation enabled operation disabled cpu clock (f cpu ) selection note css0 0 0 1 1 pcc1 0 1 0 1 f x (0.2 s) f x /2 2 (0.8 s) f xt /2 (61 s) m m m mcc 0 0 0 0 0 pcc1 0 pcc 76 54 symbol address after reset r/w fffbh 02h r/w 3210 note the cpu clock is selected according to a combination of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css). see section 5.3 (3) . cautions 1. bits 0 and 2 to 6 must all be set to 0. 2. mcc can be set only when the subsystem clock has been selected as the cpu clock. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 4. minimum instruction execution time: 2f cpu f cpu = 0.2 m s: 0.4 m s f cpu = 0.8 m s: 1.6 m s f cpu = 61 m s: 122 m s
chapter 5 clock generation circuit user's manual u13600ej2v0um00 78 (2) suboscillation mode register (sckm) sckm specifies whether to use a feedback resistor for the subsystem clock, and controls the oscillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sckm to 00h. figure 5-3. format of suboscillation mode register use of feedback resistor frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled 0 0 0 0 0 0 frc scc sckm 76 54 symbol address after reset r/w fff0h 00h r/w 3210 caution bits 2 to 7 must all be set to 0. (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be used. it also specifies how the cpu clock operates. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears css to 00h. figure 5-4. format of subclock control register cpu clock operation status cls 0 1 operation based on the (divided) main system clock operation based on the subsystem clock selection of main system or subsystem clock oscillator css0 0 1 (divided) output from the main system clock oscillator output form the subsystem clock oscillator 0 0 cls css0 0 0 0 0 css 76 54 symbol address after reset r/w fff2h 00h r/w note 3210 note bit 5 is read-only. caution bits 0 to 3, 6, and 7 must all be set to 0.
chapter 5 clock generation circuit user's manual u13600ej2v0um00 79 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the x1 pin, and input the reversed signal to the x2 pin. figure 5-5 shows the external circuit of the main system clock oscillator. figure 5-5. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock v ss0 , v ss1 x1 x2 crystal or ceramic resonator external clock x1 x2 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the xt1 pin, and input the reversed signal to the xt2 pin. figure 5-6 shows the external circuit of the subsystem clock oscillator. figure 5-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss0 , v ss1 xt1 32.768 khz external clock xt1 xt2 cautions 1. when using the main system or subsystem clock oscillator, to avoid influence of wiring capacity, etc., wire the portion enclosed by the broken line in figures 5-5 and 5-6 as follows: keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground of the capacitor of the oscillator at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not extract signals from the oscillator. when using the subsystem clock, pay special attention because the subsystem clock oscillator has low amplification to minimize current consumption. figure 5-7 shows unacceptable resonator connections.
chapter 5 clock generation circuit user's manual u13600ej2v0um00 80 figure 5-7. unacceptable resonator connections (1/2) (a) wiring too long (b) crossed signal line v ss0 , v ss1 x1 x2 v ss0 , v ss1 x1 x2 portn (n = 0 to 4) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss0 , v ss1 x1 x2 high current v ss0 , v ss1 x1 ab c p mn v dd0 high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to the xt2 pin in series.
chapter 5 clock generation circuit user's manual u13600ej2v0um00 81 figure 5-7. unacceptable resonator connections (2/2) (e) signal is extracted (f) signal conductors of the main and subsystem clocks are parallel and near to each other v ss0 , v ss1 x1 x2 v ss0 , v ss1 x2 xt2 and x1 wiring in parallel x1 xt2 xt1 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to the xt2 pin in series. cautions 2. if the x1 wire is in parallel with the xt2 wire, crosstalk noise may occur between x1 and xt2, resulting in a malfunction. to avoid this, do not lay the x1 and xt2 wires in parallel. 5.4.3 scaler the scaler divides the main system clock oscillator output (f x ) and generates clocks. 5.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect to v ss0 or v ss1 xt2: open in this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize the leakage current, the on-chip feedback resistor can be removed by setting bit 1 (frc) of the suboscillation mode register (sckm). in this case, also connect the xt1 and xt2 pins as described above.
chapter 5 clock generation circuit user's manual u13600ej2v0um00 82 5.5 clock generation circuit operation the clock generation circuit generates the following clocks and controls operation modes of the cpu, such as standby mode: main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the operation of the clock generation circuit is determined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclock control register (css), as follows: (a) the slow mode 2f cpu (1.6 m s: at 5.0-mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of cpu clocks f cpu (0.2 m s and 0.8 m s: main system clock (at 5.0-mhz operation), 61 m s: subsystem clock (at 32.768-khz operation)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt, can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (frc) of sckm so that the on-chip feedback resistor cannot be used reduces current drain during stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsystem clock so that low current drain operation is used (122 m s: at 32.768-khz operation). (e) with the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by using bit 7 (mcc) of pcc. halt mode can be used, but stop mode cannot. (f) the clock for the peripheral hardware is generated by dividing the frequency of the main system clock. the subsystem clock is supplied to 16-bit timer and the watch timer only. so, even in standby mode, 16-bit timer and the watch function can keep running. the other hardware stops when the main system clock stops, because it runs based on the main system clock (except for an external input clock).
chapter 5 clock generation circuit user's manual u13600ej2v0um00 83 5.6 changing setting of system clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the setting of pcc has been changed, and the old clock is used for the duration of several instructions after that (see table 5-2 ). table 5-2. maximum time required for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 00011 0 4 clocks 2f x /f xt clocks (306 clo cks) 0 1 2 clocks f x /2f xt clocks (76 clocks) 1 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execution time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. : don't care
chapter 5 clock generation circuit user's manual u13600ej2v0um00 84 5.6.2 switching between system clock and cpu clock the following figure illustrates how the system clock and cpu clock switch. figure 5-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x slow operation fast operation subsystem clock operation fast operation wait (6.55 ms: at 5.0-mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on power application. the effect of resetting is released when the reset pin is later made high, and the main system clock starts oscillating. at this time, the time during which oscillation settles (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execution at the slow speed of the main system clock (1.6 m s: at 5.0-mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at the high speed has elapsed, bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that the high-speed operation can be selected. <3> when a drop of the v dd voltage is detected with an interrupt request signal, the clock is switched to the subsystem clock. (at this moment, the subsystem clock must be in the oscillation settling status.) <4> when a recover of the v dd voltage is detected with an interrupt request signal, bit 7 (mcc) of pcc is set to 0 to make the main system clock start oscillating. after the time required for the oscillation to settle has elapsed, pcc1 and css0 are rewritten so that high-speed operation can be selected again. caution when the main system clock is stopped and the subsystem clock is operating, allow sufficient time for the oscillation to settle by coding the program before switching again from the subsystem clock to the main system clock.
user's manual u13600ej2v0um00 85 chapter 6 16-bit timer 6.1 16-bit timer functions the 16-bit timer has the following functions. timer interrupt timer output buzzer output count value capture (1) timer interrupt an interrupt is generated when a count value and compare value match. (2) timer output timer output can be controlled when a count value and compare value match. (3) buzzer output buzzer output can be controlled by software. (4) count value capture a count value of 16-bit timer counter 90 (tm90) is latched into a capture register synchronizing with the capture trigger and retained. 6.2 16-bit timer configuration the 16-bit timer consists of the following items of hardware. table 6-1. configuration of 16-bit timer item configuration timer counter 16 bits 1 (tm90) register compare register : 16 bits 1 (cr90) capture register : 16 bits 1 (tcp90) timer output 1 (to90) buzzer output 1 (bzo90) control register 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 3 (pm3)
chapter 6 16-bit timer user's manual u13600ej2v0um00 86 figure 6-1. block diagram of 16-bit timer f x /2 2 f x /2 4 f x /2 6 f xt f x 16-bit timer mode control register 90 (tmc90) ctp90/intp2/ p26 edge detection circuit 16-bit capture register 90 (tcp90) 16-bit counter read buffer write control circuit f x /2 cpu clock write control circuit match internal bus internal bus flip-flop ovf tod90 to90/p30 inttm90 bzo90/p31 buzzer output control register 90 (bzc90) bcs902 bcs901 / 3 bcs900 bzoe90 p30 output latch pm30 p31 output latch pm31 16-bit timer counter 90 (tm90) tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 selector selector selector sync circuit 16-bit compare register 90 (cr90)
chapter 6 16-bit timer user's manual u13600ej2v0um00 87 (1) 16-bit compare register 90 (cr90) a value specified in cr90 is compared with the count in 16-bit timer counter 90 (tm90). if they match, an interrupt request (inttm90) is issued by cr90. cr90 is set with an 8-bit or 16-bit memory manipulation instruction. any value from 0000h to ffffh can be set. reset input sets cr90 to ffffh. cautions 1. cr90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set cr90, it must be accessed in direct addressing. 2. to re-set cr90 during count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (tmc90). if cr90 is rewritten with the interrupt enabled, an interrupt request may be issued immediately. (2) 16-bit timer counter 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read with an 8-bit or 16-bit memory manipulation instruction. reset input clears tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is deselected, because the count operation is performed before oscillation settles. 2. tm90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory instruction is used to manipulate tm90, it must be accessed in direct addressing. 3. when an 8-bit memory manipulation instruction is used to manipulate tm90, the lower and upper bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of 16-bit timer counter 90 (tm90). it is set with an 8-bit or 16-bit memory manipulation instruction. reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to manipulate tcp90, it must be accessed in direct addressing. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count for 16-bit timer counter 90 (tm90).
chapter 6 16-bit timer user's manual u13600ej2v0um00 88 6.3 registers controlling 16-bit timer the following three types of registers control the 16-bit timer. 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 3 (pm3) (1) 16-bit timer mode control register 90 (tmc90) 16-bit timer mode control register 90 (tmc90) controls the setting of a count clock, capture edge, etc. tmc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc90 to 00h.
chapter 6 16-bit timer user's manual u13600ej2v0um00 89 figure 6-2. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address after reset r/w ff48h 00h r/w note 5 <6> 4321<0> 7 tof90 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge at the cpt90 pin captured at the falling edge at the cpt90 pin captured at both the rising and falling edges at the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled tcl901 0 0 1 1 16-bit timer counter 90 count clock selection tcl900 0 1 0 1 toe90 0 1 16-bit timer output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output of 0 timer output of 1 f x /2 2 (1.25 mhz) f x /2 6 (78.125 khz) f x /2 4 (31.1 khz) f xt (32.768 khz) note bit 7 is read-only. caution disable the interrupt in advance by using the interrupt mask flag register 1 (mk1) to change the data of tcl901 and tcl900. also, prevent the timer output data from being inverted by setting toe90 to 1. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer user's manual u13600ej2v0um00 90 (2) buzzer output control register 90 (bzc90) this register selects a buzzer frequency based on fcl selected with the count clock select bits (tcl901 and tcl900), and controls the output of a square wave. bzc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears bzc90 to 00h. figure 6-3. format of buzzer output control register 90 bzoe90 buzzer port output control disables buzzer port output. enables buzzer port output. 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address after reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 <0> fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 4 fcl = f xt fcl/2 4 (78.125 khz) fcl/2 5 (39.063 khz) fcl/2 8 (4.88 khz) fcl/2 9 (2.44 khz) fcl/2 10 (1.22 khz) fcl/2 11 (610 hz) fcl/2 12 (305 hz) fcl/2 13 (153 hz) fcl/2 4 (4.88 khz) fcl/2 5 (2.44 khz) fcl/2 8 (305 hz) fcl/2 9 (153 hz) fcl/2 10 (76 hz) fcl/2 11 (38 hz) fcl/2 12 (19 hz) fcl/2 13 (10 hz) fcl/2 4 (19.5 khz) fcl/2 5 (9.77 khz) fcl/2 8 (1.22 khz) fcl/2 9 (610 hz) fcl/2 10 (305 hz) fcl/2 11 (153 hz) fcl/2 12 (76.3 hz) fcl/2 13 (38.1 hz) fcl/2 4 (2.05 khz) fcl/2 5 (1.02 khz) fcl/2 8 (128 hz) fcl/2 9 (64 hz) fcl/2 10 (32 hz) fcl/2 11 (16 hz) fcl/2 12 (8 hz) fcl/2 13 (4 hz) cautions 1. bits 4 to 7 must all be set to 0. 2. if the subclock is selected as the count clock (tcl901 = 1, tcl900 = 1: see figure 6-2), the subclock is not synchronized when buzzer port output is enabled. in this case, the capture function and tm90 register read function are disabled. in addition, the count value of the tm90 register is undefined. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer user's manual u13600ej2v0um00 91 (3) port mode register 3 (pm3) pm3 is used to set each bit of port 3 to input or output. when pin p30/to90 is used for timer output, reset the output latch of p30 and pm30 to 0; when pin p31/bzo90 is used for buzzer output, reset the output latch of p31 and pm31 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 6-4. format of port mode register 3 pm3n p3n pin i/o mode (n = 0, 1) output mode (output buffer on) input mode (output buffer off) 0 1 1 1 1 1 1 1 pm31 pm30 pm3 symbol address after reset r/w ff23h ffh r/w 6 754 3 21 0
chapter 6 16-bit timer user's manual u13600ej2v0um00 92 6.4 16-bit timer operation 6.4.1 operation as timer interrupt in the timer interrupt function, interrupts are repeatedly generated at the count value set in 16-bit compare register 90 (cr90) in advance based on the intervals of the value set in tcl901 and tcl900. to operate 16-bit timer as a timer interrupt, the following settings are required. set count values in cr90 set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-5. figure 6-5. settings of 16-bit timer mode control register 90 for timer interrupt operation - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) caution if 0 is set both for cpt901 and cpt900 flags, capture operation becomes prohibited. when the count value of 16-bit timer counter 90 (tm90) coincides with the value set in cr90, counting of tm90 continues and an interrupt request signal (inttm90) is generated. table 6-2 shows interval time, and figure 6-6 shows timing of timer interrupt operation. caution perform the following processing when rewriting cr90 during count operation. <1> disable the interrupt (tmmk90 (bit 7 of the interrupt mask flag register 0 (mk0)) = 1). <2> disable inversion control of timer output data (toc90 = 0). if cr90 is rewritten with the interrupt enabled, an interrupt request may be issued immediately. table 6-2. interval time of 16-bit timer tcl901 tcl900 count clock interval time 002 2 /f x (0.8 m s) 2 18 /f x (52.4 ms) 012 6 /f x (12.8 m s) 2 22 /f x (838.9 ms) 102 4 /f x (3.2 m s) 2 20 /f x (210.0 ms) 111/f xt (30.5 m s) 2 16 /f xt (2.0 s) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer user's manual u13600ej2v0um00 93 figure 6-6. timing of timer interrupt operation count clock tm90 count value cr90 inttm90 to90 tof90 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt accept interrupt accept overflow flag set t remark n = 0000h to ffffh
chapter 6 16-bit timer user's manual u13600ej2v0um00 94 6.4.2 operation as timer output timer outputs are repeatedly generated at the count value set in 16-bit compare register 90 (cr90) in advance based on the intervals of the value set in tcl901 and tcl900. to operate 16-bit timer as a timer output, the following settings are required. set p30 to output mode (pm30 = 0). reset the output latch of p30 to 0. set the count value in cr90. set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-7. figure 6-7. settings of 16-bit timer mode control register 90 for timer output operation - 0/1 0/1 0/1 1 0/1 0/1 1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) inverse enable of timer output data to90 output enable caution if both cpt901 flag and cpt900 flag are set to 0, capture operation becomes prohibited. when the count value of 16-bit timer counter 90 (tm90) matches the value set in cr90, the output status of the to90/p30 pin is inverted. this enables timer output. at that time, tm90 count is continued and an interrupt request signal (inttm90) is generated. figure 6-8 shows the timing of timer output (see table 6-2 for the interval time of the 16-bit timer). figure 6-8. timer output timing count clock tm90 count value cr90 inttm90 to90 note tof90 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt accept interrupt accept overflow flag set t note the to90 initial value becomes low level during output enable (toe90 = 1). remark n = 0000h to ffffh
chapter 6 16-bit timer user's manual u13600ej2v0um00 95 6.4.3 capture operation the capture operation consists of latching the count value of 16-bit timer counter 90 (tm90) into a capture register synchronizing with a capture trigger, and retaining the count value. set tmc90 as shown in figure 6-9 to allow 16-bit timer to start the capture operation. figure 6-9. settings of 16-bit timer mode control register 90 for capture operation - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 90 (tcp90) starts capture operation after a cpt90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer counter 90. tcp90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-10 shows the settings of capture edge and capture operation timing, respectively. table 6-3. settings of capture edge cpt901 cpt900 capture edge selection 0 0 capture operation prohibited 0 1 cpt90 pin rising edge 1 0 cpt90 pin falling edge 1 1 cpt90 pin both edges caution because tcp90 is rewritten when a capture trigger edge is detected during tcp90 read, disable the capture trigger edge detection during tcp90 read. figure 6-10. capture operation timing (both edges of cpt90 pin are specified) remark n = 0000h to ffffh m = 0000h to ffffh count clock tm90 count read buffer tcp90 cpt90 0000h 0000h 0001h 0001h undefined n n n m e 1 m m m capture start capture start capture edge detection capture edge detection
chapter 6 16-bit timer user's manual u13600ej2v0um00 96 6.4.4 16-bit timer counter 90 readout the count value of 16-bit timer counter 90 (tm90) is read out with a 16-bit manipulation instruction. tm90 readout is performed through a counter read buffer. the counter read buffer latches the tm90 count value. and buffer operation is pended at the cpu clock falling edge after the read signal of the tm90 lower byte rises and the count value is retained. the counter read buffer value at the retention state can be read out as the count value. cancellation of pending is performed at the cpu clock falling edge after the read signal of the tm90 higher byte falls. reset input clears tm90 to 0000h and tm90 starts freerunning. figure 6-11 shows the timing of 16-bit timer counter 90 readout. cautions 1. the count value after releasing stop becomes undefined because the count operation is executed during oscillation settling time. 2. though tm90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used. when using the 8-bit transfer instruction, execute it in direct addressing. 3. when using the 8-bit transfer instruction, execute in the order from the lower byte to the higher byte in pairs. if only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. figure 6-11. 16-bit timer counter 90 readout timing cpu clock count clock tm90 count read buffer tm90 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period remark n = 0000h to ffffh
chapter 6 16-bit timer user's manual u13600ej2v0um00 97 6.4.5 buzzer output operation the buzzer frequency is set using buzzer output control register 90 (bzc90) based on the count clock selected with tcl901 and tcl900 of tmc90 (source clock). a square wave of the set buzzer frequency is output. table 6-4 shows the buzzer frequency. set the 16-bit timer counter as follows to use it for buzzer output: set p31 to output mode (pm31 = 0). reset output latch of p31 to 0. set a count clock by using tcl901 and tcl900. set bzc90 as shown in figure 6-12. figure 6-12. settings of buzzer output control register 90 for buzzer output operation 0 0 0 0 0/1 0/1 0/1 1 bcs902 bcs901 bcs900 bzoe90 bzc90 setting of buzzer frequency (see table 6-4 ) enables buzzer output table 6-4. buzzer frequency of 16-bit timer buzzer frequency bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 4 fcl = f xt 000fcl/2 4 (78.1 khz) fcl/2 4 (4.88 khz) fcl/2 4 (19.5 khz) fcl/2 4 (2.05 khz) 001fcl/2 5 (39.1 khz) fcl/2 5 (2.44 khz) fcl/2 5 (9.77 khz) fcl/2 5 (1.02 khz) 010fcl/2 8 (4.88 khz) fcl/2 8 (305 hz) fcl/2 8 (1.22 khz) fcl/2 8 (128 hz) 011fcl/2 9 (2.44 khz) fcl/2 9 (153 hz) fcl/2 9 (610 hz) fcl/2 9 (64 hz) 100fcl/2 10 (1.22 khz) fcl/2 10 (76 hz) fcl/2 10 (305 hz) fcl/2 10 (32 hz) 101fcl/2 11 (610 hz) fcl/2 11 (38 hz) fcl/2 11 (153 hz) fcl/2 11 (16 hz) 110fcl/2 12 (305 hz) fcl/2 12 (19 hz) fcl/2 12 (76.3 hz) fcl/2 12 (8 hz) 111fcl/2 13 (153 hz) fcl/2 13 (10 hz) fcl/2 13 (38.1 hz) fcl/2 13 (4 hz) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer user's manual u13600ej2v0um00 98 6.5 notes on 16-bit timer the functions of the 16-bit timer that can be used differ depending on the selection of a count clock, operation of the cpu clock, oscillation status of the system clock, and the setting of bzoe90 (bit 0 of the buzzer output control register 90 (bzc90)). table 6-5. operating status of 16-bit timer under each condition system clock count clock cpu clock main clock subclock bzoe90 capture tm90 read buzzer output timer output timer interrupt oscillation o o note 1 note 2 oo main stop oscillation/ stop oscillation o note 2 oo f x /2 2 , f x /2 4 , f x /2 6 sub stop oscillation 1/0 0 oooo oscillation 1 ooo oscillation stop 1/0 0 oscillation 1 ooo main stop (stop mode) stop 1/0 0 oooo oscillation 1 ooo 0 f xt sub stop oscillation 1 ooo notes 1. possible only when the cpu clock is in high-speed mode 2. can be output when bzoe90 = 1 cautions 1. the capture function uses f x /2 for control (see figure 6-1). therefore, the capture function cannot be used when the main system clock is stopped. 2. the read function of tm90 uses the cpu clock for control (see figure 6-1), and reads an undefined status if the cpu clock is slower than the count clock (the value cannot be guaranteed). to read tm90, check that the count clock is the same as the cpu clock (use high-speed mode if the cpu clock is the main system clock), or select a count clock slower than the cpu clock. 3. if the subsystem clock is selected as the count clock and if bzoe90 is cleared to 0, the subsystem clock synchronized with the main system clock is selected as the count clock of tm90 (see figure 6-1). if oscillation of the main system clock is stopped at this time, therefore, the clock supplied to the 16-bit timer is stopped and thus the timer itself is stopped (the timer interrupt does not occur). if the subsystem clock is selected as the count clock and if bzoe90 is set to 1, the captured value and tm90 read value are not guaranteed because the subsystem clock is not synchronized. to use the capture and tm90 read functions, therefore, clear bzoe90 to 0 (if the subsystem clock is selected as the count clock, the buzzer output, capture, and tm90 read functions cannot be used at the same time).
chapter 6 16-bit timer user's manual u13600ej2v0um00 99 to stop oscillation of the main system clock to reduce the current consumption and release halt mode by using the timer interrupt, make the following settings: count clock : subsystem clock cpu clock : subsystem clock main system clock : stop oscillation bzoe90 : 1 (buzzer output enabled) if the setting of p31, multiplexed with the buzzer output, is "pm31 = 0, p31 = 0" at this time, the square wave of the buzzer frequency is output from p31. to disable the output of the buzzer frequency: set p31 in input mode (pm31 = 1). if p31 cannot be set in input mode, set the value of the port latch of p31 to 1 (p31 = 1). (in this case, a high level is output from p31.)
user's manual u13600ej2v0um00 100 [memo]
user's manual u13600ej2v0um00 101 chapter 7 8-bit timer/event counter 7.1 functions of 8-bit timer/event counter the 8-bit timer/event counter has the following functions: interval timer external event counter square wave output pwm output (1) 8-bit interval timer when the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals set in advance. table 7-1. interval time of 8-bit timer/event counter minimum interval time maximum interval time resolution 1/f x (200 ns) 2 8 /f x (51.2 m s) 1/f x (200 ns) 2 8 /f x (51.2 m s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 m s) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. (2) external event counter the number of pulses of an externally input signal can be counted. (3) square wave output a square wave of arbitrary frequency can be output. table 7-2. square wave output range of 8-bit timer/event counter minimum pulse width maximum pulse width resolution 1/f x (200 ns) 2 8 /f x (51.2 m s) 1/f x (200 ns) 2 8 /f x (51.2 m s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 m s) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. (4) pwm output 8-bit resolution pwm output can be produced.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 102 7.2 8-bit timer/event counter configuration the 8-bit timer/event counter consists of the following items of hardware. table 7-3. 8-bit timer/event counter configuration item configuration timer counter 8 bits 1 (tm80) register compare register: 8 bits 1 (cr80) timer output 1 (to80) control register 8-bit timer mode control register 80 (tmc80) port mode register 2 (pm2) figure 7-1. block diagram of 8-bit timer/event counter internal bus internal bus 8-bit compare register 80 (cr80) 8-bit timer counter 80 (tm80) match clear ovf r s inv q q tce80 pwme80 tcl801 tcl800 toe80 ti80/p27/ to80 f x f x /2 8 8-bit timer mode control register 80 (tmc80) p27 output latch to80/p27/ti80 pm27 inttm80 selector (1) 8-bit compare register 80 (cr80) a value specified in cr80 is compared with the count in 8-bit timer counter 80 (tm80). if they match, an interrupt request (inttm80) is issued. cr80 is set with an 8-bit memory manipulation instruction. any value from 00h to ffh can be set. reset input makes cr80 undefined. cautions 1. before rewriting cr80, stop the timer operation. if cr80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately. 2. do not clear cr80 to 00h in pwm output mode (when pwme80 = 1: bit 6 of 8-bit timer mode control register 80 (tmc80)); otherwise, pwm output may not be produced normally. (2) 8-bit timer counter 80 (tm80) tm80 is used to count the number of pulses. its contents are read with an 8-bit memory manipulation instruction. reset input clears tm80 to 00h.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 103 7.3 8-bit timer/event counter control registers the following two types of registers are used to control the 8-bit timer/event counter. ? 8-bit timer mode control register 80 (tmc80) ? port mode register 2 (pm2) (1) 8-bit timer mode control register 80 (tmc80) tmc80 determines whether to enable or disable 8-bit timer counter 80 (tm80), specifies the count clock for tm80, and controls the operation of the output control circuit of 8-bit timer/event counter. tmc80 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc80 to 00h. figure 7-2. format of 8-bit timer mode control register 80 tce80 pwme80 000 tcl801tcl800 toe80 tmc80 symbol address after reset r/w ff53h 00h r/w <6> <7> 54321<0> tcl801 0 0 1 1 8-bit timer counter 80 count clock selection tcl800 0 1 0 1 f x f x /2 8 rising edge of ti80 note falling edge of ti80 note tce80 0 1 8-bit timer counter 80 operation control operation disabled (tm80 is cleared to 0.) operation enabled pwme80 0 1 operation mode selection interval timer operation mode pwm output mode (5.0 mhz) (19.5 khz) toe80 0 1 8-bit timer/event counter output control output disabled (port mode) output enabled note when inputting a clock signal externally, timer output cannot be used. cautions 1. always stop the timer before setting tmc80. 2. for pwm mode operation, tmmk80 (bit 0 of interrupt mask flag register 1 (mk1)) must be set. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 104 (2) port mode register 2 (pm2) pm2 specifies whether each bit of port 2 is used for input or output. to use the to80/p27/ti80 pin for timer output, the pm27 and p27 output latch must be reset to 0. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 7-3. format of port mode register 2 pm27 0 1 p27 pin input/output mode selection output mode (output buffer on) input mode (output buffer off) pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 76 54 symbol address after reset r/w ff22h ffh r/w 3210
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 105 7.4 operation of 8-bit timer/event counter 7.4.1 operation as interval timer the interval timer repeatedly generates an interrupt at time intervals specified by the count value set in 8-bit compare register 80 (cr80) in advance. to operate the 8-bit timer/event counter as an interval timer, the settings are required in the following sequence. <1> disable the operation of the 8-bit timer counter 80 (tm80) (tce80 (bit 7 of the 8-bit timer mode control register 80 (tmc80)) = 0). <2> set the count clock of the 8-bit timer/event counter (see table 7-4 ). <3> set a count value in cr80. <4> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, tm80 is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttm80) is generated. table 7-4 shows interval time, and figure 7-4 shows the timing of interval timer operation. cautions 1. stop the timer operation before rewriting cr80. if cr80 is rewritten while timer operation is enabled, a coincidence signal may be generated on the spot (an interrupt request will be generated if the interrupt is enabled). 2. if setting of the count clock to tmc80 and enabling the operation of tm80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. to use the 8-bit timer/event counter as an interval timer, therefore, perform the setting in the above sequence. table 7-4. interval time of 8-bit timer/event counter tcl801 tcl800 minimum interval time maximum interval time resolution 001/f x (200 ns) 2 8 /f x (51.2 m s) 1/f x (200 ns) 012 8 /f x (51.2 m s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 m s) 1 0 ti80 input cycle 2 8 ti80 input cycle ti80 i nput edge cycle 1 1 ti80 input cycle 2 8 ti80 input cycle ti80 i nput edge cycle remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 106 figure 7-4. interval timer operation timing clear clear interrupt accept interrupt accept count start interval time interval time interval time count clock tm80 count value cr80 tce80 inttm80 to80 n 01h 00h n 01h 00h n 00h 01h nn nn t remark interval time = (n + 1) t n = 00h to ffh
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 107 7.4.2 operation as external event counter the external event counter counts the number of external clock pulses input to the ti80/p27/to80 pin by using 8-bit timer counter 80 (tm80). to operate the 8-bit timer/event counter as an external event counter, the settings are required in the following sequence. <1> set p27 to input mode (pm27 = 1). <2> disable the operation of the 8-bit timer counter 80 (tm80) (tce80 (bit 7 of the 8-bit timer mode control register 80 (tmc80)) = 0). <3> specify the rising or falling edge of ti80 (see table 7-4 ). disable output of to80 (toe80 (bit 0 of tmc80) = 0) and pwm output (pwme80 (bit 6 of tmc80) = 0). <4> set a count value in cr80. <5> enable the operation of tm80 (tce80 = 1). each time the valid edge specified by bit 1 (tcl800) of tmc80 is input, the value of 8-bit timer counter 80 (tm80) is incremented. when the count value of tm80 matches the value set in cr80, tm80 is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttm80) is generated. figure 7-5 shows the timing of the external event counter operation (with rising edge specified). cautions 1. before rewriting cr80, stop the timer operation. if cr80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately. 2. if setting of the count clock to tmc80 and enabling the operation of tm80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. to use the 8-bit timer/event counter as an external event counter, therefore, perform the setting in the above sequence. figure 7-5. external event counter operation timing (with rising edge specified) ti80 pin input tm80 count value cr80 tce80 inttm80 00h 01h 02h 03h 04h 05h n ?1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 108 7.4.3 operation as square wave output the 8-bit timer/event counter can generate output square waves of an arbitrary frequency at intervals specified by the count value set in 8-bit compare register 80 (cr80) in advance. to operate 8-bit timer/event counter 80 for square wave output, the settings are required in the following sequence. <1> set p27 to output mode (pm27 = 0). set 0 for the output latch of p27. <2> disable the operation of 8-bit timer counter 80 (tm80) (tce80 = 0). <3> set a count clock for 8-bit timer/event counter (see table 7-5 ), enable output of to80 (toe80 = 1), and disable pwm output (pwme80 = 0). <4> set a count value in cr80. <5> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, the to80 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tm80 will be cleared to 0 and resumes to count, generating an interrupt request signal (inttm80). setting 0 for bit 7 (tce80) of tmc80 clears the square-wave output to 0. table 7-5 shows square wave output range, and figure 7-6 shows timing of square wave output. cautions 1. before rewriting cr80, stop the timer operation. if cr80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately. 2. if setting of the count clock to tmc80 and enabling the operation of tm80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. to use the 8-bit timer/event counter as a square wave output, therefore, perform the setting in the above sequence. table 7-5. square wave output range of 8-bit timer/event counter tcl801 tcl800 minimum pulse width maximum pulse width resolution 001/f x (200 ns) 2 8 /f x (51.2 m s) 1/f x (200 ns) 012 8 /f x (51.2 m s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 m s) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 109 figure 7-6. square wave output timing clear clear interrupt accept interrupt accept count start count clock tm80 count value cr80 tce80 inttm80 to80 note n 01h 00h n 01h 00h n 00h 01h nn nn note the initial value of to80 is low for output enable (toe80 = 1).
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 110 7.4.4 pwm output operation pwm output enables an interrupt to be generated repeatedly at intervals specified by the count value set in 8-bit compare register 80 (cr80) in advance. to use the 8-bit timer/event counter for pwm output, the following settings are required. <1> set p27 to output mode (pm27 = 0). set 0 for the output latch of p27. <2> disable the operation of 8-bit timer counter 80 (tm80) (tce80 = 0). <3> set a count clock for 8-bit timer/event counter (see table 7-4 ), and enable output of to80 (toe80 = 1) and pwm output (pwme80 = 1). <4> set a count value in cr80. <5> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, tm80 continues counting, and an interrupt request signal (inttm80) is generated. cautions 1. if cr80 is rewritten during timer operation, the pulse of the first cycle may not be generated immediately after cr80 has been rewritten. 2. if setting of the count clock to tmc80 and enabling the operation of tm80 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. to use the 8-bit timer/event counter as a pwm output, therefore, perform the setting in the above sequence. figure 7-7. pwm output timing mn n = 01h to ffh, m = 01h to ffh count clock 00h 01h ?? m ?? ffh 00h 01h 02h ?? n n + 1 n + 2 ?? ffh 00h 01h ?? n ?? ? tm80 cr80 ovf tce80 inttm80 to80 note note the initial value of to80 is low for output enable (toe80 = 1). caution do not set cr80 to 00h in pwm output mode. otherwise, pwm may not be output normally.
chapter 7 8-bit timer/event counter user's manual u13600ej2v0um00 111 7.5 notes on using 8-bit timer/event counter (1) error on starting timer an error of up to 1 clock is included in the time between the timer being started and a coincidence signal being generated. this is because 8-bit timer counter 80 (tm80) is started asynchronously to the count pulse. figure 7-8. start timing of 8-bit timer counter 80 count pulse tm80 count value timer start 00h 01h 02h 03h 04h (2) setting of 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter. figure 7-9. external event counter operation timing tl80 input cr80 00h tm80 count value 00h 00h 00h 00h interrupt request flag cautions 1. before rewriting cr80 in timer counter operation mode (pwme80 (bit 6 of the 8-bit timer mode control register 80 (tmc80) = 0), stop the timer operation. if cr80 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated immediately. 2. if cr80 is rewritten during timer operation in the pwm output operation mode (pwme80 = 1), an illegal pulse may be generated. to rewrite cr80, therefore, stop the timer operation. 3. do not set cr80 to 00h in pwm operation mode (when pwme80 = 1: bit 6 of 8-bit timer mode control register 80 (tmc80)); otherwise, pwm may not be output normally.
user's manual u13600ej2v0um00 112 [memo]
user's manual u13600ej2v0um00 113 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions: watch timer interval timer the watch and interval timers can be used at the same time. figure 8-1 is a block diagram of the watch timer. figure 8-1. block diagram of watch timer f x f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 0 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector
chapter 8 watch timer user's manual u13600ej2v0um00 114 (1) watch timer the 4.19-mhz main system clock or 32.768-khz subsystem clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5- second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwti) at specified intervals. table 8-1. interval generated using interval timer interval at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 2 4 1/f w 409.6 m s 489 m s 488 m s 2 5 1/f w 819.2 m s 978 m s 977 m s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 8.2 watch timer configuration the watch timer consists of the following items of hardware. table 8-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 8 watch timer user's manual u13600ej2v0um00 115 8.3 watch timer control register the watch timer mode control register (wtm) is used to control the watch timer. ? watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specifies whether to enable operation of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2. format of watch timer mode control register watch timer count clock selection wtm7 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w 2 5 /f w 2 6 /f w 2 7 /f w 2 8 /f w 2 9 /f w wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other than above f x /2 7 f xt (39.1 khz) (32.768 khz) not to be set wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm 76 54 symbol address after reset r/w ff4ah 00h r/w 3210 0 1 remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 8 watch timer user's manual u13600ej2v0um00 116 8.4 watch timer operation 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. the watch timer is used to generate an interrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch timer mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. only the watch timer can be started form zero seconds by clearing wtm1 to 0 when the interval timer and watch timer operate at the same time. in this case, however, an error of up to 2 9 1/f w seconds may occur in the overflow (intwt) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0. 8.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval specified by a count value set in advance. the interval can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 8-3. interval generated using interval timer wtm6 wtm5 wtm4 interval at f x = 5.0 mhz at f xt = 32.768 khz 0002 4 1/f w 409.6 m s 488 m s 0012 5 1/f w 819.2 m s 977 m s 0102 6 1/f w 1.64 ms 1.95 ms 0112 7 1/f w 3.28 ms 3.91 ms 1002 8 1/f w 6.55 ms 7.81 ms 1012 9 1/f w 13.1 ms 15.6 ms other than above not to be set remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency (f x /2 7 or f xt )
chapter 8 watch timer user's manual u13600ej2v0um00 117 figure 8-3. watch timer/interval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz.
user's manual u13600ej2v0um00 118 [memo]
user's manual u13600ej2v0um00 119 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions: watchdog timer interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect inadvertent program loops. when an inadvertent loop is detected, a non-maskable interrupt or a reset signal can be generated. table 9-1. inadvertent loop detection time of watchdog timer inadvertent loop detection time at f x = 5.0 mhz 2 11 1/f x 410 m s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary interval set in advance. table 9-2. interval time interval at f x = 5.0 mhz 2 11 1/f x 410 m s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer user's manual u13600ej2v0um00 120 9.2 watchdog timer configuration the watchdog timer consists of the following items of hardware. table 9-3. configuration of watchdog timer item configuration control register timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) figure 9-1. block diagram of watchdog timer internal bus internal bus prescaler selector control circuit f x 2 6 f x 2 8 f x 2 10 3 7-bit counter clear tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4 run
chapter 9 watchdog timer user's manual u13600ej2v0um00 121 9.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? timer clock selection register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock selection register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. figure 9-2. format of timer clock selection register 2 tcl22 0 0 1 1 tcl21 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) tcl20 0 0 0 0 not to be set other than above watchdog timer count clock selection 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x (410 s) (1.64 ms) (6.55 ms) (26.2 ms) interval m 0 0 0 0 0 tcl22 tcl21 tcl20 tcl2 76 54 symbol address after reset r/w ff42h 00h r/w 3210 remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 9 watchdog timer user's manual u13600ej2v0um00 122 (2) watchdog timer mode register (wdtm) this register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 9-3. format of watchdog timer mode register run 0 1 watchdog timer operation selection note 1 stops counting. clears counter and starts counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (generates a maskable interrupt upon overflow occurrence.) note 3 watchdog timer mode 1 (generates a non-maskable interrupt upon overflow occurrence.) watchdog timer mode 2 (starts reset operation upon overflow occurrence.) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set to 1, it cannot be cleared to 0 by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 3. the watchdog timer starts operations as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock selection register 2 (tcl2). 2. to set watchdog timer mode 1 or 2, set tmmk4 (bit 0 of interrupt mask flag register 0 (mk0)) to 1 after confirming tmif4 (bit 0 of interrupt request flag register 0 (if0)) being set to 0. when watchdog timer mode 1 or 2 is selected with tmif4 set to 1, a non- maskable interrupt is generated upon the completion of rewriting wdtm.
chapter 9 watchdog timer user's manual u13600ej2v0um00 123 9.4 watchdog timer operation 9.4.1 operation as watchdog timer the watchdog timer detects an inadvertent program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (tcl20 to tcl22) of timer clock selection register 2 (tcl2). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not set to 1, and the inadvertent loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before executing the stop instruction. cautions 1. the actual inadvertent loop detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as the cpu clock, watchdog timer count operation is stopped. table 9-4. inadvertent loop detection time of watchdog timer tcl22 tcl21 tcl20 inadvertent loop detection time at f x = 5.0 mhz 0002 11 1/f x 410 m s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer user's manual u13600ej2v0um00 124 9.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. select a count clock (or interval) by setting bits 0 to 2 (tcl20 to tcl22) of timer clock selection register 2 (tcl2). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (tmmk4) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before executing the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set, unless a reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 9-5. interval generated using interval timer tcl22 tcl21 tcl20 interval at f x = 5.0 mhz 0002 11 1/f x 410 m s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency
user's manual u13600ej2v0um00 125 chapter 10 serial interface 20 10.1 serial interface 20 functions serial interface 20 has the following three modes. operation stop mode asynchronous serial interface (uart) mode 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains a uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud rates by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmission and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75x/xl, 78k, and 17k series devices. 10.2 serial interface 20 configuration serial interface 20 consists of the following items of hardware. table 10-1. configuration of serial interface 20 item configuration register transmission shift register 20 (txs20) reception shift register 20 (rxs20) reception buffer register 20 (rxb20) control register serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20)
chapter 10 serial interface 20 user's manual u13600ej2v0um00 126 internal bus reception buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) reception shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmission shift register 20 (txs20) transmission shift clock selector csie20 dap20 data phase control reception shift clock si20/p22/ rxd20 so20/p21/ txd20 4 parity operation stop bit addition reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection csie20 csck20 sck20/p20/ asck20 ss20/p23 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 10-1. block diagram of serial interface 20 note see figure 10-2 for the configuration of the baud rate generator. port mode register (pm21)
chapter 10 serial interface 20 user's manual u13600ej2v0um00 127 reception detection clock transmission shift clock reception shift clock reception detected txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmission clock counter reception clock counter 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 sck20/asck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus figure 10-2. block diagram of baud rate generator 20
chapter 10 serial interface 20 user's manual u13600ej2v0um00 128 (1) transmission shift register 20 (txs20) txs20 is a register in which transmission data is prepared. the transmission data is output from txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmission data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory manipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and reception buffer register 20 (rxb20) are mapped at the same address, such that any attempt to read from txs20 results in a value being read from rxb20. (2) reception shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the reception data to reception buffer register 20 (rxb20). rxs20 cannot be manipulated directly by a program. (3) reception buffer register 20 (rxb20) rxb20 holds a reception data. a new reception data is transferred from reception shift register 20 (rxs20) every 1-byte data reception. when the data length is seven bits, the reception data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipulation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmission shift register 20 (txs20) are mapped at the same address, such that any attempt to write to rxb20 results in a value being written to txs20. (4) transmission control circuit the transmission control circuit controls transmission. for example, it adds start, parity, and stop bits to the data in transmission shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) reception control circuit the reception control circuit controls reception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during reception. if an error is detected, asynchronous serial interface status register 20 (asis20) is set according to the status of the error.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 129 10.3 serial interface 20 control registers serial interface 20 is controlled by the following registers. serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20) (1) serial operation mode register 20 (csim20) csim20 is set when serial interface 20 is used in 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. figure 10-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state. clock is high active, and sck20 is at low level in the idle state. cautions 1. bits 4 and 5 must all be set to 0. 2. csim20 must be cleared to 00h, if uart mode is selected.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 130 (2) asynchronous serial interface mode register 20 (asim20) asim20 is set when serial interface 20 is used in asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. figure 10-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must all be set to 0. 2. if 3-wire serial i/o mode is selected, asim20 must be cleared to 00h. 3. switch operating modes after halting serial transmit/receive operation.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 131 table 10-2. serial interface 20 operating mode settings (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 00 0 note 1 note 1 note 1 note 1 note 1 note 1 -- p22 p21 p20 other than above not to be set (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 01 external clock sck20 input 10 101 msb internal clock sck20 output 01 external clock sck20 input 00 11 1 note 2 note 2 01 01 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above not to be set (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 1 external clock asck20 input 10 0 0 0 note 1 note 1 01 note 1 note 1 internal clock p22 txd20 (cmos output) p20 1 external clock asck20 input 01 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p21 p20 1 external clock asck20 input 11 0 0 0 1 01 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p20 other than above not to be set notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p22 (cmos input/output). remark : don't care.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 132 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. asis20 is read with a 1-bit or 8-bit memory manipulation instruction. the contents of asis20 are undefined in 3-wire serial i/o mode. reset input clears asis20 to 00h. figure 10-5. format of asynchronous serial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 no parity error has occurred. a parity error has occurred (parity mismatch in transmission data). fe20 0 1 flaming error flag no framing error has occurred. a framing error has occurred (no stop bit detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (before data was read from the reception buffer register, the subsequent receive operation was completed.) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error is generated.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 133 (4) baud rate generator control register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. figure 10-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 3-bit counter source clock selection tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to the asck20 pin note not to be set (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 - note an external clock can be used only in uart mode. cautions 1. when writing to brgc20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during communication operations. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set p20 to input mode (pm20 (bit 0 of port mode register 2 (pm2)) = 1). remarks 1. f x : main system clock oscillation frequency 2. n : value determined by setting tps200 through tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 134 the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the asck20 pin. (a) generation of baud rate transmit/receive clock form system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [hz] f x : system clock oscillation frequency n : value determined by values of tps200 through tps203 as shown in figure 10-6 (2 n 8) table 10-3. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 10 serial interface 20 user's manual u13600ej2v0um00 135 (b) generation of baud rate transmit/receive clock from external clock input from asck20 pin the transmit/receive clock is generated by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clock input from the asck20 pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input from the asck20 pin table 10-4. relationships between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 10 serial interface 20 user's manual u13600ej2v0um00 136 10.4 serial interface 20 operation serial interface 20 provides the following three types of modes. operation stop mode asynchronous serial interface (uart) mode 3-wire serial i/o mode 10.4.1 operation stop mode in operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. the p20/sck20/asck20, p21/so20/txd20, and p22/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control operation disabled operation enabled csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 4 and 5 must all be set to 0. (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must all be set to 0.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 137 10.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. this device incorporates a uart-dedicated baud rate generator that enables communications at a desired baud rate from many options. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), asynchronous serial interface status register 20 (asis20), and baud rate generator control register 20 (brgc20).
chapter 10 serial interface 20 user's manual u13600ej2v0um00 138 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. set csim20 to 00h when uart mode is selected. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is high level in the idle state. clock is high active, and sck20 is low level in the idle state. caution bits 4 and 5 must all be set to 0.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 139 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception. (no parity error is generated.) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must all be set to 0. 2. switch operating modes after halting serial transmit/receive operation.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 140 (c) asynchronous serial interface status register 20 (asis20) asis20 is read with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis20 to 00h. pe20 0 1 parity error flag parity error not generated parity error generated (when the parity of transmit data does not match) framing error not generated framing error generated (when stop bit is not detected) note 1 overrun error not generated overrun error generated note 2 (when the next receive operation is completed before the data is read from the reception buffer register) fe20 0 1 0 1 flaming error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3210 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error is generated.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 141 (d) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 - not to be set 3-bit counter source clock selection external clock input to asck20 pin other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 cautions 1. when writing to brgc20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during communication operation. 2. be sure not to select n = 1 during an operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n : value determined by setting tps200 through tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the asck20 pin. (i) generation of baud rate transmit/receive clock from system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n : value determined by setting tps200 through tps203 as shown in the above table (2 n 8) f x 2 n + 1 8
chapter 10 serial interface 20 user's manual u13600ej2v0um00 142 table 10-5. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. (ii) generation of baud rate transmit/receive clock from external clock input from asck20 pin the transmit/receive clock is generated by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clock input from the asck20 pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input from the asck20 pin table 10-6. relationships between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 10 serial interface 20 user's manual u13600ej2v0um00 143 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 10-7. one data frame consists of a start bit, character bits, parity bit, and stop bit(s). the specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (asim20). figure 10-7. asynchronous serial interface transmit/receive data format d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame start bits ................... 1 bit character bits............ 7 bits/8 bits parity bits .................. even parity/odd parity/0 parity/no parity stop bit(s).................. 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". the serial transfer rate is selected by asim20 and baud rate generator control register 20 (brgc20). if a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (asis20).
chapter 10 serial interface 20 user's manual u13600ej2v0um00 144 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity at transmission the parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit may be even. the parity bit value should be as follows. the number of bits with a value of "1" is an odd number in transmit data : 1 the number of bits with a value of "1" is an even number in transmit data : 0 at reception the number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is odd, a parity error is generated. (ii) odd parity at transmission conversely to the even parity, the parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit may be odd. the parity bit value should be as follows. the number of bits with a value of "1" is an odd number in transmit data : 0 the number of bits with a value of "1" is an even number in transmit data : 1 at reception the number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to "0" irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1". (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error is not generated.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 145 (c) transmission a transmit operation is started by writing transmit data to transmission shift register 20 (txs20). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interrupt (intst20) is generated. figure 10-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite to asynchronous serial interface mode register 20 (asim20) during a transmit operation. if the asim20 register is rewritten to during transmission, subsequent transmission may not be performed (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 146 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set to 1, a receive operation is enabled and sampling of the rxd20 pin input is performed. rxd20 pin input sampling is performed using the serial clock specified by asim20. when the rxd20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to reception buffer register 20 (rxb20), and a reception completion interrupt (intsr20) is generated. if an error is generated, the receive data in which the error was generated is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset to 0 during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr20 is not generated. figure 10-9. asynchronous serial interface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read reception buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 147 (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, and overrun error. after data reception, an error flag is set in asynchronous serial interface status register 20 (asis20). receive error causes are shown in table 10-7. it is possible to determine what kind of error was generated during reception by reading the contents of asis20 in the reception error interrupt servicing (see figures 10-9 and 10-10 ). the contents of asis20 are reset to 0 by reading reception buffer register 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 10-7. receive error causes receive errors cause parity error transmission-time parity and reception data parity do not match. framing error stop bit not detected overrun error reception of next data is completed before data is read from reception buffer register. figure 10-10. receive error timing (a) parity error generated stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error generated stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register are reset to 0 by reading reception buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read reception buffer register 20 (rxb20) even if a receive error is generated. if rxb20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 148 (3) cautions related to uart mode (a) when bit 7 (txe20) of asynchronous serial interface mode register 20 (asim20) is cleared during transmission, be sure to set transmission shift register 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is cleared during reception, reception buffer register 20 (rxb20) and the receive completion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at a time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <3> , rxb20 renews the data and intsr20 is generated.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 149 10.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75xl series, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed using serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), and baud rate generator control register 20 (brgc20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state. clock is high active, and sck20 is at low level in the idle state. caution bits 4 and 5 must all be set to 0.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 150 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. when 3-wire serial i/o mode is selected, asim20 must be set to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception. (no parity error is generated.) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must all be set to 0. 2. switch operating modes after halting serial transmit/receive operation.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 151 (c) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 not to be set 3-bit counter source clock selection other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 cautions 1. when writing to brgc20 is performed during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during communication operation. 2. be sure not to select n = 1 during an operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n : value determined by setting tps200 through tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. if the internal clock is used as the serial clock for 3-wire serial i/o mode, set bits tps200 to tps203 to set the frequency of the serial clock. to obtain the frequency to be set, use the following expression. when an external serial clock is used, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n : value determined by setting tps200 through tps203 as shown in the above table (1 n 8) f x 2 n + 1
chapter 10 serial interface 20 user's manual u13600ej2v0um00 152 (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in synchronization with the serial clock. transmission shift register 20 (txs20/sio20) and reception shift register 20 (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si20 pin is latched in reception buffer register 20 (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/sio20 and rxs20 stops automatically, and the interrupt request signal (intcsi20) is generated. figure 10-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 153 figure 10-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 154 figure 10-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 155 figure 10-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 10 serial interface 20 user's manual u13600ej2v0um00 156 figure 10-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 157 figure 10-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 do4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 do4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 10 serial interface 20 user's manual u13600ej2v0um00 158 figure 10-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmission shift register (txs20/sio20) when the following two conditions are satisfied. serial operation mode register 20 (csim20) bit 7 (csie20) = 1 internal serial clock is stopped or sck20 is high after 8-bit serial transfer. caution if csie20 is set to "1" after data is written to txs20/sio20, transfer does not start. a termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (intcsi20).
user's manual u13600ej2v0um00 159 chapter 11 interrupt functions 11.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even if interrupts are disabled. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. the non-maskable interrupt has one source of interrupt from the watchdog timer. (2) maskable interrupt these interrupts undergo mask control. if two or more interrupts are simultaneously generated, each interrupt has a predetermined priority as shown in table 11-1. a standby release signal is generated. the maskable interrupt has four sources of external interrupts and seven sources of internal interrupts. 11.2 interrupt sources and configuration there are total of 12 non-maskable and maskable interrupts in the interrupt sources (see table 11-1 ).
chapter 11 interrupt functions user's manual u13600ej2v0um00 160 table 11-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/external vector table address basic configuration type note 2 non-maskable interrupt - intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) (a) 0 intwdt watchdog timer overflow (when interval timer mode is selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3intp2 pin input edge detection external 000ah (c) intsr20 end of uart reception on serial interface 20 4 intcsi20 end of three-wire sio transfer reception on serial interface 20 000ch 5 intst20 end of uart transmission on serial interface 20 000eh 6 intwt watch timer interrupt 0010h 7 intwti interval timer interrupt 0012h 8 inttm80 generation of match signal for 8-bit timer/event counter 80 0014h 9 inttm90 generation of match signal for 16-bit timer 90 internal 0016h (b) maskable interrupt 10 intkr00 key return signal detection external 0018h (c) notes 1. the priority regulates which maskable interrupt is higher, when two or more maskable interrupts are requested simultaneously. zero signifies the highest priority, while 10 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 11-1, respectively.
chapter 11 interrupt functions user's manual u13600ej2v0um00 161 figure 11-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, krm00 interrupt request edge detector vector table address generator standby release signal intm0 : external interrupt mode register 0 krm00 : key return mode register 00 if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag
chapter 11 interrupt functions user's manual u13600ej2v0um00 162 11.3 interrupt function control registers the interrupt functions are controlled by the following five registers: ? interrupt request flag registers 0 and 1 (if0 and if1) ? interrupt mask flag registers 0 and 1 (mk0 and mk1) ? external interrupt mode register 0 (intm0) ? program status word (psw) ? key return mode register 00 (krm00) table 11-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. table 11-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intsr20/intcsi20 intst20 intwt intwti inttm80 inttm90 intkr00 tmif4 pif0 pif1 pif2 srif20 stif20 wtif wtiif tmif80 tmif90 krif00 tmmk4 pmk0 pmk1 pmk2 srmk20 stmk20 wtmk wtimk tmmk80 tmmk90 krmk00
chapter 11 interrupt functions user's manual u13600ej2v0um00 163 (1) interrupt request flag registers 0 and 1 (if0 and if1) an interrupt request flag is set to 1, when the corresponding interrupt request is issued, or when the related instruction is executed. it is cleared to 0, when the interrupt request is accepted, when a reset signal is input, or when a related instruction is executed. if0 and if1 are set with a 1-bit or 8-bit memory manipulation instruction. reset input clears if0 and if1 to 00h. figure 11-2. format of interrupt request flag register 00000 krif00 tmif90 tmif80 if1 ffe1h 00h r/w if 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request has been made. 6 7 5 4 3 <2> <1> <0> wtiif wtif stif20srif20 pif2 pif1 pif0 tmif4 if0 symbol address after reset r/w ffe0h 00h r/w <6> <7> <5> <4> <3> <2> <1> <0> cautions 1. bits 3 to 7 of if1 must all be set to 0. 2. the tmif4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 3. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
chapter 11 interrupt functions user's manual u13600ej2v0um00 164 (2) interrupt mask flag registers 0 and 1 (mk0 and mk1) the interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 and mk1 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 11-3. format of interrupt mask flag register 1 1 1 1 1 krmk00 tmmk90 tmmk80 mk1 ffe5h ffh r/w mk 0 1 interrupt handling control enable interrupt handling. disable interrupt handling. 6 7 5 4 3 <2> <1> <0> wtimk stmk20 wtmk srmk20 pmk2 pmk1 pmk0 tmmk4 mk0 symbol address after reset r/w ffe4h ffh r/w <6> <7> <5> <4> <3> <2> <1> <0> cautions 1. bits 3 to 7 of mk1 must all be set to 1. 2. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read tmmk4 flag results in an undefined value being detected. 3. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
chapter 11 interrupt functions user's manual u13600ej2v0um00 165 (3) external interrupt mode register 0 (intm0) intm0 is used to specify an effective edge for intp0 to intp2. intm0 is set with an 8-bit memory manipulation instruction. reset input clears intm0 to 00h. figure 11-4. format of external interrupt mode register 0 es21 es20 es11 es10 es01 es00 0 0 intm0 76543210 es11 0 0 1 1 intp1 effective edge selection es10 0 1 0 1 falling edge rising edge not to be set both rising and falling edges es21 0 0 1 1 intp2 effective edge selection es20 0 1 0 1 falling edge rising edge not to be set both rising and falling edges es01 0 0 1 1 intp0 effective edge selection es00 0 1 0 1 falling edge rising edge not to be set both rising and falling edges symbol address after reset r/w ffech 00h r/w cautions 1. bits 0 and 1 must all be set to 0. 2. before setting intm0, set the corresponding interrupt mask flag to 1 to disable interrupts. to enable interrupts, clear to 0 the corresponding interrupt request flag, then the corresponding interrupt mask flag.
chapter 11 interrupt functions user's manual u13600ej2v0um00 166 (4) program status word (psw) the program status word is used to hold the instruction execution result and the current status of the interrupt requests. the ie flag, used to enable and disable maskable interrupts, is mapped to psw. psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is accepted, psw is automatically saved to a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 11-5. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disable enable whether to enable/disable interrupt acceptance used in the execution of ordinary instructions
chapter 11 interrupt functions user's manual u13600ej2v0um00 167 (5) key return mode register 00 (krm00) krm00 is used to specify pins for which the key return signals are detected. krm00 is set with a 1-bit or 8-bit memory manipulation instruction. bit 0 (krm000) specifies whether the detection is performed for four pins from kr00/p40 to kr03/p43 together. bits 4 to 7 (krm004 to krm007) specify whether the detection is performed for the kr04/p44 to kr07/p47 pins individually. reset input clears krm00 to 00h. figure 11-6. format of key return mode register 00 krm007 krm006 krm005 krm004 0 0 0 krm000 krm00 symbol address fff5h after reset 00h r/w r/w 76543210 krm00n 0 1 not detected detected (falling edges of port 4) key return signal detection selection cautions 1. bits 1 to 3 must all be set to 0. 2. when a bit of krm00 is set to 1, the pull-up resistor is forcibly connected to the corresponding pin. if the pin is set to output mode, however, the pull-up resistor is left disconnected. 3. before setting krm00, set bit 2 of mk1 to 1 (krmk00 = 1) to disable interrupts. after krm00 is set, clear bit 2 of if1 (krif = 0), then clear krmk00 (krmk00 = 0) to enable interrupts. remark n = 0, 4 to 7 figure 11-7. block diagram of falling edge detection circuit falling edge detection circuit krmk00 p40/kr00 p41/kr01 p42/kr02 p43/kr03 p44/kr04 p45/kr05 p46/kr06 p47/kr07 note key return mode register 00 (krm00) krif00 setting signal standby release signal selector note this selector selects pins to be used for falling-edge inputs.
chapter 11 interrupt functions user's manual u13600ej2v0um00 168 11.4 interrupt processing operation 11.4.1 non-maskable interrupt request acceptance operation the non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector table are loaded to the pc, and then program execution branches. figure 11-8 shows the flowchart from non-maskable interrupt request generation to acceptance. figure 11-9 shows the timing of non-maskable interrupt request acceptance. figure 11-10 shows the acceptance operation if multiple non-maskable interrupts are generated. caution during a non-maskable interrupt service program execution, do not input another non- maskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged.
chapter 11 interrupt functions user's manual u13600ej2v0um00 169 figure 11-8. flowchart from non-maskable interrupt request generation to acceptance start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt processing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm : watchdog timer mode register wdt : watchdog timer figure 11-9. timing of non-maskable interrupt request acceptance instruction instruction saving psw and pc, and jump to interrupt processing interrupt processing program cpu processing tmif4 figure 11-10. accepting non-maskable interrupt request second interrupt processing first interrupt processing nmi request (second) nmi request (first) main routine
chapter 11 interrupt functions user's manual u13600ej2v0um00 170 11.4.2 maskable interrupt request acceptance operation a maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vectored interrupt request is accepted in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt processing after a maskable interrupt request has been generated is shown in table 11-3. see figures 11-11 and 11-12 for the interrupt request acceptance timing. table 11-3. time from generation of maskable interrupt request to processing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immediately before bt and bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generated at the same time, they are accepted starting from the interrupt request assigned the highest priority. a pending interrupt is accepted when the status where it can be accepted is set. figure 11-11 shows the algorithm of accepting interrupt requests. when a maskable interrupt request is accepted, the contents of psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt processing, use the reti instruction. 1 f cpu
chapter 11 interrupt functions user's manual u13600ej2v0um00 171 figure 11-11. interrupt request acceptance processing algorithm start if = 1 ? mk = 0 ? ie = 1 ? vectored interrupt processing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if : interrupt request flag mk : interrupt mask flag ie : flag to control maskable interrupt request acceptance (1 = enable, 0 = disable)
chapter 11 interrupt functions user's manual u13600ej2v0um00 172 figure 11-12. interrupt request acceptance timing (example of mov a,r) clock cpu interrupt mov a,r saving psw and pc, jump to interrupt processing 8 clocks interrupt processing program if an interrupt request flag ( if) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is accepted after the instruction under execution completes. figure 11-12 shows an example of the interrupt request acceptance timing for an 8-bit data transfer instruction mov a,r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is performed after the mov a,r instruction is completed. figure 11-13. interrupt request acceptance timing (when interrupt request flag is set at the last clock during instruction execution) saving psw and pc, jump to interrupt processing 8 clocks interrupt processing program clock cpu interrupt nop mov a,r if an interrupt request flag ( if) is set at the last clock of the instruction, the interrupt acceptance processing starts after the next instruction is executed. figure 11-13 shows an example of the interrupt acceptance timing for an interrupt request flag that is set at the second clock of nop (2-clock instruction). in this case, the mov a,r instruction after the nop instruction is executed, and then the interrupt acceptance processing is performed. caution interrupt requests are reserved while interrupt request flag register 0 or 1 (if0 or if1) or interrupt mask flag register 0 or 1 (mk0 or mk1) is being accessed. 11.4.3 multiplexed interrupt processing multiplexed interrupt processing in which another interrupt is accepted while an interrupt is processed can be processed by priority. when two or more interrupts are generated at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (see table 11-1 ).
chapter 11 interrupt functions user's manual u13600ej2v0um00 173 figure 11-14. example of multiple interrupt example 1. a multiple interrupt is accepted intyy ei main processing ei intyy processing intxx processing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request intyy is accepted, and a multiple interrupt is generated. an ei instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is set. example 2. a multiple interrupt is not generated because interrupts are not enabled intyy ei main processing reti intyy processing intxx processing ie = 0 intxx reti intyy is kept pending ie = 0 because interrupts are not enabled in interrupt intxx processing (an ei instruction is not issued), interrupt request intyy is not accepted, and a multiple interrupt is not generated. the intyy request is reserved and accepted after the intxx processing is performed. ie = 0: interrupt request acceptance disabled
chapter 11 interrupt functions user's manual u13600ej2v0um00 174 11.4.4 interrupt request reserve some instructions may reserve the acceptance of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. the following shows such instructions (interrupt request reserve instruction). manipulation instruction for interrupt request flag registers 0 and 1 (if0 and if1) manipulation instruction for interrupt mask flag registers 0 and 1 (mk0 and mk1)
user's manual u13600ej2v0um00 175 chapter 12 standby function 12.1 standby function and configuration 12.1.1 standby function the standby function is to reduce the power dissipation of the system and can be effected in the following two modes: (1) halt mode this mode is set when the halt instruction is executed. halt mode stops the operation clock of the cpu. the system clock oscillation circuit continues oscillating. this mode does not reduce the current drain as much as stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is executed. stop mode stops the main system clock oscillation circuit and stops the entire system. the current drain of the cpu can be substantially reduced in this mode. the low voltage (v dd = 1.8 v min.) of the data memory can be retained. therefore, this mode is useful for retaining the contents of the data memory at an extremely low current drain. stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscillation circuit settles after stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all retained. in addition, the statuses of the output latch of the i/o ports and output buffer are also retained. caution to set stop mode, be sure to stop the operations of the peripheral hardware, and then execute the stop instruction.
chapter 12 standby function user's manual u13600ej2v0um00 176 12.1.2 standby function control register the wait time after stop mode is released upon interrupt request until the oscillation settles is controlled with the oscillation settling time selection register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, the oscillation settling time after reset input is 2 15 /f x , instead of 2 17 /f x . figure 12-1. format of oscillation settling time selection register osts2 0 0 1 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 not to be set oscillation settling time selection other than above m 00 0 0 osts1 osts2 0 osts0 osts 7 654 32 10 symbol address after reset r/w fffah 04h r/w caution the wait time after stop mode is released does not include the time from stop mode release to clock oscillation start ("a" in the figure below), regardless of release by reset input or by interrupt generation. v ss0 , v ss1 a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 12 standby function user's manual u13600ej2v0um00 177 12.2 operation of standby function 12.2.1 halt mode (1) halt mode halt mode is set by executing the halt instruction. the operation status in halt mode is shown in the following table. table 12-1. operation statuses in halt mode halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is r unning item while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running main system clock generation circuit oscillation enabled oscillation disabled cpu operation disabled port (output latch) remains in the state existing before the selection of halt mode 16-bit timer counter operation enabled operation enabled note 1 operation enabled operation enabled note 2 8-bit timer/event counter operation enabled operation enabled note 3 watch timer operation enabled operation enabled note 1 operation enabled operation enabled note 2 watchdog timer operation enabled operation disabled serial interface operation enabled operation enabled note 4 external interrupt operation enabled note 5 notes 1. operation is enabled while the main system clock is selected. 2. operation is enabled while the subsystem clock is selected. 3. operation is enabled only when ti80 is selected as the count clock. 4. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 5. maskable interrupt that is not masked
chapter 12 standby function user's manual u13600ej2v0um00 178 (2) releasing halt mode halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request halt mode is released by an unmasked interrupt request. in this case, if the interrupt request is enabled to be accepted, vectored interrupt processing is performed. if the interrupt acceptance is disabled, the instruction at the next address is executed. figure 12-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation remarks 1. the broken line indicates the case where the interrupt request that has released standby mode is accepted. 2. the wait time is as follows: when vectored interrupt processing is performed : 9 to 10 clocks when vectored interrupt processing is not performed : 1 to 2 clocks (b) releasing by non-maskable interrupt request halt mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
chapter 12 standby function user's manual u13600ej2v0um00 179 (c) releasing by reset input when halt mode is released by the reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. figure 12-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x : 6.55 ms) reset period halt mode operating mode oscillation settling wait status clock operating mode oscillation stop oscillation oscillation remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 12-2. operation after release of halt mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt processing. maskable interrupt request 1 retains halt mode. non-maskable interrupt request - executes interrupt processing. reset input -- reset processing : don't care
chapter 12 standby function user's manual u13600ej2v0um00 180 12.2.2 stop mode (1) setting and operation status of stop mode stop mode is set by executing the stop instruction. caution because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when stop mode is set, therefore, halt mode is set immediately after the stop instruction has been executed, the wait time set by the oscillation settling time selection register (osts) elapses, and then operating mode is set. the operation status in stop mode is shown in the following table. table 12-3. operation statuses in stop mode stop mode operation status while the main system clock is running item while the subsystem clock is r unning while the sub system clock is not r unning main system clock generation circuit oscillation stopped cpu operation disabled port (output latch) remains in the state existing before the selection of stop mode 16-bit timer operation enabled note 1 operation disabled 8-bit timer/event counter operation enabled note 2 watch timer operation enabled note 1 operation disabled watchdog timer operation disabled serial interface operation enabled note 3 external interrupt operation enabled note 4 notes 1. operation is enabled while the subsystem clock is selected. 2. operation is enabled only when ti80 is selected as the count clock. 3. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 4. maskable interrupt that is not masked
chapter 12 standby function user's manual u13600ej2v0um00 181 (2) releasing stop mode stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time has elapsed. if the interrupt acceptance is disabled, the instruction at the next address is executed. figure 12-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operating mode oscillation settling wait status clock operating mode oscillation stop oscillation oscillation remark the broken line indicates the case where the interrupt request that has released standby mode is accepted. (b) releasing by reset input when stop mode is released by the reset signal, the reset operation is performed after the oscillation settling time has elapsed. figure 12-5. releasing stop mode by reset input stop instruction reset signal wait (2 15 /f x : 6.55 ms) stop mode operating mode oscillation settling wait status clock operating mode oscillation stop oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 12-4. operation after release of stop mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt processing. maskable interrupt request 1 retains stop mode. reset input -- reset processing : don't care
user's manual u13600ej2v0um00 182 [memo]
user's manual u13600ej2v0um00 183 chapter 13 reset function the following two operations are available to generate reset signals. (1) external reset input with reset pin (2) internal reset by program run-away time detected with watchdog timer external and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset signal input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 13-1. each pin has a high impedance during reset input or during oscillation settling time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution is started after the oscillation settling time has elapsed. the reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation settling time has elapsed (see figures 13-2 through 13-4 ). cautions 1. for an external reset, input a low level for 10 m m m m s or more to the reset pin. 2. when stop mode is cleared by reset, stop mode contents are held during reset input. however, the port pins become high impedance. figure 13-1. block diagram of reset function reset interrupt function count clock reset control circuit watchdog timer over- flow reset signal stop
chapter 13 reset function user's manual u13600ej2v0um00 184 figure 13-2. reset timing by reset input x1 reset internal reset signal port pin normal operation reset period (oscillation stops) oscillation settling time wait normal operation (reset processing) delay delay hi-z figure 13-3. reset timing by overflow in watchdog timer x1 internal reset signal port pin overflow in watchdog timer normal operation reset period (oscillation continues) oscillation settling time wait normal operation (reset processing) hi-z figure 13-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin hi-z delay delay stop instruction execution normal operation stop status (oscillation stops) reset period (oscillation stops) oscillation settling time wait normal operation (reset processing)
chapter 13 reset function user's manual u13600ej2v0um00 185 table 13-1. state of the hardware after a reset hardware state after reset program counter (pc) note 1 loaded with the contents of the reset vector table (0000h, 0001h) stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose register undefined note 2 ports (p0 to p4) (output latch) 00h port mode registers (pm0 to pm4) ffh pull-up resistor option registers (pu0, pub2) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation settling time selection register (osts) 04h timer counter (tm90) 0000h compare register (cr90) ffffh capture register (tcp90) undefined mode control register (tmc90) 00h 16-bit timer buzzer output control register (bzc90) 00h timer counter (tm80) 00h compare register (cr80) undefined 8-bit timer/event counter mode control register (tmc80) 00h watch timer mode control register (wtm) 00h timer clock selection register (tcl2) 00h watchdog timer mode register (wdtm) 00h mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface status register (asis20) 00h baud rate generator control register (brgc20) 00h transmission shift register (txs20) ffh serial interface 20 reception buffer register (rxb20) undefined request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh external interrupt mode register (intm0) 00h interrupts key return mode register (krm00) 00h notes 1. while a reset signal is being input, and during the oscillation settling period, the contents of the pc will be undefined, while the remainder of the hardware will be the same as after the reset. 2. in standby mode, the ram enters the hold state after a reset.
user's manual u13600ej2v0um00 186 [memo]
user's manual u13600ej2v0um00 187 chapter 14 m m m m pd78f9046 the m pd78f9046 replaces the internal masked rom of the m pd789046 with flash memory. the differences between the flash memory and the masked rom versions are shown in table 14-1. table 14-1. differences between flash memory and masked rom versions flash memory masked rom item m pd78f9046 m pd789046 rom 16 kbytes (flash memory) 16 kbytes internal memory high-speed ram 512 bytes ic0 pin not provided provided v pp pin provided not provided electric characteristics varies depending on flash memory or masked rom version. caution the flash memory and masked rom versions have different noise immunity and noise radiation characteristics. do not use es versions for evaluation when considering switching from flash memory versions to those using masked rom upon the transition from preproduction to mass-production. cs versions (masked rom versions) should be used in this case.
chapter 14 m m m m pd78f9046 user's manual u13600ej2v0um00 188 14.1 flash memory programming the on-chip program memory in the m pd78f9046 is a flash memory. the flash memory can be written with the m pd78f9046 mounted on the target system (on-board). connect the dedicated flash writer (flashpro iii (part number: fl-pr3, pg-fp3)) to the host machine and target system to write the flash memory. remark fl-pr3 is made by naito densei machida mfg. co., ltd. 14.1.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 14-2. to select a communication mode, the format shown in figure 14-1 is used. each communication mode is selected by the number of v pp pulses shown in table 14-2. table 14-2. communication mode communication mode pins used number of v pp pulses 3-wire serial i/o sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 uart txd20/so20/p21 rxd20/si20/p22 8 pseudo 3-wire mode note p00 (serial clock input) p01 (serial data output) p02 (serial data input) 12 note serial transfer is performed by controlling a port by software. caution be sure to select a communication mode depending on the number of v pp pulses shown in table 14-2. figure 14-1. format of communication mode selection 10 v v ss v dd v pp v dd v ss reset 12 n
chapter 14 m m m m pd78f9046 user's manual u13600ej2v0um00 189 14.1.2 function of flash memory programming by transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. table 14-3 shows the major functions of flash memory programming. table 14-3. major functions of flash memory programming function description batch erase erases all contents of memory. batch blank check checks erased state of entire memory. data write writes to flash memory based on write start address and number of data written (number of bytes). batch verify compares all contents of memory with input data. 14.1.3 flashpro iii connection connection between the flashpro iii and the m pd78f9046 differs depending on the communication mode (3-wire serial i/o, uart, or pseudo 3-wire mode). figures 14-2 to 14-4 show the connection in the respective modes. figure 14-2. flashpro iii connection example in 3-wire serial i/o mode v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 reset sck20 si20 so20 v ss0 , v ss1 flashpro iii pd78f9046 m note n = 1, 2
chapter 14 m m m m pd78f9046 user's manual u13600ej2v0um00 190 figure 14-3. flashpro iii connection example in uart mode v pp n note v dd reset so si gnd v pp v dd0 , v dd1 reset rxd20 txd20 v ss0 , v ss1 flashpro iii pd78f9046 m note n = 1, 2 figure 14-4. flashpro iii connection example in pseudo 3-wire mode (when p0 is used) v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 reset p00 (serial clock) p02 (serial input) p01 (serial output) v ss0 , v ss1 flashpro iii pd78f9046 m note n = 1, 2
chapter 14 m m m m pd78f9046 user's manual u13600ej2v0um00 191 14.1.4 setting example with flashpro iii (pg-fp3) when writing data to the flash memory by using the flashpro iii (pg-fp3), set as follows. <1> load the parameter file. <2> select a serial mode and serial clock by using the type command. <3> an example of setting pg-fp3 is shown below. table 14-4. setting example with pg-fp3 communication mode setting example with pg-fp3 v pp pulse count note 1 comm port sio-ch0 on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz 3-wire serial i/o sio clk 1.0 mhz 0 comm port uart-ch0 cpu clk on target board on target board 4.1943 mhz uart uart bps 9,600 bps note 2 8 comm port port a on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1 khz in flashpro 4.0 mhz pseudo 3-wire mode sio clk 1 khz 12 notes 1. the number of v pp pulses supplied from the flashpro iii when serial communication is initialized. these pulse counts determine the pins used for communication. 2. select 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps. remark comm port : selects serial port. sio clk : selects serial clock frequency. cpu clk : selects source of cpu clock to be input.
user's manual u13600ej2v0um00 192 [memo]
user's manual u13600ej2v0um00 193 chapter 15 instruction set this chapter lists the instruction set of the m pd789046 subseries. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series user's manual ? ? ? ? instruction (u11047e) . 15.1 operation 15.1.1 operand identifiers and description methods operands are described in "operands" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. # : immediate data specification ! : absolute address specification $ : relative address specification [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 15-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-3 for symbols of special function registers.
chapter 15 instruction set user's manual u13600ej2v0um00 194 15.1.2 description of "operation" column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : flag indicating non-maskable interrupt servicing in progress ( ) : memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 15.1.3 description of "flag" column (blank) : unchanged 0 : cleared to 0 1 : set to 1 : set/cleared according to the result r : previously saved value is stored
chapter 15 instruction set user's manual u13600ej2v0um00 195 15.2 operation list flag mnemonic operands byte clock operation zaccy r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) mov [hl + byte], a 2 6 (hl + byte) ? a a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl, byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by processor clock control register (pcc).
chapter 15 instruction set user's manual u13600ej2v0um00 196 flag mnemonic operands byte clock operation zaccy rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 1 4 ax ? rp movw rp, ax note 14rp ? ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) add a, [hl + byte] 2 6 a, cy ? a + (hl + byte) a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy addc a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) sub a, [hl + byte] 2 6 a, cy ? a - (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by processor clock control register (pcc).
chapter 15 instruction set user's manual u13600ej2v0um00 197 flag mnemonic operands byte clock operation zaccy a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy subc a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) and a, [hl + byte] 2 6 a ? a (hl + byte) a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) or a, [hl + byte] 2 6 a ? a (hl + byte) a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) xor a, [hl + byte] 2 6 a ? a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by processor clock control register (pcc).
chapter 15 instruction set user's manual u13600ej2v0um00 198 flag mnemonic operands byte clock operation zaccy a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) cmp a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word r24r ? r + 1 inc saddr 2 4 (saddr) ? (saddr) + 1 r24r ? r + 1 dec saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 saddr.bit 3 6 (saddr.bit) ? 1 sfr.bit 3 6 sfr.bit ? 1 a.bit 2 4 a.bit ? 1 psw.bit 3 6 psw.bit ? 1 set1 [hl].bit 2 10 (hl).bit ? 1 saddr.bit 3 6 (saddr.bit) ? 0 sfr.bit 3 6 sfr.bit ? 0 a.bit 2 4 a.bit ? 0 psw.bit 3 6 psw.bit ? 0 clr1 [hl].bit 2 10 (hl).bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by processor clock control register (pcc).
chapter 15 instruction set user's manual u13600ej2v0um00 199 flag mnemonic operands byte clock operation zaccy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr psw 1 2 (sp - 1) ? psw, sp ? sp - 1 push rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 psw 1 4 psw ? (sp), sp ? sp + 1 r r r pop rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, ax 2 8 sp ? ax movw ax, sp 2 6 ax ? sp !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 br ax 1 6 pc h ? a, pc l ? x bc $saddr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 dbnz saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by processor clock control register (pcc).
chapter 15 instruction set user's manual u13600ej2v0um00 200 15.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl + byte] $addr16 1 none aadd addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a.
chapter 15 instruction set user's manual u13600ej2v0um00 201 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 15 instruction set user's manual u13600ej2v0um00 202 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user's manual u13600ej2v0um00 203 appendix a development tools the following development tools are available for development of systems using the m pd789046 subseries. figure a-1 shows development tools. compatibility with pc98-nx series unless stated otherwise, products which are supported for the ibm pc/at tm and compatibles can also be used with the pc98-nx series. when using the pc98-nx series, therefore, refer to the explanations for the ibm pc/at and compatibles. windows unless stated otherwise, "windows" refers to the following operating systems. windows 3.1 windows 95 windows nt tm ver. 4.0
appendix a development tools user's manual u13600ej2v0um00 204 figure a-1. development tools language processing software ? assembler package ? c compiler package ? system simulator ? device file ? c compiler source file ? integrated debugger embedded software ? os host machine (pc or ews) interface adapter flash writer flash memory writing adapter flash memory in-circuit emulator power supply unit emulation board emulation probe target system flash memory writing tools conversion adapter conversion socket
appendix a development tools user's manual u13600ej2v0um00 205 a.1 language processing software program that converts program written in mnemonic into object code that can be executed by microcontroller. in addition, automatic functions to generate symbol table and optimize branch instructions are also provided. used in combination with optional device file (df789046). the assembler package is a dos-based application but may be used under the windows environment by using project manager of windows (included in the package). ra78k0s assembler package part number: m s ra78k0s program that converts program written in c language into object codes that can be executed by microcontroller. used in combination with optional assembler package (ra78k0s) and device file (df789046). the c compiler package is a dos-based application but may be used under the windows environment by using project manager of windows (included in the assembler package). cc78k0s c compiler package part number: m s cc78k0s file containing the information inherent to the device. used in combination with other optional tools (ra78k0s, cc78k0s, sm78k0s). df789046 note device file part number: m s df789046 source file of functions constituting object library included in c compiler package. necessary for changing object library included in c compiler package according to customer's specifications. since this is the source file, its working environment does not depend on any particular operating system. cc78k0s-l c compiler source file part number: m s cc78k0s-l note df789046 is a common file that can be used with ra78k0s, cc78k0s, and sm78k0s. remark in the part number differs depending on the host machines and operating systems to be used. m s ra78k0s m s cc78k0s m s df789046 m s cc78k0s-l host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 ibm pc/at and compatibles japanese windows note 3.5" 2hc fd 3p16 hp9000 series 700 tm hp-ux tm (rel.10.10) dat (dds) 3k13 3.5" 2hc fd 3k15 sparcstation tm sunos tm (rel.4.1.4), solaris tm (rel.2.5.1) 1/4" cgmt 3r13 news tm (risc) news-os tm (rel.6.1) 3.5" 2hc fd note also operates under the dos environment.
appendix a development tools user's manual u13600ej2v0um00 206 a.2 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flash writer flash writer dedicated to the microcontrollers incorporating a flash memory. fa-44gb-8es flash memory writing adapter flash memory writing adapter. used in connection with flashpro iii. fa-44gb-8es: for 44-pin plastic lqfp (gb-8es type) remark fl-pr3 and fa-44gb-8es are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (044-822-3813) a.3 debugging tools a.3.1 hardware ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using 78k/0s series. supports integrated debugger (id78k0s-ns). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-70000-mc-ps-b ac adapter this is the adapter for supplying power from 100 to 240 vac outlet. ie-70000-98-if-c interface adapter this adapter is needed when pc-9800 series (excluding a notebook-type personal computer) is used as a host machine of ie-78k0s-ns (c bus compatible). ie-70000-cd-if-a pc card interface this pc card and interface cable are needed when a notebook-type personal computer is used as a host machine of ie-78k0s-ns (pcmica socket compatible). ie-70000-pc-if-c interface adapter this adapter is needed when ibm pc/at and compatibles are used as a host machine of ie-78k0s-ns (isa bus compatible). ie-70000-pci-if interface adapter this adapter is needed when a personal computer incorporating the pci bus is used as a host machine of ie-78k0s-ns. ie-789046-ns-em1 emulation board emulation board for emulating the peripheral hardware inherent to the device. used in combination with in-circuit emulator. np-44gb this is the board for connecting the in-circuit emulator and target system. used in combination with the ev-9200g-44. ev-9200g-44 conversion socket this conversion socket is used to connect a target system board designed to allow mounting of the 44-pin plastic lqfp and the np-44gb. np-44gb-tq this is the board for connecting the in-circuit emulator and target system. used in combination with the tgb-044sap. tgb-044sap conversion adapter this conversion adapter is used to connect a target system board designed to allow mounting of the 44-pin plastic lqfp and the np-44gb-tq. remarks 1. np-44gb and np-44gb-tq are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (044-822-3813) 2. tgb-044sap is a product of tokyo eletech corporation. for further information, contact: daimaru kougyou, ltd. tokyo electronics division (03-3820-7112) osaka electronics division (06-6244-6672)
appendix a development tools user's manual u13600ej2v0um00 207 a.3.2 software control program for debugging the 78k/0s series. this program provides a graphical user interface. it runs on windows for personal computer users and on osf/motif tm for engineering work station users, and has visual designs and operability that comply with these operating systems. in addition, it has a powerful debug function that supports c language. therefore, trace results can be displayed at a c language level by the window integration function that links source program, disassembled display, and memory display, to the trace result. this software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system. used in combination with optional device file (df789046). id78k0s-ns integrated debugger (supports in-circuit emulator ie-78k0s-ns) part number: m s id78k0s-ns remark in the part number differs depending on the host machines and operating system to be used. m s id78k0s-ns host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at and compatibles english windows note 3.5" 2hc fd note also operates under the dos environment. debugs program at c source level or assembler level while simulating operation of target system on host machine. sm78k0s runs on windows. by using sm78k0s, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. this enhances development efficiency and improves software quality. used in combination with optional device file (df789046). sm78k0s system simulator part number: m s sm78k0s file containing the information inherent to the device. used in combination with other optional tools (ra78k0s, cc78k0s, sm78k0s). df789046 note device file part number: m s df789046 note df789046 is a common file that can be used with ra78k0s, cc78k0s, and sm78k0s. remark in the part number differs depending on the host machines and operating system to be used. m s sm78k0s host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at and compatibles english windows note 3.5" 2hc fd note also operates under the dos environment.
appendix a development tools user's manual u13600ej2v0um00 208 a.4 conversion socket (ev-9200g-44) drawing and recommended footprint figure a-2. ev-9200g-44 package drawing (reference) (unit: mm) a f d 1 e ev-9200g-44 b c m n o l k r q i h p j g ev-9200g-44-g0e item millimeters inches a b c d e f g h i j k l m n o p q r 15.0 10.3 10.3 15.0 4-c 3.0 0.8 5.0 12.0 14.7 5.0 12.0 14.7 8.0 7.8 2.0 1.35 0.35 0.1 1.5 0.591 0.406 0.406 0.591 4-c 0.118 0.031 0.197 0.472 0.579 0.197 0.472 0.579 0.315 0.307 0.079 0.053 0.014 0.059 +0.004 C0.005 f f no.1 pin index based on ev-9200g-44 (1) package drawing (in mm)
appendix a development tools user's manual u13600ej2v0um00 209 figure a-3. ev-9200g-44 footprints (reference) (unit: mm) 0.031 0.394=0.315 0.031 0.394=0.315 a f d e b g h i j c l k ev-9200g-44-p1e item millimeters inches a b c d e f g h i j k l 15.7 11.0 11.0 15.7 5.00 0.08 5.00 0.08 0.5 0.02 1.57 0.03 2.2 0.1 1.57 0.03 0.618 0.433 0.433 0.618 0.197 0.197 0.02 0.062 0.087 0.062 0.8 0.02 10=8.0 0.05 0.8 0.02 10=8.0 0.05 f f f +0.002 C0.001 +0.002 C0.002 +0.002 C0.001 +0.002 C0.002 +0.003 C0.004 +0.003 C0.004 +0.001 C0.002 f f f +0.001 C0.002 +0.004 C0.005 +0.001 C0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution based on ev-9200g-44 (2) pad drawing (in mm)
appendix a development tools user's manual u13600ej2v0um00 210 a.5 conversion adapter (tgb-044sap) drawing figure a-4. tgb-044sap package drawing (reference) (unit: mm) item millimeters inches b 0.25 0.010 c 9.6 0.378 a 2.0 0.079 d 1.2 0.047 e 1.2 0.047 f 2.4 g 2.7 0.106 0.094 item millimeters inches b 0.8x10=8.0 0.031x0.394=0.315 c 0.8 0.031 a 10.12 0.398 d h c 2.0 c 0.079 i 9.35 0.368 j 1.325 0.052 e 8.4 0.331 f 10.8 0.425 k 1.325 0.052 l 12.0 0.472 m q 1.8 0.071 r s n 8.5 0.335 o 13.15 p 5.0 0.197 0.518 w x 6.0 0.236 y t u (16.95) v 7.35 0.289 (0.667) z 3.5 0.138 16.65 16.65 0.656 0.656 g 13.2 0.520 reference diagram: tgb-044sap (tqpack044sa+tqsocket044sap) package dimension (unit: mm) s c h a f g t note : product by tokyo eletech corporation. tgb-044sap-g0e a b g n o f e d u x z y bd e w r c protrusion height q i p jk l m 3.55 0.140 ff 0.9 0.035 ff 0.3 0.012 ff 1.2 0.047 1.85 0.073 v
user's manual u13600ej2v0um00 211 appendix b embedded software the following embedded software products are available for efficient program development and maintenance of the m pd789046 subseries. mx78k0s os mx78k0s is a subset os that is based on the m itron specification. supplied with the mx78k0s nucleus. the mx78k0s os controls tasks, events, and time. in task control, the mx78k0s os controls task execution order, and performs the switching process to a task to be executed. mx78k0s is a dos-based application. use this software in the dos pane when running it on windows. m s mx78k0s host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at compatibles english windows note 3.5" 2hc fd note also operates under the dos environment.
user's manual u13600ej2v0um00 212 [memo]
user's manual u13600ej2v0um00 213 appendix c register index c.1 register name index (alphabetic order) 16-bit capture register 90 (tcp90) ............................................................................................. ........................... 87 16-bit compare register 90 (cr90) .............................................................................................. .......................... 87 16-bit timer counter 90 (tm90) ................................................................................................. ............................. 87 16-bit timer mode control register 90 (tmc90).................................................................................. .................... 88 8-bit compare register 80 (cr80) ............................................................................................... ......................... 102 8-bit timer counter 80 (tm80) .................................................................................................. ............................ 102 8-bit timer mode control register 80 (tmc80)................................................................................... ................... 103 [a] asynchronous serial interface mode register 20 (asim20) ......................................................... 130, 136, 139, 150 asynchronous serial interface status register 20 (asis20) ...................................................................... ... 132, 140 [b] baud rate generator control register 20 (brgc20) ............................................................................. 13 3, 141, 151 buzzer output control register 90 (bzc90) ...................................................................................... ...................... 90 [e] external interrupt mode register 0 (intm0) ..................................................................................... .................... 165 [i] interrupt mask flag register 0 (mk0) ........................................................................................... ......................... 164 interrupt mask flag register 1 (mk1) ........................................................................................... ......................... 164 interrupt request flag register 0 (if0)........................................................................................ ........................... 163 interrupt request flag register 1 (if1)........................................................................................ ........................... 163 [k] key return mode register 00 (krm00)............................................................................................ ..................... 167 [o] oscillation settling time selection register (osts) ............................................................................ .................. 176 [p] port 0 (p0) .................................................................................................................... ....................................... 61 port 1 (p1) .................................................................................................................... ....................................... 62 port 2 (p2) .................................................................................................................... ....................................... 63 port 3 (p3) .................................................................................................................... ....................................... 68 port 4 (p4) .................................................................................................................... ....................................... 69 port mode register 0 (pm0) ..................................................................................................... .............................. 70 port mode register 1 (pm1) ..................................................................................................... .............................. 70 port mode register 2 (pm2) ..................................................................................................... ...................... 70, 104 port mode register 3 (pm3) ..................................................................................................... ........................ 70, 91
appendix c register index user's manual u13600ej2v0um00 214 port mode register 4 (pm4) ..................................................................................................... ...............................70 processor clock control register (pcc) ......................................................................................... .........................77 pull-up resistor option register 0 (pu0) ....................................................................................... ...........................71 pull-up resistor option register b2 (pub2)..................................................................................... .........................72 [r] reception buffer register 20 (rxb20) ........................................................................................... .......................128 [s] serial operation mode register 20 (csim20) ................................................................................129, 136, 138, 149 subclock control register (css) ................................................................................................ .............................78 suboscillation mode register (sckm)............................................................................................ .........................78 [t] timer clock selection register 2 (tcl2)........................................................................................ ........................121 transmission shift register 20 (txs20) ......................................................................................... .......................128 [w] watch timer mode control register (wtm)........................................................................................ ....................115 watchdog timer mode register (wdtm)............................................................................................ ...................122
appendix c register index user's manual u13600ej2v0um00 215 c.2 register symbol index (alphabetic order) [a] asim20 : asynchronous serial interface mode register 20................................................... 130, 136, 139, 150 asis20 : asynchronous serial interface status register 20 .................................................................. 132 , 140 [b] brgc20 : baud rate generator control register 20 ........................................................................ 133, 1 41, 151 bzc90 : buzzer output control register 90..................................................................................... ............... 90 [c] cr80 : 8-bit compare register 80.............................................................................................. ................ 102 cr90 : 16-bit compare register 90............................................................................................. ................. 87 csim20 : serial operation mode register 20......................................................................... 129, 136, 1 38, 149 css : subclock control register ............................................................................................... ................. 78 [i] if0 : interrupt request flag register 0....................................................................................... .............. 163 if1 : interrupt request flag register 1....................................................................................... .............. 163 intm0 : external interrupt mode register 0 .................................................................................... ............ 165 [k] krm00 : key return mode register 00 ........................................................................................... .............. 167 [m] mk0 : interrupt mask flag register 0 .......................................................................................... .............. 164 mk1 : interrupt mask flag register 1 .......................................................................................... .............. 164 [o] osts : oscillation settling time selection register........................................................................... .......... 176 [p] p0 : port 0 ................................................................................................................ ........................... 61 p1 : port 1 ................................................................................................................... ........................... 62 p2 : port 2 ................................................................................................................... ........................... 63 p3 : port 3 ................................................................................................................... ........................... 68 p4 : port 4 ................................................................................................................... ........................... 69 pcc : processor clock control register........................................................................................ .............. 77 pm0 : port mode register 0 .................................................................................................... ................... 70 pm1 : port mode register 1 .................................................................................................... ................... 70 pm2 : port mode register 2 .................................................................................................... ........... 70, 104 pm3 : port mode register 3 .................................................................................................... ............. 70, 91 pm4 : port mode register 4 .................................................................................................... ................... 70 pu0 : pull-up resistor option register 0 ...................................................................................... ............... 71 pub2 : pull-up resistor option register b2.................................................................................... ............... 72 [r] rxb20 : reception buffer register 20 .......................................................................................... ............... 128
appendix c register index user's manual u13600ej2v0um00 216 [s] sckm : suboscillation mode register........................................................................................... .................78 [t] tcl2 : timer clock selection register 2 ....................................................................................... ..............121 tcp90 : 16-bit capture register 90............................................................................................ .....................87 tm80 : 8-bit timer counter 80................................................................................................. ....................102 tm90 : 16-bit timer counter 90................................................................................................ .....................87 tmc80 : 8-bit timer mode control register 80 .................................................................................. .............103 tmc90 : 16-bit timer mode control register 90 ................................................................................. ..............88 txs20 : transmission shift register 20........................................................................................ ................128 [w] wdtm : watchdog timer mode register........................................................................................... ............122 wtm : watch timer mode control register....................................................................................... ..........115
user's manual u13600ej2v0um00 217 appendix d revision history the revision history for this manual is detailed below. "chapter" indicates the chapter of the edition. edition revision from previous edition chapter completion of development of m pd789046 and m pd78f9046 throughout change of recommended connection of unused pins in processing of input/output circuit type of each pin and unused pins chapter 2 pin functions correction of 16-bit timer block diagram addition of cautions on rewriting cr90 addition of cautions on 16-bit timer to section 6.5 chapter 6 16-bit timer addition of cautions on rewriting cr80 addition of description of operation to operation as interval timer addition of description of operation to operation as external event counter addition of description of operation to operation as square wave output addition of description of operation to operation as pwm output chapter 7 8-bit timer/event counter correction of pins used in pseudo 3-wire mode in communication modes change of connection of p01 and p02 pins in example of connection of flashpro iii in pseudo 3-wire mode (when p0 is used) addition of setting example of flashpro iii (pg-fp3) chapter 14 m m m m pd78f9046 correction of product name of flash memory writing adapter in flash memory writing tools addition of np-44gb-tq as emulation probe to hardware addition of package drawing of conversion adapter (tbg-044sap) appendix a development tools second edition addition of part number of mx78k0s appendix b embedded software
user's manual u13600ej2v0um00 218 [memo]
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 00.6 name company from: tel. fax facsimile message


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