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? semiconductor components industries, llc, 2006 january, 2006 ? rev. 13 1 publication order number: NBSG16/d NBSG16 2.5v/3.3vsige differential receiver/driver with rsecl* outputs *reduced swing ecl description the NBSG16 is a differential receiver/driver targeted for high frequency applications. the device is functionally equivalent to the ep16 and lvep16 devices with much higher bandwidth and lower emi capabilities. inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), hstl, lvttl, lvcmos, cml, or lvds. output s are rsecl (reduced swing ecl), 400 mv. the v bb and v mm pins are internally generated voltage supplies available to this device only. the v bb is used as a reference voltage for single ? ended necl or pecl inputs and the v mm pin is used as a reference voltage for lvcmos inputs. for all single ? ended input conditions, the unused complementary differential input is connected to v bb or v mm as a switching reference voltage. v bb or v mm may also rebias ac coupled inputs. when used, decouple v bb and v mm via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb and v mm outputs should be left open. features ? maximum input clock frequency > 12 ghz typical ? maximum input data rate > 12 gb/s typical ? 120 ps typical propagation delay ? 40 ps typical rise and fall times ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.465 v ? rsecl output level (400 mv peak ? to ? peak output), differential output only ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, and lvel devices ? v bb and v mm reference voltage output ? pb ? free packages are available a = assembly location l = wafer lot y = year w = work week = pb ? free package fcbga ? 16 ba suffix case 489 marking diagrams* qfn ? 16 mn suffix case 485g http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information (note: microdot may be in either location) sg 16 alyw 16 sg 16 alyw 1 ?? ??
NBSG16 http://onsemi.com 2 figure 1. bga ? 16 pinout (top view) v ee d d vtd v ee v bb vtd nc nc v ee v cc v cc v mm v ee q q a b c d 1234 v ee nc nc v ee v ee v bb v mm v ee v cc q q v cc vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 NBSG16 exposed pad (ep) figure 2. qfn ? 16 pinout (top view) table 1. pin description pin name i/o description bga qfn c2 1 vtd ? internal 50 termination pin. see table 2. c1 2 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. internal 75 k to v ee and 36.5 k to v cc . b1 3 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. internal 75 k to v ee . b2 4 vtd ? internal 50 termination pin. see table 2. a1,d1,a4, d4 5,8,13,16 v ee ? negative supply voltage a2,a3 6,7 nc ? no connect b3,c3 9,12 v cc ? positive supply voltage b4 10 q rsecl output noninverted differential output. typically terminated with 50 to v tt = v cc ? 2 v c4 11 q rsecl output inverted differential output. typically terminated with 50 to v tt = v cc ? 2 v d3 14 v mm ? lvcmos reference voltage output. (v cc ? v ee )/2 d2 15 v bb ? ecl reference voltage output n/a ? ep ? exposed pad. (note 2) 1. the nc pins are electrically connected to the die and must be left open. 2. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. the thermally exposed pad on package bottom (see case drawing) must be attached to a heat ? sinking conduit. 3. in the dif ferential configuration when the input termination pins (vtd, vtd ) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self ? oscillation.
NBSG16 http://onsemi.com 3 50 50 vtd d d vtd v mm q q v bb v ee v cc figure 3. logic diagram 75 k 75 k 36.5 table 2. interfacing options interfacing options connections cml connect vtd and vtd to v cc lvds connect vtd and vtd together ac ? coupled bias vtd and vtd inputs within (v ihcmr ) common mode range rsecl, pecl, necl standard ecl termination techniques lvttl the external voltage should be applied to the unused complementary differential input. nominal voltage is 1.5 v for lvttl. lvcmos v mm should be connected to the unused complementary differential input. table 3. attributes characteristics value internal input pulldown resistor (d, d ) 75 k internal input pullup resistor (d ) 36.5 k esd protection human body model machine model > 2 kv > 100 v moisture sensitivity (note 1) pb pkg pb ? free pkg fcbga ? 16 qfn ? 16 level 3 level 1 n/a level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 167 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
NBSG16 http://onsemi.com 4 table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ? 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ? 3.6 v v v inpp differential input voltage |d ? d | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v v i out output current continuous surge 25 50 ma ma i bb v bb sink/source 1 ma i mm v mm sink/source 1 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 2) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 16 fcbga 16 fcbga 16 qfn 16 qfn 108 86 41.6 35.2 c/w c/w c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 2) 2s2p (note 3) 16 fcbga 16 qfn 5 4.0 c/w c/w t sol wave solder pb pb ? free 225 225 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 2. jedec standard multilayer board ? 1s2p (1 signal, 2 power) 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NBSG16 http://onsemi.com 5 table 5. dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 4) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma v oh output high voltage (note 5) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (single ? ended) (note 6) v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 6) v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v v bb pecl output voltage reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mv v ihcmr input high voltage common mode range (note 7) (differential configuration) 1.2 2.5 1.2 2.5 1.2 2.5 v v mm cmos output voltage reference v cc /2 1100 1250 1400 1100 1250 1400 1100 1250 1400 mv r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to ? 0.965 v. 5. all loading with 50 to v cc ? 2.0 v. 6. v thr is the voltage applied to the complementary input, typically v bb or v mm . 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
NBSG16 http://onsemi.com 6 table 6. dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 8) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma v oh output high voltage (note 9) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (single ? ended) (note 10) v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 10) v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v v bb pecl output voltage reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mv v ihcmr input high voltage common mode range (note 11) (differential configuration) 1.2 3.3 1.2 3.3 1.2 3.3 v v mm cmos output voltage reference v cc /2 1500 1650 1800 1500 1650 1800 1500 1650 1800 mv r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. 8. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to ? 0.165 v. 9. all loading with 50 to v cc ? 2.0 v. 10. v thr is the voltage applied to the complementary input, typically v bb or v mm . 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
NBSG16 http://onsemi.com 7 table 7. dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v (note 12) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current 17 23 29 17 23 29 17 23 29 ma v oh output high voltage (note 13) ? 1050 ? 970 ? 925 ? 975 ? 935 ? 900 ? 950 ? 910 ? 875 mv v outpp output voltage amplitude 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (single ? ended) (note 14) v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v thr + 75 mv v cc ? 1.0* v cc v v il input low voltage (single ? ended) (note 14) v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v ee v cc ? 1.4* v thr ? 75 mv v v bb necl output voltage reference ? 1420 ? 1360 ? 1300 ? 1420 ? 1360 ? 1300 ? 1420 ? 1360 ? 1300 mv v ihcmr input high voltage common mode range (note 15) (differential configuration) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v v mm cmos output voltage reference (note 16) v mmt ? 150 v mmt v mmt + 150 v mmt ? 150 v mmt v mmt + 150 v mmt ? 150 v mmt v mmt + 150 mv r tin internal input termination resis- tor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 50 25 50 25 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. 12. input and output parameters vary 1:1 with v cc . 13. all loading with 50 to v cc ? 2.0 v. 14. v thr is the voltage applied to the complementary input, typically v bb or v mm . 15. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 16. v mm typical = |v cc ? v ee |/2 + v ee = v mmt
NBSG16 http://onsemi.com 8 table 8. ac characteristics for fcbga ? 16 v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum frequency (see figure 4. f max /jitter) (note 17) 10.7 12 10.7 12 10.7 12 ghz t plh , t phl propagation delay to output differential 90 110 130 100 120 140 105 125 145 ps t skew duty cycle skew (note 18) 3 15 3 15 3 15 ps t jitter rms random clock jitter f in < 10 ghz peak ? to ? peak data dependent jitter f in < 10 gb/s 0.2 tbd 1 0.2 tbd 1 0.2 tbd 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 19) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 30 45 75 20 40 65 20 40 65 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. measured using a 400 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 18. see figure 6. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 19. v inpp(max) cannot exceed v cc ? v ee table 9. ac characteristics for qfn ? 16 v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum frequency (see figure 4. f max /jitter) (note 20) 10.7 12 10.7 12 10.7 12 ghz t plh , t phl propagation delay to output differential 90 110 130 100 120 140 95 125 145 ps t skew duty cycle skew (note 21) 3 15 3 15 3 15 ps t jitter rms random clock jitter f in < 10 ghz peak ? to ? peak data dependent jitter f in < 10 gb/s 0.2 tbd 2 0.2 tbd 2 0.2 tbd 2 ps v inpp input voltage swing/sensitivity (differential configuration) (note 22) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 20 30 50 20 30 50 20 30 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. measured using a 400 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 21. see figure 6. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 22. v inpp(max) cannot exceed v cc ? v ee
NBSG16 http://onsemi.com 9 output amp rms jitter input frequency (ghz) figure 4. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at ambient temperature (typical) output voltage amplitude (mv) jitter out ps (rms) 700 600 500 400 300 200 100 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9.5 8.5 7.5 6.5 3.5 2.5 5.5 4.5 0.5 ? 0.5 1.5 q q figure 5. 10.709 gb/s diagram (3.0 v, 25 c) x = 17ps/div y = 70 mv/div figure 6. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q)
NBSG16 http://onsemi.com 10 figure 7. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? NBSG16ba fcbga ? 16 100 units / tray NBSG16bar2 fcbga ? 16 500 / tape & reel NBSG16mn qfn ? 16 123 units / rail NBSG16mng qfn ? 16 (pb ? free) 123 units / rail NBSG16mnr2 qfn ? 16 3000 / tape & reel NBSG16mnr2g qfn ? 16 (pb ? free) 3000 / tape & reel board description NBSG16baevb NBSG16ba evaluation board ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NBSG16 http://onsemi.com 11 package dimensions fcbga ? 16 ba suffix plastic 4x4 (mm) bga flip chip package case 489 ? 01 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view m ? m e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k ? x ? ? y ? m m ? z ?
NBSG16 http://onsemi.com 12 package dimensions 16 pin qfn case 485g ? 01 issue b 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 exposed pad mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NBSG16/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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