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november 2006 rev 3 1/62 1 nand01g-b2b NAND02G-B2C 1 gbit, 2 gbit, 2112 byte/1056 word page, 1.8v/3v, nand flash memory features high density nand flash memories ? up to 2 gbit memory array ? cost effective solutions for mass storage applications nand interface ? x8 or x16 bus width ? multiplexed address/ data ? pinout compatibility for all densities supply voltage: 1.8v/3.0v page size ? x8 device: (2048 + 64 spare) bytes ? x16 device: (1024 + 32 spare) words block size ? x8 device: (128k + 4k spare) bytes ? x16 device: (64k + 2k spare) words page read/program ? random access: 25s (max) ? sequential access: 30ns (min) ? page program time: 200s (typ) copy back program mode cache program and cache read modes fast block erase: 2ms (typ) status register electronic signature chip enable ?don?t care? serial number option data protection ? hardware block locking ? hardware program/erase locked during power transitions data integrity ? 100,000 program/erase cycles ? 10 years data retention ecopack ? packages development tools ? error correction code models ? bad blocks management and wear leveling algorithms ? hardware simulation models fbga tsop48 12 x 20mm vfbga63 9.5 x 12 x 1mm vfbga63 9 x 11 x 1mm table 1. product list reference part number nand01g-b2b nand01gr3b2b, nand01gw3b2b nand01gr4b2b , nand01gw4b2b (1) NAND02G-B2C nand02gr3b2c, nand02gw3b2c nand02gr4b2c, nand02gw4b2c (1) 1. x16 organization only available for mcp products. www.st.com
contents nand01g-b2b, NAND02G-B2C 2/62 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 read enable (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 ready/busy (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.2 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
nand01g-b2b, nand0 2g-b2c contents 3/62 6.2 cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3.1 sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3.2 random data input in a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8.1 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8.2 p/e/r controller and cache ready/busy bit (sr6) . . . . . . . . . . . . . . . 31 6.8.3 p/e/r controller bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8.4 cache program error bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.8.5 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.8.6 sr4, sr3 and sr2 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.9 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2 nand flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.5 error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6 hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.1 behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6.2 ibis simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 program and erase times and endurance cycles . . . . . . . . . . . . . . . . 40 10 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54 11.2 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
contents nand01g-b2b, NAND02G-B2C 4/62 12 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
nand01g-b2b, NAND02G-B2C list of tables 5/62 list of tables table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. address insertion, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. address definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. address definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. copy back program x8 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. copy back program x16 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. electronic signature byte/word 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. nand flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . 40 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. dc characteristics, 1.8v devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. dc characteristics, 3v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 24. ac characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. ac characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . 57 table 27. vfbga63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, package mechanical data . . 58 table 28. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data . . . 59 table 29. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
list of figures nand01g-b2b, NAND02G-B2C 6/62 list of figures figure 1. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tsop48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. vfbga63 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. page copy back program with random data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. cache program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. bad block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 16. garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18. equivalent testing circuit for ac characteristics measurement . . . . . . . . . . . . . . . . . . . . 43 figure 19. command latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 figure 20. address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 21. data input latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 22. sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 23. read status register ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 24. read electronic signature ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25. page read operation ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 26. page program ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27. block erase ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 28. reset ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 29. program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30. program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 31. ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 32. ready/busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 33. resistor value versus waveform timings for ready/busy signal. . . . . . . . . . . . . . . . . . . . . 56 figure 34. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 35. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . 57 figure 36. vfbga63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, package outline. . . . . . . . . . 58 figure 37. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline . . . . . . . . . . . 59
nand01g-b2b, nand02g -b2c description 7/62 1 description st nand01g-b2b and NAND02G-B2C flash 2112 byte/ 1056 word page is a family of non-volatile flash memories that uses nand cell technology. the devices range from 1 gbit to 2 gbits and operate with either a 1.8v or 3v voltage supply. the size of a page is either 2112 bytes (2048 + 64 spare) or 1056 words (1024 + 32 spare) depending on whether the device has a x8 or x16 bus width. the address lines are multiplexed with the data input/output signals on a multiplexed x8 or x16 input/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 100,000 cycles. to extend the lifetime of nand flash devices it is strongly recommende d to implement an error correction code (ecc). the devices feature a write protect pin that a llows performing hardware protection against program and erase operations. the devices feature an open-drain ready/busy output that can be used to identify if the program/erase/read (p/e/r) controller is currently active. the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a copy back program command is available to optimize the management of defective blocks. when a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. each device has cache program and cache read features which improve the program and read throughputs for large files. during cache programming, the device loads the data in a cache register while the previous data is transferred to the page buffer and programmed into the memory array. during cache reading, the device loads the data in a cache register while the previous data is transferred to the i/o buffers to be read. all devices have the chip enable don?t care feature, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation. all devices have the option of a unique identi fier (serial number), which allows each device to be uniquely identified. the unique identifier options is subject to an nda (non disclosure agreement) and so not described in the datasheet. for more details of this option contact your nearest st sales office. the devices are available in the following packages: tsop48 (12 x 20mm) vfbga63 (9.5 x 12 x 1mm, 0.8mm pitch) for NAND02G-B2C devices. vfbga63 (9 x 11 x 1mm, 0.8mm pitch) for nand01g-b2b devices. in order to meet environmental requirements, st offers the nand01g-b2b and nand02g- b2c in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark.
description nand01g-b2b, NAND02G-B2C 8/62 for information on how to order these options refer to table 29: ordering information scheme . devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. see table 2: product description , for all the devices available in the family. table 2. product description reference part number density bus width page size block size memory array operatin g voltage timings package random access time (max) sequential access time (min) page program time (typ) block erase (typ) nand01g -b2b nand01gr3b2b 1gbit x8 2048+ 64 bytes 128k+ 4k bytes 64 pages x 1024 blocks 1.7 to 1.95v 25s 50ns 200s 2ms vfbga63 9x11mm nand01gw3b2b 2.7 to 3.6v 25s 30ns tsop48 nand01gr4b2b x16 1024+ 32 words 64k+ 2k words 1.7 to 1.95v 25s 50ns (1) nand01gw4b2b 2.7 to 3.6v 25s 30ns (1) nand02g -b2c nand02gr3b2c 2gbit x8 2048+ 64 bytes 128k+ 4k bytes 64 pages x 2048 blocks 1.7 to 1.95v 25s 50ns 2ms vfbga63 9.5x12mm nand02gw3b2c 2.7 to 3.6v 25s 30ns tsop48 nand02gr4b2c x16 1024+ 32 words 64k+ 2k words 1.7 to 1.95v 25s 50ns (1) nand02gw4b2c 2.7 to 3.6v 25s 30ns (1) 1. x16 organization only available for mcp
nand01g-b2b, nand02g -b2c description 9/62 figure 1. logic block diagram figure 2. logic diagram 1. x16 organization only available for mcp address register/counter command interface logic p/e/r controller, high voltage generator wp i/o buffers & latches i/o8-i/o15, x16 e w ai12799 r y decoder page buffer nand flash memory array x decoder i/o0-i/o7, x8/x16 command register cl al cache register rb ai13101 w i/o8-i/o15, x16 v dd nand01g-b2b NAND02G-B2C e v ss wp al cl rb r i/o0-i/o7, x8/x16
description nand01g-b2b, NAND02G-B2C 10/62 table 3. signal names i/o8-15 data input/outputs for x16 devices i/o0-7 data input/outputs, address inputs, or command inputs for x8 and x16 devices al address latch enable cl command latch enable e chip enable r read enable rb ready/busy (open-drain output) w write enable wp write protect v dd supply voltage v ss ground nc not connected internally du do not use
nand01g-b2b, nand02g -b2c description 11/62 figure 3. tsop48 connections 1. available only for nand01gw3b2 b and nand02gw3b2c 8-bit devices. i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai13102 nand01gw3b2b nand02gw3b2c 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc
description nand01g-b2b, NAND02G-B2C 12/62 figure 4. vfbga63 connections (top view through package) 1. available only for nand01gr3b2b and nand02gr3b2c 8-bit devices. ai13103 i/o7 wp i/o4 i/o3 nc v dd i/o5 v dd nc h v ss i/o6 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o0 al du nc nc nc nc nc nc nc nc nc nc v ss nc nc nc nc rb i/o2 du nc du i/o1 10 9 r nc nc nc v ss du du du du du du du du du du du m l k j
nand01g-b2b, NAND02G-B2C me mory array organization 13/62 2 memory array organization the memory array is made up of nand structures where 32 cells are connected in series. the memory array is organized in blocks where each block contains 64 pages. the array is split into two areas, the main area and the spare area. the main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification. in x8 devices the pages are split into a 2048 byte main area and a spare area of 64 bytes. in the x16 devices the pages are split into a 1,024 word main area and a 32 word spare area. refer to figure 5: memory array organization . 2.1 bad blocks the nand flash 2112 byte/ 1056 word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to section 8.1: bad block management for more details). table 4: valid blocks shows the minimum number of valid blocks in each device. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. these blocks need to be managed using bad blocks management, block replacement or error correction codes (refer to section 8: software algorithms ). table 4. valid blocks density of device min max 2 gbits 2008 2048 1 gbit 1004 1024
memory array organizati on nand01g-b2b, NAND02G-B2C 14/62 figure 5. memory array organization ai09854 block = 64 pages page = 2112 bytes (2,048 + 64) 2,048 bytes 2048 bytes spare area 64 bytes block 8 bits 64 bytes 8 bits page page buffer, 2112 bytes block = 64 pages page = 1056 words (1024 + 32) 1,024 words 1024 words spare area main area 32 words 16 bits 32 words 16 bits page buffer, 1056 words block page x8 devices x16 devices main area
nand01g-b2b, NAND02G-B2C signals description 15/62 3 signals description see figure 2: logic diagram , and table 3: signal names , for a brief overview of the signals connected to this device. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x16 devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 3.3 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.4 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.5 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains selected and does not go into standby mode. 3.6 read enable (r ) the read enable pin, r , controls the sequential data output during read operations. data is valid t rlqv after the falling edge of r . the falling edge of r also increments the internal column address co unter by one.
signals description nand 01g-b2b, NAND02G-B2C 16/62 3.7 write enable (w ) the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time. 3.8 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.9 ready/busy (rb ) the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active . when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. refer to the section 11.1: ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. 3.10 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). an internal voltage detector disables all functions whenever v dd is below v lko (see ta bl e 2 2 and ta bl e 2 3 ) to protect the device from any involuntary program/erase during power-transitions. each device in a system should have v dd decoupled with a 0.1f capacitor. the pcb track widths should be sufficient to carry the required program and erase currents. 3.11 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
nand01g-b2b, nand02g -b2c bus operations 17/62 4 bus operations there are six standard bus operations that control the memory. each of these is described in this section, see table 5: bus operations , for a summary. typically, glitches of less than 5 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 4.1 command input command input bus operations are used to give commands to the memory. commands are accepted when chip enable is low, command latch enable is high, address latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 19 and ta b l e 2 4 for details of the timings requirements. 4.2 address input address input bus operations are used to input the memory addresses. four bus cycles are required to input the addresses for 1gb devices whereas five bus cycles are required for the 2gb device (refer to ta bl e 6 and ta b l e 7 , address insertion). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 20 and ta b l e 2 4 for details of the timings requirements. 4.3 data input data input bus operations are used to input the data to be programmed. data is accepted only when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 21 and ta b l e 2 4 and ta b l e 2 5 for details of the timings requirements. 4.4 data output data output bus operations are used to read: the data in the memory array, the status register, the lock status, the electronic signature and the unique identifier. data is output when chip enable is low, writ e enable is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal. see figure 22 and ta b l e 2 5 for details of the timings requirements.
bus operations nand01g-b2b, NAND02G-B2C 18/62 4.5 write protect write protect bus operations are used to pr otect the memory against program or erase operations. when the write protect signal is low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. the write protect signal is not latched by write enable to ensure protection even during power-up. 4.6 standby when chip enable is high the memory enters standby mode, the device is deselected, outputs are disabled and power consumption is reduced. table 5. bus operations bus operation e al cl r w wp i/o0 - i/o7 i/o8 - i/o15 (1) 1. only for x16 devices. command input v il v il v ih v ih rising x (2) 2. wp must be v ih when issuing a program or erase command. command x address input v il v ih v il v ih rising x address x data input v il v il v il v ih rising v ih data input data input data output v il v il v il fallin g v ih x data output data output write protect x x x x x v il xx standby v ih xxx x v il /v d d xx table 6. address insertion, x8 devices bus cycle (1) 1. any additional address input cycles will be ignored. i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd v il v il v il v il a11 a10 a9 a8 3 rd a19 a18 a17 a16 a15 a14 a13 a12 4 th a27 a26 a25 a24 a23 a22 a21 a20 5 th(2) 2. the fifth cycle is valid for 2gb dev ices. a28 is for 2gb devices only. v il v il v il v il v il v il v il a28
nand01g-b2b, nand02g -b2c bus operations 19/62 table 7. address insertion, x16 devices bus cycle (1) 1. any additional address input cycles will be ignored. i/o8- i/o15 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st x a7a6a5a4a3a2a1a0 2 nd x v il v il v il v il v il a10 a9 a8 3 rd x a18 a17 a16 a15 a14 a13 a12 a11 4 th x a26 a25 a24 a23 a22 a21 a20 a19 5 th(2) 2. the fifth cycle is valid for 2gb devices. a27 is for 2gb devices only. x v il v il v il v il v il v il v il a27 table 8. address definitions, x8 address definition a0 - a11 column address a12 - a17 page address a18 - a27 block address 1gb device a18 - a28 block address 2gb device table 9. address definitions, x16 address definition a0 - a10 column address a11 - a16 page address a17 - a26 block address 1gb device a17 - a27 block address 2gb device
command set nand01g-b2b, NAND02G-B2C 20/62 5 command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are selected by writing specific commands to the command register. the two-step command sequences for program and erase operations are imposed to maximize data security. the commands are summarized in table 10: commands . table 10. commands command bus write operations (1) 1. the bus cycles are only shown for issuing t he codes. the cycles re quired to input the addresses or input/output data are not shown. commands accepted during busy 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle read 00h 30h ? ? random data output 05h e0h ? ? cache read 00h 31h ? ? exit cache read 34h ? ? ? ye s (2) 2. only during cache read busy. page program (sequential input default) 80h 10h ? ? random data input 85h ? ? ? copy back program 00h 35h 85h 10h cache program 80h 15h ? ? block erase 60h d0h ? ? reset ffh ? ? ? ye s read electronic signature 90h ? ? ? read status register 70h ? ? ? ye s
nand01g-b2b, NAND02G-B2C device operations 21/62 6 device operations the following section gives the details of the device operations. 6.1 read memory array at power-up the device defaults to read mode. to enter read mode from another mode the read command must be issued, see table 10: commands . once a read command is issued two types of operations are available: random read and page read. 6.1.1 random read each time the read command is issued the first read is random read. 6.1.2 page read after the first random read access, the page data (2112 bytes or 1056 words) is transferred to the page buffer in a time of t whbh (refer to ta b l e 2 5 for value). once the transfer is complete the ready/busy signal goes high. the data can then be read out sequentially (from selected column address to last column address) by pulsing the read enable signal. the device can output random data in a page, instead of the consecutive sequential data, by issuing a random data output command . the random data output command can be used to skip some data during a sequential data output. the sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the random data output command. the random data output command can be issued as many times as required within a page. the random data output command is not accepted during cache read operations.
device operations nand 01g-b2b, NAND02G-B2C 22/62 figure 6. read operations 1. highest address depends on device density. cl e w al r i/o rb 00h ai08657b busy command code data output (sequentially) address input tblbh1 30h command code
nand01g-b2b, NAND02G-B2C device operations 23/62 figure 7. random data output during sequential data output i/o rb address inputs ai08658 data output busy tblbh1 (read busy time) 00h cmd code 30h address inputs data output 05h e0h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code cmd code cmd code 2add cycles main area spare area col add 1,2 r
device operations nand 01g-b2b, NAND02G-B2C 24/62 6.2 cache read the cache read operation is used to improve the read throughput by reading data using the cache register. as soon as the user starts to read one page, the device automatically loads the next page into the cache register. an cache read operation consists of three steps (see table 10: commands ): 1. one bus cycle is required to setup the cache read command (the same as the standard read command) 2. four or five (refer to ta b l e 6 and ta bl e 7 ) bus cycles are then required to input the start address 3. one bus cycle is required to issue the cache read confirm command to start the p/e/r controller. the start address must be at the beginning of a page (column address = 00h, see ta b l e 8 and ta bl e 9 ). this allows the data to be output uninterrupted after the latency time (t blbh1 ), see figure 8 the ready/busy signal can be used to monitor the start of the operation. during the latency period the ready/busy signal goes low, after this the ready/busy signal goes high, even if the device is internally downloading page n+1. once the cache read operation has started, the status register can be read using the read status register command. during the operation, sr5 can be read, to find out whether the internal reading is ongoing (sr5 = ?0?), or has completed (sr5 = ?1?), wh ile sr6 indicates whether the cache register is ready to download new data. to exit the cache read operation an exit cache read command must be issued (see ta bl e 1 0 ). if the exit cache read command is issued while the device is internally reading page n+1, pages n and n+1 will not be output. figure 8. cache read operation i/o rb address inputs ai13104 00h read setup code 31h cache read confirm code busy tblbh1 (read busy time) 1st page data output 2nd page 3rd page last page 34h exit cache read code block n tblbh4 r trhrl2 trhrl2
nand01g-b2b, NAND02G-B2C device operations 25/62 6.3 page program the page program operation is the standard operation to program data to the memory array. generally, the page is programmed sequentially, however the device does support random input within a page. it is recommended to address pages sequentially within a given block. the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed. the maximum number of consecutive partial page program operations allowed in the same page is four. after exceeding this a block erase command must be issued before any further program operations can take place in that page. 6.3.1 sequential input to input data sequentially the addresses must be sequential and remain in one block. for sequential input each page program operation consists of five steps (see figure 9 ): 1. one bus cycle is required to setup the pa ge program (sequential input) command (see ta bl e 1 0 ) 2. four or five bus cycles are then required to input the program address (refer to ta b l e 6 and ta bl e 7 ) 3. the data is then loaded into the data registers 4. one bus cycle is required to issue the page program confirm command to start the p/e/r controller. the p/e/r will only start if the data has been loaded in step 3. 5. the p/e/r controller then programs the data into the array. 6.3.2 random data input in a page during a sequential input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a random data input command. the following two steps are required to issue the command: 1. one bus cycle is required to setup the random data input command (see ta b l e 1 0 ) 2. two bus cycles are then required to input the new column address (refer to ta b l e 6 ) random data input can be repeated as often as required in any given page. once the program operation has started the status register can be read using the read status register command. during program ope rations the status register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read status register and reset commands will be accepted, all other comm ands will be ignored. once the program operation has completed the p/ e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface.
device operations nand 01g-b2b, NAND02G-B2C 26/62 figure 9. page program operation figure 10. random data input during sequential data input i/o rb address inputs sr0 ai08659 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time) i/o address inputs ai08664 data intput 80h cmd code address inputs data input 85h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code 2 add cycles main area spare area col add 1,2 rb busy tblbh2 (program busy time) sr0 10h 70h confirm code read status register
nand01g-b2b, NAND02G-B2C device operations 27/62 6.4 copy back program the copy back program operation is used to copy the data stored in one page and reprogram it in another page. the copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. the operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. if the copy back program operation fails an error is signalled in the status register. however as the standard external ecc cannot be used with the copy back program operation bit error due to charge loss cannot be detected. for this reason it is recommended to limit the number of copy back program operations on the same data and or to improve the performance of the ecc. the copy back program operation requires four steps: 1. the first step reads the source page. the operation copies all 1056 words/ 2112 bytes from the page into the data buffer. it requires: ? one bus write cycle to setup the command ? 4 or 5 bus write cycles to input the source page address (see ta bl e 6 and ta b l e 7 ) ? one bus write cycle to issue the confirm command code 2. when the device returns to the ready state (ready/busy high), the next bus write cycle of the command is given with the 4 or 5 bus cycles to input the target page address (see ta bl e 6 and ta bl e 7 ). refer to ta bl e 1 1 for the addresses that must be the same for the source and target pages. 3. then the confirm command is issued to start the p/e/r controller. to see the data input cycle for modifying the source page and an example of the copy back program operation refer to figure 11 . a data input cycle to modify a portion or a multiple distant portion of the source page, is shown in figure 12 . table 11. copy back program x8 addresses density same address for source and target pages 1 gbit no constraint 2 gbit a28 table 12. copy back program x16 addresses density same address for source and target pages 1 gbit no constraint 2 gbit a27
device operations nand 01g-b2b, NAND02G-B2C 28/62 figure 11. copy back program 1. copy back program is only permitted bet ween odd address pages or even address pages. figure 12. page copy back program with random data input i/o rb source add inputs ai09858b 85h copy back code read code read status register target add inputs tblbh1 (read busy time) busy tblbh2 (program busy time) 00h 10h 70h sr0 busy 35h i/o rb source add inputs ai11001 85h read code target add inputs tblbh1 (read busy time) 00h busy 35h 85h data 2 cycle add inputs data copy back code 10h 70h unlimited number of repetitions busy tblbh2 (program busy time) sr0
nand01g-b2b, NAND02G-B2C device operations 29/62 6.5 cache program the cache program operation is used to improve the programming throughput by programming data using the cache register. the cache program operation can only be used within one block. the cache register allo ws new data to be in put while the previous data that was transferred to the page buffer is programmed into the memory array. the following sequence is required to issue a cache program operation (refer to figure 13 ): 1. first of all the program setup command is issued: one bus cycle to issue the program setup command then 4 or 5 bus write cycles to input the address (see ta b l e 6 and ta bl e 7 ). the data is then input (up to 2112 bytes/ 1056 words) and loaded into the cache register. 2. one bus cycle is required to issue the confirm command to start the p/e/r controller. 3. the p/e/r controller then transfers the data to the page buffer. during this the device is busy for a time of t whbh2 . 4. once the data is loaded into the page buffer the p/e/r controller programs the data into the memory array. as soon as the cache registers are empty (after t whbh2 ) a new cache program command can be issued, wh ile the internal programming is still executing. once the program operation has started the status register can be read using the read status register command. during cache program operations sr5 can be read to find out whether the internal programming is ongoing (sr5 = ?0?) or has completed (sr5 = ?1?) while sr6 indicates whether the cache register is re ady to accept new data. if any errors have been detected on the previous page ( page n-1 ), the cache program error bit sr1 will be set to ?1', while if the error has been detected on page n the error bit sr0 will be set to '1?. when the next page (page n) of data is input with the cache program command, t whbh2 is affected by the pendin g internal programming. the data w ill only be transferred from the cache register to the page buffer when the pending program cycle is finished and the page buffer is available. if the system monitors the progress of the op eration using only the ready/busy signal, the last page of data must be programmed with the page program confirm command (10h). if the cache program confirm command (15h) is used instead, status register bit sr5 must be polled to find out if the last programming is finished before starting any other operations. figure 13. cache program operation 1. up to 64 pages can be programm ed in one cache program operation. 2. t cachepg is the program time for the last page + the program time for the (last ? 1) th page ? (program command cycle time + last page data loading time). i/o rb address inputs ai08672 80h page program code read status register busy data inputs 15h cache program code 80h page program code 15h cache program confirm code busy last page tblbh5 (cache busy time) tblbh5 tcachepg sr0 70h 80h 10h page program confirm code busy first page second page (can be repeated up to 63 times) address inputs data inputs address inputs data inputs
device operations nand 01g-b2b, NAND02G-B2C 30/62 6.6 block erase erase operations are done one block at a time. an erase operation sets all of the bits in the addressed block to ?1?. all previous data in the block is lost. an erase operation consists of three steps (refer to figure 14 ): 1. one bus cycle is required to setup the block erase command. only addresses a18- a28 (x8) or a17-a27 (x16) are used, the other address inputs are ignored. 2. two or three bus cycles are then required to load the address of the block to be erased. refer to ta b l e 8 and ta b l e 9 for the block addresses of each device. 3. one bus cycle is required to issue the block erase confirm command to start the p/e/r controller. the operation is initiated on the rising edge of write enable, w , after the confirm command is issued. the p/e/r controller handles block erase and implements the verify process. during the block erase operation, only the read status register and reset commands will be accepted, all other commands will be ignored. once the program operation has completed the p/ e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the operation completed successfully, the write status bit sr0 is ?0?, otherwise it is set to ?1?. figure 14. block erase operation 6.7 reset the reset command is used to reset the command interface and status register. if the reset command is issued during any operation, the operati on will be aborted. if it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be pa rtially programmed or erased. if the device has already been reset then the new reset command will not be accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was performing when the command was issued, refer to table 25: ac characteristics for operations for the values. i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time)
nand01g-b2b, NAND02G-B2C device operations 31/62 6.8 read status register the device contains a status register which provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register information is present on the output data bus (i/o0-i/ o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enab le signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read enable signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status register command is issued during a random read cycle a new read command must be issued to continue with a page read operation. the status register bits are summarized in table 13: status register bits ,. refer to ta bl e 1 3 in conjunction with the following text descriptions. 6.8.1 write protection bit (sr7) the write protection bit can be used to identify if the device is protected or not. if the write protection bit is set to ?1? the device is not protected and program or erase operations are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. 6.8.2 p/e/r contro ller and cache ready/busy bit (sr6) status register bit sr6 has two different functions depending on the current operation. during cache program operations sr6 acts as a cache program ready/busy bit, which indicates whether the cache register is ready to accept new data. when sr6 is set to '0', the cache register is busy and when sr6 is set to '1', the cache register is ready to accept new data. during all other operations sr6 acts as a p/e/r controller bit, which indicates whether the p/e/r controller is active or inactive. when th e p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is bu sy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). 6.8.3 p/e/r contro ller bit (sr5) the program/erase/read controller bit indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is busy); when the bit is set to ?1?, the p/e/ r controller is inactive (device is ready).
device operations nand 01g-b2b, NAND02G-B2C 32/62 6.8.4 cache progra m error bit (sr1) the cache program error bit can be used to identify if the previous page (page n-1) has been successfully programmed or not in a cache program operation. sr1 is set to ?1? when the cache program operation has failed to program the previous page (page n-1) correctly. if sr1 is set to ?0? the operation has completed successfully. the cache program error bit is only valid during cache program operations, during other operations it is don?t care. 6.8.5 error bit (sr0) the error bit is used to identify if any errors have been detected by the p/e/r controller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0? the operation has completed successfully. the error bit sr0, in a cache program operation, indicates a failure on page n. 6.8.6 sr4, sr3 and sr2 are reserved table 13. status register bits bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 program/ erase/ read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy cache ready/busy '1' cache register ready (cache operation only) '0' cache register busy (cache operation only) sr5 program/ erase/ read controller (1) '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy sr4, sr3, sr2 reserved don?t care sr1 cache program error (2) '1' page n-1 failed in cache program operation '0' page n-1 programmed successfully sr0 generic error ?1? error ? operation failed ?0? no error ? operation successful cache program error ?1? page n failed in cache program operation ?0? page n programmed successfully 1. only valid for cache progr am operations, for other operations it is same as sr6. 2. only valid for cache operations, for other operations it is don?t care.
nand01g-b2b, NAND02G-B2C device operations 33/62 6.9 read electronic signature the device contains a manufacturer code and device code. to read these codes three steps are required: 1. one bus write cycle to issue the read electronic signature command (90h) 2. one bus write cycle to input the address (00h) 3. four bus read cycles to sequentially output the data (as shown in table 14: electronic signature ). table 14. electronic signature part number byte/word 1 byte/word 2 byte/word 3 (see table 15 ) byte/word 4 (see table 16 ) manufacturer code device code nand01gr3b2b 20h a1h 80h 15h nand01gw3b2b f1h 1dh nand01gr4b2b 0020h b1h 55h nand01gw4b2b c1h 5dh nand02gr3b2c 20h aah 15h nand02gw3b2c dah 1dh nand02gr4b2c 0020h bah 55h nand02gw42c cah 5dh table 15. electronic signature byte 3 i/o definition value description i/o1-i/o0 internal chip number 0 0 0 1 1 0 1 1 1 2 4 8 i/o3-i/o2 cell type 0 0 0 1 1 0 1 1 2-level cell 4-level cell 8-level cell 16-level cell i/o5-i/o4 number of simultaneously programmed pages 0 0 0 1 1 0 1 1 1 2 4 8 i/o6 interleaved programming between multiple devices 0 1 not supported supported i/o7 cache program 0 1 not supported supported
device operations nand 01g-b2b, NAND02G-B2C 34/62 table 16. electronic signature byte/word 4 i/o definition value description i/o1-i/o0 page size (without spare area) 0 0 0 1 1 0 1 1 1kbytes 2kbytes reserved reserved i/o2 spare area size (byte / 512 byte) 0 1 8 16 i/o7, i/o3 minimum sequential access time 0 0 0 1 1 0 1 1 50ns 30ns 25ns reserved i/o5-i/o4 block size (without spare area) 0 0 0 1 1 0 1 1 64kbytes 128kbytes 256kbytes reserved i/o6 organization 0 1 x8 x16
nand01g-b2b, nand02g-b 2c data protection 35/62 7 data protection the device has hardware features to protect against program and erase operations. it features a write protect, wp , pin, which can be used to protect the device against program and erase operations. it is recommended to keep wp at v il during power-up and power- down. in addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever v dd is below v lko (see ta b l e 2 2 and ta bl e 2 3 ).
software algorithms nand 01g-b2b, NAND02G-B2C 36/62 8 software algorithms this section gives information on the software algorithms that st recommends to implement to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunneling using a high voltage. exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. for this reason, the number of program and erase cycles is limited (see ta b l e 1 8 for value) and it is recommended to implement garbage collection, a wear-leveling algorithm and an error correction code, to extend the number of program and erase cycles and increase the data retention. to help integrate a nand memory into an applic ation st microelectronics can provide a file system os native reference software, whic h supports the basic commands of file management. contact the nearest st microelectronics sales office for more details. 8.1 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block, where the 1st and 6th bytes, or 1st word, in the spare area of the 1st page, does not contain ffh, is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in figure 15 . 8.2 nand flash memory failure modes over the lifetime of the device additional bad blocks may develop. to implement a highly reliable system, all the possible failure modes must be considered: program/erase failure: in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see section 6.4: copy back program for more details. read failure: in this case, ecc correction must be implemented. to efficiently use the memory space, it is recommended to recover single-bit error in read by ecc, without replacing the whole block. refer to ta b l e 1 7 for the procedure to follow if an error occurs during an operation.
nand01g-b2b, NAND02G-B2C software algorithms 37/62 figure 15. bad block management flowchart figure 16. garbage collection table 17. nand flash failure modes operation procedure erase block replacement program block replacement or ecc read ecc ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table valid page invalid page free page (erased) old area ai07599b new area (after gc)
software algorithms nand 01g-b2b, NAND02G-B2C 38/62 8.3 garbage collection when a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. after several updates it is necessary to remove invalid pages to free some memory space. to free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm. in a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see figure 16 ). 8.4 wear-leveling algorithm for write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algorithm not all blocks get used at the same rate. blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: first level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. the second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. 8.5 error correction code an error correction code (ecc) can be implemented in the nand flash memories to identify and correct errors in the data. for every 2048 bits in the device it is recommended to implement 22 bits of ecc (16 bits for line parity plus 6 bits for column parity). an ecc model is available in vhdl or verilog. contact the nearest st microelectronics sales office for more details.
nand01g-b2b, NAND02G-B2C software algorithms 39/62 figure 17. error detection 8.6 hardware simulation models 8.6.1 behavioral simulation models denali software corporation models are platform independent functional models designed to assist customers in perfor ming entire system simulations (typical vhdl/verilog). these models describe the logic behavior and timings of nand flash devices, and so allow software to be developed before hardware. 8.6.2 ibis simulations models ibis (i/o buffer information specification) models describe the behavior of the i/o buffers and electrical characteristics of flash devices. these models provide information such as ac characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. ibis models are used to simu late pcb connections and can be used to resolve compatibility issues when upgrading devices. they can be imported into spicetools. new ecc generated during read xor previous ecc with new ecc all results = zero? 22 bit data = 0 yes 11 bit data = 1 no 1 bit data = 1 correctable error ecc error no error ai08332 >1 bit = zero? yes no
program and erase times and endura nce cycles nand01g- b2b, NAND02G-B2C 40/62 9 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 8 . table 18. program, erase times and program erase endurance cycles parameters nand flash unit min typ max page program time 200 700 s block erase time 2 3ms program/erase cycles (per block) 100,000 cycles data retention 10 years
nand01g-b2b, nand02g -b2c maximum rating 41/62 10 maximum rating stressing the device above the ratings listed in table 19: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 19. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) 1. minimum voltage may undershoot to ?2v for less than 20ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2v for less than 20ns duri ng transitions on i/o pins. input or output voltage 1.8v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v v dd supply voltage 1.8v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v
dc and ac parameters nand01g-b2b, NAND02G-B2C 42/62 11 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 20: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. table 20. operating and ac measurement conditions parameter nand flash units min max supply voltage (v dd ) 1.8v devices 1.7 1.95 v 3v devices 2.7 3.6 v ambient temperature (t a ) grade 1 0 70 c grade 6 ?40 85 c load capacitance (c l ) (1 ttl gate and c l ) 1.8v devices 30 pf 3v devices (2.7 - 3.6v) 50 pf input pulses voltages 1.8v devices 0 v dd v 3v devices 0.4 2.4 v input and output timing ref. voltages v dd /2 v output circuit resistor r ref 8.35 k ? input rise and fall times 5 ns table 21. capacitance (1) 1. t a = 25c, f = 1 mhz. c in and c i/o are not 100% tested symbol parameter test condition typ max unit c in input capacitance v in = 0v 10 pf c i/o input/output capacitance (2) 2. input/output capacitances double in stacked devices v il = 0v 10 pf
nand01g-b2b, NAND02G-B2C dc and ac parameters 43/62 figure 18. equivalent testing circuit for ac characteristics measurement table 22. dc characteristics, 1.8v devices symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma -815ma i dd2 program - - 8 15 ma i dd3 erase - - 8 15 ma i dd5 standby current (cmos) (1) e =v dd -0.2, wp =0/v dd - 10 50 a i li input leakage current (1) v in = 0 to v dd max - - 10 a i lo output leakage current (1) v out = 0 to v dd max - - 10 a v ih input high voltage - v dd -0.4 - v dd +0.3 v v il input low voltage - -0.3 - 0.4 v v oh output high voltage level i oh = -100a v dd -0.1 - - v v ol output low voltage level i ol = 100a - - 0.1 v i ol (rb ) output low current (rb ) v ol = 0.1v 3 4 ma v lko v dd supply voltage (erase and program lockout) - - - 1.1 v 1. leakage current and standby curr ent double in stacked devices ai11085 nand flash c l 2r ref v dd 2r ref gnd gnd
dc and ac parameters nand01g-b2b, NAND02G-B2C 44/62 table 23. dc characteristics, 3v devices symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma -1020ma i dd2 program - -1020 ma i dd3 erase - -1020 ma i dd4 standby current (ttl) (1) e=v ih , wp =0/v dd 1 ma i dd5 standby current (cmos) (1) e =v dd -0.2, wp =0/v dd - 10 50 a i li input leakage current (1) v in = 0 to v dd max - - 10 a i lo output leakage current (1) v out = 0 to v dd max - - 10 a v ih input high voltage - 0.8v dd - v dd +0.3 v v il input low voltage - -0.3 - 0.2v dd v v oh output high voltage level i oh = -400a 2.4 - - v v ol output low voltage level i ol = 2.1ma - - 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4v 8 10 ma v lko v dd supply voltage (erase and program lockout) - - - 1.7 v 1. leakage current and standby current double in stacked devices
nand01g-b2b, NAND02G-B2C dc and ac parameters 45/62 table 24. ac characteristics for command, address, data input symbol alt. symbol parameter 1.8v devices 3v devices unit t allwh t als address latch low to write enable high al setup time min 25 15 ns t alhwh address latch high to write enable high t clhwh t cls command latch high to write enable high cl setup time min 25 15 ns t cllwh command latch low to write enable high t dvwh t ds data valid to write enable high data setup time min 20 15 ns t elwh t cs chip enable low to write enable high e setup time min 35 20 ns t whalh t alh write enable high to address latch high al hold time min 10 5 ns t whall write enable high to address latch low al hold time min t whclh t clh write enable high to command latch high cl hold time min 10 5 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 10 5 ns t wheh t ch write enable high to chip enable high e hold time min 10 5 ns t whwl t wh write enable high to write enable low w high hold time min 15 10 ns t wlwh t wp write enable low to write enable high w pulse width min 25 15 ns t wlwl t wc write enable low to write enable low write cycle time min 45 30 ns
dc and ac parameters nand01g-b2b, NAND02G-B2C 46/62 table 25. ac characteristics for operations (1) symbol alt. symbol parameter 1.8v devices 3v devices unit t allrl1 t ar address latch low to read enable low read electronic signature min 10 10 ns t allrl2 read cycle min 10 10 ns t bhrl t rr ready/busy high to read enable low min 20 20 ns t blbh1 ready/busy low to ready/busy high read busy time max 25 25 s t blbh2 t prog program busy time max 700 700 s t blbh3 t bers erase busy time max 3 3 ms t blbh4 reset busy time, during ready max 5 5 s t blbh5 t cbsy cache busy time ty p 3 3 s max 700 700 s t whbh1 t rst write enable high to ready/busy high reset busy time, during read max 5 5 s reset busy time, during program max 10 10 s reset busy time, during erase max 500 500 s t cllrl t clr command latch low to read enable low min 10 10 ns t dzrl t ir data hi-z to read enable low min 0 0 ns t ehqz t chz chip enable high to output hi-z max 30 30 ns t rhqz t rhz read enable high to output hi-z max 30 30 ns t whwh t adl (2) last address latched to data loading time during program operations min 100 100 ns t vhwh t vlwh t ww (3) write protection time min 100 100 ns t rhrl2 t crrh read enable high hold time during cache read operation min 50 50 ns t elqv t cea chip enable low to output valid max 45 25 ns t rhrl t reh read enable high to read enable low read enable high hold time min 15 10 ns t ehqx t oh chip enable high or read enable high to output hold min 10 10 ns t rhqx t rlrh t rp read enable low to read enable high read enable pulse width min 25 15 ns t rlrl t rc read enable low to read enable low read cycle time min 50 30 ns t rlqv t rea read enable low to output valid read enable access time max 30 20 ns read es access time (4) t whbh t r write enable high to ready/busy high read busy time max 25 25 s t whbl t wb write enable high to ready/busy low max 100 100 ns t whrl t whr write enable high to read enable low min 60 60 ns
nand01g-b2b, NAND02G-B2C dc and ac parameters 47/62 figure 19. command latch ac waveforms 1. the time to ready depends on the value of the pul l-up resistor tied to the ready/busy pin. see figure 31 , figure 32 and figure 33 . 2. t whwh is the time from w rising edge during the fi nal address cycle to w rising edge during the first data cycle. 3. during a program/erase enable operation, t ww is the delay from wp high to w high. during a program/erase disable operation, t ww is the delay from wp low to w high. 4. es = electronic signature. ai13105 cl e w al i/o tclhwh telwh twhcll twheh twlwh tallwh twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) h(e setup time) (e hold time)
dc and ac parameters nand01g-b2b, NAND02G-B2C 48/62 figure 20. address latch ac waveforms 1. a fifth address cycle is r equired for 2gb devices only. figure 21. data input latch ac waveforms 1. data in last is 2112 in x8 devices and 1056 in x16 devices. ai13106 cl e w al i/o twlwh telwh twlwl tcllwh twhwl talhwh tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time) adrress cycle 5 twlwl twlwh tdvwh twhdx twhwl twhall twhclh cl e al w i/o tallwh twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai13107 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time)
nand01g-b2b, NAND02G-B2C dc and ac parameters 49/62 figure 22. sequential data output after read ac waveforms 1. cl = low, al = low, w = high. figure 23. read status register ac waveform e ai08031 r i/o rb trlrl trlqv trhrl trlqv data out data out data out trhqz tbhrl trlqv trhqz tehqz (read cycle time) (r accesstime) (r high holdtime) telwh tdvwh status register output 70h cl e w r i/o tclhwh twhdx twlwh twhcll tcllrl tdzrl trlqv tehqz trhqz twhrl telqv twheh ai13108 (data setup time) (data hold time)
dc and ac parameters nand01g-b2b, NAND02G-B2C 50/62 figure 24. read electronic signature ac waveform 1. refer to table 14 for the values of the manufacturer and device codes, and to table 15 and table 16 for the information contained in byte 3 and 4. 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address ai08667 (read es access time) tallrl1 00h byte4 byte3 byte1 byte2 see note.1
nand01g-b2b, NAND02G-B2C dc and ac parameters 51/62 figure 25. page read operation ac waveform 1. a fifth address cycle is r equired for 2gb devices only. cl e w al r i/o rb twlwl twhbl tallrl2 00h data n data n+1 data n+2 data last twhbh trlrl tehqz trhqz ai13109b busy command code address n input data output from address n to last byte or word in page add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (read cycle time) trlrh tblbh1 30h add.n cycle 5
dc and ac parameters nand01g-b2b, NAND02G-B2C 52/62 figure 26. page program ac waveform 1. a fifth address cycle is r equired for 2gb devices only. cl e w al r i/o rb sr0 ai13110b n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time) add.n cycle 5 twhwh
nand01g-b2b, NAND02G-B2C dc and ac parameters 53/62 figure 27. block erase ac waveform 1. address cycle 3 is requ ired for 2gb devices only. figure 28. reset ac waveform d0h 60h sr0 70h ai08038b twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 w r i/o rb tblbh4 al cl ffh ai08043 (reset busy time)
dc and ac parameters nand01g-b2b, NAND02G-B2C 54/62 figure 29. program/erase enable waveform figure 30. program/erase disable waveform 11.1 ready/busy signal electrical characteristics figure 32 , figure 31 and figure 33 show the electrical charac teristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: so, where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . w rb tvhwh ai12477 wp i/o 80h 10h w rb tvlwh ai12478 wp i/o 80h 10h high r p min v ddmax v olmax ? () i ol i l + ------------------------------------------------------------- = r p min 1.8v () 1.85v 3ma i l + --------------------------- = r p min 3v () 3.2v 8ma i l + --------------------------- =
nand01g-b2b, NAND02G-B2C dc and ac parameters 55/62 figure 31. ready/busy ac waveform figure 32. ready/busy load circuit ai07564b busy v oh ready v dd v ol t f t r ai07563b r p v dd v ss rb device open drain output ibusy
dc and ac parameters nand01g-b2b, NAND02G-B2C 56/62 figure 33. resistor value versus waveform timings for ready/busy signal 1. t = 25c. 11.2 data protection the st nand device is designed to guarantee data protection during power transitions. a v dd detection circuit disables all nand operations, if v dd is below the v lko threshold. in the v dd range from v lko to the lower limit of nominal range, the wp pin should be kept low (v il ) to guarantee hardware protection during power transitions as shown in the below figure. figure 34. data protection ai07565b r p (k ?) 12 34 100 300 200 t r , t f (ns) 1 2 3 1.7 0.85 30 1.7 1.7 1.7 1.7 t r t f ibusy 0 400 4 r p (k ?) 12 34 100 300 200 1 2 3 ibusy (ma) 2.4 1.2 0.8 0.6 100 200 300 400 3.6 3.6 3.6 3.6 0 400 4 v dd = 1.8v, c l = 30pf v dd = 3.3v, c l = 100pf t r , t f (ns) ibusy (ma) 60 90 120 0.57 0.43 ai11086 v lko v dd w nominal range locked locked
nand01g-b2b, nand02g-b 2c package mechanical 57/62 12 package mechanical figure 35. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 26. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 3 0 5 3 0 5
package mechanical nand 01g-b2b, NAND02G-B2C 58/62 figure 36. vfbga63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, package outline 1. drawing is not to scale e d eb sd se a2 a1 a bga-z67 ddd fd1 d2 e2 e fe fe1 e e1 d1 fd ball "a1" table 27. vfbga63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.05 0.0413 a1 0.25 0.0098 a2 0.70 0.0276 b 0.45 0.40 0.50 0.0177 0.0157 0.0197 d 9.50 9.40 9.60 0.3740 0.3701 0.3780 d1 4.00 0.1575 d2 7.20 0.2835 ddd 0.10 0.0039 e 12.00 11.90 12.10 0.4724 0.4685 0.4764 e1 5.60 0.2205 e2 8.80 0.3465 e 0.80 ? ? 0.0315 ? ? fd 2.75 0.1083 fd1 1.15 0.0453 fe 3.20 0.1260 fe1 1.60 0.0630 sd 0.40 0.0157 se 0.40 0.0157
nand01g-b2b, nand02g-b 2c package mechanical 59/62 figure 37. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline 1. drawing is not to scale e d e d1 sd fd se b a2 fe a1 a bga-z75 ddd fd1 d2 e2 e1 e fe1 ball "a1" table 28. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a1.050.041 a1 0.25 0.010 a2 0.70 0.028 b 0.45 0.40 0.50 0.018 0.016 0.020 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 4.00 0.157 d2 7.20 0.283 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 5.60 0.220 e2 8.80 0.346 e0.80??0.031?? fd 2.50 0.098 fd1 0.90 0.035 fe 2.70 0.106 fe1 1.10 0.043 sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ?
part numbering nand01g-b2b, NAND02G-B2C 60/62 13 part numbering devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. table 29. ordering information scheme example: nand02gr3b2c za 6 e device type nand flash memory density 01g = 1gb 02g = 2gb operating voltage r = v dd = 1.7 to 1.95v w = v dd = 2.7 to 3.6v bus width 3 = x8 4 = x16 (1) 1. x16 organization only av ailable for mcp products. family identifier b = 2112 bytes/ 1056 word page device options 2 = chip enable don't care enabled product version b= second version (1gb devices) c= third version (2gb devices) package n = tsop48 12 x 20mm za = vfbga63 9.5 x 12 x 1mm, 0.8mm pitch (2) 2. for NAND02G-B2C devices only. za= vfbga63 9 x 11 x 1mm, 0.8mm pitch (3) 3. for nand01g-b2b devices only. temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option e = lead free package, standard packing f = lead free package, tape & reel packing
nand01g-b2b, NAND02G-B2C revision history 61/62 14 revision history table 30. document revision history date version revision details 18-may-2006 0.1 first issue 01-jun-2006 1 datasheet status changed to preliminary data. 09-jun-2006 2 vfbga63 9x11x1mm package added for nand01g-b2b devices and vfbga63 9.5x12x1mm dedicated to NAND02G-B2C devices. 23-nov-2006 3 note 2 below commands removed. overview of section 6.1: read memory array updated. paragraph concerning exit cache read command updated in section 6.2: cache read . block replacement section replaced by section 8.2: nand flash memory failure modes . t whall added in table 24: ac characteristics for command, address, data input . rb waveform updated in figure 25: page read operation ac waveform , and cl waveform modified in figure 26: page program ac waveform .
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