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? semiconductor ML50000 1/26 ? semiconductor ML50000 echo canceler general description the ML50000 is an echo canceler with improved characteristics for the speakerphone applications, such as hands-free phones. (the ML50000 can also be used for line echo suppression.) the ML50000 is a low power cmos lsi device for canceling echo (in acoustic or line systems) generated in the communication path. using digital signal processing, the echo path is estimated and a pseudo-echo signal is generated to cancel the echo. when used as an acoustic echo canceler, the device cancels the acoustic echo generated between a loud speaker and a microphone, occurring during hands-free communication such as when using a cellular phone or a conference system phone. when used as a line echo canceler, the device cancels the line echo caused by hybrid impedance mismatching. the ML50000 enables high quality telephone communication by preventing howling and controlling levels with howling detection, double talk detection, attenuator function, and gain control functions, and by suppressing low level noise with a center clipper function. the i/o interface of the ML50000 supports m -law pcm. use of a single chip codec such as the msm7704 (3v) or the msm7533 (5v) allows economical and highly efficient echo canceller units to be configured. features ? compatible with echo paths that amplify e.r.l. ? an improved center clipper function (nlp) attenuates echo of 50 db or more when nlp is used. ? fast convergencetime (as compared to the msm7620). ? supports abrupt changes in the echo path. no need to reset for each communication. ? the gain control function (gc) becomes effective at the level of C10 dbm0. ? cancellable echo delay time: ML50000-001 .............................. for a single chip: 21 ms (max.) ML50000-011 .............................. for a cascade connection (can also be used for a single chip) master chip: 21 ms (max.) slave chip: 31 ms (max.) cancelable up to 207 ms (1 master plus 6 slaves) for a single chip: 21 ms (max.) ? echo attenuation : 30 db (typ.) ? clock frequency : 19.2 mhz 17.5 to 20 mhz (when the internal sync signal is not used) ? power supply voltage : 2.7 v to 5.5 v ? package 28 pin plastic ssop (ssop28-p-485-0.65-k) (product name: ML50000-001gs-k) 56 pin plastic qfp (qfp56-p-910-0.65-2k) (product name: ML50000-011gs-2k) e2u0066-28-92 this version: sep. 1998 preliminary
? semiconductor ML50000 2/26 block diagram ML50000-001 (single chip only) howling detector double talk detector power calculator adaptive fir filter (aff) nonClinear/ linear s/p att gain linear/ nonClinear p/s nonClinear/ linear s/p + + C att linear/ nonClinear p/s center clip rin rout sout sin rst v dd v ss wdt pwdwn clock generator mode selector i/o controller int irld sck sync nlp hcl adp att gc synco scko x2 x1/clkin mcko * hd ML50000-011 (cascade connection or single chip) howling detector double talk detector power calculator nonClinear/ linear s/p att gain linear/ nonClinear p/s nonClinear/ linear s/p + + C att linear/ nonClinear p/s center clip rin rout sout sin rst * v dd * v ss * wdt * pwdwn clock generator mode selector i/o controller int * irld sck sync nlp hcl * adp att gc synco scko x2 x1/clkin * sf2 * sf1 * of2 * of1 * pd 0 * pd15 * ms * adaptive fir filter (aff) parallel i/o controller parallel i/o port e * if the ML50000-011 is used in the slave mode, only the diagonally hatched blocks and the p ins marked with * are used. mcko * hd
? semiconductor ML50000 3/26 pin configuration (top view) 28-pin plastic ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin 1 2 3 4 5 6 7 symbol nlp hcl adp v dd att int irld pin 8 9 10 11 12 13 14 symbol sin rin sck sync sout rout v ss pin 15 16 17 18 19 20 21 symbol v ss hd x1/clkin x2 v dd pwdwn v ss pin 22 23 24 25 26 27 28 symbol synco scko rst wdt gc v dd mcko
? semiconductor ML50000 4/26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 28 16 17 18 19 20 21 22 23 24 25 26 27 56 43 55 54 53 52 51 50 49 48 47 46 45 44 56-pin plastic qfp pin 1 2 3 4 5 6 7 symbol hcl adp ms att int irld sin pin 15 16 17 18 19 20 21 symbol pd0 pd1 pd2 pd3 pd4 pd5 v ss pin 29 30 31 32 33 34 35 symbol pd12 pd13 x1/clkin x2 v dd pwdwn synco pin 43 44 45 46 47 48 49 symbol * pd14 pd15 mcko sf2 of1 v ss *: no connect pin 8 22 pd6 36 scko 50 * nlp rin 9 23 pd7 37 rst 51 v ss sck 10 24 pd8 38 wdt 52 sf1 sync 11 25 pd9 39 gc 53 of2 sout 12 26 pd10 40 54 v dd rout 13 27 pd11 41 v dd 55 v dd v ss 14 28 hd 42 v dd 56 * v ss
? semiconductor ML50000 5/26 pin descriptions (1/5) pin 28-pin ssop 56-pin qfp symbol type description 1 1 nlp i 2 2 hcl i 3 3 adp i 4 ms i control pin for the center clipping function. this pin forces the sout output to a minimum value when the sout signal is below C36 dbm0. effective for reducing low-level noise. ? single chip or master chip in a cascade connection "h": center clip on "l": center clip off ? slave chip in a cascade connection fixed at "l" this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. through mode control. when this pin is in the through mode, rin and sin data is output to rout and sout. at the same time, the coefficient of the adaptive fir filter is cleared. ? single chip or master chip in a cascade connection "h": through mode "l": normal mode (echo canceler operates) ? slave chip in a cascade connection same as master this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. aff coefficient control. this pin stops updating of the adaptive fir filter (aff) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. this pin is used when holding the aff coefficient which has been once converged. ? single chip or master chip in a cascade connection "h": coefficient fix mode "l": normal mode (coefficient update) ? slave chip in a cascade connection fixed at "l" this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. select signal. this pin selects between the master chip and slave chip when used in a cascade connection. "l": single chip or master chip "h": slave chip
? semiconductor ML50000 6/26 (2/5) pin 28-pin ssop 56-pin qfp symbol type description 5 5 att i 66 int i 77 irld o 8 8 sin i 9 9 rin i 10 10 sck i control for the att function. this pin prevents howling by attenuators (att) for the rin input and sout output. if there is input only to rin, the att for the sout output is activated. if there is no input to sin, or if there is input to both sin and rin, the att for the rin input is activated. either the att for the rin output or the att for the sout is always activated in all cases, and the attenuation of att is 6 db. ? single chip or master chip in a cascade connection "h": att off "l": att on "l" is recommended if performing echo cancellation. ? slave chip in a cascade connection fixed at "l" this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. interrupt signal which starts 1 cycle (8 khz) of the signal processing. signal processing starts when "h"-to-"l" transition is detected. ? single chip or master chip in a cascade connection connect the irld pin. ? slave chip in a cascade connection connect the irld pin of the master chip. int input is invalid for 100 m s after reset due to initialization. refer to the control pin connection example. load detection signal output when the sin and rin serial input data is loaded in the internal registers. ? single chip connect to the int pin. ? master chip in a cascade connection connect to the int pin of the master chip and all the slave chips. ? slave chip in a cascade connection leave open. refer to the control pin connection example. transmit serial data. input the pcm signal synchronized to sync and sck. data is read in at the falling edge of sck. receive serial data. input the pcm signal synchronized to sync and sck. data is read at the falling edge of sck. clock input for transmit/receive serial data. this pin uses the external sck or the scko. input the pcm codec transmit/receive clock (64 to 2048 khz).
? semiconductor ML50000 7/26 (3/5) pin 28-pin ssop 56-pin qfp symbol type description 11 11 sync i 12 12 sout o 13 13 rout o 15 20 22 27 29 30 44 45 pd0 pd5 pd6 pd11 pd12 pd13 pd14 pd15 i/o 17 31 x1/clkin i 18 32 x2 o 16 28 hd i sync signal for transmit/receive serial data. this pin uses the external sync or synco. input the pcm codec transmit/receive sync signal (8 khz). transmit serial data. outputs the pcm signal synchronized to sync and sck. this pin is in a high impedance state during no data output. receive serial data. outputs the pcm signal synchronized to sync and sck. this pin is in a high impedance state during no data output. this is the bidirectional bus pin for parallel data transfer between the master chip and slave chip when used in a cascade connection. the pd15 pin corresponds to msb. this pin is in a high impedance state during no data output. data is loaded in at the falling edge of sfx . controls the howling detect function. this pin detets and cancels a howling generated during hand-free talking for acoustic system. this function is used to cancel acoustic echoes. ? single chip or master chip in a cascade connection "l": howling detector on "h": howling detector off ? slave chip in a cascade connection fixed at "l" external input for the basic clock (17.5 to 20 mhz) or for the crystal oscillator. when the internal sync signal (synco, scko) is used, input the basic clock of 19.2 mhz. crystal oscillator output. used to configure the oscilation circuit. refer to the internal clock generator circuit example.
? semiconductor ML50000 8/26 (4/5) pin 28-pin ssop 56-pin qfp symbol type description 22 36 synco o 23 37 scko o 24 38 rst i 25 39 wdt o 26 40 gc i input signal by which the gain controller for the rin input is controlled and the rin input level is controlled and howling is prevented. the gain controller adjusts the rin input level when it is C10 dbm0 or above. rin input levels from C10 to C1.5 dbm0 will be suppressed to C10 dbm0 in the attenuation range from 0 to 8.5 db. rin input levels above C1.5 dbm0 will always be attenuated by 8.5 db. ? single chip or master chip in a cascade connection "h": gain control on "l": gain control off "h" is recommended for echo cancellation. ? slave chip in a cascade connection fixed at "l" this pin is loaded in synchronization with the falling edge of the int signal or the rising edge of rst . test program end signal. this signal is output when the one cycle (8khz) of processing is completed. leave it open. reset signal. "l": reset mode "h": normal operation mode due to initialization, input signals are disabled for 100 m s after reset (after rst is returned from l to h). input the basic clock during the reset. output pins during the reset are in the following states : high impedance: sout, rout, pd0 to 15 "l": wdt "h": of1 , of2 not affected: x2, synco, scko, irld , mcko transmit clock signal (256 khz) for the pcm codec. connect to the sck pin and the pcm codec transmit/receive clock pin. leave it open if using an external sck. 8 khz sync signal for the pcm codec. connect to the sync pin and the pcm codec transmit/receive sync pin. leave it open if using an external sync. 20 34 pwdwn i power-down mode control when powered down. "l": power-down mode "h": normal operation mode during power-down mode, all input pins are disabled and output pins are in the following states : high impedance : sout, rout, pd0 to 15 "l": synco, scko, mcko "h": of1 , of2 , x2 holds the last state : wdt, irld reset after the power-down mode is released.
? semiconductor ML50000 9/26 (5/5) pin 28-pin ssop 56-pin qfp symbol type description 47 sf2 i 48 of1 o 52 sf1 i 53 of2 o parallel data output flag. ? single chip connect to sf1 . ? master chip in a cascade connection connect to sf2 of the 1st stage slave chip. ? slave chip in a cascade connection leave open. refer to the control pin connection example. parallel data transfer flag. ? single chip connect of2 . ? master chip in a cascade connection connect of1 of the last stage slave chip. ? slave chip in a cascade connection connect of1 of master chip for all slave chips. refer to the control pin connection example. parallel data transfer flag. ? single chip leave open. ? master chip in a cascade connection connect to the sf1 of all slaves. ? slave chip in a cascade connection connect to the sf2 of the next stage slave chip. connect the last stage slave chip to the sf1 of the master chip. refer to the control pin connection example. parallel data transfer flag. ? single chip fixed at "h" ? master chip in a cascade connection fixed at "h" ? slave chip in a cascade connection connect of2 of the master chip to the 1st stage slave chip. connect of1 of the previous stage slave chip to the 2nd and later stage slave chips. refer to the control pin connection example. 28 46 mcko o basic clock.
? semiconductor ML50000 10/26 absolute maximum ratings parameter power supply voltage input voltage power dissipation storage temperature symbol v dd v in p d t stg condition ta = 25?c rating C0.3 to +7 C0.3 to v dd + 0.3 1 C55 to +150 unit v v w ?c recommended operating conditions electrical characteristics dc characteristics (v dd = 2.7 v to 3.6 v, ta = C40?c to +85?c) parameter output load capacitance input capacitance power supply current (stand-by) power supply current (operating) c load c i i dds i ddo pwdwn = "l" 20 10 20 15 30 50 pf pf ma m a C60 C1 C33 C0.1 C6 m a m a low level output leakage current i ozl v ol = v ss pd15 to pd0 with pull-up input other than the above high level output voltage low level output voltage high level input current low level input current high level output leakage current symbol condition min. typ. max. unit 0.1 1 m a C60 C33 C6 m a C1 C0.1 m a 6 60 120 m a 0.1 1 m a 0 0.4 v 2.2 v dd v v oh v ol i ih i il i ozh i oh = 40 m a i ol = 1.6 ma v ih = v dd ms with pull-down v il = v ss sf1 , sf2 with pull-up v oh = v dd parameter power supply voltage power supply voltage high level input voltage low level input voltage operating temperature symbol v dd v ss v ih v il ta condition pins other than x1 min. 2.7 2.0 0 C40 unit v v v v ?c typ. 3.3 0 +25 max. 3.6 v dd 0.5 +85 (v dd = 2.7 v to 3.6 v) x1 pin 2.2 v v dd parameter power supply voltage power supply voltage high level input voltage low level input voltage operating temperature symbol v dd v ss v ih v il ta condition pins other than x1, sck min. 4.5 2.4 0 C40 unit v v v v ?c typ. 5 0 +25 max. 5.5 v dd 0.8 +85 (v dd = 4.5 v to 5.5 v) x1, sck pins 3.5 v v dd
? semiconductor ML50000 11/26 condition min. typ. max. unit parameter symbol output load capacitance input capacitance input capacitance power supply current (operating) i ddo i dds c i c load pwdwn = "l" 30 10 45 15 20 50 ma pf pf m a (v dd = 4.5 v to 5.5 v, ta = C40?c to +85?c) high level output voltage low level output voltage high level input current low level input current high level output leakage current i ozl low level output leakage current pd15 to pd0 with pull-up input other than the above v ol = v ss C100 C10 C50 C0.1 C10 m a m a i ozh i il i ih v ol v oh v oh = v dd sf1 , sf2 with pull-up v il = v ss ms with pull-down v ih = v dd i ol = 1.6 ma i oh = 40 m a 4.2 v dd v 0 0.4 v 0.1 10 m a 10 100 200 m a C10 C0.1 m a C100 C50 C10 m a 0.1 10 m a echo canceler characteristics (refer to characteristics diagram) cancelable echo delay time for a slave chip in a cascade cancelable echo delay time for a single chip or a master chip in a cascade echo attenuation parameter symbol condition min. typ. max. unit 30db l res r in = C10 dbm0 (5 khz band white noise) e. r. l. (echo return loss) = 6 db t d = 20 ms att, gc, nlp: off t d t ds 21 ms 31 ms r in = C10 dbm0 (5 khz band white noise) e. r. l. = 6 db att, gc, nlp: off
? semiconductor ML50000 12/26 ac characteristics parameter clock frequency when internal sync signal is not used clock cycle time when internal sync signal is not used clock duty ratio clock "h" level pulse width fc = 19.2 mhz clock "l" level pulse width fc = 19.2 mhz clock rise time clock fall time sync clock output time internal sync clock frequency internal sync clock output cycle time internal sync clock duty ratio internal sync signal output delay time internal sync signal period internal sync signal output width transmit/receive operation clock frequency transmit/receive sync clock cycle time transmit/receive sync clock duty ratio transmit/receive sync signal period sync timing sync signal width receive signal setup time receive data input time irld signal output delay time serial output delay time symbol f c t mck t dmc t mch t mcl t r t f t dcm f co t co t dco t dcc t cyo t wso f sck t sck t dsc t cyc t xs t sx t wsy t ds t id t dic t wir t sd t xd t wr min. 17.5 50 40 20.8 20.8 64 0.488 40 123 45 t sck 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck t sck max. 20 57.14 60 31.3 31.3 2048 15.6 60 t cyc -t sck min. 17.5 50 40 20.8 20.8 64 0.488 40 123 45 45 t sck 45 1 typ. 19.2 52.08 256 3.9 50 125 t co 50 125 7t sck t sck max. 20 57.14 60 31.3 31.3 5 5 30 5 2048 15.6 60 t cyc -t sck 138 90 90 unit mhz ns ns ns ns ns ns ns khz m s % ns m s m s khz m s % m s ns ns m s ns m s ns m s ns ns m s v dd = 2.7 v to 3.6 v v dd = 4.5 v to 5.5 v (ta = C40?c to +85?c) reset start time t drs 5ns reset end time t dre 52 ns processing operation start time t dit 100 100 m s irld signal output width reset signal input width 30 5 5 5 45 45 138 5 90 90 52 receive signal hold time t dh 45 ns 45
? semiconductor ML50000 13/26 ac characteristics (continued) parameter power down start time power down end time control pin setup time ( int ) control pin hold time ( int ) parallel data output signal width flag signal output time flag signal output width flag signal input width data read setup time data read hold time symbol t dps t dts t dth t wpd t df t wfo t wfi t fs f fh min. typ. 2t mck t mck /2 t wfo max. min. 20 120 typ. 2t mck t mck t mck /2 t wfo 20 10 max. 111 15 unit ns ns ns ns ns ns ns ns ns v dd = 2.7 v to 3.6 v v dd = 4.5 v to 5.5 v (ta = C40?c to +85?c) t dpe ns control pin hold time ( rst )t dhr 10ns control pin setup time ( rst )t dsr 20ns t mck 20 10 10 20 120 20 15 111
? semiconductor ML50000 14/26 timing diagram clock timing x1/clkin t r t f t mch t mcl f c , t mck , t dmc scko t dcm scko synco t cyo t dco t dcc t dcc t wso f co , t co t dcm serial input timing sck sync sin rin msb 7 t cyc f sck , t sck t sx t xs t wsy t dh t ds 654321 lsb 0 msb 7 t dsc irld t id t dic t dic t wir
? semiconductor ML50000 15/26 serial output timing operation timing after reset power down timing t dps t dpe internal operation processing start power down pwdwn sck sync sout rout msb 7 t cyc f sck , t sck t sx t xs t wsy t sd 654321 lsb 0 msb 7 t dsc high-z t xd t xd high-z t xd t drs rst t wr t dre internal operaion processing start t dit reset initialization *reset timing can be asynchronous note: int is invalid in the diagonally shaded interval.
? semiconductor ML50000 16/26 control pin load-in timing int ( irld ) *t cyc nlp, hcl, hd, att, adp, gc t dhr rst t wr t dsr nlp, hcl, hd, att, adp, gc t dth t dts *for irld output timing, refer to serial input timing parallel output timing pd15 pd 0 output data t wpd t wfo of1 of2 C t df high-z high-z parallel input timing input data t fs t fh t wfi sf1 sf2 pd15 pd 0 C
? semiconductor ML50000 17/26 how to use the ML50000 the ML50000 cancels (based on the rin signal) the echo which returns to sin. connect the base signal to the r side and the echo generated signal to the s side. connection methods according to echos example 1: canceling acoustic echo (to handle acoustic echo from line input) + + C aff rout sin rin sout ML50000 codec codec h line input acoustic echo example 2: canceling line echo (to handle line echo from microphone input) + + C aff rin sout rout sin ML50000 h line echo microphone input codec codec example 3: canceling line echo in a cascade connection (to handle line echo from microphone input) + + C aff rin sout rout sin ML50000 codec codec h line echo microphone input h aff slave pd0 - 15 master
? semiconductor ML50000 18/26 example 4: canceling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input) sin rout codec h line input acoustic echo + + C aff rout sin ML50000 + + C aff sout rin ML50000 rin sout microphone input for acoustic echo line echo codec for line echo ms nlp nlp hcl hcl adp adp att att gc gc pwdwn pwdwn rst rst int sf1 sf2 pd15 pd 0 irld of1 of2 +5 v ms nlp hcl adp att gc pwdwn rst int sf1 sf2 pd15 C pd 0 irld of1 of2 +5 v master chip slave chip C hd hd hd ms * nlp nlp hcl hcl adp adp att att gc gc pwdwn pwdwn rst rst int sf1 * sf2 * * pd15 C * pd 0 irld * of1 * of2 +5 v asterisk ( * ) indicates a pin onl y for the ML50000-011 hd hd control pin connection example single chip connection 2-stage cascade connection master + (slave 1)
? semiconductor ML50000 19/26 4-stage cascade connection master + (slave 3) ms nlp nlp hcl hcl adp adp att att gc gc pwdwn pwdwn rst rst int sf1 sf2 pd15 C pd 0 irld of1 of2 +5 v ms nlp hcl adp att gc pwdwn rst int sf1 sf2 pd15 pd 0 irld of1 of2 +5 v master chip slave chip 1 ms nlp hcl adp att gc pwdwn rst int sf1 sf2 pd15 pd 0 irld of1 of2 +5 v slave chip 2 ms nlp hcl adp att gc pwdwn rst int sf1 sf2 pd15 pd 0 irld of1 of2 +5 v slave chip 3 C C C hd hd hd hd hd internal clock generator circuit example ML50000 x1/clkin x2 xtal r c1 c2 r xtal c1 c2 gnd gnd : 19.2 mhz : 1 m w : 27 pf : 27 pf
? semiconductor ML50000 20/26 echo canceler characteristics diagram erl vs. echo attenuation echo attenuation [db] erl [db] measurement conditions rin input = C20 dbm 5 khz band white noise echo delay time t d = 20 ms att, gc, nlp = off power supply voltage 5 v rin input level vs. echo attenuation echo attenuation [db] rin input level [dbm0] measurement conditions rin input: 5 khz band white noise echo delay time t d = 20 ms erl = 6 db power supply voltage 5 v echo delay time vs. echo attenuation echo attenuation [db] echo dela y time [ ms ] measurement conditions rin input = C10 dbm 5 khz band white noise erl = 6 db att, gc, nlp = off the second through seventh chips are connected in a cascade. power supply voltage 5 v 0 10 20 30 40 40 30 20 10 0 C10 ML50000 msm7602 0 10 20 30 40 50 60 C50 C40 C30 C20 C10 0 att, gc, nlp=off att, gc=off nlp=on 0 10 20 30 0 50 100 150 200 1 40 2 note: the characteristics above are for the msm7533 (v dd 5 v, m -law interface). the msm7704 (v dd 3 v, m -law interface) provides the same characleristics without input and output levels. refer to are pcm codec data sheet. msm7533 (for both transmit and receive) 0 dbm0 = 0.85 vrms = 0.8 dbm (600 w ) msm7704 (for transmit side) 0 dbm0 = 0.35 vrms = C6.9 dbm (600 w ) msm7704 (for receive side) 0 dbm0 = 0.5 vrms = C3.8 dbm (600 w )
? semiconductor ML50000 21/26 measurement system block diagram rin sout rout sin ML50000 delay t d echo delay time att erl (echo return loss) power supply voltage 5 v rin sout l. p. f. 5 khz level meter white noise generator a a pcm pcm pcm pcm a a 2ch m -law codec msm7533
? semiconductor ML50000 22/26 application circuit bidirectional connection example microphone input c1 r1 speaker output dv r3 21 22 4 13 12 15 10 16 19 5 6 dv ain1 gsx1 aout1 dout1 din1 xsync rsync bclk a / m pdn chp ain2 gsx2 aout2 dout2 din2 v dd sgc ag dg 24 23 2 14 11 8 1 18 9 r2 r5 dv r7 r6 av + c9 c10 c11 c5 line input line output (ag) for cancellation of acoustic echo ML50000-001gs-k dv r8 dv r4 8 13 11 10 22 23 6 24 28 4 19 27 dv pwdwn rst 12 9 1 2 5 26 25 14 15 21 3 16 18 sin rout sync sck synco scko rst pwdwn mcko v dd v dd v dd sout rin nlp hcl att gc x1 v ss v ss v ss adp hd wdt x2 sout rin nlp hcl att gc wdt x2 v ss v ss v ss adp hd sin rout sync sck synco scko rst v dd v dd v dd pwdwn 12 9 1 2 5 26 25 r9 14 15 21 3 16 18 dv dv 8 13 11 10 23 6 20 24 28 4 19 27 dv + c6 c7 c2 c3 + r1 = 20 k w r2 = 20 k w r3 = 2.2 k w r4 = 10 k w r10 = 10 k w c1 = 1 m f c2 = 10 m f c3 = 0.1 m f c4 = 0.1 m f r5 = 20 k w r6 = 20 k w r7 = 2.2 k w r8 = 10 k w r11 = 10 k w c5 = 1 m f c6 = 10 m f c7 = 0.1 m f c8 = 0.1 m f 2ch codec msm7533vgs-k for cancellation of line echo ML50000-001gs-k dv r10 dv r11 7 20 int irld 17 c13 x1 c12 17 x1 22 7 irld int r9 = 1 m w c12 = 27 pf c13 = 27 pf x1 = 19.2 mhz c14 = 5 pf c14 c9 = 0.1 m f c10 = 10 m f c11 = 0.1 m f use the msm7704-01gs-vk for pcm codec when v dd 3v. the msm7533 and msm7704 are pin compatible.
? semiconductor ML50000 23/26 cascade connection example sgc 12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7 46 39 35 49 13 12 15 11 14 10 8 13 10 11 38 34 1 2 3 4 5 40 28 37 36 31 r11 32 33 41 42 55 54 51 14 21 sin rout sck sync rst pwdwn nlp hcl adp ms att gc hd scko synco x1 x2 v dd v dd v dd v dd v dd v ss v ss v ss sout rin pd15 pd14 pd13 pd12 pd11 pd10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 of2 sf2 of1 sf1 int irld mcko wdt v ss v ss sin rout sck sync rst pwdwn nlp hcl adp ms att gc hd scko synco x1 x2 v dd v dd v dd v dd v dd v ss v ss v ss sout rin pd15 pd14 pd13 pd12 pd11 pd10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 of2 sf2 of1 sf1 int irld mcko wdt v ss v ss 12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7 46 39 35 49 13 12 15 11 14 10 19 8 13 10 11 38 34 1 2 3 4 5 40 28 37 36 31 32 33 41 42 55 54 51 14 21 23 6 21 22 1 23 6 21 22 1 pcmout pcmin bclock rsync xsync pdm tmc pcmout pcmin bclock rsync xsync pdm ain + vfro gsx ainC msm7543gs-vk msm7543gs-vk master slave r1 r2 r3 16 c1 sin rout r4 r5 9 dg + c4 c12 c11 x1 56-pin qfp 56-pin qfp rst pwdwn + c8 rin sout r7 r8 r6 r7 > 20 k w r8 > 20 k w r9 = 2.2 k w r10 = 10 k w r12 = 0-22 w r13 = 0-22 w c6 = 10 m f c7 = 0.1 m f c8 = 10 m f c9 = 0.1 m f c10 = 0.1 m f c13 = 5 pf r1 > 50 k w r2 > 20 k w r3 > 20 k w r4 = 2.2 k w r5 = 10 k w r6 > 50 k w c1 = 0.1 m f c2 = 10 m f c3 = 0.1 m f c4 = 10 m f c5 = 0.1 m f r11 = 1 m w c11 = 27 pf c12 = 27 pf x1 = 19.2 mhz when v dd is 3 v, use the msm7566 for pcm codec. the msm7543 and msm7566 are pin compatible. dg r9 r10 c5 9 ML50000-011gs-2k ML50000-011gs-2k ain+ vfro gsx ain sg sgc v dd ag 24 5 3 aoutC pwi 19 tmc sg v dd ag 8 24 5 3 pwi aoutC 16 8 + c7 c6 c10 r12 c2 + c9 r13 c3 c13
? semiconductor ML50000 24/26 notes on use 1. set echo return loss (erl) to be attenuated. the echo can be eliminated even if the echo return loss is set to be amplified. this may cause an excessive input. refer to the characteristics diagram for erl vs. echo attenuation quantity. 2. set the level of the analog input so that the pcm codec does not overflow. 3. the recommended input level is C10 to C20 dbm0. refer to the characteristics diagram for the rin input level vs. echo attenuation quantity. 4. applying the tone signal to this echo canceler for long duration may decrease echo attenuation. when used with the hd pin "l" (howling detector on), this echo canceler may operate faultily if, while a signal is input to the rin pin, a tone signal with a higher level than the signal being input to rin is input to the sin pin. a signal should therefore be input either to the rin pin or to the sin pin. if, however, the tone signal is input to the sin pin while a signal is input to the rin pin, the adp, hd, or hcl pin must be set to "h". 5. when turning the power on, set the pwdwn pin to "1" and input the basic clock simultaneously with power on. if powering down immediately after power on, be sure fast input 10 or more clocks of the basic clock. 6. after powering on, be sure to reset. 7. after the power down mode is released (when the pwdwn pin is changed to "h" from "l"), be sure to reset the device. 8. if this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 db.
? semiconductor ML50000 25/26 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop28-p-485-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.39 typ. mirror finish
? semiconductor ML50000 26/26 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-2k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.43 typ. mirror finish

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